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preliminary aec q100 grade 1 compliant this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results. 1850 ramtron drive, colorado springs, co 80921 (800) 545-fram, (719) 481-7000 rev. 1.0 http://www.ramtron.com feb. 2011 page 1 of 13 fm25c160b ? automotive temp. 16kb fram serial memory features 16k bit ferroelectric nonvolatile ram ? organized as 2,048 x 8 bits ? high endurance 10 trillion (10 13 ) read/writes ? nodelay? writes ? advanced high-reliability ferroelectric process fast serial peripheral interface - spi ? up to 15 mhz maximum bus frequency ? direct hardware replacement for eeprom ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme ? hardware protection ? software protection low power consumption ? 10 a standby current (+85 c) industry standard configuration ? automotive temperature -40 c to +125 c o qualified to aec q100 specification ? ?green?/rohs 8-pin soic description the fm25c160b is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or fram is nonvolatile but operates in other respects as a ram. it provides reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. the fm25c160b performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte has been transferred to the device. the next bus cycle may commence without the need for data polling. the fm25c160b is capable of supporting 10 13 read/write cycles, or 10 million times more write cycles than eeprom. these capabilities make the fm25c160b ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding automotive controls where the long write time of eeprom can cause data loss. the fm25c160b provides substantial benefits to users of serial eeprom, in a hardware drop-in replacement. the fm25c160b uses the high-speed spi bus, which enhances the high-speed write capability of fram technology. the specifications are guaranteed over the automotive temperature range of -40c to +125c. pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd 5v vss ground ordering information fm25c160b-ga ?green?/rohs 8-pin soic, automotive grade 1 FM25C160B-GATR ?green? /rohs 8-pin soic, automotive grade 1, tape & reel cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 2 of 13 instruction decode clock generator control logic write protect instruction register address register counter 256 x 64 fram array 11 data i/o register 8 nonvolatile status register 3 wp cs hold sck so si figure 1. block diagram pin description pin name i/o pin description /cs input chip select: this active low input activates the device. when high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op-code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 15 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active low pin prevents write operations to the status register. this is critical since other write protection features are controlled through the status register. a complete explanation of write protection is provided on page 6. *note that the function of /wp is different from the fm25160. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * si may be connected to so for a single pin data interface. so output serial output. so is the data output pin. it is driven actively during a read and remains tri-state at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply supply voltage. 5v vss supply ground
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 3 of 13 overview the fm25c160b is a serial fram memory. the memory array is logically organized as 2,048 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the fram is similar to serial eeproms. the major difference between the fm25c160b and a serial eeprom with the same pin-out relates to its superior write performance. it also differs from ramtron?s 25160 by supporting spi mode 3 and the industry standard 16-bit addressing protocol. this makes the fm25c160b a drop-in replacement for most 16kb spi eeproms that support modes 0 & 3. memory architecture when accessing the fm25c160b, the user addresses 2,048 locations each with 8 data bits. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op-code and a two-byte address. the upper 5 bits of the address range are ?don?t care? values. the complete address of 11-bits specifies each byte address uniquely. most functions of the fm25c160b either are controlled by the spi interface or are handled automatically by on-board circuitry. the access time for memory operation essentially is zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the fm25c160b due to its fast write cycle and high endurance as compared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast-write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note: the fm25c160b contains no power management circuits other than a simple internal power-on reset. it is the user?s responsibility to ensure that vdd is within data sheet tolerances to prevent incorrect operation. it is recommended that the part is not powered down with chip enable active. serial peripheral interface ? spi bus the fm25c160b employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 15 mhz. this high-speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25c160b operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data-in, data-out, and chip select. a typical system configuration uses one or more fm25c160b devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data-in, and data-out pins are common among all devices. the chip select and hold pins must be driven separately for each fm25c160b device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the hold pin. figure 3 shows a configuration that uses only three pins. protocol overview the spi interface is a synchronous serial interface using clock and data lines. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm25c160b will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm25c160b supports modes 0 and 3. figure 4 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm25c160b on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op-codes. these op-codes specify the commands to the part. after /cs is activated the first byte transferred from the bus master is the op-code. following the op-code, any addresses and data are then transferred. note that the wren and wrdi op-codes are commands with no subsequent data transfer. important: the /cs pin must go inactive after an operation is complete and before a new op-code can be issued. there is one valid op-code only per active chip select.
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 4 of 13 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 0 1 2 3 4 5 6 7 spi mode 3: cpol=1, cpha=1 0 1 2 3 4 5 6 7 figure 4. spi modes 0 & 3
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 5 of 13 data transfer all data transfers to and from the fm25c160b occur in 8-bit groups. they are synchronized to the clock signal (sck) and they transfer most significant bit (msb) first. serial inputs are clocked in on the rising edge of sck. outputs are driven on the falling edge of sck. command structure there are six commands called op-codes that can be issued by the bus master to the fm25c160b. they are listed in the table below. these op-codes control the functions performed by the memory. they can be divided into three categories. first, are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register. last are commands for memory transactions followed by address and one or more bytes of data. table 1. op-code commands name description op-code value wren set write enable latch 0000 _ 0110b wrdi write disable 0000 _ 0100b rdsr read status register 0000 _ 0101b wrsr write status register 0000 _ 0001b read read memory data 0000 _ 0011b write write memory data 0000 _ 0010b wren - set write enable latch the fm25c160b will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op-code will allow the user to issue subsequent op-codes for write operations. these include writing the status register and writing the memory. sending the wren op-code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. a write to the status register has no effect on the wel bit. completing any write operation will automatically clear the write-enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 6 of 13 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading status provides information about the current state of the write protection features. following the rdsr op- code, the fm25c160b will return one byte with the contents of the status register. the status register is described in detail in a later section. wrsr ? write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /wp pin must be high or inactive. note that on the fm25c160b, /wp only prevents writing to the status register, not the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. the bus timing for rdsr and wrsr are shown below. figure 7. rdsr bus timing figure 8. wrsr bus timing (wren not shown) status register & write protection the write protection features of the fm25c160b are multi-tiered. first, a wren op-code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the status register. as described above, writes to the status register are performed using the wrsr command and subject to the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4-6 are fixed at 0 and cannot be modified. note that bit 0 (/rdy in eeproms) is wired low since fram writes have no delay and the memory is never busy. all eeproms use ready to indicate whether a write cycle is complete or not. the wpen, bp1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. this bit is internally set by the wren command and is cleared by terminating a write cycle (/cs high) or by using the wrdi command. bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 600h to 7ffh (upper ?) 1 0 400h to 7ffh (upper ?) 1 1 000h to 7ffh (all)
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 7 of 13 the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register. thus the status register is write protected if wpen=1 and /wp=0. this scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, with its relatively high maximum clock frequency, highlights the fast write capability of the fram technology. unlike spi-bus eeproms, the fm25c160b can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op-code. the next op-code is the write instruction. this op-code is followed by a two-byte address value. the upper 5-bits of the address are don?t care. in total, the 11-bits specify the address of the first byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7ffh is reached, the counter will roll over to 0000h. data is written msb first. unlike eeproms, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op-code operation. read operation after the falling edge of /cs, the bus master can issue a read op-code. following this instruction is a two- byte address value. the upper 5-bits of the address are don?t care. in total, the 11-bits specify the address of the first byte of the read operation. after the op- code and address are complete, the si line is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7ffh is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read op-code operation. the bus configuration for read and write operations is shown below. hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master takes the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state.
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 8 of 13 figure 9. memory write (wren not shown) figure 10. memory read endurance the fm25c160b devices are capable of being accessed at least 10 13 times, reads or writes. an f- ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f-ram architecture is based on an array of rows and columns. rows are defined by a10-a3 and column addresses by a2-a0. see block diagram (pg 2) which shows the array as 256 rows of 64-bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. this causes each byte to experience one endurance cycle through the loop. f-ram read and write endurance is virtually unlimited even at 10mhz clock rate. table 5. time to reach endurance limit for repeating 64-byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach limit 10 18,660 5.88 x 10 11 17.0 5 9,330 2.94 x 10 11 34.0 1 1,870 5.88 x 10 10 170.1
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 9 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +7.0v v in voltage on any pin with respect to v ss -1.0v to +7.0v and v in < v dd +1.0v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 260 c v esd electrostatic discharge voltage - human body model (aec-q100-002 rev. e) - charged device model (aec-q100-011 rev. b) - machine model (aec-q100-003 rev. e) tbd tbd tbd package moisture sensitivity level msl-1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to +125 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 4.5 5.0 5.5 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 15.0 mhz - - 0.3 3.0 ma ma 1 i sb standby current @ +85 c @ +125 c - - 10 30 a a 2 i li input leakage current 1 1 notes 1. sck toggling between v dd -0.3v and v ss , other inputs v ss or v dd -0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v in or v out = v ss to v dd . 4. this parameter is characterized but not 100% tested. applies only to /cs and sck pins.
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 10 of 13 ac parameters (t a = -40 c to +125 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes f ck sck clock frequency 0 15 mhz t ch clock high time 30 ns 1 t cl clock low time 30 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable 25 ns 2 t odv output data valid 25 ns t oh output hold 0 ns t d deselect time 80 ns t r data in rise time 50 ns 2,3 t f data in fall time 50 ns 2,3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi-z 25 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. this parameter is characterized and not 100% tested. 3. rise and fall times measured between 10% and 90% of waveform. capacitance (t a = 25 c, f=1.0 mhz, v dd = 5v) symbol parameter min max units notes c o output capacitance (so) - 8 pf 1 c i input capacitance - 6 pf 1 notes 1. this parameter is characterized and not 100% tested. ac test conditions input pulse levels 10% and 90% of v dd input and output timing levels 0.5 v dd input rise and fall times 5 ns output load capacitance 30 pf power cycle timing power cycle timing (t a = -40 c to +125 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes t pu v dd (min) to first access start 10 - ms t pd last access complete to v dd (min) 0 - notes 1. slope measured at any point on v dd waveform.
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 11 of 13 serial data bus timing 1/fck tcl tch tcsh todv toh tod tcsu tsu th td tr tf /hold timing data retention (v dd = 4.5v to 5.5v) parameter min max units notes data retention @ t a = +55 c @ t a = +105 c @ t a = +125 c 17 10,000 1,000 - - - years hours hours note: data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied: (1) 17 years at a temperature of +55 c, (2) 10,000 hours at +105 c, and (3) 1,000 hours at +125 c. typical grade 1 operating profile 0 200 400 600 800 1000 1200 1400 1600 70 75 80 85 90 95 100 105 110 115 120 125 temperature (c) hours typical grade 1 storage profile 0 5000 10000 15000 20000 25000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 temperature (c) hours
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 12 of 13 mechanical drawing 8-pin soic (jedec ms-012, variation aa) pin 1 3.90 0.10 6.00 0.20 4.90 0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45 0.40 1.27 0.19 0.25 0 - 8 recommended pcb footprint 7.70 0.65 1.27 2.00 3.70 refer to jedec ms-012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxxx= part number, p= package type (g=soic), t= temp (a= automotive, blank=ind.) r=rev code, lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm25c160b, ?green? soic, automotive temperature, rev a, lot l3502g1, year 2011, work week 04 25c160bga al3502g1 ric1104 xxxxxxxpt lllllll ricyyww
fm25c160b - automotive temp. rev. 1.0 feb. 2011 page 13 of 13 revision history revision date summary 1.0 2/18/2011 initial release.

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