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the cs-5155 is a 5-bit synchronous dual n-channel buck controller. it is designed to provide unprece- dented transient response for today?s demanding high-density, high-speed logic. the regulator operates using a proprietary control method, which allows a 100ns response time to load transients. the cs-5155 is designed to operate over a 4.25-20v range (v cc ) using 12v to power the ic and 5v or 12v as the main supply for conversion. the cs-5155 is specifically designed to power pentium ii processors and other high performance core logic. it includes the following fea- tures: on board, 5-bit dac, short circuit protection, 1.0% output tol- erance, v cc monitor, and pro- grammable soft start capability. the cs-5155 is backwards compatible with the 4 bit cs-5150, allowing the mother board designer the capabili- ty of using either the cs-5150 or the cs-5155 with no change in layout. the cs-5155 is available in 16 pin surface mount and dip packages. features n dual n-channel design n excess of 1mhz operation n 100ns transient response n 5-bit dac n backward compatible with 4 bit cs-5150/5151 and adjustable cs-5120/5121 n 30ns gate rise/fall times n 1% dac accuracy n 5v & 12v operation n remote sense n programmable soft start n lossless short circuit protection n v cc monitor n 25ns fet nonoverlap time n adaptive voltage positioning n v 2 a control topology n current sharing n overvoltage protection package option cpu 5-bit synchronous buck controller cs-5155/5155h description application diagram 1 v id0 v id1 v id2 v id3 ss v id4 c off v ffb v fb comp lgnd v cc1 v gate(l) pgnd v gate(h) v cc2 16 lead so narrow & pdip 1 cherry semiconductor corporation 2000 south county trail east greenwich, rhode island 02818-1530 tel: (401)885-3600 fax (401)885-5786 email: info@cherry-semi.com switching power supply for core logic - pentium ii processor 0.33 m f v id0 v id1 v id2 v id3 v id0 v id1 v id2 v id3 v cc1 ss cs-5155 c off lgnd v fb v ffb comp irl3103 irl3103 0.1 m f 12v 5v 2 m h 1.3v to 3.5v @ 13a v cc2 v gate(h) v gate(l) pgnd 1200 m f/16v x 3 alel 3.3k 0.1 m f 1200 m f/16v x 5 alel 100pf 330pf v id4 v id4 v 2 is a trademark of switch power, inc. pentium is a registered trademark of intel corporation. a company cs-5155/5155h rev. 11/2/98 part number max input voltage cs-5155 16v cs-5155h 20v
2 pin name max operating voltage max current v cc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ma dc/1.5a peak v cc2 (cs-5155) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma dc/1.5a peak v cc2 (cs-5155h) . . . . . . . . . . . . . . . . . . . . . . . . . 20v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma dc/1.5a peak ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-100a comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200a v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2a c off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2a v ffb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2a v id0 - v id4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50a v gate(h) (cs-5155). . . . . . . . . . . . . . . . . . . . . . . . 16v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 00ma dc/1.5a peak v gate(h) (cs-5155h) . . . . . . . . . . . . . . . . . . . . . . 20v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100m a dc/1.5a peak v gate(l) (cs-5155) . . . . . . . . . . . . . . . . . . . . . . . . 16v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 00ma dc/1.5a peak v gate(l) (cs-5155h) . . . . . . . . . . . . . . . . . . . . . . 20v/-0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100m a dc/1.5a peak lgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ma pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100ma dc/1.5a peak operating junction temperature, t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0? to 125? c operating temperature range, t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0? to 70?c lead temperature soldering wave solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 se c. max, 260?c peak reflow (smd styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max a bove 183?c, 230?c peak storage temperature range, t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65? to 150?c esd susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 parameter test conditions min typ max unit cs-5155/5155h electrical characteristics: 0?c < t a < +70?c; 0?c < t j < +85?c; 8v < v cc1 < 14v; (cs-5155: 5v < v cc2 < 14v), (cs-5155h: 5v < v cc2 < 20v); dac code: v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0; cv gate(l) and cv gate(h) = 1nf; c off = 330pf; c ss = 0.1f, unless otherwise specified. absolute maximum ratings n error amplifier v fb bias current v fb = 0v 0.3 1.0 a open loop gain 1.25v < v comp < 4v; note 1 50 60 db unity gain bandwidth note 1 500 3000 kh comp sink current v comp = 1.5v; v fb = 3v; v ss > 2v 0.4 2.5 8.0 ma comp source current v comp = 1.2v; v fb = 2.7v; v ss = 5v 30 50 70 a comp clamp current v comp = 0v; v fb = 2.7v 0.4 1.0 1.6 ma comp high voltage v fb = 2.7v; v ss = 5v 4.0 4.3 5.0 v comp low voltage v fb =3v 160 600 mv psrr 8v < v cc1 < 14v @ 1khz; note 1 60 85 db n v cc1 monitor start threshold output switching 3.75 3.90 4.05 v stop threshold output not switching 3.70 3.85 4.00 v hysteresis start-stop 50 mv n dac input threshold v id0 , v id1 , v id2 , v id3 , v id4 1.00 1.25 2.40 v input pull up resistance v id0 , v id1 , v id2 , v id3 , v id4 25 50 100 k? pull up voltage 4.85 5.00 5.15 v accuracy measure v fb = v comp , 25?c 2 t j 2 85?c 1.0 % v id4 v id3 v id2 v id1 v id0 01111 1.3266 1.3400 1.3534 v 01110 1.3761 1.3900 1.4039 v 01101 1.4256 1.4400 1.4544 v 0 1 1 0 0 1.4751 1.4900 1.5049 v
cs-5155/5155h 3 parameter test conditions min typ max unit electrical characteristics: 0?c < t a < +70?c; 0?c < t j < +85?c; 8v < v cc1 < 14v; (cs-5155: 5v < v cc2 < 14v), (cs-5155h: 5v < v cc2 < 20v); dac code: v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0; cv gate(l) and cv gate(h) = 1nf; c off = 330pf; c ss = 0.1f, unless otherwise specified. n dac: continued v id4 v id3 v id2 v id1 v id0 01011 1.5246 1.5400 1.5554 v 01010 1.5741 1.5900 1.6059 v 01001 1.6236 1.6400 1.6564 v 0 1 0 0 0 1.6731 1.6900 1.7069 v 0 0 1 1 1 1.7226 1.7400 1.7574 v 0 0 1 1 0 1.7721 1.7900 1.8079 v 0 0 1 0 1 1.8216 1.8400 1.8584 v 0 0 1 0 0 1.8711 1.8900 1.9089 v 00011 1.9206 1.9400 1.9594 v 00010 1.9701 1.9900 2.0099 v 00001 2.0196 2.0400 2.0604 v 0 0 0 0 0 2.0691 2.0900 2.1109 v 11111 1.2315 1.2440 1.2564 v 11110 2.1186 2.1400 2.1614 v 11101 2.2176 2.2400 2.2624 v 11100 2.3166 2.3400 2.3634 v 11011 2.4156 2.4400 2.4644 v 11010 2.5146 2.5400 2.5654 v 11001 2.6136 2.6400 2.6664 v 11000 2.7126 2.7400 2.7674 v 10111 2.8116 2.8400 2.8684 v 10110 2.9106 2.9400 2.9694 v 10101 3.0096 3.0400 3.0704 v 10100 3.1086 3.1400 3.1714 v 10011 3.2076 3.2400 3.2724 v 10010 3.3066 3.3400 3.3734 v 10001 3.4056 3.4400 3.4744 v 10000 3.5046 3.5400 3.5754 v n v gate(h) and v gate(l) out source sat at 100ma measure v cc1 e v gate(l), ;v cc2 e v gate(h) 1.2 2.0 v out sink sat at 100ma measure v gate(h) e vpgnd; 1.0 1.5 v v gate(l) e vpgnd out rise time 1v < v gate(h) < 9v; 1v < v gate(l) < 9v 30 50 ns v cc1 = v cc2 = 12v out fall time 9v > v gate(h) > 1v; 9v > v gate(l) > 1v 30 50 ns v cc1 = v cc2 = 12v shoot-through current note 1 50 ma delay v gate(h) to v gate(l) v gate(h) falling to 2v; v cc1 = v cc2 = 8v 25 50 ns v gate(l) rising to 2v delay v gate(l) to v gate(h) v gate(l) falling to 2v; v cc1 = v cc2 = 8v 25 50 ns v gate(h) rising to 2v v gate(h) , v gate(l) resistance resistor to lgnd 20 50 100 k? v gate(h) , v gate(l) schottky lgnd to v gate(h) @ 10ma 600 800 mv lgnd to v gate(l) @ 10ma
parameter test conditions min typ max unit 4 cs-5155/5155h package pin description package pin # pin symbol function electrical characteristics: 0?c < t a < +70?c; 0?c < t j < +85?c; 8v < v cc1 < 14v; (cs-5155: 5v < v cc2 < 14v), (cs-5155h: 5v < v cc2 < 20v); dac code: v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0; cv gate(l) and cv gate(h) = 1nf; c off = 330pf; c ss = 0.1f, unless otherwise specified. 16l so narrow & pdip 1,2,3,4,6 v id0 e v id4 voltage id dac input pins. these pins are internally pulled up to 5v providing logic ones if left open. v id4 selects the dac range. when v id4 is high (logic one), the dac range is 2.14v to 3.54v with 100mv incre- ments. when v id4 is low (logic zero), the dac range is 1.34v to 2.09v with 50mv increments. v id0 - v id4 select the desired dac output volt- age. leaving all 5 dac input pins open results in a dac output voltage of 1.244v, allowing for adjustable output voltage, using a traditional resistor divider. 5 ss soft start pin. a capacitor from this pin to lgnd in conjunction with internal 60a current source provides soft start function for the con- troller. this pin disables fault detect function during soft start. when a fault is detected, the soft start capacitor is slowly discharged by internal 2a current source setting the time out before trying to restart the ic. charge/discharge current ratio of 30 sets the duty cycle for the ic when the regulator output is shorted. n soft start (ss) charge time 1.6 3.3 5.0 ms pulse period 25 100 200 ms duty cycle (charge time/pulse period) 100 1.0 3.3 6.0 % comp clamp voltage v fb = 0v; v ss = 0 0.50 0.95 1.10 v v ffb ss fault disable v gate(h) = low; v gate(l) = low 0.9 1.0 1.1 v high threshold 2.5 3.0 v n pwm comparator transient response v ffb = 0 to 5v to v gate(h) = 9v to 1v; 100 125 ns v cc1 = v cc2 = 12v v ffb bias current v ffb = 0v 0.3 a n supply current i cc1 no switching 8.5 13.5 ma i cc2 no switching 1.6 3.0 ma operating i cc1 v fb = comp = v ffb 813ma operating i cc2 v fb = comp = v ffb 25ma n c off normal charge time v ffb = 1.5v; v ss = 5v 1.0 1.6 2.2 s extension charge time v ss = v ffb = 0 5.0 8.0 11.0 s discharge current c off to 5v; v fb >1v 5.0 ma n time out timer time out time v fb = v comp ; v ffb = 2v; 10 30 50 s record v gate(h) pulse high duration fault mode duty cycle v ffb = 0v 35 50 65 % note 1: guaranteed by design, not 100% tested in production.
5 cs-5155/5155h block diagram q v id1 v cc1 ss comp v fb v id0 lgnd v ffb v cc2 v gate(h) pgnd v gate(l) v id2 v id3 - + 5 bit dac c off slow feedback maximum on-time timeout v cc1 r q s c off one shot pwm comp ss high comparator fault latch 2.5v error amplifier fast feedback - + v cc1 monitor comparator v id4 - + - + - + - + v ffb low comparator pwm comparator ss low comparator r q s q r q s 2 m a 5v 60 m a normal off-time timeout extended off-time timeout time out timer (25 m s) edge triggered off-time timeout 3.90v 3.85v fault fault gate(h) = on gate(h) = off pgnd pwm latch 1v 0.7v package pin description: continued package pin # pin symbol function 16l so narrow & pdip 7c off a capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture. 8v ffb fast feedback connection to the pwm comparator. this pin is connect- ed to the regulator output. the inner feedback loop terminates on time. 9v cc2 boosted power for the high side gate driver. 10 v gate(h) high fet driver pin capable of 1.5a peak switching current. internal circuit prevents v gate(h) and v gate(l) from being in high state simul- taneously. 11 pgnd high current ground for the ic. the mosfet drivers are referenced to this pin. input capacitor ground and the source of lower fet should be tied to this pin. 12 v gate(l) low fet driver pin capable of 1.5a peak switching current. 13 v cc1 input power for the ic and low side gate driver. 14 lgnd signal ground for the ic. all control circuits are referenced to this pin. 15 comp error amplifier compensation pin. a capacitor to ground should be provided externally to compensate the amplifier. 16 v fb error amplifier dc feedback input. this is the master voltage feedback which sets the output voltage. this pin can be connected directly to the output or a remote sense trace.
v 2 a control method the v 2 a method of control uses a ramp signal that is gen- erated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is gen- erated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. figure 1: v 2 a control diagram the v 2 a control method is illustrated in figure 1. the out- put voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is affected by any change in the output regard- less of the origin of that change. the ramp signal also con- tains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 a control scheme to compensate the duty cycle. since the change in inductor current modifies the ramp signal, as in current mode control, the v 2 a control scheme has the same advantages in line transient response. a change in load current will have an affect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this ?slow? feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sens- ing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. line and load regulation are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compen- sate for a deviation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error sig- nal for a deviation in load. the v 2 a method of control maintains a fixed error signal for both line and load varia- tion, since the ramp signal is affected by both line and load. constant off time to maximize transient response, the cs-5155 uses a con- stant off time method to control the rate of output pulses. during normal operation, the off time of the high side switch is terminated after a fixed period, set by the c off capacitor. to maintain regulation, the v 2 a control loop varies switch on time. the pwm comparator monitors the output voltage ramp, and terminates the switch on time. constant off time provides a number of advantages. switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line tran- sients. pwm slope compensation to avoid sub-harmonic oscillations at high duty cycles is avoided. switch on time is limited by an internal 25s timer, mini- mizing stress to the power components. programmable output the cs-5155 is designed to provide two methods for pro- gramming the output voltage of the power supply. a five bit on board digital to analog converter (dac) is used to program the output voltage within two different ranges. the first range is 2.14v to 3.54v in 100mv steps, the second is 1.34v to 2.09v in 50mv steps, depending on the digital input code. if all five bits are left open, the cs-5155 enters adjust mode. in adjust mode, the designer can choose any output voltage by using resistor divider feedback to the v fb and v ffb pins, as in traditional controllers. the cs-5155 is specifically designed to be backwards compatible with the cs-5150, which uses a four bit dac code. start up until the voltage on the v cc1 supply pin exceeds the 3.9v monitor threshold, the soft start and gate pins are held low. the fault latch is reset (no fault condition). the output of the error amplifier (comp) is pulled up to 1v by the comparator clamp. when the v cc1 pin exceeds the monitor threshold, the gateh output is activated, and the soft start capacitor begins charging. the gateh output will remain on, enabling the nfet switch, until terminated by either the pwm comparator, or the maximum on time timer. if the maximum on time is exceeded before the regulator output voltage achieves the 1v level, the pulse is terminat- ed. the gateh pin drives low, and the gatel pin drives high for the duration of the extended off time. this time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. the gatel pin will then drive low, the gateh pin will drive high, and the cycle repeats. reference voltage + c e + ramp signal output voltage feedback error signal v gate(h) v gate(l) error amplifier v ffb comp v fb pwm comparator theory of operation cs-5155/5155h applications information 6
cs-5155/5155h 7 applications information: continued when regulator output voltage achieves the 1v level pre- sent at the comp pin, regulation has been achieved and normal off time will ensue. the pwm comparator termi- nates the switch on time, with off time set by the c off capacitor. the v 2 a control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. the soft start and comp capacitors will charge to their final levels, providing a controlled turn on of the regulator output. regulator turn on time is determined by the comp capacitor charging to its final value. its voltage is limited by the soft start comp clamp and the voltage on the soft start pin (see figures 2 and 3). figure 2: cs-5155 demonstration board startup in response to increasing 12v and 5v input voltages. extended off time is followed by normal off time operation when output voltage achieves regulation to the error amplifier output. figure 3: cs-5155 demonstration board startup waveforms. if the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see figure 4). figure 4: cs-5155 demonstration board enable startup waveforms. normal operation during normal operation, switch off time is constant and set by the c off capacitor. switch on time is adjusted by the v 2 a control loop to maintain regulation. this results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. output voltage ripple will be determined by inductor rip- ple current working into the esr of the output capacitors (see figures 5 and 6). figure 5: peak-to-peak ripple on v out = 2.8v, i out = 0.5a (light load). trace 1 - regulator output voltage (10v/div.) trace 2 - inductor switching node (5v/div.) trace 1 - regulator output voltage (5v/div.) trace 2 - inductor switching node (5v/div.) trace 1 - regulator output voltage (1v/div.) trace 3 - comp pin (error amplifier output) (1v/div.) trace 4 - soft start pin (2v/div.) trace 1 - regulator output voltage (1v/div.) trace 2 - inductor switching node (2v/div.) trace 3 - 12v input (v cc1 and v cc2 ) (5v/div.) trace 4 - 5v input (1v/div.)
applications information: continued cs-5155/5155h 8 figure 6: peak-to-peak ripple on v out = 2.8v, i out = 13a (heavy load). transient response the cs-5155 v 2 a control loop?s 100ns reaction time pro- vides unprecedented transient response to changes in input voltage or output current. pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. overall load transient response is further improved through a feature called adaptive voltage positioning. this technique pre-positions the output capacitor?s voltage to reduce total output voltage excursions during changes in load. holding tolerance to 1% allows the error amplifier?s refer- ence voltage to be targeted +40mv high without compro- mising dc accuracy. a droop resistor, implemented through a pc board trace, connects the error amplifier?s feedback pin (v fb ) to the output capacitors and load and carries the output current. with no load, there is no dc drop across this resistor, producing an output voltage tracking the error amplifier?s, including the +40mv offset. when the full load current is delivered, an 80mv drop is developed across this resistor. this results in output volt- age being offset -40mv low. the result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. when load current sud- denly increases from it?s minimum level, the output capaci- tor is pre-positioned +40mv. conversely, when load cur- rent suddenly decreases from it?s maximum level, the out- put capacitor is pre-positioned -40mv (see figures 7, 8, and 9). for best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. if the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor. figure 7: cs-5155 demonstration board response to a 0.5 to 13a load pulse (output set for 2.8v). figure 8: cs-5155 demonstration board response to 13a load turn on (output set for 2.8v). upon completing a normal off time, the v 2 a con- trol loop immediately connects the inductor to the input voltage, pro- viding 100% duty cycle. regulation is achieved in less than 20s. trace 1 - regulator output voltage (1v/div.) trace 2 - inductor switching node (5v/div.) trace 3 - output current (0.5 to 13 amps) (20v/div.) trace 1 - regulator output voltage (1v/div.) trace 3 - regulator output current (20v/div.) trace1 - regulator output voltage (10v/div.) trace 2 - inductor switching node (5v/div.)
cs-5155/5155h applications information: continued 9 figure 9: cs-5155 demonstration board response to 13a load turn off (output set for 2.8v). v 2 a control topology immediately connects inductor to ground, providing 0% duty cycle. regulation is achieved in less than 10s. v cc1 monitor to maintain predictable startup and shutdown character- istics an internal v cc1 monitor circuit is used to prevent the part from operating below 3.75v minimum startup. the v cc1 monitor comparator provides hysteresis and guaran- tees a 3.70v minimum shutdown threshold. short circuit protection a lossless hiccup mode short circuit protection feature is provided, requiring only the soft start capacitor to imple- ment. if a short circuit condition occurs (v ffb < 1v), the v ffb low comparator sets the fault latch. this causes the top mosfet to shut off, disconnecting the regulator from it?s input voltage. the soft start capacitor is then slowly dis- charged by a 2a current source until it reaches it?s lower 0.7v threshold. the regulator will then attempt to restart nor- mally, operating in it?s extended off time mode with a 50% duty cycle, while the soft start capacitor is charged with a 60a charge current. if the short circuit condition persists, the regulator output will not achieve the 1v low v ffb comparator threshold before the soft start capacitor is charged to it?s upper 2.5v thresho ld. if this happens the cycle will repeat itself until the short is removed. the soft start charge/discharge current ratio sets the duty cycle for the pulses (2a/60a = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). this protection feature results in less stress to the regulator components, input power supply, and pc board traces than occurs with constant current limit protection (see figures 10 and 11). if the short circuit condition is removed, output voltage will rise above the 1v level, preventing the fault latch from being set, allowing normal operation to resume. figure 10: cs-5155 demonstration board hiccup mode short circuit pro- tection. gate pulses are delivered while the soft start capacitor charges, and cease during discharge. figure 11: startup with regulator output shorted. overvoltage protection overvoltage protection (ovp) is provided as result of the normal operation of the v 2 a control topology and requires no additional external components. the control loop responds to an overvoltage condition within 100ns, causing the top mosfet to shut off, disconnecting the regulator from it?s input voltage. the bottom mosfet is then acti- vated, resulting in a crowbar action to clamp the output voltage and prevent damage to the load (see figures 12 and 13). the regulator will remain in this state until the over- voltage condition ceases or the input voltage is pulled low. trace 4 = 5v from pc power supply (2v/div.) trace 2 = inductor switching node (2v/div.) trace 4 - 5v supply voltage (2v/div.) trace 3 - soft start timing capacitor (1v/div.) trace 2 - inductor switching node (2v/div.) protection and monitoring features trace1 - regulator output voltage (1v/div.) trace 2 - inductor switching node (5v/div.) trace 3 - output current (13 to 0.5 amps) (20v/div.)
applications information: continued cs-5155/5155h 10 the bottom fet and board trace must be properly designed to implement the ovp function. figure 12: ovp response to an input-to-output short circuit by immedi- ately providing 0% duty cycle, crow-barring the input voltage to ground. figure 13: ovp response to an input-to-output short circuit by pulling the input voltage to ground. external output enable circuit on/off control of the regulator can be implemented through the addition of two additional discrete compo- nents (see figure 14). this circuit operates by pulling the soft start pin high, and the v ffb pin low, emulating a short circuit condition. figure 14: implementing shutdown with the cs-5155. external power good circuit an optional power good signal can be generated through the use of four additional external components (see figure 15). the threshold voltage of the power good signal can be adjusted per the following equation: v power good = this circuit provides an open collector output that drives the power good output to ground for regulator voltages less than v power good . figure 15: implementing power good with the cs-5155. v out cs-5155 r1 10k r2 6.2k r3 10k power good 5v pn3904 pn3904 (r1 + r2) 0.65v r2 shutdown input 5v v ffb cs-5155 ss 5 8 in4148 mmun2111t1 (sot-23) trace 4 = 5v from pc power supply (2v/div.) trace 1 = regulator output voltage (1v/div.) trace 4 = 5v from pc power supply (5v/div.) trace1 = regulator output voltage (1v/div.) trace 2 = inductor switching node (5v/div.)
cs-5155/5155h applications information: continued 11 figure 16: cs-5155 demonstration board during power up. power good signal is activated when output voltage reaches 1.70v. selecting external components the cs-5155 can be used with a wide range of external power components to optimize the cost and performance of a particular design. the following information can be used as general guidelines to assist in their selection. nfet power transistors both logic level and standard mosfets can be used. the reference designs derive gate drive from the 12v supply which is generally available in most computer systems and utilize logic level mosfets. a charge pump may be easily implemented to permit use of standard mosfets or sup- port 5v or 12v only systems (maximum of 20v, cs-5155h only). multiple mosfets may be paralleled to reduce loss- es and improve efficiency and thermal management. voltage applied to the mosfet gates depends on the application circuit used. both upper and lower gate driver outputs are specified to drive to within 1.5v of ground when in the low state and to within 2v of their respective bias supplies when in the high state. in practice, the mos- fet gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller ic. for the typical application where v cc1 = v cc2 = 12v and 5v is used as the source for the regulator output current, the fol- lowing gate drive is provided; v gate(h) = 12v - 5v = 7v, v gate(l) = 12v (see figure 17). figure 17: cs-5155 gate drive waveforms depicting rail to rail swing. the most important aspect of mosfet performance is rds on , which effects regulator efficiency and mosfet thermal management requirements. the power dissipated by the mosfets may be estimated as follows; switching mosfet: power = i load 2 rds on duty cycle synchronous mosfet: power = i load 2 rdson (1 - duty cycle) duty cycle = off time capacitor (c off ) the c off timing capacitor sets the regulator off time: t off = c off 4848.5 when the v ffb pin is less than 1v, the current charging the c off capacitor is reduced. the extended off time can be cal- culated as follows: t off = c off 24,242.5. off time will be determined by either the t off time, or the time out timer, whichever is longer. the preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the v out + (i load rds on of synch fet ) v in + (i load rds on of synch fet ) - (i load rds on of switch fet ) trace 3 = v gate(h) (10v/div.) math 1= v gate(h) - 5v in trace 4 = v gate(l) (10v/div.) trace 2 = inductor switching node (5v/div.) trace 3 = 12v input (v cc1 ) and v cc2 ) (10v/div.) trace 4 = 5v input (2v/div.) trace 1 = regulator output voltage (1v/div.) trace 2 = power good signal (2v/div.)
applications information: continued cs-5155/5155h 12 c off timing capacitor: c off = , where: period = schottky diode for synchronous mosfet a schottky diode may be placed in parallel with the syn- chronous mosfet to conduct the inductor current upon turn off of the switching mosfet to improve efficiency. the cs-5155 reference circuit does not use this device due to it?s excellent design. instead, the body diode of the syn- chronous mosfet is utilized to reduce cost and conducts the inductor current. for a design operating at 200khz or so, the low non-overlap time combined with schottky forward recovery time may make the benefits of this device not worth the additional expense (see figure 6, channel 2). the power dissipation in the synchronous mosfet due to body diode conduction can be estimated by the following equation: power = v bd i load conduction time switching frequency where v bd = the forward drop of the mosfet body diode. for the cs-5155 demonstration board as shown in figure 6; power = 1.6v 13a 100ns 233khz = 0.48w this is only 1.3% of the 36.4w being delivered to the load. droop resistor for adaptive voltage positioning adaptive voltage positioning is used to reduce output volt- age excursions during abrupt changes in load current. regulator output voltage is offset +40mv when the regula- tor is unloaded, and -40mv at full load. this results in increased margin before encountering minimum and maxi- mum transient voltage limits, allowing use of less capaci- tance on the regulator output (see figure 7). to implement adaptive voltage positioning, a droop resistor must be connected between the output inductor and output capacitors and load. this is normally imple- mented by a pc board trace of the following value: r droop = adaptive voltage positioning can be disabled for improved dc regulation by connecting the v fb pin directly to the load using a separate, non-load current carrying circuit trace. input and output capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to pro- vide acceptable ripple on the input supply lines and regula- tor output voltage. key specifications for input capacitors are their ripple rating, while esr is important for output capacitors. for best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. output inductor the inductor should be selected based on its inductance, current capability, and dc resistance. increasing the induc- tor value will decrease output voltage ripple, but degrade transient response. thermal considerations for power mosfets and diodes in order to maintain good reliability, the junction tempera- ture of the semiconductor components should be kept to a maximum of 150?c or lower. the thermal impedance (junc- tion to ambient) required to meet this requirement can be calculated as follows: thermal impedance = a heatsink may be added to to-220 components to reduce their thermal impedance. a number of pc board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. emi management as a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. when designing for compliance with emi/emc regulations, additional com- ponents may be added to reduce noise emissions. these components are not required for regulator operation and experimental results may allow them to be eliminated. the input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the cir- cuit board and input power supply. placement of the power component to minimize routing distance will also help to reduce emissions. figure 18: filter components figure 19: input filter layout guidelines 1. place 12v filter capacitor next to the ic and connect capacitor ground to pin 11 (pgnd). 2. connect pin 11 (pgnd) with a separate trace to the ground terminals of the 5v input capacitors. 3. place fast feedback filter capacitor next to pin 8 (v ffb ) and connect it?s ground terminal with a separate, wide trace directly to pin 14 (lgnd). + 2 m h 1200 m f x 3/16v 33 w 1000pf 2 m h t junction(max) - t ambient power thermal management 80mv i max 1 switching frequency period (1 - duty cycle) 4848.5
cs-5155/5155h applications information: continued 13 4. connect the ground terminals of the compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the pwm comparator. 5. place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (lgnd). 6. to implement adaptive voltage positioning, connect both slow and fast feedback pins 16 (v fb ) and 8 (v ffb ) to the regulator output right at the inductor terminal. connect inductor to the output capacitors via a trace with the fol- lowing resistance: r trace = this causes the output voltage to be +40mv with no load, and -40mv with a full load, improving regulator transient response. this trace must be wide enough to carry the full output current. (typical trace is 1.0 inch long, 0.17 inch wide). care should be taken to minimize any additional losses after the feedback connection point to maximize reg- ulation. 7. if dc regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage position- ing can be disabled by connecting to v fb pin directly to the load with a separate trace (remote sense). 8. place 5v input capacitors close to the switching mosfet and synchronous mosfet. route gate drive signals v gate(h) (pin 10) and v gate(l) (pin 12 when used) with traces that are a minimum of 0.025 inches wide. figure 20: layout guidelines 15 to the negative terminal of the input capacitors 100pf v ffb 11 8 off time 5 softstart v cc 0.1 m f to the negative terminal of the output capacitors 1.0 m f v comp 80mv i max figure 21: 5v to 3.3v/10a converter. figure 22: 5v to 3.3v/10a converter with current sharing. figure 23: 12v to 3.3v/5a converter with remote sense. figure 24: 3.3v to 2.5v/7a converter with 12v bias. 0.33 m f v id0 v id1 v id2 v id3 v cc1 cs-5155 c off v fb v ffb comp si9410 si9410 12v + + 5 m h 2.5v/7a v cc2 pgnd 3.3k 0.1 m f 100 m f/10v x 2 tantalum 100pf 330pf 1 m f 33 m f/25v x 3 tantalum 3.3v ss lgnd v gate(h) v gate(l) v id4 0.33 m f v id0 v id1 v id2 v id3 v cc1 ss cs-5155h c off lgnd v fb v ffb comp 12v + + 1.1 m h 3.3v/5a v cc2 v gate(h) v gate(l) pgnd 3.3k 0.1 m f 100pf 330pf 1 m f 0.1 m f v id4 1n4746 18v 1w 1 m f 1n5818 1n5818 22 w 1/4w fy10aaj- 03 820 m f/16v 4 aluminum electrolytic 1200 m f/10v 2 aluminum electrolytic fy10aaj- 03 fy10aaj- 03 +12v 0.33 m f v id0 v id1 v id2 v id3 v cc1 cs-5155 c off v fb v ffb comp si9410 si4410 1 m f 5v + + 3 m h 3.3v/10a v cc2 pgnd 3.3k 0.01 m f 100 m f/10v x 3 tantalum 100pf 330pf 0.1 m f 1 m f mbrs120 mbrs120 100 m f/10v x 3 tantalum 10 w remote sense connect to other circuits for current sharing ss lgnd v gate(h) v gate(l) v id4 mbrs 120 0.33 m f v id0 v id1 v id2 v id3 v cc1 cs-5155 c off v fb v ffb comp si9410dy si4410dy 1 m f 5v + + 3 m h 3.3v/10a v cc2 pgnd 3.3k 0.1 m f 100 m f/10v x 3 tantalum 100pf 330pf 0.1 m f 1 m f mbrs120 mbrs120 100 m f/10v x 3 tantalum ss lgnd v gate(h) v gate(l) v id4 mbrs 120 additional application circuits
14 thermal data 16l 16l so narrow pdip r q jc typ 28 42 ?c/w r q ja typ 115 80 ?c/w d lead count metric english max min max min 16l so narrow 10.00 9.80 .394 .385 16l pdip 19.18 18.92 .755 .745 cs-5155/5155h package specification package dimensions in mm (inches) package thermal data 1.27 (.050) 0.48 (.019) 0.35 (.014) 6.20 (.244) 5.80 (.228) 4.01 (.158) 3.80 (.150) 1.75 (.069) 1.35 (.053) 0.25 (.010) 0.10 (.004) 0.89 (.035) 0.41 (.016) d surface mount narrow body (d); 150 mil wide rev. 11/2/98 ordering information part number description cs-5155d16 16l so narrow cs-5155n16 16l pdip cs-5155dr16 16l so narrow (tape & reel) cs-5155hd16 16l so narrow CS-5155HN16 16l pdip cs-5155hdr16 16l so narrow (tape & reel) 0.41 (.016) 0.51 (.020) 0.38 (.015) min. 2.54 (.100) 1.65 (.065) 1.40 (.055) 6.60 (.260) 6.10 (.240) 4.32 (.170) max d 8.26 (.325) 7.49 (.295) some 8 and 16 lead packages may have 1/2 lead at the end of the package. all specs are the same. plastic dip (n); 300 mil wide ? 1998 cherry semiconductor corporation cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information.

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