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? 1998 mos integrated circuit pd16432b data sheet 1/8, 1/15 duty lcd controller/driver document no. s11092e6v0ds00 (6th edition) date published december 2000 ns cp(k) printed in japan the mark shows major revised points. description the pd16432b is a controller/driver with 1/8 and 1/15 duty dot matrix lcd display capability. it has 60 segment outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12 columns 2 lines (at 1/15 duty). led drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use in a car stereo front panel, etc. features ? dot matrix lcd controller/driver pictograph display segment drive capability (max. 64) lcd driver unit power supply v lcd independently settable (max. 10 v) on-chip key scan circuit (8 4 matrix) alphanumeric character and symbol display capability provided by on-chip rom (5 7 dots) 240 characters + 16 user-defined characters display contents 1/8 duty: 13 columns 1 line, 64 pictograph displays, 4 leds 1/15 duty: 12 columns 2 lines, 60 pictograph displays, 4 leds serial data input/output (sck, stb, data) on-chip oscillator reduced power consumption possible using standby mode ordering information part number package pd16432bgc-001-9eu 100-pin plastic tqfp (fine pitch, 14 14), standard rom code the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet s11092ej6v0ds 2 pd16432b content 1. block diagram ............................................................................................................... .............. 3 2. pin configuration (top view) ................................................................................................ .... 4 3. pin descriptions............................................................................................................ ............... 5 4. pin function ................................................................................................................ ................... 6 4.1 lcd display............................................................................................................... ................................6 4.2 character codes and character patterns ..................................................................................... .............7 4.3 display ram addresses.................................................................................................... ...............8 4.4 pictograph display ram addresses.......................................................................................... ................8 4.5 cgram column addresses ................................................................................................... ..................9 4.6 configuring a key matrix ................................................................................................... .......................10 4.7 construction of key data ram............................................................................................... ..................12 4.8 key input equivalent circuit............................................................................................... .......................12 4.9 key request (key req) ..................................................................................................... ....................13 4.10 led output latch configuration........................................................................................... ...................13 4.11 commands .................................................................................................................. .............................14 4.12 standby mode.............................................................................................................. .............................17 4.13 serial communication formats............................................................................................ .....19 5. electrical specifications ............................................................................................... .... 20 6. access procedures ...................................................................................................... .......... 29 6.1 initialization.............................................................................................................. .................................29 6.2 display data rewrite (address setting) ................................................................................... ..............31 6.3 key data read .............................................................................................................. ...........................32 6.4 cgram write ................................................................................................................ ...........................33 6.5 standby (released by status command) ....................................................................................... .........34 6.6 standby (released by key n )....................................................................................................................35 7. pd16432b application circuits .......................................................................................... 36 7.1 example 1 of pd16432b application circuit ..........................................................................................36 7.2 example 2 of pd16432b application circuit ..........................................................................................37 8. package drawing ......................................................................................................... ............. 38 9. recommended soldering conditions .............................................................................. 39
data sheet s11092e6v0ds 3 pd16432b 1. block diagram led driver led 1 led 4 4 4-bit led output latch 4 4 stb sck data serial i/f reset lcd off sync segment driver 65-bit output latch 65 65 seg 1 /ks 1 seg 8 /ks 8 seg 9 seg 60 seg 61 /com 14 seg 65 /com 10 5 65-bit shift register parallel/serial conversion cg ram 5 7 16 5 cg rom 5 7 240 5 8 display data ram 8 25 8 5 character display ram 64 bits 8 common driver 15-bit shift register 15 com 9 com 0 5 5 timing generator 2 osc in osc osc out key data ram 4 8 key 1 key 4 command decoder key req v dd v ss v lcd v lc1 v lc2 v lc3 v lc4 v lc5
data sheet s11092ej6v0ds 4 pd16432b 2. pin configuration (top view) ? pd16432bgc-001-9eu seg 50 seg 49 seg 48 seg 47 seg 46 seg 45 seg 44 seg 43 seg 42 seg 41 seg 40 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 led 1 led 2 led 3 led 4 v ss v lc5 v lc4 v lc3 v lc2 v lc1 v lcd v dd sync lcd off reset key req sck data stb osc in osc out key 1 key 2 key 3 key 4 seg 25 seg 24 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 /ks 8 seg 7 /ks 7 seg 6 /ks 6 seg 5 /ks 5 seg 4 /ks 4 seg 3 /ks 3 seg 2 /ks 2 seg 1 /ks 1 seg 51 seg 52 seg 53 seg 54 seg 55 seg 56 seg 57 seg 58 seg 59 seg 60 seg 61 /com 14 seg 62 /com 13 seg 63 /com 12 seg 64 /com 11 seg 65 /com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com 1 com 0 75 51 125 26 50 100 76
data sheet s11092e6v0ds 5 pd16432b 3. pin descriptions symbol pin name pin no. i/o function seg 1 /ks 1 to seg 8 /ks 8 segment /key source dual- function 26 to 33 o pins with dual function as dot matrix lcd segment outputs and key scanning key source outputs seg 9 to seg 60 segment 34 to 85 o dot matrix lcd segment outputs seg 61 /com 14 to seg 85 /com 10 segment /common dual- function 86 to 90 o switchable to either dot matrix lcd segment outputs or common outputs com 0 to com 9 common 91 to 100 o dot matrix lcd common outputs led 1 to led 4 led 1 to 4 o led outputs are nch open-drain sck shift clock 17 i data shift clock. data is read on rising edge, and output on falling edge. data data 18 i/o performs input of commands, key data, etc., and key data output. input is performed from the msb on the rise of the shift clock, and the first 8 bits are recognized as a command. output is performed from the msb on the fall of the shift clock. output is nch open-drain. stb strobe 19 i data input is enabled when ? h ? . command processing is performed on a fall. key req key request 16 o ? h ? if there is key data, ? l ? if there is none. key data can be read irrespective of the state of this pin. output is cmos output. reset reset 15 i initial state is set when ? l ? . lcd off lcd off 14 i when ? l ? , a forced lcd off operation is performed, and seg n & com n output the unselected waveform. sync synchronization 13 i/o synchronization signal input/output pin. when 2 or more chips are used, wired-or connection is made to each chip. a pull-up resistor is also required when one chip is used. osc in 20 i osc out oscillation 21 o connect oscillator resistor. when an external oscillator is used, input a clock signal to the osc in pin and leave the osc out pin open, depending on the setting status of the cls pin. key 1 to key 4 key data 22 to 25 i key scanning key data inputs v dd logic power supply 12 ? internal logic power supply pin v ss gnd 5 ? gnd pin v lcd lcd drive voltage 11 ? lcd drive power supply pin v lc1 to v lc5 lcd drive power supply 10 to 6 ? dot matrix lcd drive power supply. connect v lc5 to ground when an internal oscillator is used.
data sheet s11092ej6v0ds 6 pd16432b 4. pin function 4.1 lcd display in the pd16432b lcd display, a 5 7-segment display and pictograph display segments can be driven. the pictograph display segment common output is allocated to com 0 , and up to 64 can be driven. (1) example of 1/8 duty connections 1 64 pictograph segments seg com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 0 2345 61 62 63 64 65 678910 (2) example of 1/15 duty connections 1 seg com 1 com 2 com 3 com 4 com 5 com 6 com 7 2345 56 57 58 59 60 678910 60 pictograph segments com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 0
data sheet s11092e6v0ds 7 pd16432b 4.2 character codes and character patterns the relation between character codes and character patterns is shown below. character codes 00h to 0fh are allocated to cgram. character codes 10h to 1fh and e0h to ffh are undefined. x0hram higher bits 0xh cg (1) 1xh 2xh 3xh 4xh 5xh 6xh 7xh 8xh 9xh axh bxh cxh dxh exh fxh lower bits x1hram cg (2) x2hram cg (3) x3hram cg (4) x4hram cg (5) x5hram cg (6) x6hram cg (7) x7hram cg (8) x8hram cg (9) x9hram cg (10) xahram cg (11) xbhram cg (12) xchram cg (13) xdhram cg (14) xehram cg (15) xfhram cg (16)
data sheet s11092ej6v0ds 8 pd16432b 4.3 display ram addresses display ram addresses are allocated as shown below irrespective of the display mode. column no.12345678910111213 line 1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch line 2 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 4.4 pictograph display ram addresses pictograph display ram addresses are allocated as shown below. segment output no. address b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 9 10111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 remark when 1/15 duty is used (12 columns 2 lines), 61 to 64 are disabled.
data sheet s11092e6v0ds 9 pd16432b 4.5 cgram column addresses a maximum of any sixteen 5 7-dot characters can be written in cgram. the row address within one character is allocated as shown below, and is specified by bits b7 to b5. the character code for which a write is to be performed must be specified beforehand with an address setting command. dot data row address b7 b6 b5 b4 b3 b2 b1 b0 00h 0 0 0 ***** 01h 0 0 1 ***** 02h 0 1 0 ***** 03h 0 1 1 ***** 04h 1 0 0 ***** 05h 1 0 1 ***** 06h 1 1 0 ***** row address font data (5 7 dots) remark * : font data (1: on, 0: off)
data sheet s11092ej6v0ds 10 pd16432b 4.6 configuring a key matrix examples of key matrix configurations are shown below. (1) assumed case when 3 or more keys simultaneously pressed a configuration example is shown below. in this kind of configuration, between 0 and 32 switches in the on state can be identified. key 1 ks 1 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 key 2 key 3 key 4 = (2) assumed case when 2 or fewer keys simultaneously pressed a configuration example is shown below. in this kind of configuration, between 0 and 2 switches in the on state can be identified. key 1 ks 1 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 key 2 key 3 key 4 = diode a
data sheet s11092e6v0ds 11 pd16432b in this example, if 3 or more keys are simultaneously pressed, switches in the off state may be inadvertently judged as being on. take, for example, the case shown below where sw2 to sw4 are on and ks 1 is selected (low level). normally, the i1 current would flow and sw3 would be detected as being in the on state. however, because sw2 and sw4 are on, the i2 current flows, and sw1 is mistakenly identified as being on. key 1 ks 1 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 key 2 key 3 key 4 = i2 i1 sw1 sw2 selected sw3 sw4 also, if diode a is not connected, not only will the key data be unable to be read correctly, but the lcd may also be affected and the ic damaged or its characteristics degraded. take, for example, the case shown below where sw1 and sw2 are on, and ks 1 is selected (low level). in this case, in addition to i1, which is the current that normally flows, the short current between ks 1 and ks 2 (i2) also flows, potentially causing the following three problems. <1> incorrect transmission of the level to key 2 will prevent the key data from being latched properly. <2> because ks 1 and ks 2 have alternate functions as seg outputs, the lcd will not display correctly. <3> the flowing of the short current between ks 2 (high level) and ks 1 (low level) (i2) will damage or degrade the ic. key 1 ks 1 ks 2 ks 3 ks 4 ks 5 ks 6 ks 7 ks 8 key 2 key 3 key 4 = i2 i1 sw1 sw2 selected not selected (high level) (low level)
data sheet s11092ej6v0ds 12 pd16432b 4.7 construction of key data ram key data is stored as shown below, and is read in msb-first order by a read command. b7 b4 b3 ks 7 read order ks 5 key 1 key 2 key 3 key 4 ks 3 ks 1 b0 ks 8 ks 6 ks 4 ks 2 key data is as follows: 1: on 0: off ? ? 4.8 key input equivalent circuit key n v dd r pull-up control signal to key data ram remark in the event of key source output, the pull-up control signal becomes ? h ? , and the pull-up transistor is turned on.
data sheet s11092e6v0ds 13 pd16432b 4.9 key request (key req) a key request is output as shown below according to the state. state key req note key scan internal pull-up resistor in key scan operation high level is output while any key data is ? 1 ? . note during key scan : on during display : off in standby mode or when seg n & com n are fixed at v lc5 high level is output in case of key input only. always on when key scanning is stopped fixed at low level always off note key req does not become low until the key data is all ? 0 ? (it is not synchronized with the key data reads). 4.10 led output latch configuration the low-order 4 bits of the led output latch are enabled, and the high-order 4 bits disabled, as shown below. b3 b2 b1 b0 lsb msb : don ? t care led 1 led 2 led 3 led 4 latch data is as follows: 1: on 0: off ? ?
data sheet s11092ej6v0ds 14 pd16432b 4.11 commands commands set the display mode and status. the first byte after a rise edge on the stb pin is regarded as a command. if stb is driven low during command/data transfer, serial communication is initialized and the command/data being transferred is invalidated (however, a command or data that has already been transferred is valid). (1) display setting command this command initializes the pd16432b, and sets the duty, number of segments, number of commons, master/ slave operation, and the drive voltage supply method. w hen multiple chips are used, only the chip that sent the command is enabled. if initialization is performed during display, the display may be affected (especially when multiple chips are used). the state set when this command is executed is: lcd off, led on, key scanning stopped. to restart the display, it is necessary to execute ? status command ? normal operation. however, nothing is done if the same mode is selected. b2 b1 b0 0 0 lsb msb : don ? t care duty setting 0: 1/8 duty (seg 61 /com 14 to seg 65 /com 10 segment outputs) 1: 1/15 duty (seg 61 /com 14 to seg 65 /com 10 common outputs) master/slave setting 0: master 1: slave drive voltage supply method selection 0: external 1: internal 000 after powering on note note please set only one pd16432b to master, and the other to slave when in multi-chip mode. and please set to master, when in single chip mode.
data sheet s11092e6v0ds 15 pd16432b (2) data setting command sets the data write mode, read mode, and address increment mode. b3 b2 b1 b0 1 0 lsb msb : don ? t care data write mode/read mode setting 000: write to display data ram 001: write to character display ram 010: write to cgram 011: write to led output latch 100: read key data address increment mode setting (display data ram, character display ram) 0: increment after data write 1: address fixed 0000 after powering on (3) address setting command sets the display data ram or character display ram address. b3 b2 b1 b0 b4 0 1 lsb msb : don ? t care address display data ram character display ram cgram 0000 0 after powering on : 00h to 18h : 00h to 07h : 00h to 0fh caution if an unspecified address is set, data cannot be written until a correct address is next set. the address is not incremented even in increment mode.
data sheet s11092ej6v0ds 16 pd16432b (4) status command controls the status of the pd16432. b3 b2 b1 b0 b4 b5 1 1 lsb msb lcd cotrol 00: lcd forced off (segn, comn = v lc5 ) 01: lcd forced off (segn, comn = unselected waveform) 10: normal operation 11: normal operation led control 0: led forced off 1: normal operation key scan control 0: key scanning stopped 1: key scan operation test mode setting 0: normal operation 1: test mode standby mode setting 0: normal operation 1: standby mode ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note1 0000 0 0 after powering on note2 notes 1. the following states are use prohibited modes, and key scanning does not operate if these states are set. 1000 0 0 1100 0 0 2. the key data input operation is stopped. the key source signals from segn pin are output even in this state.
data sheet s11092e6v0ds 17 pd16432b 4.12 standby mode if standby mode is selected with bit b4 of the status command, the following state is set irrespective of bits b3 to b0 of the status command. (1) lcd forced off (seg n , com n = v lc5 ) (2) led forced off (3) key scanning stopped (but key n = key input wait) (4) osc stopped there are two ways of releasing standby mode, as follows: (a)using status command (b)using key n (a) using status command select normal operation with bit b4 of the status command. table 4-1 example of use of status command command/data item stb b7 b6 b5 b4 b3 b2 b1 b0 description standby mode l status command h 1 1 0 0 0 0 0 0 standby release (osc oscillation start), lcd control off (seg n , com n = v lc5 ), led forced off, key scanning stopped standby transition time l 10 s note status command h 1 1 0 0 1 1 1 0 normal operation end l note if lcd normal operation or key scan operation is initiated within the standby transition time, the lcd may flicker.
data sheet s11092ej6v0ds 18 pd16432b (b) using key n if any key is set to the on state, the standby mode is released and osc oscillation starts. also, key req is set to ? h ? , informing the microcomputer that a key has been pressed and standby mode has been released. in this state, the key data is not memorized, and therefore it is necessary to set key scanning to the normal state after the standby transition time, and fetch the key data. table 4-2 example of use of key n command/data item stb b7 b6 b5 b4 b3 b2 b1 b0 description standby mode l key data present l standby release (key req = h, osc oscillation start) standby transition time l 10 s note status command h 1 1 0 0 1 0 0 1 lcd forced off (unselected waveform), led forced off, key scan operation key scan l 1 frame or more data setting command h 0 1 0 0 0 1 0 0 key data read, address increment key data h ******** for ks 8 , ks 7 key data h ******** for ks 6 , ks 5 key data h ******** for ks 4 , ks 3 key data h ******** for ks 2 , ks 1 end l key distinction note if lcd normal operation or key scan operation is initiated within the standby transition time, the lcd may flicker. remark * : key data (1:on, 0 : off)
data sheet s11092e6v0ds 19 pd16432b 4.13 serial communication formats (1) reception (command/data write) sck 123 678 data b7 stb b6 b5 b1 b0 b2 if data continues (2) transmission (command/data read) sck data stb 1 2 3 6 7 8 1 2 3 4 5 6 b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 1 s wait time t wait data read data read command setting caution as the data pin is an nch open-drain output, a pull-up resistor must be connected externally (1 k ? ? ? ? to 10 k ? ? ? ? ).
data sheet s11092ej6v0ds 20 pd16432b 5. electrical specifications absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol rating unit logic supply voltage v dd ?0.3 to +7.0 v logic input voltage v in ?0.3 to +v dd + 0.3 v logic output voltage (d out , ledn) v out ?0.3 to +7.0 v lcd drive supply voltage v lcd ?0.3 to +12.0 v lcd drive power supply input voltage v lc1 to v lc5 ?0.3 to +v lcd + 0.3 v driver output voltage (segment, common) v out2 ?0.3 to +v lcd + 0.3 v led drive current i ol1 20 ma package allowable dissipation p t 1000 mw operating ambient temperature t a ?40 to +85 c storage temperature range t stg ?55 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating ranges parameter symbol conditions min. typ. max. unit logic supply voltage v dd 2.7 5.0 5.5 v lcd drive supply voltage v lcd v dd 8.0 10.0 v logic input voltage v in 0v dd v driver input voltage v lcd1 to v lcd5 0v lcd v led drive current i ol1 15 ma
data sheet s11092ej6v0ds 21 pd16432b electrical characteristics (unless specified otherwise, t a = ?40 to +85c, v dd = 5 v 10%, v lcd = 8 v 10%) parameter symbol conditions min. typ. max. unit high-level input voltage v ih 0.7 v dd v dd v low-level input voltage v il 0 0.3 v dd v high-level input current i ih sck, stb, lcdoff, reset, key 1 to key 4 1 a low-level input current i il sck, stb, lcd off, reset, key 1 to key 4 ?1 a low-level output voltage v ol1 led 1 to led 4 , i ol1 = 15 ma 1.0 v high-level output voltage v oh2 osc out , key req, i oh2 = ?1 ma 0.9 v dd v low-level output voltage v ol2 data, osc out , sync, i ol2 = 4 ma 0.1 v dd v high-level leak current i loh2 data, sync, v in/out = v dd 1 a low-level leak current i lol2 data, sync, v in/out = v ss ?1 a common output on- resistance r com v lcd to v lc5 com 0 to com 14 , | i o | = 100 a 2.4 k ? segment output on- resistance r seg v lcd to v lc5 seg 1 to seg 60 , | i o | = 100 a 4.0 k ? i dd1 normal operation note , v i = v dd or v ss , f osc = 250 khz 500 a current consumption (logic) i dd2 standby mode, v i = v dd or v ss , f osc stopped 5 a i lcd1 normal operation, internal bias selected, no load 1000 a current consumption (driver) i lcd2 standby mode, internal bias used, no load 5 a note normal operation: v dd = 5 v, v lcd = 8 v
data sheet s11092ej6v0ds 22 pd16432b switching characreristics (unless specified otherwise, t a = ?40 to +85c, v dd = v lcd = 5 v 10%, r l = 5 k ? ? ? ? , c l = 150 pf) parameter symbol conditions min. typ. max. unit oscillator frequency f osc r = 100 k ? 175 250 325 khz output data delay time t pzl sck data 100 ns output data delay time t plz sck data 300 ns sync delay time t dsync 1.5 s remarks 1. the time for one frame is found as follows. 1 frame = 1/f osc 128 clocks duty number + 1/f osc 64 clocks if f osc = 250 khz and duty = 1/15, 1 frame = 4 s 128 15 + 4 s 64 = 7.94 ms 2. typ. values are reference values for t a = 25c. required timing conditions (unless specified otherwise, t a = ?40 to +85c, v dd = 5 v 10%, v lcd = 8 v 10%, r l = 5 k ? ? ? ? , c l = 150 pf) parameter symbol conditions min. typ. max. unit clock frequency f osc osc in external clock 100 500 khz high-level clock pulse width t whc osc in external clock 1 5 s low-level clock pulse width t wlc osc in external clock 1 5 s shift-clock cycle t cyk sck 900 ns high-level shift clock pulse width t whk sck 400 ns low-level shift clock pulse width t wlk sck 400 ns shift clock hold time t hstbk stb sck 1.5 s data setup time t ds data sck 100 ns data hold time t dh sck data 200 ns stb hold time t hkstb sck stb 1 s stb hold time t wstb 1 s wait time t wait 8th sck 9th sck , in data read 1 s sync removal time t srem 250 ns standby transition time t pstb 10 s reset pulse width t wrs reset 0.1 s power-on reset time t pon from power-on 4 clk output load circuit v dd 5 k ?
data sheet s11092ej6v0ds 23 pd16432b switching specifications waveform diagrams (1/2) osc in v il v ih 1/f c t whc t wlc v ih v ih v il t hstbk t wstb t cyk t wlk t wlk v il v ih v il v ih t ds t dh t hkstb stb sck data
data sheet s11092ej6v0ds 24 pd16432b switching specification waveform diagrams (2/2) f osc sync internal reset one frame one frame sync timing (master) t dsync one frame one frame sync timing (slave) t srem t pzl v il v ol2 t plz sck data reset reset t wre
data sheet s11092ej6v0ds 25 pd16432b output waveforms (1) 1/8 duty (1/4 bias: v lc2 : v lc3 ) v lcd v lc1 v lc2 v lc4 v lc5 com 0 0 1 2 3 4 5 6 7 k 0 1 * v lcd v lc1 v lc2 v lc4 v lc5 com 1 v lcd v lc1 v lc2 v lc4 v lc5 com 7 v lcd v lc1 v lc2 v lc4 v lc5 seg 2 v lcd v lc1 v lc2 v lc4 v lc5 seg 1 v lcd 3/4v lcd 2/4v lcd ? 1/4v lcd ? 2/4v lcd seg 1 ? ? 3/4v lcd 1/4v lcd 0 ? v lcd v lcd 3/4v lcd 2/4v lcd ? 1/4v lcd ? 2/4v lcd seg 1 ? ? 3/4v lcd 1/4v lcd 0 ? v lcd 256 s 512 s
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data sheet s11092ej6v0ds 27 ? 1/5v lcd ? 1/2v lcd seg 1 ? ? 3/5v lcd 1/5v lcd 0 ? v lcd 512 s
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data sheet s11092ej6v0ds 29 ?
data sheet s11092ej6v0ds 30 ?
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data sheet s11092ej6v0ds 32 ? 0 ? . (it is not synchronized with the key data reads.)
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data sheet s11092ej6v0ds 36 ? ? ?
data sheet s11092ej6v0ds 37 ? ? ?
data sheet s11092ej6v0ds 38 + ? + ? + ?
data sheet s11092ej6v0ds 39 pd16432b should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual(c10535e). for soldering methods and conditions other than those recommended below, contact your nec sales representative. pd16432bgc-001-9eu : 100-pin plastic tqfp (14 c, time : 30 sec. max. (at 210 or higher), count : 3 times or less. exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-3 vps package peak temperature : 235 c, time : 40 sec. max. (at 210 or higher), count : 3 times or less. exposure limit: 7 days note (after that, prebake at 125 c for 10 hours). vp15-107-3 partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) ? ? ? ? c ro less and 65% rh or less for the allowable storeage period. caution do not use different soldering methods together (except the partial heating).
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