View MT4LSDT864HG-10EF2_6719085.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev. 8/02 1 ?2002, micron technology inc. 32mb / 64mb / 128mb (x64) 144-pin sdram sodimms small-outline sdram module mt4lsdt464(l)h(i) - 32mb mt4lsdt864(l)h(i) - 64mb mt4lsdt1664(l)h(i) - 128mb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? jedec-standard pc100 and pc133 compliant 144-pin, small-outline, dual in-line memory module (sodimm) unbuffered 32mb (4meg x 64), 64mb (8 meg x 64), and 128mb (16 meg x 64) single +3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal sdram banks for hiding row access/precharge programmable burst length s: 1, 2, 4, 8, or full page auto precharge and auto refresh modes self refresh mode: standard and low power 32mb and 64mb: 64ms, 4,096-cycle refresh (15.625s refresh interval); 128mb: 64ms, 8,192- cycle refresh (7.81s refresh interval) lvttl-compatible inputs and outputs serial presence-detect (spd) options marking self refresh current standard none low-power 1 l operating temperature range commercial (0 c to + 70 c ) industrial (-40 c to +85 c) 2 none i package 144-pin sodimm (gold) g memory clock/cas latency 7.5ns (133 mhz)/cl = 2 -13e 7.5ns (133 mhz)/cl = 3 -133 10ns (100 mhz)/cl = 2 -10e note: 1. low power and industrial temperature options not avail- able concurrently. consult micron for available option combinations. 2. consult micron for availability; industrial temperature option available in -133 speed only. address table 32mb module 64mb module 128mb module refresh count 4k 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device conf. 4 meg x16 8 meg x 16 16 meg x 16 row addr. 4k (a0?a11) 4k (a0?a11) 8k (a0?a12) column addr. 256 (a0?a7) 512 (a0?a8) 512 (a0?a8) modulebanks 1(s0) 1(s0) 1(s0) timing parameters module markings pc100 cl - t rcd - t rp pc133 cl - t rcd - t rp -13e 2 - 2 - 2 2 - 2 - 2 -133 2 - 2 - 2 3 - 3 - 3 -10e 2 - 2 - 2 na 144-pin sodimm (mo 190)
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 2 ?2002, micron technology inc. note: 1. pin 70 is no connect for 32mb and 64m b modules, or a12 for 128mb modules. pin locations (144-pin sodimm) part numbers part number 1 configura- tion system bus speed part number 1 configura- tion system bus speed mt4lsdt464(l)h(i)g-13e_ 4 meg x 64 133 mhz mt4lsdt864(l)hg-10e_ 8 meg x 64 100 mhz mt4lsdt464(l)h(i)g-133_ 4 meg x 64 133 mhz mt4lsdt1664(l)h(i)g-13e_ 16 meg x 64 133 mhz mt4lsdt464(l)hg-10e_ 4 meg x 64 100 mhz mt4lsdt1664(l)h(i)g-133_ 16 meg x 64 133 mhz mt4lsdt864(l)h(i)g-13e_ 8 meg x 64 133 mhz mt4lsdt1664(l)hg-10e_ 16 meg x 64 100 mhz mt4lsdt864(l)h(i)g-133_ 8 meg x 64 133 mhz note: 1. the designators for component and pcb revision are the last two characters of each part number. consult factory for current r evi- sion codes. example: mt4lsdt1664hg-133b1 pin assignment (144-pin sodimm front) pin symb ol pin symb ol pin symb ol pin symb ol 1v ss 37 dq8 73 nc 109 a9 3dq039dq975v ss 111 a10 5 dq1 41 dq10 77 dnu 113 v dd 7 dq2 43 dq11 79 dnu 115 dqmb2 9dq345v dd 81 v dd 117 dqmb3 11 v dd 47 dq12 83 dq16 119 vss 13 dq4 49 dq13 85 dq17 121 dq24 15 dq5 51 dq14 87 dq18 123 dq25 17 dq6 53 dq15 89 dq19 125 dq26 19 dq7 55 v ss 91 v ss 127 dq27 21 vss 57 dnu 93 dq20 129 v dd 23 dqmb0 59 dnu 95 dq21 131 dq28 25 dqmb1 61 ck0 97 dq22 133 dq29 27 v dd 63 v dd 99 dq23 135 dq30 29 a0 65 ras# 101 v dd 137 dq31 31 a1 67 we# 103 a6 139 v ss 33 a2 69 s0# 105 a8 141 sda 35 v ss 71 dnu 107 vss 143 v dd pin assignment (144-pin sodimm back) pin symbo l pin symbo l pin symbo l pin symbo l 2v ss 38 dq40 74 dnu 110 ba1 4 dq32 40 dq41 76 v ss 112 a11 6 dq33 42 dq42 78 dnu 114 v dd 8 dq34 44 dq43 80 dnu 116 dqmb6 10 dq35 46 v dd 82 v dd 118 d qmb7 12 v dd 48 dq44 84 dq48 120 v ss 14 dq36 50 dq45 86 dq49 122 dq56 16 dq37 52 dq46 88 dq50 124 dq57 18 dq38 54 dq47 90 dq51 126 dq58 20 dq39 56 v ss 92 v ss 128 dq59 22 v ss 58 dnu 94 dq52 130 v dd 24 dqmb4 60 dnu 96 dq53 132 dq60 26 dqmb5 62 cke0 98 dq54 134 dq61 28 v dd 64 v dd 100 dq55 136 dq62 30 a3 66 cas# 102 v dd 138 dq63 32 a4 68 dnu 104 a7 140 v ss 34 a5 70 nc/ a12 1 106 ba0 142 scl 36 v ss 72 nc 108 v ss 144 v dd u3 u4 (all even pins) pin 144 pin 2 back view u1 u2 u5 pin 1 pin 143 (all odd pins) front view
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 3 ?2002, micron technology inc. pin descriptions pin numbers may not correlate with symbols. refer to the pin assignment table for pin number and symbol information. pin numbers symbol type description 65, 66, 67 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 61 ck0 input clock: ck is driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 62 cke0 input clock enable: cke activates (high) and deactivates (low) the ck signal. deactivating the clock provides precharge power-down and self refresh operation (all device banks idle), active power-down (row active in any device bank) or clock suspend operation (burst access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including ck, are disabled during power-down and self refresh modes, providing low standby power. 69 s0# input chip select: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 23, 24, 25, 26, 115, 116, 117, 118 dqmb0-dqmb7 input input/output mask: dqmb is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two- clock latency) when dqmb is sampled high during a read cycle. 106, 110 ba0, ba1 input bank address: ba0 and ba1 define to which device bank the active, read, write, or precharge command is being applied. 29, 30, 31,32, 33, 34, 70 (128mb) , 103, 104, 105, 109, 111, 112 a0-a11 (32mb, 64mb) a0-a12 (128mb) input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. 142 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 141 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18, 19, 20, 37, 38, 39, 40, 41, 43, 44, 47, 48, 49, 50, 51, 52, 53, 54, 83, 84, 85, 86, 87, 88, 89, 90, 93, 94, 95, 96, 97, 98, 99, 100, 121, 122, 123, 124, 125, 126, 127, 128, 131, 132, 133, 134, 135, 136, 137, 138 dq0-dq63 input/ output data i/o: data bus. 11, 12, 27, 28, 45, 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 v dd supply power supply: +3.3v 0.3v.
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 4 ?2002, micron technology inc. 1, 2, 21, 22, 35, 36, 55, 56, 75, 76, 91, 92, 107, 108, 119, 120, 139, 140 v ss supply ground. 70 (32mb, 64mb), 72, 73 nc ? not connected: these pins should be left unconnected. 57, 58, 59, 60, 68, 71, 74, 77, 78, 79, 80 dnu ? do not use: these pins are not connected on these modules, but are assigned pins on other modules in this product family. pin descriptions pin numbers may not correlate with symbols. refer to the pin assignment table for pin number and symbol information. pin numbers symbol type description
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 5 ?2002, micron technology inc. functional block diagram a0 spd u5 scl sda a1 a2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 we# cas#: sdrams cke0: sdrams we#: sdrams a0-a11: sdrams a0-a12: sdrams ba0-ba1: sdrams a0-a11 (32mb, 64mb) a0-a12 (128mb) ba0-ba1 v dd v ss sdrams sdrams u1, u2, u3, u4 dq dq dq dq dq dq dq dq dqml so# dqmb1 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmh u3 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dq dq dq dq dq dq dq dq dqml so# dqmb5 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u2 dq dq dq dq dq dq dq dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dq dq dq dq dq dq dq dq dqml so# dqmb3 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmh u4 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dq dq dq dq dq dq dq dq dqml so# dqmb7 ck0 ras#: sdrams 10 pf ck1 wp sdrams = mt48lc4m16a2tg for 32mb module, comm. temp. sdrams = mt48lc8m16a2tg for 64mb module, comm. temp. sdrams = mt48lc16m16a2tg for 128mb module, comm. temp. sdrams = mt48lc4m16a2tg it for 32mb module, indust. temp. sdrams = mt48lc8m16a2tg it for 64mb module, indust. temp. sdrams = mt48lc16m16a2tg it for 128mb module, indust. temp. industrial temperature modules use -75-speed components only. notes: all resistor values are 10 ? unless otherwise specified. per industry standard, micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/numberguide .
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 6 ?2002, micron technology inc. general description the mt4lsdt464h, mt4lsdt864h, and mt4lsdt1664h are high-speed cmos, dynamic ran- dom-access 32mb, 64mb, and 128mb unbuffered memory modules, organized in x64 configurations. these modules use internally configured quad- bank sdrams with a synchronous interface (all signals are registered on the positive edge of the clock signal ck). the four banks of a x16, 64mb device (for the 32mb modules) are each configured as 4,096 bit-rows, by 256 bit-columns, by 16 input/output bits. the four banks of a x16, 128mb device (for the 64mb modules) are configured as 4,096 bit-rows, by 512 bit columns, by 16 input/output bits . the four banks of a x16, 256mb device (for the 128mb modules) are configured as 8,192 bit-rows, by 512 bit columns, by 16 input/out- put bits . read and write accesses to the sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select the device bank, a0-a11 [32mb and 64mb], or a0-a12 [128mb] select the device row). the address bits a0?a7 (32mb), or a0-a8 (64mb and 128mb), registered coincident with the read or write command, are used to select the starting device column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. these modules use an internal pipelined architec- ture to achieve high-speed operation. this architec- ture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram oper- ation, refer to the 64mb, 128mb, or 256mb sdram component data sheets. serial presence detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes are pro- grammed by micron to identify the module type, sdram characteristics and module timing parame- ters. the remaining 128 bytes of storage are available for use by the customer. system read/write opera- tions between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses. register definition prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device opera- tion. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to v dd and v dd q (simul- taneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 7 ?2002, micron technology inc. programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode, and a write burst mode, as shown in the mode register definition dia- gram. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. for the 128mb module, m12 (a12) is undefined, but should be driven low during loading of the mode register. the mode register must be loaded when all device banks are idle, and the controller must wait the speci- fied time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. mode register definition diagram reserved* reserved* m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 2 3 reserved reserved reserved reserved m6 0 0 0 1 1 1 1 m4 0 0 1 0 1 0 1 m5 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 a11 10 11 12 wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. a12 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 op mode a10 a11 10 11 reserved* wb *should program m11, m10 = ?0, 0? to ensure compatibility with future devices. 32mb and 64mb module 128mb module
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 8 ?2002, micron technology inc. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in mode register definition diagram. the burst length determines the maximum number of col- umn locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 loca- tions are available for both the sequential and the interleaved burst types, and a full-page burst is avail- able for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the burst definition table. the block is uniquely selected by a1? a i (where i is the most significant column address bit for a given device configuration) when the burst length is set to two; by a2?a i when the burst length is set to four; and by a3?a i when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in the burst definition table. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in the burst definition ta b l e. burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2a0 00-1 0-1 11-0 1-0 4a 1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2a 1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = i* (location 0- y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported * i = 7 for 32mb modules i = 8 for 64mb and 128mb modules note: 1. for full-page accesses: y = 256 (32mb), y= 512 (64mb and 128mb) 2. for a burst length of two, a1-a i select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-a i select the block-of-four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a i select the block-of- eight burst; a0-a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-a i select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a i select the unique col- umn to be accessed, and mode register bit m3 is ignored.
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 9 ?2002, micron technology inc. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in the cas latency dia- gram. the cas latency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used, because un- known operation or incompatibility with future ver- sions may result. cas latency diagram operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used, because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (non- burst) accesses. clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop cas latency table allowable operating clock frequency (mhz) speed cas latency = 2 cas latency = 3 -13e 133 143 -133 100 133 -10e 100 na
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 10 ?2002, micron technology inc. commands the truth table provides a quick reference of avail- able commands. this is followed by written descrip- tion of each command. for a more detailed des- cription of commands and operations, refer to the 64mb, 128mb, or 256mb sdram component data sheet. truth table ? sdram commands and dqmb operation 1 note: 1. cke is high for all commands shown except self refresh. name (function) cs# ras# cas# we# dqmb addr dq notes command inhibit (nop) hx xx x x x no operation (nop) lhhh x x x active (select bank and activate row) llhhx bank/ row x 2 2. a0-a11 (32mb and 64mb) , or a0-a12 (128mb) provide device row address, and ba0, ba1 determine which device bank is made active. read (select bank and column, and start read burst) lh lh l/h 8 bank/col x 3 3. a0-a7 (32mb) or a0-a8 (64mb and 128mb) provide device column address; a10 high enables the auto precharge feature (nonper- sistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which device bank is being read from or written to. write (select bank and column, and start write burst) lh ll l/h 8 bank/col valid 3 burst terminate lhhl x x active precharge (deactivate row in bank or banks) l l h l x code x 4 4. a10 low: ba0, ba1 determine which device bank is being precharged. a10 high: all device banks are precharged and ba0, ba1 are ?don?t care.? auto refresh or self refresh (enter self refresh mode) ll lhx x x 5, 6 5. this command is auto refresh if cke is high, self refresh if cke is low. 6. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. load mode register l l l l x op-code x 7 7. a0-a11 define the op-code written to the mode register, and for the 128mb module, a12 should be driven low. write enable/output enable ?? ?? l ? active 8 8. activates or deactivates the dq s during writes (zero-clock delay) and reads (two-clock delay). write inhibit/output high-z ?? ?? h ? high-z 8
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 11 ?2002, micron technology inc. absolute maximum ratings* voltage on v dd , v dd q supply relative to v ss . . . . . . . . . . . . . . . . . . . . . -1v to +4.6v voltage on inputs nc or i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v operating temperature t a (ambient). . . . . . . . . . . . . . . . . . . . .. 0c to +70c t a (industrial temperature) . . . . .. -40c to +85c storage temperature (plastic) . . . . . .-55c to +150c power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4w short circuit output current . . . . . . . . . . . . . . . .50ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions notes: 2, 6, 7; notes appear following parameter tables; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v23 input low voltage: logic 0; all inputs v il -0.3 0.8 v 23 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) command and address inputs i i -20 20 a 33 ck, s# -20 20 a dq, dqmb -5 5 a output leakage current: dq pins are disabled; 0v v out v dd q dq i oz -5 5 a 33 output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4 v i dd specifications and conditions ? 32mb module notes: 1, 2, 6, 7, 12, 14; notes appear following parameter tables; v dd , v dd q = +3.3v 0.3v max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 500 460 380 ma 4, 19, 20, 31 standby current: power-down mode; all device device banks idle; cke = low i dd 2 888ma 31 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 180 180 140 ma 4, 13, 20, 31 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 600 560 480 ma 4, 19, 20, 31 auto refresh current t rfc = t rfc (min) i dd 5 920 840 760 ma 4, 13, 19, 20, 31,32 cke = high; s# = high t rfc = 15.625s i dd 6 12 12 12 ma self refresh current: cke 0.2v (low power not available with industrial temperature option) standard i dd 7 444ma 4 low power i dd 7 222ma
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 12 ?2002, micron technology inc. i dd specifications and conditions ? 64mb module notes: 1, 2, 6, 7, 12, 14; notes appear following parameter tables; v dd , v dd q = +3.3v 0.3v max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 640 600 560 ma 4, 19, 20, 31 standby current: power-down mode; all device device banks idle; cke = low i dd 2 8 88ma 31 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 200 200 160 ma 4, 13, 20, 31 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 660 600 560 ma 4, 19, 20, 31 auto refresh current t rfc = t rfc (min) i dd 5 1,320 1,240 1,080 ma 4, 13, 19, 20, 31, 32 cke = high; s# = high t rfc = 15.625s i dd 6 12 12 12 ma self refresh current: cke 0.2v (low power not available with industrial temperature option) standard i dd 7 8 88ma 4 low power i dd 7 4 44ma i dd specifications and conditions ? 128mb module notes: 1, 2, 6, 7, 12, 14; notes appear following parameter tables; v dd , v dd q = +3.3v 0.3v max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 540 500 500 ma 4, 19, 20, 31 standby current: power-down mode; all device device banks idle; cke = low i dd 2 888ma 31 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 160 160 160 ma 4, 13, 20, 31 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 540 540 540 ma 4, 19, 20, 31 auto refresh current t rfc = t rfc (min) i dd 5 1,140 1,080 1,080 ma 4, 13, 19, 20, 31, 32 cke = high; s# = high t rfc = 7.8125s i dd 6 14 14 14 ma self refresh current: cke 0.2v (low power not available with industrial temperature option) standard i dd 7 10 10 10 ma 4 low power i dd 7 666ma
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 13 ?2002, micron technology inc. capacitance notes: 1, 2; notes appear following parameter tables. parameter symbol min max units input capacitance: a0-a12 , ba0, ba1, ras#, cas#, we#, s0#, cke0, dqmb0-dqmb7 c i1 10 15.2 pf input capacitance: ck0 ci2 10 14 pf input/output capacitance: scl, sa0-sa2, sda c i6 ?10pf input/output capacitance: dq0-dq63 c io 46pf electrical characteristics and recommended ac operating conditions notes: 1, 6, 7, 9, 10, 12; notes appear following parameter tables. module ac timing parameters comply with pc100 and pc133 design specs, based on component parameters. ac characteristics symbol -13e -133 -10e units notes parameter min max min max min max access time from clk (positive edge) cl = 3 t ac(3) 5.4 5.4 6 ns 27 cl = 2 t ac(2) 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high-level width t ch 2.5 2.5 3 ns clk low-level width t cl 2.5 2.5 3 ns clock cycle time cl = 3 t ck(3) 77.58 ns24 cl = 2 t ck(2) 7.5 10 10 ns 24 cke hold time t ckh 0.8 0.8 1 ns cke setup time t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-impedance time cl = 3 t hz(3) 5.4 5.4 6 ns 11 cl = 2 t hz(2) 5.4 6 7 ns 11 data-out low-impedance time t lz 111 ns data-out hold time (load) t oh 333 ns data-out hold time (no load) t ohn 1.8 1.8 1.8 ns 29 active to precharge command t ras 37 120,000 44 120,000 50 120,000 ns 30 active to active command period t rc 60 66 70 ns active to read or write delay t rcd 15 20 20 ns refresh period t ref 64 64 64 ms auto refresh period t rfc 66 66 70 ns precharge command period t rp 15 20 20 ns active bank a to active bank b command t rrd 14 15 20 ns transition time t t 0.31.20.31.20.31.2 ns 8 write recovery time t wr 1 clk + 7ns 1 clk + 7.5ns 1 clk + 7ns ns 25 14 15 15 ns 26 exit self refresh to active command t xsr 67 75 80 ns 21
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 14 ?2002, micron technology inc. ac functional characteristics notes: 6, 7, 8, 9, 10, 12; notes appear following parameter tables. parameter symbol -13e -133 -10e units notes read/write command to read/write command t ccd 11 1 t ck 18 cke to clock disable or power-down entry mode t cked 11 1 t ck 15 cke to clock enable or power-down exit setup mode t ped 11 1 t ck 15 dqm to input data delay t dqd 00 0 t ck 18 dqm to data mask during writes t dqm 00 0 t ck 18 dqm to data high-impedance during reads t dqz 22 2 t ck 18 write command to input data delay t dwd 00 0 t ck 18 data-in to active command t dal 45 4 t ck 16, 22 data-in to precharge command t dpl 22 2 t ck 17, 22 last data-in to burst stop command t bdl 11 1 t ck 18 last data-in to new read/write command t cdl 11 1 t ck 18 last data-in to precharge command t rdl 22 2 t ck 17, 22 load mode register command to active or refresh command t mrd 22 2 t ck 27 data-out to high-impedance from precharge command cl=3 t roh(3) 33 3 t ck 18 cl = 2 t roh(2) 22 2 t ck 18
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 15 ?2002, micron technology inc. notes 1. module ac timing parameters comply with pc100 and pc133 design specs, based on component parameters. 2. all voltages referenced to v ss . 3. this parameter is sampled. v dd , v dd q = +3.3v; f= 1 mhz; t a = 25c; pin under test biased at 1.4v. 4. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 5. enables on-chip refresh and address counters. 6. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (com- mercial temperature: 0c t a +70c and indus- trial temperature: -40c t a +85c). 7. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at the same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 8. ac characteristics assume t t = 1ns. 9. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 10. outputs measured at 1.5v with equivalent load: 11. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 12. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the 1.5v crossover point. 13. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 14. idd specifications are tested after the device is properly initialized. 15. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 16. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 17. timing actually specified by t wr. 18. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 19. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 20. address transitions average one transition every two clocks. 21. clk must be toggled a minimum of two times during this period. 22. based on t ck = 10ns for -10e, and t ck = 7.5ns for -133 and -13e. 23. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns. 24. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 25. auto precharge mode only. the precharge timing budget ( t rp) begins 7ns for -13e; 7.5ns for -133 and 7ns for -10e after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 26. precharge mode only. 27. jedec and pc100 specify three clocks. 28. t ac for -133/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 29. parameter guaranteed by design. 30. the value of t ras used in -13e speed grade mod- ule spds is calculated from t rc - t rp = 45ns. 31. for -10e, cl= 2 and t ck = 10ns; for -133, cl = 3 and t ck = 7.5ns; for -13e, cl = 2 and t ck = 7.5ns. 32. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 33. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. q 50pf
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 16 ?2002, micron technology inc. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 1 data validity figure 2 definition of start and stop figure 3 acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 17 ?2002, micron technology inc. eeprom device select code note: the most significant bit (b7) is sent first . device type identifier chip enable rw b7 b6 b5 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 10100e2e1e0rw protection register select code 0 1 1 0 e2 e1 e0 rw eeprom operating modes mode rw bit w c bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = 1 random address read 0v ih or v il 1 start, device select, rw = 0, address 1v ih or v il 1 restart, device select, rw = 1 sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = 0 page write 0v il 16 start, device select, rw = 0 serial presence-detect eeprom dc operating conditions notes: 1, 2; notes appear following eeprom ac and dc operating conditions tables. parameter/condition symbol min max units supply voltage v dd 33.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ?0.4 v input leakage current: v in = gnd to v dd i li ?10 a output leakage current: v out = gnd to v dd i lo ?10 a standby current: scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v 10% i sb ?30 a power supply current: i cc ?2 ma scl clock frequency = 100 khz
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 18 ?2002, micron technology inc. spd eeprom timing diagram note: 1. v dd = +3.3v 0.3v 2. all voltages referenced to v ss . 3. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pul l- up resistor, and the eeprom does not respond to its slave address. scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom ac operating conditions notes: 1, 2; notes appear following eeprom ac and dc operating conditions tables. parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0s start condition hold time t hd:sta 4s clock high period t high 4s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r 1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 3
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 19 ?2002, micron technology inc. serial presence-d etect matrix notes: 1, 2; notes appear at end of serial presence-detect matrix byte description entry (version) mt4lsdt464(l)h(i) mt4lsdt864(l)h(i) mt4lsdt1664(l)h(i) 0 number of bytes used by micron 128 80 80 80 1 total number of spd memory bytes 256 08 08 08 2 memory type sdram 04 04 04 3 number of rowaddresses 12 or 13 0c 0c 0d 4 number of column addresses 8 or9 08 09 09 5 number of module banks 1 01 01 01 6 module data width 64 40 40 40 7 module data width (continued) 000 00 00 8 module voltage interface levels lvttl 01 01 01 9 sdram cycle time, t ck (cas latency = 3) 7ns (-13e) 7.5ns (-133) 8ns (-10e) 70 75 80 70 75 80 70 75 80 10 sdram access from clk, t ac (cas latency = 3) 5.4ns (-13e/-133) 6ns (-10e) 54 60 54 60 54 60 11 module configuration type none 00 00 00 12 refresh rate/type 15.6s or 7.81s/self 80 80 82 13 sdram width (primary sdram) 16 10 10 16 14 error-checking sdram data width 00 00 00 15 minimum clock delay from back-to- back random column addresses, t ccd 101 01 01 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 8f 17 number of banks on sdram device 404 4 04 18 cas latencies supported 2, 3 06 6 06 19 cs latency 001 01 01 20 we latency 001 01 01 21 sdram module attributes unbuffered 00 00 00 22 sdram device attributes: general 0e 0e 0e 0e 23 sdram cycle time , t ck (cas latency = 2) 7.5ns (13e) 10ns (-133/-10e) 75 a0 75 a0 75 a0 24 sdram access from clk, t ac (cas latency = 2) 54ns (-13e) 6ns (-133/-10e) 54 60 54 60 54 60 25 sdram cycle time, t ck (cas latency = 1) 00 00 00 26 sdram access from clk, t ac (cas latency = 1) 00 00 00 27 minimum row precharge time, t rp 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14 28 minimum row active to row active, t rrd 14ns (-13e) 15ns (-133) 20ns (-10e) 0e 0f 14 0e 0f 14 0e 0f 14 29 minimum ras# to cas# delay, t rcd 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14 30 minimum ras# pulse width, t ras (note 3) 45ns (-13e) 44ns (133) 50ns (-10e) 2d 2c 32 2d 2c 32 2d 2c 32
32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms micron technology, inc., reserves the right to change products or specifications without notice. sd4c4_8_16x64hg_b.fm - rev 8/02 20 ?2002, micron technology inc. note: 1. v dd = +3.3v 0.3v. 2. ?1?/?0?: serial data, ?driven to high?/?driven to low.? 3. the value of t ras used for -13e modules is calculated from t rc - t rp. actual device spec. value is 37ns. 31 module bank density 32mb, 64mb, or 128mb 08 10 20 32 command and address setup time, t as, t cms 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 33 command and address hold time, t ah, t cmh 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 34 data signal input setup time, t ds 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 35 data signal input hold time, t dh 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 36-61 reserved 00 00 00 62 spd revision rev. 1.2 12 12 12 63 checksum for bytes 0-62 (-13e) (-133) (-10e) 56 9c e4 5f a5 ed 72 b8 00 64 manufacturer?s jedec id code micron 2c 2c 2c 65-71 manufacturer?s jedec id code (cont.) ff ff ff 72 manufacturing location 1 - 11 01 - 0b 01 - 0b 01 - 0b 73-90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1 - 9 01-09 01 - 09 01-09 92 identification code (cont.) 000 00 00 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95-98 module serial number variable data variable data variable data 99-125 manufacturer-specific data (rsvd) variable data variable data variable data 126 system frequency 100 mhz (-13e/-133/-10e) 64 64 64 127 sdram component and clock detail 8f 8f 8f serial presence-d etect matrix (continued) notes: 1, 2; notes appear at end of serial presence-detect matrix byte description entry (version) mt4lsdt464(l)h(i) mt4lsdt864(l)h(i) mt4lsdt1664(l)h(i)
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron and the m logo are registered trademarks and the micron logo is a trademark of micron technology, inc. 32mb / 64mb / 128mb (x64) 144-pin sdram sodimms 4, 8, and 16meg x 64 sdram sodimms ?2002, micron technology inc. sd4c4_8_16x64hg_b.fm - rev 8/02 21 144-pin sodimm note: all dimensions in inches (millimeters) or typical where noted. u1 u2 u5 u3 u4 .043 (1.10) .035 (0.90) pin 1 2.666 (67.72) 2.656 (67.45) .787 (20.00) typ .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .83.82 (3.30) .024 (.60) typ .079 (2.00) r (2x) pin 143 .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ .157 (4.00) .150 (3.80) max 1.005 (25.53) 0.995 (25.27) pin 144 pin 2 front view back view max min

▲Up To Search▲

Price & Availability of MT4LSDT864HG-10EF2

	To Download MT4LSDT864HG-10EF2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .