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1 da9191a.000 july 31, 1997 MAS9191A single chip amps/etacs/namps audio/data processor ? single chip solution for all audio and data processing ? low power consumption with several power down modes ? sat decoding and transponding circuitry ? simple 4-wire serial interface description the MAS9191A is a high integration becmos ic for implementing the audio and data signal processing in amps, etacs or namps cellular phones. the power consumption of the device is very low due to several automatic and software controlled power down modes as well as the low power characteristics of the becmos process. dtmf receiver is also included to enable answering machine functions for the cellular phone. only a minimal number of external components are needed to meet typical baseband requirements. features applications ? voice signal processing including compressor, expander, de-emphasis and pre-emphasis filters and digital gain adjustments ? dtmf and st generators and dtmf receiver ? busy/idle extraction and arbitration with tx block, voting, bch, data buffering and framing, dcc coding with hardware ? three 8-bit dacs and two operational amplifiers ? on-chip oscillator with clock output for up ? 3.3v or 5v operation with low power consumption(rx block at 2ma/3.3v) ? 64-pin tqfp package, -40..85 o c operation range ? amps/etacs cellular phone ? namps cellular phone block diagram mic serial interfac e tx buffer dcc conversion framing rx buffer dtmf receiver voting manchester decoder dpll scl stb srxd stxd rx tx expander ba ndp ass filter de-emphasi s gain control comparator gain control compressor pre-emphas is limiter lo wp ass fi lter manchester coding bch coding sat generation frame decoding sat detection comparator dtmf generator sidetone speaker 3 8-bit dacs 2 utility operational amplif iers ampl ifier ampl ifier anti - aliasing buzzer am pl ifier xstal1 xstal2 lo wp ass fi lter lo wp ass fi lter lo wp ass fi lter gain control gain control gain control gain control gain control amplifier amplifier lo wp ass filter lo wp ass filter lo wp ass fi lter lo wp ass filter gain control highpa ss filter lo wp ass fi lter bch decoding busy / i dl e si gnall ing tone ba ndp ass filter sy s1 (namps ) sy s1 (namps )
2 da9191a.000 july 31, 1997 pin configuration agnd tx taudout taudin lpfin vsat vdat txaccout cout camp2i cwcin camp20 compin micout dacout1 dacout2 dacout3 xint busy txon einr sidetone sidefb earp1 earp2 exterp buzout buzfb srxd stgt est raudin rxaccout expout txaccin prein 12 13 14 15 16 17 64 63 62 61 60 59 33 32 31 30 29 28 27 26 25 34 35 36 37 38 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 23 24 rxaccin ewcin eampout expin vdar vsar rbpfout rbpfin deout vref 39 40 41 42 43 44 45 46 47 48 58 57 vdd xtal1 xtal2 vss txctrl clkout test1 test2 alp rx 56 55 54 53 52 51 50 49 micsgnd scl xreset extmic micfb mic stb stxd tqfp64 package pin description pin name pin type function agnd 1 ao signal ground. the signal ground is generated internally and is equal to v dd /2. the analog ground needs an exter nal capacitor connected to system ground. tx 2 ao transmitted data signal output. connect this output through a 22nf capacitor to the transmitter. taudout 3 ao tx audio output from the tx audio block.. taudin 4 ai tx audio input. the input fo r the tx audio signal, normally connected through a 22nf capacitor to taudout lpfin 5 ai input for tx limiter, lowpa ss filter or gc6 depending on the position of switches s15 and s16. the pi n is normally left unconnected. vsat 6 g ground for tx. connect to system ground. vdat 7 p power supply for tx block. use a bypass capacitor between pins vsat and vdat. txaccin 8 ai tx block extra op amp inpu t. see application note in the applications section. txaccout 9 ao tx block op amp output. prein 10 ai pre-emphasis filter input. f ilter has a +6db/octave (1db) frequency response in the range 300hz...3khz. cout 11 ao compressor output signal. the compression ratio is 2:1
3 da9191a.000 july 31, 1997 pin description pin name pin type function camp2i 12 ai compressor 2nd amplifier input as well as gc4 input. use an external 22nf capacitor between cout and this pin. cwcin 13 ai compressor window comparator input. use an external 22nf capacitor between camp2o and this pin. camp2o 14 ao compressor 2nd amplifier output. compin 15 ai compressor input. the input is connected through a 22nf capacitor to micout. micout 16 ao microphone amplifier output. see compin. this output is used as a source for the side tone and for det ection of the tx audio level. micsgnd 17 ao microphone signal ground. this is the internal signal ground v dd /2. if noise appears on the microphone signal an external capacitor may be needed between this pin and system ground. mic 18 ai microphone amplifier input. usi ng this pin and the micfb output the microphone amplifier frequency response can be adjusted according to the microphone used. the level at this input should be in the range 5..10mvrms. the maximum gain of the microphone amplifier is 30 db. micfb 19 ao microphone amplifier feedback output extmic 20 ai external microphone input. t he level should be 100mvrms at 1khz. xreset 21 i master reset. active low. scl 22 i serial interface clock input. the dat a is transferred in both directions at the rising edge of this signal. stb 23 i serial interface strobe signal. wi th strobe signal the MAS9191A stores the given address from the serial inte rface buffer and enters the data mode. the serial interface stays in t he data mode until eight scl pulses are received after the strobe signal. stxd 24 o serial interface transmit data output. srxd 25 i serial interface receive data input buzfb 26 ai buzzer feedback is t he input for the buzzer driver. buzout 27 ao buzzer output. exterp 28 ao output for external accessories earp1 29 ao earpiece differential outputs of earpiece amplifier. the outputs are capable of driving a ceramic earpiece directly. earp2 30 ao sidefb 31 ao side tone feedback output sidetone 32 ai side tone input. the level of the side tone is controlled with external components. einr 33 ai external rx input. stgt 34 ai steering control input for dtmf receiver. when the level at this input changes from below v dd /2 to above v dd /2 the pin is pulled up internally. when this occurs the dtmf tone is stored and an interrupt is generated. est 35 ao enable steering output. this pin is high when the dtmf receiver has detected a valid dtmf tone. raudin 36 ai input for filter 6. connect th rough a 22nf capacitor to the expander output (expout). rxaccout 37 ao output of uncommitted op amp in MAS9191A. the op amp is normally used for rx audio level detection. the app lication circuit for this function is in the applications section. connect the level detected by the circuit to the a/d converter of the general purpose micro controller.
4 da9191a.000 july 31, 1997 pin description pin name pin type function rxaccin 38 ai rx block extra op amp input expout 39 ao expander output. the expander ratio is 1:2. ewcin 40 ai expander window comparator input. connect a 22nf capacitor between ewcin and eampout. eampout 41 ao expander amplifier output. expin 42 ai expander input. connect a 22nf capacitor between expin and rbpfout. vdar 43 p power supply for rx audio blo ck. use a bypass capacitor between vdar and vsar. vsar 44 g ground for rx block. connect to system ground. rbpfout 45 ao rx bandpass filter output. rbpfin 46 ai rx bandpass filter input. c onnect a 22nf capacitor between this pin and deout deout 47 ao rx de-emphasis filter output. the filter has a -6db/octave (1db) frequency response in the range 300hz...3khz. vref 48 ao reference voltage. connect a capacitor between this pin and system ground. rx 49 ai rx input from rf. th is level is 100mvrms at 1khz. alp 50 ai audio loop input. connect through a 22nf capacitor to the tx pin. test2 51 i test input. connect to ground during normal operation. test1 52 i test input. connect to ground during normal operation. if connected to v dd and test2 is connected to ground, the external clock can then be connected to xtal1. clkout 53 o 4.8 mhz clock output from oscillator circuit. txctrl 54 ao transmission control output. if a tx collision occurs this open-collector output is set to low. the txctrl will remain low until the tx block is reset with the txrst bit or with xreset. vss 55 g digital ground. connect a bypass capacitor between vss and vdd. xtal2 56 o crystal oscillator output. xtal1 57 i crystal oscillator input or exter nal clock input if test1 is high and test2 is low. vdd 58 p power supply input for digital block. txon 59 o transmission detection for debugging. this output indicates when a transmission is occurring. busy 60 o busy/idle output. indicates the state of the busy/idle bit. xint 61 o active low interrupt output to micr o controller. the interrupt is active until status register 10 hex is read. dacout3 62 ao output of dac 3. the dac out put is connected to ground if the dac is in power down mode. the output of the dac is controlled by register 18 hex . enter the values in two?s complement form into the dac register. dacout2 63 ao output of the dac 2. t he control register is located at 17 hex . dacout2 64 ao output of the dac 1. t he control register is located at 16 hex .
5 da9191a.000 july 31, 1997 absolute maximum ratings (gnd = 0v) parameter symbol conditions min max unit supply voltage* v dd 6.0 v storage temperature* ts -55 +125 o c recommended operation conditions (gnd = 0v) parameter symbol conditions min typ max unit supply voltage* v dd ta=-40...85 o c 3.0 3.3 3.6 v supply current i dd ta=-40...85 o c, v dd =3.3v5% 1.0 2.5 23 ma operating temperature* ta -40 +85 o c electrical characteristics digital inputs (ta=-40...85 o c) parameter symbol conditions min typ max unit input high voltage* v ih 0.7v dd v input low voltage* v il 0.7v dd v input leakage current i il -10 +10 ua input capacitance load* c i 1 pf digital outputs (vdd = 3.3v 5%, ta=-40...85 o c) parameter symbol conditions min typ max unit output low voltage* v ol xint @ +0.4ma 0.1v dd v output high voltage* v oh xint @ -0.4ma 0.9v dd v analog inputs (ta=-40...85 o c) parameter symbol conditions min typ max unit external microphone level* v extmic 100 mv rms microphone level* v mic 10 mv rms rx input level* v rx 100 mv rms * guaranteed by design only.
6 da9191a.000 july 31, 1997 electrical characteristics analog outputs (ta=-40...85 o c) parameter symbol conditions min typ max unit signal ground agnd v dd /2- 0.1v v dd /2+ 0.1v v reference voltage v ref agnd +1.2v v earpiece output impedance* z o 500 ? earpiece load resistance* r l 1 k ? earpiece series load capacitance* c l 120 nf external earpiece load resistance* r l 30 k ? external earpiece load capacitance* c l 1 nf earpiece amplifier gain a vol 1.26 3.26 db rx level v o rx level 100mv rms 200 mv rms earpiece level non-differential* v o rx level 100mv rms 70 mv rms earpiece level differential* v o rx level 100mv rms 155 mv rms tx level v o extmic level 100mv rms 200 mv rms dtmf signal levels at tx v o f = 697 ? 941 hz -1 +1 db f = 1209 ? 1633 hz -1 +1 sat signal level at tx v o etacs 131 148 163 mv rms amps 123 138 152 data signal level at tx (amps/etacs) v o 470 556 612 mv rms st signal level at tx (amps/etacs) v o 488 556 612 mv rms data, st, sat level at tx v o namps, dtx mode off 81 93 105 mv rms namps, dtx mode on 325 373 421 dacs, output level v o 0.3v v dd - 0.3 v dacs, differential nonlinearity dnl -0.95 +0.95 lsb dacs, integral nonlinearity inl -2.0 +2.0 lsb dacs, settling time* vdac 1% 10 ms dacs, load resistance* r l 30 k ? dacs, load capacitance* c l 80 pf op amps, load capacitance* c l 1 nf * guaranteed by design only.
7 da9191a.000 july 31, 1997 electrical characteristics expander (ta=-40...85 o c) parameter conditions min typ max unit expanding ratio* 1:2 operation range input* -24 +10 db operation range output* -48 +20 db gain step* 1.333 db integral nonlinearity -0.5 +0.5 db attack time* 7.4 9.2 14.3 ms decay time* 9.5 11.9 14.3 ms compressor (ta=-40...85 o c) parameter conditions min typ max unit compressing ratio* 2:1 operation range input* -39.4 +20 db operation range output* -19.7 +10 db gain step* 1.333 db integral nonlinearity -0.5 +0.5 db attack time* 2.9 3.9 4.6 ms decay time* 13 16.9 20 ms ac characteristics (ta=-40...85 o c) parameter conditions min typ max unit rx s/n ratio psophometric weighting 48 db tx s/n ratio 50 db rx thd 34 db tx thd 34 db crosstalk rx to tx* 50 db crosstalk tx to rx* 50 db mute attenuation 50 db * guaranteed by design only.
8 da9191a.000 july 31, 1997 electrical characteristics 100hz 1khz 10khz -60.0 db -56.0 db -52.0 db -48.0 db -44.0 db -40.0 db -36.0 db -32.0 db -28.0 db -24.0 db -20.0 db -16.0 db -12.0 db -8.0 db -4.0 db 0.0 db 4.0 db 8.0 db 12.0 db 16.0 db 20.0 db rx total frequency response -60.0 db -56.0 db -52.0 db -48.0 db -44.0 db -40.0 db -36.0 db -32.0 db -28.0 db -24.0 db -20.0 db -16.0 db -12.0 db -8.0 db -4.0 db 0.0 db 4.0 db 8.0 db 12.0 db 16.0 db 20.0 db 100 hz 1khz 10khz tx total frequenc y response
9 da9191a.000 july 31, 1997 electrical characteristics -40.0 db -37.0 db -34.0 db -31.0 db -28.0 db -25.0 db -22.0 db -19.0 db -16.0 db -13.0 db -10.0 db -7.0 db -4.0 db -1.0 db 2.0 db 5.0 db 8.0 db 11.0 db 14.0 db 17.0 db 20.0 db 100hz 1khz 10khz filter f2 frequency response
10 da9191a.000 july 31, 1997 electrical characteristics timing (ta=-40...85 o c) parameter symbol conditions min typ max unit scl cycle t1 0.5 us data setup time t2 60 ns data hold time t3 20 ns stb rising edge after scl falling edge t4 10 ns stb width t5 5 us msb data bit valid after stb falling edge t6 register read 5 us scl rising edge after scl falling edge t7 register read 5 us next data bit valid after scl falling edge t8 register read 30 ns ready for next address t9 7 us timing diagram a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r/w stb scl srxd stxd d7 d6 d5 d4 d3 d2 d1 d0 r /w t1 t2 t3 t4 t5 t6 t7 t8 t9
11 da9191a.000 july 31, 1997 functions schematic diagram mic micfb 2:1 1:2 dtmf receiver serial interface tx-buffer bch coding dcc conversion framing manchester coding rx-buffer bch decoding voting frame decoding manchester decoder dpll sat detection sat generation osc clkout scl stb srxd stxd xreset xint sidetone sidefb buzout earp2 exterp einr raudin expout expin rbpfout rbpfin deout rx alp taudout taudin lpfin prein cout compin micout tx dtmf generator gc3 f9lp compressor f11 limiter gc6 gc7 gc9 f14 f12 gc8 f2 f1 gc1 f5 f4 expander f6 gc2 f7 a5 a4 a3 a2 m2 s12 s15 s16 s19 s18 s17 sys1 saten signaling tone txdata rxmute s3 s5 s7 s8 s11 s10 m1 s9 c2 c1 f3 s1 8-bit dac 8-bit dac 8-bit dac dacout1 dacout2 dacout3 rxaccou t + - rxaccin txaccout + - txaccin sgnd s20 s13 ewcin eampout camp2o cwcin est stgt extmic a6 micsgnd earp1 buzfb f8 a1 a7 agnd vref txctrl txon busy camp2i s2 rxtst s4 gc4 gc5 s14 f13 f9hp lpfin f9hp lpfin f15 taudin f9hp sys0 sys1 sys0 sys1 sys0 sys1 f10 txtst txtst sys1 busy / idle est stgt
12 da9191a.000 july 31, 1997 functions data reception the data reception block is in the power down state after a reset. the power down mode of the block is controlled by the rxsip bit in register 07 hex. the manchester encoded data is received through the rx pin. the data is amplified with gc1 and filtered with filter f1. the comparator c1 is used to convert data to a digital signal. the digital pll circuit recovers the bit clock from the manchester encoded data. the bit clock is 8khz in the etacs mode and 10khz in the amps mode. the mode is set with the sys0 bit of register 12 hex . the recovered bit clock is used in the manchester decoder and the data is then transmitted to the frame decoding block. the frame decoding block finds dotting sequences, busy/idle bits and word syncs from the data. to avoid data being generated by random noise, the frame decoding block enters the data reception mode only after it has received two consecutive word syncs (11100010010) separated by 463 bits in the forward control channel and 77 bits in the forward voice channel. in this case the voting and bch block are activated. when the frame decoding block loses five consecutive synchronization patterns it rejects the data reception mode and sets the voting and bch blocks in power down state. the voice and control channel modes are selected with the ctcv bit of register 12 hex . forward control channel data format. the numbers under the frames show the number of bits in each section. busy/ idle bit sync busy/ idle word sync busy/ idle data busy/ idle data busy/ idle data busy/ idle data 1 10 1 11 1 10 1 10 1 10 1 10 1. repeat of word a busy/ idle data busy/ idle data busy/ idle data busy/ idle data busy/ idle data busy/ idle data 1 10 1 10 1 10 1 10 1 10 1 10 1. repeat of word b 2. repeat of word a busy/ idle data busy/ idle data busy/ idle data busy/ idle data busy/ idle bit sync busy/ idle 1 10 1 10 1 10 1 10 1 10 1 5. repeat of word b bit sync = 1010101010 word sync = 11100010010 the busy/idle bits are extracted from the data. busy/idle bits are used to indicate the current status of the reverse control channel (recc). the recc is busy if the busy/idle bit is low and idle if the busy/idle bit is high. the state determination is made with 2-out-of-3 voting. the tx block uses the busy/idle indication for arbitration. the str bit of register 12 hex selects the words from stream a or stream b. forward voice channel data format. bit sync word sync 1.word repeat bit sync word sync 2.word repeat bit sync word sync 3.word repeat 101 11 40 37 11 40 37 11 40 bit sync word sync 9.word repeat bit sync word sync 10.word repeat bit sync word sync 11.word repeat 37 11 40 37 11 40 37 11 40 on the forward voice channel after bit synchronization and word synchronization are received and the aumut bit in register 13 hex is set to high, the rx audio block will be muted until the 920 bits are received. the repeated words are transferred to the voting block. the voting is done bit by bit, 3-out -of-5. if three consecutive words are identical, the receiver is powered down and no remaining words are read. after the voting block the data is transmitted to the bch block. this block performs decoding of the received bch coded data. the following polynomial is used: g(x) = x 12 + x 10 + x 8 + x 5 + x 4 + x 3 + x 0 if only one error occurs in data the bch block can correct it. if more than one error occurs the bch block cannot correct them and the bcher bit of register 11 hex is set to high. the bch block transfers the data to the rx buffer. when the buffer is full the rxwrd bit of register 10 hex is set to high and this causes interrupt line xint to go active. when register 10 hex is read the interrupt is cleared. the data buffer can be read by reading register 15 hex four times. if the next word is coming and the previous word has not been read from the buffer, the word is missed. the new and the old words are compared.
13 da9191a.000 july 31, 1997 functions data transmission after a reset the tx block is in power down. the power down mode is controlled by bit txsip (tx section in power down) in register 07 hex. the txrst bit located in register 12 hex is used every time a tx collision occurs or for any other tx block reset causes. when the device is ready to receive data, the txwrd bit of register 10 hex is high. if five bytes are written into register 19 hex the data transmission begins. the data is transferred from the serial interface to the tx buffer and the txwrd bit is set high again, which causes xint to become active. when the block comes out of power down mode the xint is active because the device is ready to receive data (txwrd goes high). the lower nibble of the fifth byte is ignored. the 36 bits of data are coded by the bch coder with following polynomial: g(x) = x 12 + x 10 + x 8 + x 5 + x 4 + x 3 + x 0 the bch coder adds 12 parity bits to the data and the data is transferred to the dcc coding block. the dcc coder adds a digital color code on the reverse control channel (recc) according following table. dcc(1:0) coded dcc 00 0000000 01 0011111 10 1100011 11 1111100 the framing block adds bit sync (101010...10) and word sync (11100010010) sequences to the frames and performs needed repeats depending on the mode. reverse control channel data format. the numbers under the frames show the number of bits in each section. bit sync word sync coded dcc first word repeated 5 times second word repeated 5 times 30 11 7 240 240 reverse voice channel data format. bit sync word sync 1.repeat of word 1 bit sync word sync 2.repeat of word 1 bit sync word sync 101 11 48 37 11 48 37 11 bit sync word sync 5.repeat of word 1 bit sync word sync 1.repeat of word 2 bit sync word sync 37 11 48 37 11 48 37 11 bit sync word sync 5.repeat of word 2 37 11 48 the manchester encoder block encodes the data into a manchester coded format with bit clock. the bit clock is 8khz in the etacs mode and 10khz in the amps mode. the mode can be controlled by bit sys0 of register 12 hex . the data polarity can be inverted with bit invtx of register 13 hex .if the busy bit does not go active between 56 and 104 bits of the transmitted message a transmission collision occurs. in this case the data which is in the tx block and the data that the user is writ ing to the device will not be transmitted. the txcol bit of register 10 hex will go high in this case and cause an interrupt. the txcol will remain active until the tx block is reset with the txrst bit of register 12 hex . if the txctren bit is active in register 12 hex the txctrl output turns the transmitter off when a tx collision occurs. if the aumut bit in register 13 hex is set to high the tx audio block is muted with switch s19 on the voice channel while data transmission is occurring.
14 da9191a.000 july 31, 1997 functions data reception in narrow band mode forward voice channel data format for narrow band. dsat sync word data dsat 24 30 40 24 sync word = 011001010110101001100110100110 dsat = digital supervisory audio tone is one of sev en 24-bit digital sequences added to the voice transmission. dsat is transmitted at 200 nrz bits/second. the following is a list of the seven dsat sequences. dsat sequence 0 2556cb hex 1 255b2b hex 2 256a9b hex 3 25ad4d hex 4 26ab2b hex 5 26b2ad hex 6 2669ab hex the 40-bit long data sequence is generated at a 100 manches ter bits/second rate. the data sequence contains 28 bits of data and 12 parity bits. the incoming data is captured by two 8-bit shift registers. when one shift register is full the rxwrd flag is set and an interrupt is generated. the captured data must be read by the micro controller within 20ms after the interrupt. meanwhile, the other shift register is being filled and when it is full a new interrupt is generated. the shift registers are clocked in at 400 hz. two samples of each state of both the 200 nrz bits/second data and the 100 manchester bits/second data are loaded into the registers. note that there are as many transitions in the 200 nrz bits/second data as in the 100 manchester bits/second data. the micro controller will then be used to filter the digital bit sequence and detect the dsat, sync word and data out of the bit stream. the data must be checked with following algorithm: g(x) = x 12 + x 10 + x 8 + x 5 + x 4 + x 3 + x 0 8-bit shift register 8-bit shift register stxd scl scl 400 hz 400 hz c1 rx
15 da9191a.000 july 31, 1997 functions data transmission in narrow band mode reverse voice channel data format for narrow band. dsat/dst sync word data dsat/dst 24 30 40 24 sync word = 011001010110101001100110100110 the data contains 36 data bits and 12 parity bits. the transmitted data is 100 bits /sec manchester code. dsat, dst and sync word are transmitted as 200 bits/sec nrz code. the dsat on the tx side is similar to the dsat on rx side. however, under certain conditions the inverted dsat, or dst (digital signaling tone), must be transmitted. the dst is one of seven 24-bit digital sequences consisting of the logical inverse of the seven dsat sequences. the conversions dsat/ dst and dst/dsat must be made without disturbing the phase of the dsat. there is also a special 24-bit digital mask for each of the seven sequences. the mask defines the first bit to be inverted when converting from dsat to dst or vice versa. only when the bit in the mask is one can the polarity be changed. dsat dst mask 0 2556cb hex daa934 hex ff003e hex 1 255b2b hex daa4d4 hex 0bbf82 hex 2 256a9b hex da9564 hex bd780f hex 3 25ad4d hex da52b2 hex 3ff118 hex 4 26ab2b hex d954d4 hex 0ae6f6 hex 5 26b2ad hex d94d52 hex 8001ff hex 6 2669ab hex d69654 hex 1c0fcd hex MAS9191A does not include frame coding logic for narrow band operation. the dsat, dst, sync word and data must be generated by micro controller. the bch function must also be performed by the micro controller using the following algorithm: g(x) = x 12 + x 10 + x 8 + x 5 + x 4 + x 3 + x 0 the generated bit sequence is written into shift register 19 hex 8 bits at a time. while the next byte is written to one of the 8-bit shift registers the other is clocked out with a 200hz clock. each time the contents of a shift regist er transmitted, the txwrd flag is set and an interrupt is generated. note that 200 nrz bits/second data has as many transitions as 100 manchester bits/second data. 8-bit shift register 8-bit shift register f12 gc8 srxd scl scl 200 hz 200 hz tx
16 da9191a.000 july 31, 1997 functions sat detection & regeneration sat detection is active on voice channel in amps or tacs mode (sys1=0). the supervisory audio tone is detected with a digital pll. the detector compares the received sat to the given sat color code (scc). when the given sat is detected the satdet bit of register 11 hex is set to high. if satinten bit of register 13 hex is on the rising and falling edge of satdet will cause the interrupt satint. on the voice channel the sat regeneration can be enabled with bit saten of register 14 hex . by setting bit nomsat of register 14 hex nominal sat frequency is generated. otherwise, the sat output frequency will follow received sat frequency. the block is in power down mode when the txsip (transmit section in power down) bit is active in register 07 hex . after a reset the block is in power down mode. scc1 scc0 sat frequency 0 0 5970 hz 0 1 6000 hz 1 0 6030 hz 1 1 invalid code sat, st or data transmission the sat and signaling tone (st) are sent only on the voice channel in amps or tacs mode (sys1=0). the saten and ston can be used to control the sat and st transmission. however, the device will automatically stop transmitting sat and st signals whenever data is being transmitted, even though saten or ston is high. the signaling tone is 8khz in etacs and 10khz in amps. also, switch s17 for tx data and switch s18 for st can be used to disable the transmission. the switches must be on during transmission. the control bits for these switches are located in register 0d hex . the sat, txdata and the st are summed and amplified with gc8. the gain of the amp lifier is -3.75db...+3.75db with 16 steps. the adjustment is made with bits 0..3 of register 0d hex . after being amplified the signal is filtered with 4th order sc filter f12. the cutoff frequency of the filter is 19khz in amps, 15khz in etacs and 200hz in namps (sys1=1). the gain of the filter at 1khz is 0db . in the namps mode, the signal is then fed to low pass filter f15, which is a 2nd order rc type filter. afte r filtering the signal is summed to the tx audio signal depending on the state of switch s20. the sw itch is controlled by bit 6 of register 01 hex .register 07 hex bit audiop is used to set these blocks into power down mode. dtmf receiver for enabling answering machine functions, the chip has an internal dtmf receiver. the receiver is in power down mode after a reset. the dtmfrp bit of register 07 hex controls the receiver power down mode. the receiver has two separate filters for separation of the low and high frequencies. the comparator and logic section measures the low and high frequency periods with an averaging algorithm. when the valid dtmf tone is detected the external steering logic output pin est is set to high. with an external rc time constant the tone detect time and tone dropout times can be adjusted. the stgt input/output pin has an internal comparator and pull- up and pull-down transistors . when est is active and stgt goes from below to above the vref level (vdd/2) the stgt is pulled up with an internal transistor. this causes the std signal to go high, which causes the xint line to become active. at the same time the detected dtmf tone is stored in register 04 hex . when the dtmf tone is not present the est will go low, which causes the stgt to fall. when the stgt falls below the vref level (vdd/2) the internal logic pulls the input down. the external rc circuit will filter out very short gaps in the received dtmf tone. the interrupt caused by the dtmf detector is cleared by reading status register 10 hex . if the interrupt is cleared but register 04 hex is not read until the next dtmf tone is received, then the previous tone will be lost. the formula below can be used to calculate tone present and tone absent times. by adding diodes to the external circuit the tone present and tone dropout times can be altered. if one of the diodes is removed, the absent and present times are calculated using the parallel combination of r1 and r2. est stgt est stgt c r2 c r1 r1 time = r*c ln(v dd /v ref )
17 da9191a.000 july 31, 1997 functions rx audio the rx audio block starts with switch s1. the switch is controlled by bit s1 of register 0e hex . the input alp is used for enabling the audio loopback mode. in normal operation rx is used. behind the switch is amplifier gc1 with adjustable gain from -3db to +3db. the gain is controlled with bits 0..3 in register 0e hex .the amplifier output is connected to the second order lowpass filter f1. the cutoff frequency of the filter is 50 khz and the gain at 1khz is 0db. the filter output is connec ted to data comparator c1 and to the sat bandpass filter f2 and to the rest of the rx audio block. the pol arity of the received data can be inverted with bit invrx, which is located in register 13 hex . the data comparator output is connected to the dpll and manchester decoder blocks. the filter f2 is a 6khz bandpass filter for supervisory audio tone. the filter is a second order sc filter. the filter output is connected to sat comparator c2 and the sat detection block. the signal from f1 is connected to filter f3 through a switch which is used by the internal logic when the aumut bit of register 13 hex is active. in this case if the data is received on the voice channel the lowpass filter f3 input is grounded automatically with this switch. with switches s6 and s7 the received audio and transmitted audio can be summed. the control bits of the switches are located in register 03 hex . this signal is fed to f4 and to the dtmf receiver. the function of the dtmf receiver is described in the next secti on rx de-emphasis filter f4 has a -6db/octave (1db) frequency response in the range 300hz ... 3khz. the filter can be bypassed with s2-rxtst0-rxtst1. switch s2-rxtst0- rxtst1 is connected to the deout pin. the performance of c1, c2 and f2 can be monitored with switch s2-rxtst0-rxtst1. bits 5 and 6 in register 02 hex and bit 5 in register 0e hex control this switch. an external capacitor is needed between deout and rbpfin. the rbpfin input is connected to filter f5, which is a 6th order bandpass filter. the gain of this filter is 0db at 1khz . the filter can be bypassed with switch s4. after s4 the signal is connected to the rbpfout pin. an exter nal capacitor is used to connect the signal to the expin input. 1:2 + gc1 f1 f3 f4 f5 rx data, sat rxmute s6 s7 micout s1 alp rx dtmf receiver c1 c2 f2 s4 s2 rxtst0 rxtst1 expander s5 f6 + + gc2 f7 s8 s11 s10 m1 s9 a2 a5 a4 a3 est stgt deout rbpfin rbpfout expin eampout ewcin expout raudin einr exterp earp1 earp2 buzfb buzout sidefb sidetone audio receive path
18 da9191a.000 july 31, 1997 functions the signal is fed to the sc-type audio expander with expansion ratio 1:2. the expander can also be bypassed with switch s5. the switch is controlled with bit s5 in register 03 hex . after switch s5 the signal goes to the expout output pin. an external capacitor is used to connect the signal to the raudin input and to filter f6. filter f6 is a 4th order sc-type lowpass filter. the gain at 1khz is 0db. after filtering the signal and the external accessory input einr can be summed with switch s8. the control bit for the switch is in register 03 hex . the summed signal is amplified with gc2, which has a -15db...+15db gain with 16 steps. the gain is controlled with bits 0..3 in register 03 hex . the amplified signal can be summed with sidetone. the side tone can be switched on with s9, which has a control bit in register 02 hex . the side tone input has an internal op amp with feedback signal sidefb. the gain of the op amp is controlled by external components. compin is normally used as an input for the side tone amplifier circuit. filter f7 is a second order low pass filter. the cutoff frequency is 20khz and the gain at 1khz is 0db. after filtering the signal can be connected to three amplifiers with switches m1, s10 and s11. the control bits are located in registers 02 hex and 03 hex . a4 is the earphone amplifier, which is a single input differential output amplifier. amplifier a5 is for external accessories and is capable of driving a capacitive load. the load capacitance is 1nf and the block has a 4.82db gain. the third amplifier a3 is a buzzer driver. it drives the signal to the power transistor, which drives the buzzer. the buzzer represents a high inductive load of 1.2mh/25ohm. the block stabilizes the current flow through the external buzzer which depends on the current gain factor of the external bipolar transistor. the emitter resistor of the transistor must be 6.8 ohms. three current values (peak values) can be chosen with switch m1:10ma, 66ma and 160ma. the tolerance of the external resistor w ill directly affect the buzzer current. the rx audio block can be set into power down mode together with the tx audio block. the audiop bit in register 07 hex is used for this purpose. the blocks are in power down mode after a reset.
19 da9191a.000 july 31, 1997 function tx audio the tx audio block is in the power down mode after a reset. the block is set to the operation mode with the audiop bit of register 07 hex . the same bit also controls the rx audio bl ock. the tx audio block starts with switch m2, which is controlled by bits 4 and 5 in register 00 hex . switch m2 connects one of the following blocks as an input source: 1) after a reset the input source is connected to signal ground. 2) in the second position the input is connected to the microphone amplifier a6. the gain of amplifier a6 is determined with external components. the maximum gain is 30 db. 3) in the third position the input is connected to extmic, which is for external accessories. 4) the fourth position selects the dtmf generator. the dtmf generator is controlled with registers 05 hex and 06 hex . register 05 hex controls the low frequencies and register 06 hex controls the high frequencies. a detailed description of how to use these registers is in the registers section. the dtmf generator is in the power down mode after a reset and can be set up with the dtmftp bit of register 07 hex . the signal is then filtered with anti-aliasing filter f8. the gain at 1khz is 0db and the cutoff frequency is 15khz. after the filter the signal is amplified with gc3. the gain is -3db...+3db with 16 steps according to bits 0..3 in register 00 hex . the amplified signal is then fed to lowpass filter f9lp and highpass filter f9hp, which are 4th order sc filters. during normal operation the output of filter f9hp is connected to output micout. with switch sys0- sys1 the highpass filter can be transferred to the output of gc5 after the signal has been compressed and pre-emphasized. bit 6 in register 12 hex and bit 6 in register 14 hex control switch sys0-sys1. connect micout through a 22nf capacitor to the compressor input compin. the micout can also be used as a source for the side tone amplifier and for detecting the audio level with the uncommitted op amp (see applications section). the compressor is an sc audio type with a 2:1 compressing ratio. the detailed values are found in the electrical characteristics sect ion under compressor. the compressor can be bypassed internally with switch s12 or externally wi th s13. the bypass gain is 0db (100 mv rms ). the compressor requires one external 22nf capacitor between pins camp20 and cwcin. another 22nf capacitor is needed between pins camp2in and cout. this capacitor also serves as an external dc blocking capacitor between the compressor output and gain control gc4 input. 2:1 dtmf generator a6 audio transmit path mic micsgnd micfb extmic f8 gc3 f9lp m2 sys0 sys1 sys0 sys1 f9hp compressor s13 s12 gc4 f10 micout compin cwcin camp2o cout camp2i prein s14 pre-emphasis lpfin gc5 sys0 sys1 limiter s15 f11 s16 gc7 gc6 taudout taudin txtst s19 f13 gc9 f14 tx data, st s20 + tx s7
20 da9191a.000 july 31, 1997 functions the gain of gc4 can be adjusted in the range - 0.67..+5.33db with bits 0..3 in register 0a hex . after gc4 the signal is filtered with pre-emphasis filter f10, which has a +6db/octave (1db) frequency response at the range 300hz..3khz. at 1khz the gain is 0db. the pre-emphasis filter can be bypassed with switch s14.the signal is then amplified with gc5. gain control gc5 is an sc-type with a programmable gain adjustment. the range is 0db..- 20 db with 16 steps according to bits 0..3 in register 0a hex . at the output of gc5 is output pin lpfin (or highpass filter f9hp) and a sc-type limiter. the limiting level is 439mv p and the tolerance is 5%. the 0db level is 370mv p. the limiter can be bypassed with switch s15. the lowpass filter f11 with a 6khz notch follows the limiter. the gain of the filter is 2.94db at 1khz. t he filter and the limiter can be bypassed with switch s16. gc6 and gc7 are continuous time programmable gain adjustment blocks. the gain of gc6 is -3db ... +3db with 16 step according to bits 0..3 in register 0b hex . the gain of gc7 is adjustable within - 3db ... +1db with bits 0..3 in register 0b hex in 16 steps. gc7 output is connected to pin taudout through switch txtst. the data transmission signal can be examined at taudout with this switch. also with switch txtst, the performance of gc8, 3.75..3.75db., f12 and f15 can be observed with an input at taudin. an exter nal capacitor between pins tadout and taudin is required. the taudin input is connected to switch s19. the switch can be used to mute the tx audio block. s19 is controlled with bit 5 in register 01 hex . switch s19 is also controlled by the tx fr aming block. during data transmission on the voice channel and with the aumut bit in register 13 hex set to high the tx audio block is muted with s19. following s19 is a second order lowpass filter f13 with 15khz cutoff frequency. after filtering the signal is summed with the data signal and amplified with gc9. the gain of the amplifier gc9 is adjustable with bits 0..3 located in register 0c hex . the adjustment is done in 16 steps in the range -3.0.. +3.0db .the output of the amplifier gc9 is then filtered with f14. the filter is a third order lowpass filter with 54khz cutoff frequency. the gain at 1khz is 0db. dtx bit of the regiter 0d hex is used to set data, dsat and dst deviation. when the device is not in dtx (discontinous transmission) the dtx = 0 and there is nominal level at tx, 93 mv rms . if dtx is on, the level is increased to 373 mv rms .
21 da9191a.000 july 31, 1997 functions dacs the device has three 8-bit dacs. the dacs can be set to the power down mode by using bits xpddac1, xpddac2 and xpddac3. the dacs are in power down mode after a reset. the vref for the dacs is vdd/2. the out put values of the dacs are entered in 8-bit two?s complement form into registers 16 hex , 17 hex and 18 hex . the typical step size is 13 mv and the dc output level is in the range 0.3v..vdd-0.3v. the differential nonlinearity is 0.5 lsb and the integral 2lsb. the settling time is 10ms (max). the minimum load resistance is 30k and the maximum load capacitance is 80pf. op amps there are two uncommitted inverting operational amplifiers in the device. the input pins are rxaccin and txaccin. the output pins are rxaccout and txaccout. the op amps are capable of driving capacitive loads up to 1nf. serial interface the serial interface has three inputs: scl (serial clock), stb (strobe) and srxd(received data). output pin stxd is used for transmitting data. the data is latched with the rising edge of the scl signal. the msb is received first and the lsb last. before the stb signal, eight address bits must first be shifted in. the stb signal sets the device into the data mode. the msb of the address byte defines the read/write operation. if the msb is high the data is read from the device. if the msb is low, the data is written to the device. after the stb the written data is shifted in with the rising edge of the scl. if the data is to be read from the device, the stxd output is in the state of msb data bit after the stb signal. the falling edge of the scl shifts the next data bit to the stxd output. eight data bits must be shifted out at which time the device exit s the data mode. because the serial interface transmit buffer is dynamic, data will be valid on the buffer only 200 us after the stb signal appears. this means that the scl frequency must be at least 5khz. a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r/w address address data data stb scl srxd stxd stb scl srxd stxd
22 da9191a.000 july 31, 1997 functions registers address i/o bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 hex write 0 0 m2[1:0] gc3[3:0] 01 hex write 0 s20 s19 s16 s15 s14 s13 s12 02 hex write 0 rxtst[1:0] s9 s11 s10 m1[1:0] 03 hex write s8 s7 s6 s5 gc2[3:0] 04 hex write 0 vref[2:0] 0 0 0 0 (84 hex) read x x x x dtmf[3:0] 05 hex write 0 0 lowf[5:0] 06 hex write highf[7:0] 07 hex write xpddac3 xpddac2 xpddac1 rxsip txsip audiop dtmfrp dtmftp 0a hex write gc4[3:0] gc5[3:0[ 0b hex write gc7[3:0] gc6[3:0] 0c hex write 0 0 0 txtst gc9[3:0] 0d hex write 0 s18 s17 dtx gc8[3:0] 0e hex write s4 s3 s2 s1 gc1[3:0] 10 hex (90 hex ) read x x satint txcol txwrd rxwrd std 11 hex (11 hex ) read x bcherr busy txon wsync dot satdet x 12 hex write saten sys0 str rxrst txrst txctre ctcv ston 13 hex write satinte stde rxinte aumut invrx invtx dcc[1:0] 14 hex write nomsat sys1 0 0 0 0 scc[1:0] 15 hex (95 hex ) read 1 st rx[0:7] amps 2 nd rx[8:15] 3 rd rx[16:23] 4 th rx[24:27] 0 0 0 0 15 hex (95 hex ) read 8 bits of captured data after comparat or with shift register clocked at 400hz namps 16 hex write dac1[7:0] 17 hex write dac2[7:0] 18 hex write dac3[7:0] 19 hex write 1 st tx[0:7] amps 2 nd tx[8:15] 3 rd tx[16:23] 4 th tx[24:31] 5 th tx[32:35] 0 0 0 0 19 hex write 8 bit sequence to be transmitted wi th shift register clocked at 200hz namps
23 da9191a.000 july 31, 1997 functions register 00 hex (write only) bit name state function 3-0 gc3[3:0] 0000-1111 control range for gc3: -3.0db ? +3.0db, 0.4db/step 0000 -3.0db 0001 -2.6db 0010 -2.2db ??. 1111 +3.0db 1000 +0.2db default value 5-4 m2[1:0] 00 agnd connected to f8 input 01 a6-out 10 extmic 11 dtmfgen 6 reserved 0 reserved for future use, set to 0 7 reserved 0 reserved for future use, set to 0 register 01 hex (write only) bit name state function 0 s12 0 compressor output connected to cout 1 compressor input 1 s13 0 cout connected to gc4 input 1 prein 2 s14 0 f10 output connected to gc5 input 1 f10 input 3 s15 0 limiter output connected to f11 input 1 limiter input 4 s16 0 f11 output connected to gc6 input 1 limiter input 5 s19 0 agnd connected to f13 input 1 taudin 6 s20 0 (sys1 = 0) agnd summed to gc9 input 1 (sys1 = 1) f12 output 0 (sys1 = 0) agnd 1 (sys1 = 1) f15 output 7 reserved 0 reserved for future use, set to 0
24 da9191a.000 july 31, 1997 functions register 02 hex (write only) bit name state function 1-0 m1[1:0] 00 agnd connected to amplifier a3 input 01 10ma gain 10 66ma gain 11 160ma gain 2 s10 0 agnd connected to amplifier a4 input 1 filter f7 output 3 s11 0 agnd connected to amplifier a5 input 1 filter f7 output 4 s9 0 agnd summed to f7 input 1 amplifier a2 output 6-5 rxtst0- 00 determined by s2 connected to deout rxtst1 01 c1 10 f2 11 c2 7 reserved 0 reserved for future use, set to 0 register 03 hex (write only) bit name state function 3-0 gc2[3:0] 0000-1111 control range for gc2: -15.0db ? +15.0db, 2.0db/step 0000 -15.0db 0001 -13.0db 0010 -11.0db ??. 1111 +15.0db 1000 +1.0db default value 4 s5 0 expout connected to expout 1 expin 5 s6 0 agnd summed into f6 input 1 raudin 6 s7 0 agnd 1 compin 7 s8 0 agnd summed into gc2 input 1 einr
25 da9191a.000 july 31, 1997 functions register 04 hex (bits 7-4 write only, bits 3-0 read only) bit name state function 3-0 dtmf[3:0] 0001 ?1? tone detected 0010 ?2? tone detected 0011 ?3? tone detected 0100 ?4? tone detected 0101 ?5? tone detected 0110 ?6? tone detected 0111 ?7? tone detected 1000 ?8? tone detected 1001 ?9? tone detected 1010 ?0? tone detected 1011 ?*? tone detected 1100 ?#? tone detected 1101 ?a? tone detected 1110 ?b? tone detected 1111 ?c? tone detected 0000 ?d? tone detected 6-4 vref[2:0] internal re ference voltage adjustment 000 +0.75db 001 +0.50db 010 +0.25db 011 0.00db default value 100 -0.25db 101 -0.50db 110 -0.75db 111 -1.00db 7 reserved 0 reserved for future use, set to 0 register 05 hex (write only) bit name state function 5-0 lowf[5:0] 00h-3fh transmitted low frequency dtmf tone nominal real frequency 000000 no signal no signal 100110 697 hz 695.8 hz 101010 770 hz 769.0 hz 101111 852 hz 860.6 hz 110011 941 hz 933.8 hz 7-6 reserved 00 reserved for future use, set to 0
26 da9191a.000 july 31, 1997 the register value for other frequencies may be calculated with the formula: lg[5:0] = (f out * 2 17 ) / 2.4mhz. functions register 06 hex (write only) bit name state function 7-0 highf[7:0] 00h-ffh transmitted high frequency dtmf tone nominal real frequency 00000000 no signal no signal 01000010 1209 hz 1208.5 hz 01001001 1336 hz 1336.7 hz 01010001 1477 hz 1483.2 hz 01011001 1633 hz 1629.6 hz the register value for other frequencies may be calculated with the formula: hg[7:0] = (f out * 2 17 ) / 2.4mhz. register 07 hex (write only) bit name state function 0 dtmftp 0 dtmf transmitter in power down 1 dtmf transmitter active 1 dtmfrp 0 dtmf receiver in power down 1 dtmf receiver active 2 audiop 0 audio in power down 1 audio active 3 txsip 0 digital tx section in power down 1 digital tx section active 4 rxsip 0 digital rx section in power down 1 digital rx section active 5 xpddac1 0 dac1 in power down 1 dac1 active 6 xpddac2 0 dac2 in power down 1 dac2 active 7 xpddac3 0 dac3 in power down 1 dac3 active
27 da9191a.000 july 31, 1997 functions register 0a hex (write only) bit name state function 3-0 gc5[3:0] 0000-1111 control range for gc5: 0.0db ? -20.0db, 1.33.0db/step 0000 0.0db 0001 -1.33db 0010 -2.67db ??. 1111 -20.0db 0000 0.0db default value 7-4 gc4[3:0] 0000-1111 control range for gc 4: -0.67db ? +5.33db, 0.4.0db/step 0000 -0.67db 0001 -0.27db 0010 +0.13db ??. 1111 +5.33db 1000 +2.53db default value register 0b hex (write only) bit name state function 3-0 gc6[3:0] 0000-1111 control range for gc6: -3.0db ? +3.0db, 0.4db/step 0000 -3.0db 0001 -2.6db 0010 -2.2db ??. 1111 +3.0db 1000 +0.2db default value 7-4 gc7[3:0] 0000-1111 control range for gc 7: -3.0db ? +1.0db, 0.266.0db/step 0000 -3.0db 0001 -2.6db 0010 -2.2db ??. 1111 +1.0db 1011 -0.067db default value
28 da9191a.000 july 31, 1997 functions register 0c hex (write only) bit name state function 3-0 gc9[3:0] 0000-1111 control range for gc9: -3.0db ? +3.0db, 0.4db/step 0000 -3.0db 0001 -2.6db 0010 -2.2db ??. 1111 +3.0db 1000 +0.2db default value 4 txtst 0 gc7 output connected to taudout st, sat and txdata connected to gc8 input 1 st, sat and txdata connected to taudout taudin connected to gc8 input 7-5 reserved 000 reserved for future use, set to 0 register 0d hex (write only) bit name state function 3-0 gc8[3:0] 0000-1111 control range for gc8: -3.75db ? +3.75db, 0.5db/step 0000 -3.75db 0001 -3.25db 0010 -2.75db ??. 1111 +3.75db 1000 +0.25db default value 4 dtx 0 discontinuous transmission disabled 1 discontinuous transmission enabled 5 s17 0 (sys1 = 0) agnd summed into gc8 input 1 (sys1 = 0) txdata signal 0 (sys1 = 1) agnd 1 (sys1 = 1) tx buffer output signal 6 s18 0 agnd 1 signaling tone 7 reserved 0 reserved for future use, set to 0
29 da9191a.000 july 31, 1997 functions register 0e hex (write only) bit name state function 3-0 gc1[3:0] 0000-1111 control range for gc1: -3.0db ? +3.0db, 0.4db/step 0000 -3.0db 0001 -2.6db 0010 -2.2db ??. 1111 +3.0db 1000 +0.2db default value 4 s1 0 rx connected to gc1 input 1 alp 5 s2 0 f4 output connected to deout 1 f4 input 6 s3 0 signal from s2-rxtst0-rxtst1 connected to f5 input 1 rbpfin 7 s4 0 f5 output connected to rbpfout 1 f5 input register 10 hex (read only) bit name state function 0 std 0 dtmf tone not received 1 dtmf tone received 1 rxwrd 0 rx buffer empty 1 rx word received (sys1 = 0) next captured byte ready (sys1 = 1) 2 txwrd 0 transmitting previous byte or word 1 tx buffer empty 3 txcol 0 no tx collision detected 1 tx collision detected 4 satint 0 satdet signal stable 1 rising or falling edge of satdet detected 7-5 reserved 0,1 not in use the rising edge of the signals std, rx wrd, txwrd, txcol and satint activa tes the interrupt line xint. if the signal(s) changes when register 10 hex or one of the other registers is read, the interrupt line will be activated right after the register read. reading this register sets the interrupt line inactive. if a new interrupt is generated during register read , the interrupt line will be acti vated again right after register is read.
30 da9191a.000 july 31, 1997 functions register 11 hex (read only) bit name state function 0 reserved 0,1 not in use 1 satdet 0 invalid sat frequency received 1 valid sat frequency received. see scc in register 14 hex. 2 dot 0 no dotting sequence detected 1 dotting sequence detected 3 wsync 0 no word sync detected 1 word sync detected 4 txon 0 no transmission 1 word transmission on 5 busy 0 busy bit detected 1 idle bit detected 6 bcherr 0 no bch error detected 1 bch error detected 7 reserved 0,1 not in use register 12 hex (write only) bit name state function 0 ston 0 no signaling tone transmission 1 signaling transmission on 1 ctcv 0 control channel 1 voice channel 2 txctren 0 tx control disabled 1 tx control active. txctrl output pin can be used to control transmitter 3 txrst 0 digital tx section operating 1 digital tx section reset 4 rxrst 0 digital rx section operating 1 digital rx section reset 5 str 0 stream a 1 stream b 6 sys0 0 (sys1 = 0) etacs mode 1 (sys1 = 0) amps mode 0 (sys1 = 1) f9hp input connected to f9lp output. namps mode 1 (sys1 = 1) f9hp input connected to gc5 output. namps mode 7 saten 0 sat transmission disabled 1 sat transmission enabled
31 da9191a.000 july 31, 1997 functions register 13 hex (write only) bit name state function 1-0 dcc[1:0] 00-11 digital color code 00 0000000 01 0011111 10 1100011 11 1111100 2 invtx 0 txdata not inverted 1 invert txdata polarity 3 invrx 0 rx input not inverted 1 invert rx input polarity 4 aumut 0 no automatic mute 1 tx and rx audio muted automatically on the voice channel 5 rinte 0 rx interrupts disabled 1 rx interrupts enabled 6 stde 0 stde (dtmf receiver) interrupts disabled 1 stde (dtmf receiver) interrupts enabled 7 satinte 0 sat detection interrupts disabled 1 sat detection interrupts enabled register 14 hex (write only) bit name state function 1-0 scc[1:0] 00 5958hz-5982hz sat frequency expected 01 5988hz-6012hz sat frequency expected 10 6018hz-6042hz sat frequency expected 11 invalid state 5-2 reserved 0000 reserved for future use, set to 0 6 sys1 0 wide band mode (amps/etacs) 1 narrow band mode (namps) 7 nomsat 0 transmitted sat will follow received sat 1 nominal sat frequency transmitted
32 da9191a.000 july 31, 1997 functions register 15 hex (read only) bit name state function 7-0 rx byte sys1 = 0 00h-ffh when rxwrd is high 1 st byte b0 b1 b2 b3 b4 b5 b6 b7 2 nd byte b8 b9 b10 b11 b12 b13 b14 b15 3 rd byte b16 b17 b18 b19 b20 b21 b22 b23 4 th byte b24 b25 b26 b27 0 0 0 0 7-0 rx byte sys1 = 1 00h-ffh captured byte with 400hz after data comparator. msb = first captured bit. the received word is read by reading register 15 hex four times. register 16 hex (write only) bit name state function 7-0 dac1[7:0] 00h-ffh control port for dac1 output level 80h 100mv dc ffh 100mv dc + 7fh x 13mv dc 00h 100mv dc + 80h x 13mv dc 7fh 100mv dc + ffh x 13mv dc register 17 hex (write only) bit name state function 7-0 dac2[7:0] 00h-ffh control port for dac2 output level 80h 100mv dc ffh 100mv dc + 7fh x 13mv dc 00h 100mv dc + 80h x 13mv dc 7fh 100mv dc + ffh x 13mv dc register 18 hex (write only) bit name state function 7-0 dac3[7:0] 00h-ffh control port for dac3 output level 80h 100mv dc ffh 100mv dc + 7fh x 13mv dc 00h 100mv dc + 80h x 13mv dc 7fh 100mv dc + ffh x 13mv dc
33 da9191a.000 july 31, 1997 functions register 19 hex (write only) bit name state function 7-0 tx byte sys1 = 0 00h-ffh when txwrd is high 1 st byte b0 b1 b2 b3 b4 b5 b6 b7 2 nd byte b8 b9 b10 b11 b12 b13 b14 b15 3 rd byte b16 b17 b18 b19 b20 b21 b22 b23 4 th byte b24 b25 b26 b27 b28 b29 b30 b31 5 th byte b32 b33 b34 b35 0 0 0 0 7-0 tx byte sys1 = 1 00h-ffh byte for transmitter. byte is shifted out with 200hz clock. msb will be transmitted first. the transmitted word is written by writing to register 19 hex five times.
34 da9191a.000 july 31, 1997 application information MAS9191A micro controller memory interfaces - display - keypad rf front end if demodulator dual synthesizer duplex filter power amp vcxo rx vco tx vco audio/data processor rx tx dac typical MAS9191A application in amps/etacs cellular system. test circuit 22nf 22nf 22nf 22nf 100nf 100nf 22pf 22pf 22nf 22nf 1m 4.8mhz 22nf 22nf 22nf 22nf c r 161513141112432 57 56 1 48 49 47 46 45 42 41 40 39 36 35 34 28 30 29 26 27 20 19 17 18 rf modulator if earphone buzzer mic 6.8 100 22nf 100nf 100nf 100nf extmic 1 2 3 4 mas 9191a r r extearp 1nf side tone side tone a3 a4 micro controller a6 serial bus c c 32 r r a6 c c 31 vdd components determine the gain of sidetone amplifier a2 components determine the gain of microphone amplifier a6 npn transistor for the buzzer components determine rc time constant if dtmf receiver is used 4 1 2 3 dtmf receiver
35 da9191a.000 july 31, 1997 package outlines 16.00 typical 14.00 typical 0 - 7 0.80 typical 64 lead tqfp outline all measurements in mm 16.00 typical 14.00 typical 0.75 0.45 0.45 0.30 0.15 0.05 0 . 0 9 0 . 2 0 seating plane 1.45 1.35 max 1.60
36 da9191a.000 july 31, 1997 ordering information product code product package comments MAS9191Aj amps/etacs single chip audio/data processor tqfp64 MAS9191Aj-t amps/etacs single chip audio/data processor tqfp64 tape and reel local distributor micro analog systems oy contacts micro analog systems oy kamreerintie 2, p.o. box 51 fin-02771 espoo, finland tel. +358 9 80 521 fax +358 9 805 3213 http://www.mas-oy.com notice micro analog systems oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible pr oducts. micro analog systems oy assumes no responsibility for the use of any circ uits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes n o claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and micro analog systems oy makes no claim or warranty that such applications w ill be suitable for the use specified without further testing or modification.

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