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1 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer ------table of contents------ - sio3 ..................................................... 141 a-d converter .............................................. 144 d-a converter .............................................. 154 crc calculation circuit ................................ 156 can module ................................................ 158 programmable i/o ports .............................. 178 usage precaution ........................................ 188 electrical characteristics (vcc = 5 v) .......... 190 flash memory description ........................... 206 cpu rewrite mode ....................................... 209 parallel i/o mode ......................................... 224 standard serial i/o mode ............................. 239 description ...................................................... 1 memory .......................................................... 9 central processing unit (cpu) ...................... 18 processor mode ............................................ 21 protection ..................................................... 32 reset ............................................................ 33 clock generating circuit ............................... 38 interrupts ...................................................... 52 dmac ........................................................... 72 wdt ............................................................. 79 timer ............................................................ 81 serial i/o ..................................................... 111 - uart0-2 .............................................. 127 specifications written in this manual are believed to be ac- curate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. description the m16c/6nt group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 100-pin plastic molded qfp. these single- chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling office, communications, industrial equip- ment, and other high-speed processing applications. being equipped with two can (controller area network) modules, the microcomputer is suited to drive automotive and industrial control systems. the can modules comply with the 2.0b specification. features ? memory capacity ................................. rom 128k/256k bytes ram 5k/10k bytes ? shortest instruction execution time ...... 62.5 ns (f(x in ) = 16mhz, 1 / 1 prescaler, without software wait) 100 ns (f(x in ) = 20mhz, 1 / 2 prescaler, without software wait) ? supply voltage ..................................... 4.2 to 5.5v (f(x in ) = 16mhz, 1 / 1 prescaler, without software wait) 4.2 to 5.5v (f(x in ) = 20mhz, 1 / 2 prescaler, without software wait) ? low power consumption ...................... tbd (f(x in ) = 16mhz, 1 / 1 prescaler, without software wait) tbd (f(x in ) = 20mhz, 1 / 2 prescaler, without software wait) ? interrupts ............................................. 29 internal and 9 external interrupt sources, 4 software interrupt sources; 7 priority levels (including key input interrupt) ? multifunction 16-bit timer ..................... 5 output timers + 6 input timers ? serial i/o ............................................. 4 channels (3 for uart or clock synchronous, 1 for clock synchronous) ? dmac ................................................. 2 channels (trigger: 23 sources) ? can module ........................................ 2 channels, 2.0b active ? a-d converter ...................................... 10 bits x 26 analog inputs ? d-a converter ...................................... 8 bits x 2 analog outputs ? crc calculation circuit ........................ 1 circuit ? watchdog timer ................................... 1 15-bit timer ? programmable i/o ............................... 87 lines ? input port ............................................. 1 line (p8 5 shared with nmi pin) ? chip select output ................................ 4 lines ? memory expansion .............................. available (to a maximum of 1m bytes) ? clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) applications automotive and industrial control systems
2 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer pin configuration (top view) package: 100p6s-a figure 1-1. pin configuration (top view) pin configuration figure 1-1 shows the pin configuration (top view). 123456789101112131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0 7 /an 07 /d 7 p1 0 /d 8 p1 1 /d 9 p1 2 /d 10 p1 3 /d 11 p1 4 /d 12 v ref av ss v cc x in x out v ss reset cnvss p8 7 /x cin p8 6 /x cout byte p3 0 /a 8 (/-/d 7 ) p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 p4 3 /a 19 p7 4 /ta2 out /w p5 6 /ale p5 5 /hold p5 4 /hlda p5 3 /bclk p5 2 /rd vcc vss p5 7 /rdy/clk out p4 5 /cs1 p4 6 /cs2 p4 7 /cs3 avcc p6 3 /t x d 0 p6 5 /clk 1 p6 6 /rxd 1 p6 7 /t x d 1 p6 1 /clk 0 p6 2 /rxd 0 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p9 3 /da 0 /tb3 in p9 4 /da 1 /tb4 in p9 6 /anex1/ctx 0 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s out 3 p8 0 /ta4 out /u p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p7 2 /clk 2 /ta1 out /v p8 2 /int 0 p7 1 /rxd 2 /scl/ta0 in /tb5 in p8 3 /int 1 p8 5 /nmi p9 7 /ad trg p4 4 /cs0 p5 0 /wrl/wr p5 1 /wrh/bhe p9 0 /tb0 in /clk3 p7 0 /t x d 2 /sda/ta0 out p8 4 /int 2 p8 1 /ta4 in /u p7 5 /ta2 in /w p1 5 /d 13 /int3 p1 6 /d 14 /int4 p1 7 /d 15 /int5 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4/ ki 0 m16c/6n group p7 3 /cts 2 /rts 2 /ta1 in /v p0 6 /an 06 /d 6 p0 5 /an 05 /d 5 p0 4 /an 04 /d 4 p0 3 /an 03 /d 3 p0 2 /an 02 /d 2 p0 1 /an 01 /d 1 p0 0 /an 00 /d 0 p2 0 /an 20 /a 0 /(d 0 /-) p2 1 /an 21 /a 1 /(d 1 /d 0 ) p2 2 /an 22 /a 2 /(d 2 /d 1 ) p2 3 /an 23 /a 3 /(d 3 /d 2 ) p2 4 /an 24 /a 4 /(d 4 /d 3 ) p2 5 /an 25 /a 5 /(d 5 /d 4 ) p2 6 /an 26 /a 6 /(d 6 /d 5 ) p2 7 /an 27 /a 7 /(d 7 /d 6 ) p9 5 /anex0/crx 0 p7 7 /ta3 in /crx 1 p7 6 /ta3 out /ctx 1
3 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer block diagram figure 1-2 is a block diagram of the m16c/6n group. block diagram of the m16c/6n group figure 1-2. block diagram of m16c/6n group timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) internal peripheral functions watchdog timer (15 bits) dmac (2 channels) a-d converter (10 bits x 26 inputs) uart/clock synchronous si/o (8 bits x 3 channels) system clock generator x in -x out x cin -x cout m16c/60 series16-bit cpu core i/o ports port p0 8 port p1 8 port p2 8 port p3 8 port p4 8 port p5 8 port p6 8 8 r0l r0h r1h r1l r2 r3 a0 a1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers isp usp stack pointer vector table intb can module (2 channels) multiplier 7 8 8 port p10 port p9 port p8 port p7 memory port p8 5 rom (note 1) (note 1) ram sb flg pc program counter clock synchronous si/o (8 bits x 1 channel) d-a converter (8 bits x 2 outputs) timer tb3 (16 bits) timer tb4 (16 bits) timer tb5 (16 bits) crc arithmetic circuit (ccitt) (polynomial : x 16 +x 12 +x 5 +1) note 1: memory sizes depend on mcu type.
4 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer performance outline table 1-1 is a performance outline of the m16c/6n group. table 1-1. performance outline of m16c/6n group item performance number of basic instructions 91 instructions shortest instruction execution time 62.5 ns (f(x in ) = 16mhz, 1 / 1 prescaler, without software wait) 100ns (f(x in ) = 20mhz, 1 / 2 prescaler, without software wait) memory rom 128k to 256k byte capacity ram 5k to 10k byte i/o ports p0 to p10 (except p8 5 ) 8 bit x 10, 7 bit x 1 input port p8 5 1 bit x 1 multifunction ta0, ta1, ta2, ta3, ta4 16 bit x 5 timer tb0, tb1, tb2, tb3, tb4, tb5 16 bit x 6 serial i/o uart0, uart1, uart2 (uart or clock synchronous) x 3 si/o3 clock synchronous a-d converter 10 bits x (8 + 8 + 8 + 2) inputs d-a converter 8 bits x 2 channels crc calculation circuit crc-ccitt dmac 2 channels (trigger: 23 sources) can module 2 channels, 2.0b active watchdog timer 15 bits x 1 (with prescaler) interrupt 29 internal and 9 external sources, 4 software sources, 7 priority levels clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage 4.2 to 5.5v (f(x in ) = 16mhz, 1 / 1 prescaler, without software wait) 4.2 to 5.5v (f(x in ) = 20mhz, 1 / 2 prescaler, without software wait) power consumption tbd (f(x in ) = 16mhz, 1 / 1 prescaler, without software wait) tbd (f(x in ) = 20mhz, 1 / 2 prescaler, without software wait) i/o i/o withstand voltage 5v characteristics output current 5ma operating ambient temperature C40 to 85 o c device configuration cmos high performance silicon gate package 100-pin plastic mold qfp
5 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 1-3. rom expansion rom size (byte) external rom 128k 96k 64k 32k m306n0mct-xxxfp mask rom version one-time prom version eprom version flash version M306N0FGTFP 256k external rom version remarks type no apr. 1998 m306n0mct-xxxfp mask rom version flash 5v version M306N0FGTFP rom size 128k byte 256k byte ram size 5k byte 10k byte package type 100p6s-a 100p6s-a table 1-2. m16c/6n group
6 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 1-4. type no., memory size, and package package type: fp : package 100p6s-a rom no. omitted for flash version rom capacity: 1 : 8k bytes 7 : 56k bytes 2 : 16k bytes 8 : 64k bytes 3 : 24k bytes 9 : 80k bytes 4 : 32k bytes a : 96k bytes 5 : 40k bytes c : 128k bytes 6 : 48k bytes g : 256k bytes memory type: m : mask rom version f : flash rom version type no. m 3 0 6 n 0 m c t C x x x f p m16c/6n group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning) temperature range t : automotive 85 o c version
7 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer pin description table 1-3. pin description of m16c/6n group (1) v cc , v ss cnv ss x in x out byte av cc av ss v ref p0 0 to p0 7 d 0 to d 7 p1 0 to p1 7 d 8 to d 15 p2 0 to p2 7 a 0 to a 7 a 0 /d 0 to a 7 /d 7 a 0 , a 1 /d 0 to a 7 /d 6 p3 0 to p3 7 a 8 to a 15 a 8 /d 7 , a 9 to a 15 p4 0 to p4 7 signal name power supply input cnv ss reset input clock input clock output external data bus width select input analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 supply 4.0 to 5.5 v to the v cc pin. supply 0 v to the v ss pin. function this pin switches between processor modes. connect it to the v ss pin to operate in single-chip or memory expansion mode. connect it to the v cc pin to operate in microprocessor mode. a l on this input resets the microcomputer. these pins are provided for the main clock generating circuit.connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin selects the width of an external data bus. a 16-bit width is selected when this input is l; an 8-bit width is selected when this input is h. this input must be fixed to either h or l. when operating in single-chip mode,connect this pin to v ss . this pin is a power supply input for the a-d converter. connect this pin to v cc . this pin is a power supply input for the a-d converter. connect this pin to v ss . this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. when set as a separate bus, these pins input and output data (d 0 Cd 7 ). this is an 8-bit i/o port equivalent to p0. pins in this port also function as external interrupt pins as selected by software. when set as a separate bus, these pins input and output data (d 8 Cd 15 ). these pins output 8 low-order address bits (a 0 Ca 7 ). if the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (d 0 Cd 7 ) and output 8 low-order address bits (a 0 Ca 7 ) separated in time by multiplexing. if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 0 Cd 6 ) and output address (a 1 Ca 7 ) separated in time by multiplexing. they also output address (a 0 ). this is an 8-bit i/o port equivalent to p0. these pins output 8 middle-order address bits (a 8 Ca 15 ). if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 7 ) and output address (a 8 ) separated in time by multiplexing. they also output address (a 9 Ca 15 ). this is an 8-bit i/o port equivalent to p0. pin name input input input output input input input/output input/output input/output input/output i/o type analog power supply input input/output output input/output output input/output input/output output input/output output input/output output output cs 0 to cs 3 , a 16 to a 19 these pins output cs 0 Ccs 3 signals and a 16 Ca 19 . cs 0 Ccs 3 are chip select signals used to specify an access space. a 16 Ca 19 are 4 high- order address bits. reset this is an 8-bit i/o port equivalent to p0. pins in this port also function as a-d converter input pins. pins in this port also function as a-d converter input pins.
8 description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer pin description table 1-4. pin description of m16c/6n group (2) signal name function pin name i/o type i/o port p5 input/output input/output input/output input/output input/output input/output input input/output input/output i/o port p6 i/o port p7 i/o port p8 input port p8 5 i/o port p9 i/o port p10 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 4 , p8 6 , p8 7 , p8 5 p9 0 to p9 7 p10 0 to p10 7 this is an 8-bit i/o port equivalent to p0. in single-chip mode, p5 7 in this port outputs a divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as x cin as selected by software. output output output output output input output input this is an 8-bit i/o port equivalent to p0. pins in this port also function as uart0 and uart1 i/o pins as selected by software. as timer a 0 - a 3 , timer b5, uart2 i/o or can1 transmit/receive data pins as selected by software. this is an 8-bit i/o port equivalent to p0. pins in this port also function as si/o3 i/o pins, timer b0 - b4 input pins, d-a converter output pins, a-d converter extended input pins, a-d trigger input pins or can0 transmit/receive data pins as selected by software. this is an 8-bit i/o port equivalent to p0. pins in this port also function as a-d converter input pins. furthermore, p10 4 - p10 7 also function as input pins for the key input interrupt function. wrl / wr, wrh / bhe, rd, bclk, hlda, hold, ale, rdy output wrl, wrh (wr and bhe), rd, bclk, hlda, and ale signals. wrl and wrh, and bhe and wr can be switched using software control. wrl, wrh, and rd selected with a 16-bit external data bus, data is written to even addresses when the wrl signal is l and to the odd addresses when the wrh signal is l . data is read when rd is l . wr, bhe, and rd selected data is written when wr is l . data is read when rd is l . odd addresses are accessed when bhe is l . use this mode when using an 8-bit external data bus. while the input level at the hold pin is l , the microcomputer is placed in the hold state. while in the hold state, hlda outputs a l level. ale is used to latch the address. while the input level of the rdy pin is l , the microcomputer is in the ready state. bclk outputs a clock with the same cycle as the internal clock f . p8 0 to p8 4 , p8 6 and p8 7 are i/o ports with the same functions as p0. using software, they can be made to function as the i/o pins for timer a4 and the input pins for external interrupts. p8 6 and p8 7 can be set using software to function as the i/o pins for a sub clock generation circuit. in this case, connect a quartz oscillator between p8 6 (x cout pin) and p8 7 (x cin pin). p8 5 is an input-only port that also functions for nmi. the nmi interrupt is generated when the input at this pin changes from h to l . the nmi function cannot be cancelled using software. the pull-up cannot be set for this pin. this is an 8-bit i/o port equivalent to p0. pins in this port also function
9 memory under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer operation of functional blocks the m16c/6n group accommodates several units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as can module, timers, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, and i/o ports. each unit is explained in the following. memory figure 2-1 depicts the memory map of the m16c/6n group. the address space extends the 1m bytes from address 00000 16 to fffff 16 . rom is located from fffff 16 down. for example, in the m306n0mct- xxxfp, there is 128k byte of internal rom from e0000 16 to fffff 16 . the vector table for fixed interrupts such as the reset and nmi are mapped to fffdc 16 to fffff 16 . the starting addresses of the interrupt routines are stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. ram is located from 00400 16 up. for example, in the m306n0mct-xxxfp, 5k bytes of internal ram are mapped to the space from 00400 16 to 017ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, can controller and timers, etc. figure 2-2 to 2-9 are locations of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be implemented as 2-byte instructions, reducing the number of program steps. in memory expansion mode and microprocessor mode, a part of the space is reserved and cannot be used. for example, in the m306n0mct-xxxfp, the following space cannot be used. ? the space between 01800 16 and 03fff 16 (memory expansion and microprocessor modes) ? the space between d0000 16 and dffff 16 (memory expansion mode) figure 2-1. memory map 00000 16 yyyyy 16 fffff 16 00400 16 04000 16 xxxxx 16 d0000 16 external area internal rom area sfr area internal ram area internal reserved area (note 1) internal reserved area (note 2) ffe00 16 fffdc 16 fffff 16 note 1: during memory expansion and microprocessor modes, can not be used. note 2: in memory expansion mode, can not be used. undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi type no. address xxxxx 16 address yyyyy 16 m306n0mc 017ff 16 e0000 16 m306n0fg 02bff 16 c0000 16
10 memory u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-2. location of peripheral unit control registers (1) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 processor mode register 0 (pm0) processor mode register 1(pm1) system clock control register 0 (cm0) system clock control register 1 (cm1) chip select control register (csr) address match interrupt enable register (aier) protect register (prcr) oscillation stop detection register (cm2) watchdog timer start register (wdts) watchdog timer control register (wdc) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) dma0 source pointer (sar0) dma0 destination pointer (dar0) dma0 transfer counter (tcr0) dma0 control register (dm0con) dma1 source pointer (sar1) dma1 destination pointer (dar1) dma1 transfer counter (tcr1) dma1 control register (dm1con) 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 can0/1 wake up interrupt control register (c01wkpic) can0 receive successful interrupt control register (c0recic) can0 transmit successful interrupt control register (c0trmic) int3 interrupt control register (int3ic) timer b5 interrupt control register (tb5ic) timer b4 interrupt control register (tb4ic) timer b3 interrupt control register (tb3ic) can1 receive successful interrupt control register (c1recic) int5 interrupt control register (int5ic) can1 transmit successful interrupt control register (c1trmic) sio3 interrupt control register (s3ic) int4 interrupt control register (int4ic) bus collision detection interrupt control register (bcnic) dma0 interrupt control register (dm0ic) dma1 interrupt control register (dm1ic) can0/1 error interrupt control register (c01erric) a-d conversion interrupt control register (adic) key input interrupt control register (kupic) uart2 transmit interrupt control register (s2tic) uart2 receive interrupt control register (s2ric) uart0 transmit interrupt control register (s0tic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) timer a0 interrupt control register (ta0ic) timer a1 interrupt control register (ta1ic) timer a2 interrupt control register (ta2ic) timer a3 interrupt control register (ta3ic) timer a4 interrupt control register (ta4ic) timer b0 interrupt control register (tb0ic) timer b1 interrupt control register (tb1ic) timer b2 interrupt control register (tb2ic) int0 interrupt control register (int0ic) int1 interrupt control register (int1ic) int2 interrupt control register (int2ic) can0 slot 0: message identifier / dlc can0 slot 0: data field can0 slot 0: time stamp can0 slot 1: message identifier / dlc can0 slot 1: data field can0 slot 1: time stamp
11 memory under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-3. location of peripheral unit control registers (2) 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 0089 16 008a 16 008b 16 008c 16 008d 16 008e 16 008f 16 0090 16 0091 16 0092 16 0093 16 0094 16 0095 16 0096 16 0097 16 0098 16 0099 16 009a 16 009b 16 009c 16 009d 16 009e 16 009f 16 00a0 16 00a1 16 00a2 16 00a3 16 00a4 16 00a5 16 00a6 16 00a7 16 00a8 16 00a9 16 00aa 16 00ab 16 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 00b1 16 00b2 16 00b3 16 00b4 16 00b5 16 00b6 16 00b7 16 00b8 16 00b9 16 00ba 16 00bb 16 00bc 16 00bd 16 00be 16 00bf 16 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c8 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 00fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 can0 slot 6: message identifier / dlc can0 slot 6: data field can0 slot 6: time stamp can0 slot 7: message identifier / dlc can0 slot 7: data field can0 slot 7: time stamp can0 slot 8: message identifier / dlc can0 slot 8: data field can0 slot 8: time stamp can0 slot 9: message identifier / dlc can0 slot 9: data field can0 slot 9: time stamp can0 slot 2: message identifier / dlc can0 slot 2: data field can0 slot 2: time stamp can0 slot 3: message identifier / dlc can0 slot 3: data field can0 slot 3: time stamp can0 slot 4: message identifier / dlc can0 slot 4: data field can0 slot 4: time stamp can0 slot 5: message identifier / dlc can0 slot 5: data field can0 slot 5: time stamp
12 memory u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-4. location of peripheral unit control registers (3) 0100 16 0101 16 0102 16 0103 16 0104 16 0105 16 0106 16 0107 16 0108 16 0109 16 010a 16 010b 16 010c 16 010d 16 010e 16 010f 16 0110 16 0111 16 0112 16 0113 16 0114 16 0115 16 0116 16 0117 16 0118 16 0119 16 011a 16 011b 16 011c 16 011d 16 011e 16 011f 16 0120 16 0121 16 0122 16 0123 16 0124 16 0125 16 0126 16 0127 16 0128 16 0129 16 012a 16 012b 16 012c 16 012d 16 012e 16 012f 16 0130 16 0131 16 0132 16 0133 16 0134 16 0135 16 0136 16 0137 16 0138 16 0139 16 013a 16 013b 16 013c 16 013d 16 013e 16 013f 16 0140 16 0141 16 0142 16 0143 16 0144 16 0145 16 0146 16 0147 16 0148 16 0149 16 014a 16 014b 16 014c 16 014d 16 014e 16 014f 16 0150 16 0151 16 0152 16 0153 16 0154 16 0155 16 0156 16 0157 16 0158 16 0159 16 015a 16 015b 16 015c 16 015d 16 015e 16 015f 16 0160 16 0161 16 0162 16 0163 16 0164 16 0165 16 0166 16 0167 16 0168 16 0169 16 016a 16 016b 16 016c 16 016d 16 016e 16 016f 16 0170 16 0171 16 0172 16 0173 16 0174 16 0175 16 0176 16 0177 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 can0 slot 14: message identifier / dlc can0 slot 14: data field can0 slot 14: time stamp can0 slot 15: message identifier / dlc can0 slot 15: data field can0 slot 15: time stamp can0 global mask (c0gmr) can0 local mask a (c0lmar) can0 local mask b (c0lmbr) can0 slot 10: message identifier / dlc can0 slot 10: data field can0 slot 10: time stamp can0 slot 11: message identifier / dlc can0 slot 11: data field can0 slot 11: time stamp can0 slot 12: message identifier / dlc can0 slot 12: data field can0 slot 12: time stamp can0 slot 13: message identifier / dlc can0 slot 13: data field can0 slot 13: time stamp
13 memory under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-5. location of peripheral unit control registers (4) 01c0 16 01c1 16 01c2 16 01c3 16 01c4 16 01c5 16 01c6 16 01c7 16 01c8 16 01c9 16 01ca 16 01cb 16 01cc 16 01cd 16 01ce 16 01cf 16 01d0 16 01d1 16 01d2 16 01d3 16 01d4 16 01d5 16 01d6 16 01d7 16 01d8 16 01d9 16 01da 16 01db 16 01dc 16 01dd 16 01de 16 01df 16 01e0 16 01e1 16 01e2 16 01e3 16 01e4 16 01e5 16 01e6 16 01e7 16 01e8 16 01e9 16 01ea 16 01eb 16 01ec 16 01ed 16 01ee 16 01ef 16 01f0 16 01f1 16 01f2 16 01f3 16 01f4 16 01f5 16 01f6 16 01f7 16 01f8 16 01f9 16 01fa 16 01fb 16 01fc 16 01fd 16 01fe 16 01ff 16 timer b3,4,5 count start flag (tbsr) timer a1-1 register (ta11) timer a2-1 register (ta21) timer a4-1 register (ta41) three-phase pwm control register 0 (invc0) three-phase pwm control register 1 (invc1) three-phase output buffer register 0 (idb0) three-phase output buffer register 1 (idb1) dead time timer (dtt) timer b2 interrupt occurrence frequency set counter (ictb2) timer b3 register (tb3) timer b4 register (tb4) timer b5 register (tb5) timer b3 mode register (tb3mr) timer b4 mode register (tb4mr) timer b5 mode register (tb5mr) interrupt cause select register 0 (ifsr0) interrupt cause select register 1 (ifsr1) si/o3 transmit/receive register (s3trr) si/o3 control register (s3c) si/o3 bit rate generator (s3brg) uart2 special mode register 2 (u2smr2) uart2 special mode register (u2smr) uart2 transmit/receive mode register (u2mr) uart2 bit rate generator (u2brg) uart2 transmit buffer register (u2tb) uart2 transmit/receive mode register 0 (u2c0) uart2 transmit/receive mode register 1 (u2c1) uart2 receive buffer register (u2rb) 0200 16 0201 16 0202 16 0203 16 0204 16 0205 16 0206 16 0207 16 0208 16 0209 16 020a 16 020b 16 020c 16 020d 16 020e 16 020f 16 0210 16 0211 16 0212 16 0213 16 0214 16 0215 16 0216 16 0217 16 0218 16 0219 16 021a 16 021b 16 021c 16 021d 16 021e 16 021f 16 0220 16 0221 16 0222 16 0223 16 0224 16 0225 16 0226 16 0227 16 0228 16 0229 16 022a 16 022b 16 022c 16 022d 16 022e 16 022f 16 0230 16 0231 16 0232 16 0233 16 0234 16 0235 16 0236 16 0237 16 0238 16 0239 16 023a 16 023b 16 023c 16 023d 16 023e 16 023f 16 can0 message control register 0 (c0mctl0) can0 message control register 1 (c0mctl1) can0 message control register 2 (c0mctl2) can0 message control register 3 (c0mctl3) can0 message control register 4 (c0mctl4) can0 message control register 5 (c0mctl5) can0 message control register 6 (c0mctl6) can0 message control register 7 (c0mctl7) can0 message control register 8 (c0mctl8) can0 message control register 9 (c0mctl9) can0 message control register 10 (c0mctl10) can0 message control register 11 (c0mctl11) can0 message control register 12 (c0mctl12) can0 message control register 13 (c0mctl13) can0 message control register 14 (c0mctl14) can0 message control register 15 (c0mctl15) can0 control register (c0ctlr) can0 status register (c0str) can0 slot status register (c0sstr) can0 slot interrupt control register (c0sicr) can0 extid register (c0idr) can0 configuration register (c0conr) can0 rec register (c0recr) can0 tec register (c0tecr) can0 time stamp register (c0str) can1 message control register 0 (c1mctl0) can1 message control register 1 (c1mctl1) can1 message control register 2 (c1mctl2) can1 message control register 3 (c1mctl3) can1 message control register 4 (c1mctl4) can1 message control register 5 (c1mctl5) can1 message control register 6 (c1mctl6) can1 message control register 7 (c1mctl7) can1 message control register 8 (c1mctl8) can1 message control register 9 (c1mctl9) can1 message control register 10 (c1mctl10) can1 message control register 11 (c1mctl11) can1 message control register 12 (c1mctl12) can1 message control register 13 (c1mctl13) can1 message control register 14 (c1mctl14) can1 message control register 15 (c1mctl15) can1 control register (c1ctlr) can1 status register (c1str) can1 slot status register (c1sstr) can1 slot interrupt control register (c1sicr) can1 extid register (c1idr) can1 configuration register (c1conr) can1 rec register (c1recr) can1 tec register (c1tecr) can1 time stamp register (c1str)
14 memory u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-6. location of peripheral unit control registers (5) 0240 16 0241 16 0242 16 0243 16 0244 16 0245 16 0246 16 0247 16 0248 16 0249 16 024a 16 024b 16 024c 16 024d 16 024e 16 024f 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0260 16 0261 16 0262 16 0263 16 0264 16 0265 16 0266 16 0267 16 0268 16 0269 16 026a 16 026b 16 026c 16 026d 16 026e 16 026f 16 0270 16 0271 16 0272 16 0273 16 0274 16 0275 16 0276 16 0277 16 0278 16 0279 16 027a 16 027b 16 027c 16 027d 16 027e 16 027f 16 peripheral function clock select register (pclkr) can0/1 clock select register (c01clkr) can1 slot 0: message identifier / dlc can1 slot 0: data field can1 slot 0: time stamp can1 slot 1: message identifier / dlc can1 slot 1: data field can1 slot 1: time stamp can1 acceptance filter support register (c1afs) can0 acceptance filter support register (c0afs) 0280 16 0281 16 0282 16 0283 16 0284 16 0285 16 0286 16 0287 16 0288 16 0289 16 028a 16 028b 16 028c 16 028d 16 028e 16 028f 16 0290 16 0291 16 0292 16 0293 16 0294 16 0295 16 0296 16 0297 16 0298 16 0299 16 029a 16 029b 16 029c 16 029d 16 029e 16 029f 16 02a0 16 02a1 16 02a2 16 02a3 16 02a4 16 02a5 16 02a6 16 02a7 16 02a8 16 02a9 16 02aa 16 02ab 16 02ac 16 02ad 16 02ae 16 02af 16 02b0 16 02b1 16 02b2 16 02b3 16 02b4 16 02b5 16 02b6 16 02b7 16 02b8 16 02b9 16 02ba 16 02bb 16 02bc 16 02bd 16 02be 16 02bf 16 can1 slot 2: message identifier / dlc can1 slot 2: data field can1 slot 2: time stamp can1 slot 3: message identifier / dlc can1 slot 3: data field can1 slot 3: time stamp can1 slot 4: message identifier / dlc can1 slot 4: data field can1 slot 4: time stamp can1 slot 5: message identifier / dlc can1 slot 5: data field can1 slot 5: time stamp
15 memory under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-7. location of peripheral unit control registers (6) 02c0 16 02c1 16 02c2 16 02c3 16 02c4 16 02c5 16 02c6 16 02c7 16 02c8 16 02c9 16 02ca 16 02cb 16 02cc 16 02cd 16 02ce 16 02cf 16 02d0 16 02d1 16 02d2 16 02d3 16 02d4 16 02d5 16 02d6 16 02d7 16 02d8 16 02d9 16 02da 16 02db 16 02dc 16 02dd 16 02de 16 02df 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02eb 16 02ec 16 02ed 16 02ee 16 02ef 16 02f0 16 02f1 16 02f2 16 02f3 16 02f4 16 02f5 16 02f6 16 02f7 16 02f8 16 02f9 16 02fa 16 02fb 16 02fc 16 02fd 16 02fe 16 02ff 16 can1 slot 6: message identifier / dlc can1 slot 6: data field can1 slot 6: time stamp can1 slot 7: message identifier / dlc can1 slot 7: data field can1 slot 7: time stamp can1 slot 8: message identifier / dlc can1 slot 8: data field can1 slot 8: time stamp can1 slot 9: message identifier / dlc can1 slot 9: data field can1 slot 9: time stamp 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030a 16 030b 16 030c 16 030d 16 030e 16 030f 16 0310 16 0311 16 0312 16 0313 16 0314 16 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 031c 16 031d 16 031e 16 031f 16 0320 16 0321 16 0322 16 0323 16 0324 16 0325 16 0326 16 0327 16 0328 16 0329 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 can1 slot 10: message identifier / dlc can1 slot 10: data field can1 slot 10: time stamp can1 slot 11: message identifier / dlc can1 slot 11: data field can1 slot 11: time stamp can1 slot 12: message identifier / dlc can1 slot 12: data field can1 slot 12: time stamp can1 slot 13: message identifier / dlc can1 slot 13: data field can1 slot 13: time stamp
16 memory u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-8. location of peripheral unit control registers (7) 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 can1 slot 14: message identifier / dlc can1 slot 14: data field can1 slot 14: time stamp can1 slot 15: message identifier / dlc can1 slot 15: data field can1 slot 15: time stamp can1 global mask (c1gmr) can1 local mask a (c1lmar) can1 local mask b (c1lmbr) count start flag (tabsr) clock prescaler reset flag (cpsrf) one-shot start flag (onsf) trigger select register (trgsr) up-down flag (udf) timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) timer a3 (ta3) timer a4 (ta4) timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) uart0 transmit/receive mode register (u0mr) uart0 bit rate generator (u0brg) uart0 transmit buffer register (u0tb) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 bit rate generator (u1brg) uart1 transmit buffer register (u1tb) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart1 receive buffer register (u1rb) uart transmit/receive control register 2 (ucon) flash memory control register 2 (fmcr2) flash memory control register (fmcr) dma0 cause select register (dm0sl) dma1 cause select register (dm1sl) crc data register (crcd) crc input register (crcin) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16
17 memory under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 2-9. location of peripheral unit control registers (8) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) a-d register 7 (ad7) a-d control register 2 (adcon2) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) port p0 (p0) port p1 (p1) port p0 direction register (pd0) port p1 direction register (pd1) port p2 (p2) port p3 (p3) port p2 direction register (pd2) port p3 direction register (pd3) port p4 (p4) port p5 (p5) port p4 direction register (pd4) port p5 direction register (pd5) port p6 (p6) port p7 (p7) port p6 direction register (pd6) port p7 direction register (pd7) port p8 (p8) port p9 (p9) port p8 direction register (pd8) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) pull-up control register 2 (pur2) port control register (pcr) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16
18 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can be used as 32-bit data registers (r2r0/r3r1). (2) address rgisters (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). figure 3-1. central processing unit register central processing unit (cpu) the cpu has a total of 13 registers shown in figure 3-1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these registers have two register banks. cpu h l b15 b8 b7 b0 r0 (note) h l b15 b8 b7 b0 r1 (note) r2 (note) b15 b0 r3 (note) b15 b0 a0 (note) b15 b0 a1 (note) b15 b0 fb (note) b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. c d z s b o i u ipl
19 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (3) frame base register (fb) the frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) the program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) the interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointers come in two types: the user stack pointer (usp) and the interrupt stack pointer (isp), each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) the static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) the flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 3-2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation results in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation results in a negative value; otherwise, cleared to 0. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation results in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged. cpu
20 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer ? bit 7: stack pointer select flag (u flag) the interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has a priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. figure 3-2. flag register (flg) cpu carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) c d z s b o i u ipl b0 b15
21 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer processor mode (1) processor mode types one of three processor modes can be selected: single-chip mode, memory expansion mode and micro- processor mode. the functions of some pins, the memory map and the access space differ according to the selected processor mode. ? single-chip mode in single-chip mode, only internal memory space (sfr, internal ram, and internal rom) can be accessed. ports p0 to p10 can be used as programmable i/o ports or as i/o ports for the internal peripheral functions. ? memory expansion mode in memory expansion mode, external memory can be accessed in addition to the internal memory space (sfr, internal ram, and internal rom). in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus set- tings for details.) ? microprocessor mode in microprocessor mode, the sfr, internal ram, and external memory space can be accessed. the internal rom area cannot be accessed. in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus set- tings for details.) (2) setting processor modes the processor mode is set using the cnv ss pin and the processor mode bits (bits 1 and 0 at address 0004 16 ). do not set the processor mode bits to 10 2 . regardless of the level of the cnv ss pin, changing the processor mode bits selects the mode. therefore, never change the processor mode bits when changing the contents of other bits. also do not attempt to shift to or from the microprocessor mode within the program stored in the internal rom area. ? applying v ss to cnv ss pin the microcomputer begins operation in single-chip mode after being reset. memory expansion mode is selected by writing 01 2 to the processor mode is selected bits. ? applying v cc to cnv ss pin the microcomputer starts to operate in microprocessor mode after being reset. figure 3-3 shows the processor mode register 0 and 1. figure 3-4 shows the memory maps applicable for each of the modes when memory area dose not be expanded (normal mode). processor mode
22 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer processor mode figure 3-3. processor mode register 0 and 1 processor mode register 0 (note 1) symbol address when reset pm0 0004 16 00 16 (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0: single-chip mode 0 1: memory expansion mode 1 0: inhibited 1 1: microprocessor mode b1 b0 pm03 pm01 pm00 processor mode bit pm02 r/w mode select bit 0 : rd,bhe,wr 1 : rd,wrh,wrl software reset bit the device is reset when this bit is set to 1. the value of this bit is 0 when read. pm04 0 0 : multiplexed bus is not used 0 1 : allocated to cs2 space 1 0 : allocated to cs1 space 1 1 : allocated to entire space (note4) b5 b4 multiplexed bus space select bit pm05 pm06 pm07 port p4 0 to p4 3 function select bit (note 3) 0 : address output 1 : port function (address is not output) bclk output disable bit 0 : bclk is output 1 : bclk is not output (pin is left floating) note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: if the v cc voltage is applied to the cnv ss , the value of this register when reset is 03 16 . (pm00 and pm01 both are set to 1.) note 3: valid in microprocessor and memory expansion modes. note 4: if the entire space is of multiplexed bus in memory expansion mode, choose an 8- bit width.the processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. the higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. processor mode register 1 (note 1) symbol address when reset pm1 0005 16 00000xx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. reserved bit must always be set to 0 0 note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: be sure to set this bit to 0 except products whose ram size and rom size exceed 15k bytes and 192k bytes respectively. set this bit to "1" for m306n0fg. specify e0000 16 or a subsequent address, which becomes an internal rom area if pm13 is set to 0 at the time reset is revoked, for the reset vector table of user program. note 3: with the processor running in memory expansion mode or in microprocessor mode, setting this bit provides the means of expanding the external memory area. (normal mode: up to 1m byte, expansion mode 1: up to 1.2 m bytes, expansion mode 2: up to 4m bytes) for details, see memory space expansion functions. pm17 wait bit 0 : no wait state 1 : wait state inserted memory area expansion bit (note 3) 0 0 : normal mode (do not expand) 0 1 : inhibited 1 0 : memory area expansion mode 1 1 1 : memory area expansion mode 2 b5 b4 pm15 pm14 reserved bit must always be set to 0 0 internal reserved area expansion bit (note 2) pm13 0: the same internal reserved area as that of m16c/60 and m16c/61 group 1: expands the internal ram area and internal rom area to 23 k bytes and to 256k bytes respectively. (note 2)
23 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer processor mode figure 3-4. memory maps in each processor mode single-chip mode sfr area internal ram area inhibited internal rom area microprocessor mode sfr area internal ram area external area internally reserved area 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 external area : accessing this area allows the user to access a device connected externally to the microcomputer. 04000 16 memory expansion mode sfr area internal ram area external area internal rom area internally reserved area internally reserved area type no. address xxxxx 16 address yyyyy 16 m306n0mc 017ff 16 e0000 16 02bff 16 c0000 16 m306n0fg
24 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer bus setting switching factor switching external address bus width bit 6 of processor mode register 0 switching external data bus width byte pin switching between separate and multiplex bus bits 4 and 5 of processor mode register 0 (1) selecting external address bus width the address bus width for external output in the 1m bytes of address space can be set to 16 bits (64k bytes address space) or 20 bits (1m bytes address space). when bit 6 of the processor mode register 0 is set to 1, the external address bus width is set to 16 bits, and p2 and p3 become part of the address bus. p4 0 to p4 3 can be used as programmable i/o ports. when bit 6 of processor mode register 0 is set to 0, the external address bus width is set to 20 bits, and p2, p3, and p4 0 to p4 3 become part of the address bus. (2) selecting external data bus width the external data bus width can be set to 8 or 16 bits. (note, however, that only the separate bus can be set.) when the byte pin is l, the bus width is set to 16 bits; when h, it is set to 8 bits. (the internal bus width is permanently set to 16 bits.) (3) selecting separate/multiplex bus the bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. ? separate bus in this mode, the data and address are input and output separately. the data bus can be set using the byte pin to be 8 or 16 bits. when the byte pin is h, the data bus is set to 8 bits and p0 functions as the data bus and p1 as a programmable i/o port. when the byte pin is l, the data bus is set to 16 bits and p0 and p1 are both used for the data bus. when the separate bus is used for access, a software wait can be selected. ? multiplex bus in this mode, data and address i/o are time multiplexed. with an 8-bit data bus selected (byte pin = h), the 8 bits from d 0 to d 7 are multiplexed with a 0 to a 7 . with a 16-bit data bus selected (byte pin = l), the 8 bits from d 0 to d 7 are multiplexed with a 1 to a 8 . d 8 to d 15 are not multiplexed. in this case, the external devices connected to the multiplexed bus are mapped to the microcomputers even addresses (every 2nd address). to access these external de- vices, access the even addresses as bytes. the ale signal latches the address. it is output from p5 6 . before accessing the multiplex bus, always set the csi wait bit of the chip select control register to 0. in microprocessor mode, multiplexed bus for the entire space cannot be selected. in memory expansion mode, when multiplexed bus for the entire space is selected, address bus range is 256 bytes in each chip select. table 3-1. factors for switching bus settings bus settings bus settings the byte pin and bits 4 to 6 of the processor mode register 0 (address 0004 16 ) are used to change the bus settings. table 3-1 shows the factors used to change the bus settings.
25 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer bus settings table 3-2. pin functions for each processor mode p0 0 to p0 7 i/o port data bus data bus data bus data bus i/o port multiplexed bus and separate bus separate bus multiplexed bus (note 1) single-chip mode memory expansion mode/microprocessor modes memory expansion mode external bus type data bus width byte pin level port p4 0 to p4 3 function select bit = 0 01 , 10 00 11 (note 2) 8 bita = h 8 bits = h 16 bits = l 8 bits = h 16 bits = l note 1: in memory expansion mode, do not select a 16-bit multiplex bus. note 2: in microprocessor mode, multiplexed bus for the entire space cannot be selected. in memory expansion mode, when multiplexed bus for the entire space is selected, address bus range is 256 bytes in each chip select. note 3: address bus when in separate bus mode. processor mode multiplexed bus space select bit cs (chip select) or programmable i/o port (for details, refer to bus control ) outputs rd, wrl, wrh, and bclk or rd, bhe, wr, and bclk (for details, refer to bus control ) port p4 0 to p4 3 function select bit = 1 p1 0 to p1 7 i/o port i/o port data bus i/o port data bus i/o port p2 1 to p2 7 i/o port address bus address bus address bus address bus address bus /data bus (note 3) /data bus (note 3) /data bus p2 0 i/o port address bus address bus address bus address bus address bus /data bus (note 3) /data bus p3 0 i/o port address bus address bus address bus address bus i/o port /data bus (note 3) p3 1 to p3 7 i/o port address bus address bus address bus address bus i/o port p4 0 to p4 3 i/o port i/o port i/o port /o port i/o port i/o port p4 0 to p4 3 i/o port address bus address bus address bus address bus i/o port p4 4 to p4 7 i/o port p5 0 to p5 3 i/o port p5 4 i/o port hlda hlda hlda hlda hlda p5 5 i/o port hold hold hold hold hold p5 6 i/o port ale ale ale ale ale p5 7 i/o port rdy rdy rdy rdy rdy
26 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer bus control the following explains the signals required for accessing external devices and software waits. the signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. the software waits are valid in all processor modes. (1) address bus/data bus the address bus consists of the 20 pins a 0 to a 19 for accessing the 1m bytes of address space. the data bus consists of the pins for data i/o. when the byte pin is h, the 8 ports d 0 to d 7 function as the data bus. when byte is l, the 16 ports d 0 to d 15 function as the data bus. both the address and data bus retain their previous states when internal rom or ram is accessed. also, when a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) chip select signal the chip select signal is output using the same pins as p4 4 to p4 7 . bits 0 to 3 of the chip select control register (address 0008 16 ) set each pin to function as a port or to output the chip select signal. the chip select control register is valid in memory expansion mode and microprocessor mode. in single-chip mode, p4 4 to p4 7 function as programmable i/o ports regardless of the value in the chip select control register. in microprocessor mode, only cs0 outputs the chip select signal after the reset state has been can- celled. cs1 to cs3 function as input ports. figure 3-5 shows the chip select control register. the chip select signal can be used to split the external area into as many as four blocks. table 3-3 shows the external memory areas specified using the chip select signal. table 3-3. external areas specified by the chip select signals special address range memory expansion mode 30000 16 to cffff 16 (640k) 28000 16 to 2ffff 16 (32k) 08000 16 to 27fff 16 (128k) 04000 16 to 07fff 16 (16k) chip select cs0 microprocessor mode 30000 16 to fffff 16 (832k) 28000 16 to 2ffff 16 (32k) 08000 16 to 27fff 16 (128k) 04000 16 to 07fff 16 (16k) cs1 cs2 cs3
27 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 3-5. chip select control register table 3-5. operation of rd, wr, and bhe signals note: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1. w function bit symbol bit name chip select control register symbol address when reset csr 0008 16 01 16 r b7 b6 b5 b4 b3 b2 b1 b0 cs1 cs0 cs3 cs2 cs0 output enable bit cs1 output enable bit cs2 output enable bit cs3 output enable bit cs1w cs0w cs3w cs2w cs0 wait bit cs1 wait bit cs2 wait bit cs3 wait bit 0 : chip select output disabled (normal port pin) 1 : chip select output enabled 0 : wait state inserted 1 : no wait state status of external data bus read data write 1 byte of data to even address write 1 byte of data to odd address write data to both even and odd addresses wrh wrl rd data bus width 16-bit (byte = l ) h h h h l h l h h l l l status of external data bus rd bhe wr hll lhl hlh lhh write 1 byte of data to odd address read 1 byte of data from odd address write 1 byte of data to even address read 1 byte of data from even address data bus width a0 h h l l hll l lhl l h l h / l l h h / l 8-bit (byte = h ) write data to both even and odd addresses read data from both even and odd addresses write 1 byte of data read 1 byte of data 16-bit (byte = l ) not used not used (3) read/write signals with a 16-bit data bus (byte pin =l), bit 2 of the processor mode register 0 (address 0004 16 ) select the combinations of rd, bhe, and wr signals or rd, wrl, and wrh signals. with an 8-bit data bus (byte pin = h), use the combination of rd, wr, and bhe signals. (set bit 2 of the processor mode register 0 (address 0004 16 ) to 0.) tables 3-4 and 3-5 show the operation of these signals. after a reset has been cancelled, the combination of rd, wr, and bhe signals is automatically selected. when switching to the rd, wrl, and wrh combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16 ) has been set (note). table 3-4. operation of rd, wrl, and wrh signals
28 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (4) ale signal the ale signal latches the address when accessing the multiplex bus space. latch the address when the ale signal falls. figure 3-7. example of rd signal extended by rdy signal note: the ready signal cannot be received immediately prior to a software wait. figure 3-6. ale sigal and address/data bus table 3-6. microcomputer status in ready state (note) item status oscillation on r/w signal, address bus, data bus, cs maintain status when ready signal received ale signal, hlda, programmable i/o ports internal peripheral circuits on when byte pin = h when byte pin = l ale address data (note 1) address (note 2) d 0 /a 0 to d 7 /a 7 a 8 to a 19 ale address data (note 1) address d 0 /a 1 to d 7 /a 8 a 9 to a 19 address a 0 note 1: floating when reading. note 2: when multiplexed bus for the entire space is selected, these are i/o ports. bclk rd csi (i = 0 to 3) rdy tsu (rdy C bclk) : wait using ready function : wait using software (5) ready signal the ready signal facilitates access of external devices that require a long time for access. as shown in figure 3-7, inputting l to the rdy pin at the falling edge of bclk causes the microcomputer to enter the ready state. inputting h to the rdy pin at the falling edge of bclk cancels the ready state. table 3-6 shows the microcomputer status in the ready state. figure 3-7 shows the example of the rd signal being extended using the rdy signal. ready is valid when accessing the external area during the bus cycle in which the software wait is applied.
29 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer table 3-7. microcomputer status in hold state item status oscillation on r/w signal, address bus, data bus, cs, bhe floating programmable i/o ports p0, p1, p2, p3, p4, p5 floating p6, p7, p8, p9, p10 main tains status when hold signal is received hlda output l internal peripheral circuits on (but watchdog timer stops) ale signal undefined (7) bclk output the output of the internal clock f can be selected using bit 7 of the processor mode register 0 (address 0004 16 ) (note). the output is floating when bit 7 is set to 1. note: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1. (6) hold signal the hold signal is used to transfer the bus privileges from the cpu to the external circuits. inputting l to the hold pin places the microcomputer in the hold state at the end of the current bus access. this status is maintained and l is output from the hlda pin as long as l is input to the hold pin. table 3-7 shows the microcomputer status in the hold state.
30 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (8) software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note) and bits 4 to 7 of the chip select control register (address 0008 16 ). a software wait is inserted in the internal rom/ram area and in the external memory area by setting the wait bit of the processor mode register 1. when set to 0, each bus cycle is executed in one bclk cycle. when set to 1, each bus cycle is executed in two or three bclk cycles. after the microcomputer has been reset, this bit defaults to 0. when set to 1, bits 4 to 7 of the chip select control register are invalid and a wait is applied to all external memory areas (two or three bclk cycles). however, this is not necessary if the oscillation frequency is less than 3mhz. when the wait bit of the processor mode register 1 is 0, software waits can be set independently for each of the 4 areas selected using the chip select signal. bits 4 to 7 of the chip select control register correspond to chip selects cs0 to cs3. when one of these bits is set to 1, the bus cycle is executed in one bclk cycle. when set to 0, the bus cycle is executed in two or three bclk cycles. these bits default to 0 after the microcomputer has been reset. the sfr area is always accessed in two bclk cycles regardless of the setting of these control bits. also, the corresponding bits of the chip select control register must be set to 0 if using the multiplex bus to access the external memory area. table 3-8 shows the software wait and bus cycles. figure 3-8 shows example bus timing when using software waits. note: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1. table 3-8. software waits and bus cycles area bus status wait bit bits 4 to 7 of chip select control register bus cycle invalid 1 2 bclk cycles external memory area separate bus 0 1 1 bclk cycle separate bus 0 0 2 bclk cycles separate bus 1 0 (note) 2 bclk cycles multiplex bus 0 0 (note) 3 bclk cycles multiplex bus 1 3 bclk cycles 0 (note) sfr internal rom/ram 0 invalid 1 bclk cycle invalid invalid 2 bclk cycles note: always set to "0".
31 bus control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 3-8. typical bus timings using software wait output input address address bus cycle < separate bus (with wait) > bclk read signal write signal data bus address bus chip select bclk read signal address bus/ data bus chip select address address address bus data output address address input ale bus cycle < multiplexed bus > write signal bclk read signal write signal address bus address address bus cycle < separate bus (no wait) > output data bus chip select input
32 bus control under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 3-9 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control register 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ), peripheral function clock select register (address 025e 16 ), can0/1 clock select register (address 025f 16 ), serial i/o 3 control register (01e2 16 ), port p7 direction register (address 03ef 16 ) and port p9 direction register (address 03f3 16 ) can only be changed when the respective bit in the protect register is set to 1. therefore, important outputs can be allocated to port p7 or port p9. if, after 1 (write-enabled) has been written to the port p7 or port p9 direction registers write-enable bit (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to 0 (write-inhibited). however, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. figure 3-9. protect register protection protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to the system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ), oscillation stop detection register (address 000c 16 ), peripheral function clock select regis- ter (address 025e 16 ), and can0/1 clock select register (address 025f 16 ) enables writing to port p7/9 direction register (address 03f3 16 and 03ef 16 ) and si/o3 control register (address 01e2 16 ) (note) 0 : write-inhibited 1 : write-enabled w r nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. note: writing a value to an address after 1 is written to this bit returns the bit to 0 . other bits do not automatically return to 0 and they must therefore be reset by the program.
33 reset under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 4-2. reset sequence reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles of f(x in ). when the reset pin level is then returned to the h level while main clock is stable, the reset status is released and program execution resumes from the address in the reset vector table. figure 4-1 shows the example reset circuit. figure 4-2 shows the reset sequence. figure 4-1. example reset circuit reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v example when v cc = 5v . bclk address address address microprocessor mode byte = h microprocessor mode byte = l content of reset vector single chip mode bclk 24cycles ffffc 16 ffffd 16 ffffe 16 content of reset vector ffffc 16 ffffe 16 content of reset vector ffffe 16 x in reset rd wr cs0 rd wr cs0 ffffc 16 more than 20 cycles are needed
34 reset under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer table 4-1 shows the statuses of the other pins while the reset pin level is l. figures 4-3, 4-4 and 4-5 show the internal status of the microcomputer immediately after the reset is released. status cnv ss = v cc cnv ss = v ss byte = v ss byte = v cc pin name p0 p1 p2, p3, p4 0 to p4 3 p4 4 p4 5 to p4 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p6, p7, p8 0 to p8 4 , p8 6 , p8 7 , p9, p10 input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) data input (floating) data input (floating) address output (undefined) bclk output ale output ( l level is output) cs0 output ( h level is output) wr output ( h level is output) rd output ( h level is output) rdy input (floating) input port (floating) bclk output bhe output (undefined) hlda output (the output value depends on the input to the hold pin) hold input (floating) data input (floating) address output (undefined) cs0 output ( h level is output) input port (floating) (pull-up resistor is on) input port (floating) input port (floating) rdy input (floating) ale output ( l level is output) hold input (floating) hlda output (the output value depends on the input to the hold pin) rd output ( h level is output) bhe output (undefined) wr output ( h level is output) input port (floating) (pull-up resistor is on) table 4-1. pin status when reset pin level is l
35 reset under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 4-3. device's internal status after a reset is cleared x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note: when the v cc level is applied to the cnv ss pin, it is 03 16 at a reset. (1) (0004 16 ) processor mode register 0 (note) 00 16 (2) (0005 16 ) processor mode register 1 0 0 0 (3) (0006 16 ) system clock control register 0 1 00 00 10 0 (4) (0007 16 ) system clock control register 1 0 00 10 00 0 (5) (0008 16 ) chip select control register 0 00 00 01 0 (6) (0009 16 ) address match interrupt enable register 0 0 (7) protect register (000a 16 ) 00 0 (8) (000f 16 ) watchdog timer control register 0 0? 0???? (10) (0014 16 ) address match interrupt register 1 (0015 16 ) (0016 16 ) 0 00 16 00 16 0 0 0 (11) (002c 16 ) dma0 control register 00000?00 (12) (003c 16 ) dma1 control register 00000?00 (23) (004b 16 ) dma0 interrupt control register ? 0 0 0 (24) (004c 16 ) dma1 interrupt control register ? 0 0 0 (25) (004d 16 ) ? 0 0 0 (22) (004a 16 ) bus collision detection interrupt control register 0 0 0 ? (0010 16 ) address match interrupt register 0 (0011 16 ) (0012 16 ) 0 00 16 00 16 0 0 0 (9) (16) (0044 16 ) int3 interrupt control register 00?000 (17) (0045 16 ) timer b5 interrupt control register ?000 (18) (0046 16 ) timer b4 interrupt control register ?000 (19) (0047 16 ) timer b3 interrupt control register ?000 (20) (0048 16 ) 00?000 (21) (0049 16 ) 00?000 (26) a-d conversion interrupt control register (004e 16 ) ? 0 0 0 (27) (28) (29) (30) (31) (32) (004f 16 ) uart2 transmit interrupt control register (0050 16 ) uart2 receive interrupt control register (0051 16 ) uart0 transmit interrupt control register (0052 16 ) uart0 receive interrupt control register (0053 16 ) uart1 transmit interrupt control register (0054 16 ) uart1 receive interrupt control register ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 (33) (34) (35) (36) (37) (38) (39) (0055 16 ) timer a0 interrupt control register (0056 16 ) timer a1 interrupt control register (0057 16 ) timer a2 interrupt control register (0058 16 ) timer a3 interrupt control register (0059 16 ) timer a4 interrupt control register (005a 16 ) timer b0 interrupt control register (005b 16 ) timer b1 interrupt control register ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 (40) (005c 16 ) timer b2 interrupt control register ? 0 0 0 (41) (005d 16 ) int0 interrupt control register ? 000 00 (42) (005e 16 ) int1 interrupt control register ? 000 00 (43) (005f 16 ) int2 interrupt control register ? 000 00 (47) (01ca 16 ) three-phase output buffer register 0 00 16 (48) (01cb 16 ) three-phase output buffer register 1 00 16 (01c8 16 ) three-phase pwm control register 0 00 16 (45) (01c9 16 ) three-phase pwm control register 1 00 16 (46) (44) (01c0 16 ) timer b3,4,5 count start flag 00 16 00? 0000 (49) (01db 16 ) timer b3 mode register 00? 0000 (50) (01dc 16 ) timer b4 mode register 00? 0000 (51) (01dd 16 ) timer b5 mode register (53) (01df 16 ) interrupt cause select register1 00 16 (13) (0041 16 ) ?000 (14) (0042 16 ) can0 receive successful interrupt ?000 (15) (0043 16 ) ?000 can0/1 wake up interrupt control register control register can0 transmit successful interrupt control register can1 receive successful interrupt control register can1 transmit successful interrupt control register can0/1 state/error interrupt control register (52) (01de 16 ) interrupt cause select register0 0 0 uart2 transmit/receive control register 1 uart2 transmit/receive control register 0 (01f8 16 ) (01fd 16 ) (01fc 16 ) 00 16 000 00001 010 00000 (58) uart2 transmit/receive mode register (56) (57) (01e2 16 ) 40 16 si/o3 control register (54) (01f7 16 ) 00 16 uart2 special mode register (55) 0 0?
36 reset under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 4-4. device's internal status after a reset is cleared (59)can0 message control register 0 (0200 16 )... (60)can0 message control register 1 (0201 16 )... (61)can0 message control register 2 (0202 16 )... (62)can0 message control register 3 (0203 16 )... (63)can0 message control register 4 (0204 16 )... (64)can0 message control register 5 (0205 16 )... (65)can0 message control register 6 (0206 16 )... (66)can0 message control register 7 (0207 16 )... (67)can0 message control register 8 (0208 16 )... (68)can0 message control register 9 (0209 16 )... (69)can0 message control register 10 (020a 16 )... (70)can0 message control register 11 (020b 16 )... (71)can0 message control register 12 (020c 16 )... (72)can0 message control register 13 (020d 16 )... (73)can0 message control register 14 (020e 16 )... (74)can0 message control register 15 (020f 16 )... (75)can0 control register (0210 16 )... (0211 16 )... (76)can0 status register (0212 16 )... (0213 16 )... (77)can0 slot status register (0214 16 )... (0215 16 )... (78)can0 interrupt control register (0216 16 )... (0217 16 )... (79)can0 extid register (0218 16 )... (0219 16 )... (80)can0 configuration register (021a 16 )... (021b 16 )... (81)can0 rec register (021c 16 )... (82)can0 tec register (021d 16 )... (83)can0 time stamp register (021e 16 )... x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. 000 0001 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 000 0001 0 00 16 00 16 00 16 00 16 00 16 00 16 xx 16 xx 16 00 16 00 16 00 16 (84)can1 message control register 0 (0220 16 )... (85)can1 message control register 1 (0221 16 )... (86)can1 message control register 2 (0222 16 )... (87)can1 message control register 3 (0223 16 )... (88)can1 message control register 4 (0224 16 )... (89)can1 message control register 5 (0225 16 )... (90)can1 message control register 6 (0226 16 )... (91)can1 message control register 7 (0227 16 )... (92)can1 message control register 8 (0228 16 )... (93)can1 message control register 9 (0229 16 )... (94)can1 message control register 10 (022a 16 )... (95)can1 message control register 11 (022b 16 )... (96)can1 message control register 12 (022c 16 )... (97)can1 message control register 13 (022d 16 )... (98)can1 message control register 14 (022e 16 )... (99)can1 message control register 15 (022f 16 )... (100)can1 control register (0230 16 )... (0231 16 )... (101)can1 status register (0232 16 )... (0233 16 )... (102)can1 slot status register (0234 16 )... (0235 16 )... (103)can1 interrupt control register (0236 16 )... (0237 16 )... (104)can1 extid register (0238 16 )... (0239 16 )... (105)can1 configuration register (023a 16 )... (023b 16 )... (106)can1 rec register (023c 16 )... (107)can1 tec register (023d 16 )... (108)can1 time stamp register (023e 16 )... 000 0001 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 000 0001 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 xx 16 xx 16
37 reset under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. figure 4-5. device's internal status after a reset is cleared he initial values x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. t must therefore be set. note: when the v cc level is applied to the cnv ss pin, it is 02 16 at a reset. (136) a-d control register 0 (03d6 16 )... (137) a-d control register 1 (03d7 16 )... (138) d-a control register (03dc 16 )... (139) port p0 direction register (03e2 16 )... (140) port p1 direction register (03e3 16 )... (141) port p2 direction register (03e6 16 )... (142) port p3 direction register (03e7 16 )... (143) port p4 direction register (03ea 16 )... (144) port p5 direction register (03eb 16 )... (145) port p6 direction register (03ee 16 )... (146) port p7 direction register (03ef 16 )... (147) port p8 direction register (03f2 16 )... (148) port p9 direction register (03f3 16 )... (149) port p10 direction register (03f6 16 )... (150) pull-up control register 0 (03fc 16 )... (151) pull-up control register 1 (note) (03fd 16 )... (152) pull-up control register 2 (03fe 16 )... (153) port control register (03ff 16 )... (154) data registers (r0/r1/r2/r3) (155) address registers (a0/a1) (156) frame base register (fb) (157) interrupt table register (intb) (158) user stack pointer (usp) (159) interrupt stack pointer (isp) (160) static base register (sb) (161) flag register (flg) 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0000 16 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 00 0 0 000 00 16 00 16 (109) peripheral function clock select register (025e 16 )... (110) can0/1 clock select register (025f 16 )... (111) count start flag (0380 16 )... (112) clock prescaler reset flag (0381 16 )... (113) one-shot start flag (0382 16 )... (114) trigger select flag (0383 16 )... (115) up-down flag (0384 16 )... (116) timer a0 mode register (0396 16 )... (117) timer a1 mode register (0397 16 )... (118) timer a2 mode register (0398 16 )... (119) timer a3 mode register (0399 16 )... (120) timer a4 mode register (039a 16 )... (121) timer b0 mode register (039b 16 )... (122) timer b1 mode register (039c 16 )... (123) timer b2 mode register (039d 16 )... (124) uart0 transmit/receive mode register (03a0 16 )... (125) uart0 transmit/receive control register 0(03a4 16 )... (126) uart0 transmit/receive control register 1(03a5 16 )... (127) uart1 transmit/receive mode register (03a8 16 )... (128) uart1 transmit/receive control register 0(03ac 16 )... (129) uart1 transmit/receive control register 1(03ad 16 )... (130) uart transmit/receive control register 2 (03b0 16 )... (131) flash memory control register 2 (03b6 16 )... (132) flash memory control register (03b7 16 )... (133) dma0 cause select register (03b8 16 )... (134) dma1 cause select register (03ba 16 )... (135) a-d control register 2 (03d4 16 )... 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00? 0000 00? 0000 00? 0000 00 16 000 1000 0 000 0010 0 00 16 000 1000 0 000 0010 0 00 0000 0 00 16 00 16 0 000 0??? 0 00 16 0 00 0000 00 16 0 00 16 0 0 0 0 0 00001 0 0
38 clock generating circuit under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd figure 5-1. examples of main clock figure 5-2. examples of sub clock example of oscillator circuit figure 5-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 5-2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 5-1 and 5-2 vary with each oscillator used. use the values recom- mended by the manufacturer of your oscillator. microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. main clock generating circuit sub clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/bs count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input table 5-1. main clock and sub clock generating circuits
39 clock generating circuit under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 5-3. clock generating circuit clock control figure 5-3 shows the block diagram of the clock generating circuit. sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 1 write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 2 f 2ad q s r nmi interrupt request level judgment output reset software reset f c cm07=0 cm07=1 a g 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 g a details of divider x in f 8 b d 1/2 f f 8sio2 internal clock f b c e f 32 c d e f cclki:bit i at address 025f 16 0 0 0 a 0 0 1 b 0 1 0 c 0 1 1 d 1 0 0 e b 6 b 5 b 4 c01clkr c01clkr f 2sio2 pclk0=1 pclk0=0 pclk0=0 pclk0=0 pclk0=1 pclk0=1 f 32sio2 f can1 f can0 f can1 f can0 selector 0 0 0 a 0 0 1 b 0 1 0 c 0 1 1 d 1 0 0 e b 2 b 1 b 0 ring oscillator divider main clock circuit switching oscillation stop detection circuit a ring oscillator is built in the microcomputer. you can use it, instead of xin, as a main clock by setup of the bit 1 of the oscillation stop detect register. you can use it when for example at such a wait time as executing confirmation of port value only. at this time, the frequency generated by the ring oscillator is low enough, compared to xin, to realize a low power consumption.
40 clock generating circuit under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer the following paragraphs describe the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to form the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock reduces the power consumption. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the x out pin can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the x out pin reduces the power consumption. this bit defaults to 1 when shifting to stop mode and after a reset. you can switch over from the main clock to the ring oscillator by changing the value of the main clock switch bit (bit 5 at address 000c 16 ). (2) sub clock the sub clock is generated by the sub clock oscillation circuit. no sub clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub clock oscillation has fully stabilized before switching. after the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the x cout pin can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the x cout pin reduces the power consumption. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu and the watchdog timer, i.e. the internal clock f , and is either the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. after a reset the bclk is derived by dividing the main clock by 8 . when shifting to stop mode, the main clock division select bit (bit 6 at 0006 16 ) is set to 1. (4) peripheral function clocks ? f 2 , f 8 , f 32, f 2sio2, f 8sio2 , f 32sio2 the clock for the peripheral devices is derived by dividing the main clock by 2(or no division), 8 or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. as to f 2 and f 2sio2, you can select division by 2 or no division by changing the value of the peripheral function clock select register. select the mode without division only when xin is 16 mhz or lower. ? f 2ad this clock is derived by dividing the main clock by 2(or no division) and is used for a-d conversion. you can select division by 2 or no division by changing the value of the peripheral function clock select register. ? f can0 ,f can1 these clocks are derived by dividing the main clock by 1, 2, 4, 8 or 16 and they are used for the corresponding can module. (5) f c32 this clock is derived by dividing the sub clock by 32. it is used for the timer a and timer b counts. (6) f c this clock has the same frequency as the sub clock. it may be selected as the bclk and for the watchdog timer.
41 clock generating circuit under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 5-4. clock control registers 0 and 1 figure 5-4 shows the system clock control registers 0 and 1. system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 7 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit wait peripheral function clock stop bit 0 : do not stop f 2 , f 8 , f 32 in wait mode 1 : stop f 2 , f 8 , f 32 in wait mode x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 3, 4 and 5) 0 : on 1 : off main clock division select bit 0 (note 2) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: changes to 1 when shifting to stop mode. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to 0. when main clock oscillation is operating by itself, set system clock select bit (cm07) to 1 before setting this bit to 1. note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: changes to 1 when shifting to stop mode. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is 0. if 1, division mode is fixed at 8. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to 0 reserved bit always set to 0 main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to 0 reserved bit always set to 0 0 0 note 5: if this bit is set to 1, x out turns "h". the built-in feedback resistor remains on, so x in turns pulled note 6: set port xc select bit (cm04) to 1 before writing to this bit. the both bits can not be written at the same time. up to x out ("h") via the feedback resistor. (note 6) (note 4) note 4: if this bit is set to 1, x out turns "h", and the built-in feedback resistor turns null.
42 clock generating circuit under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 5-5 shows the can0/1 clock select register and figure 5-6 shows the peripheral function clock select register. figure 5-5. can0/1 clock select register figure 5-6. peripheral function clock select register peripheral function clock select register (note 1) symbol address when reset pclkr 025e 16 xxxxxx00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. these bits can neither be set nor reset. when read, their contents are "0". pclk0 timera, timerb, a-d converter function clock pclk1 0: division by 2 mode 1: division by 1 mode (note 2) uart0-2, sio3 function clock 0: division by 2 mode 1: division by 1 mode (note 2) note1: set bit 0 of the protect register (address 000a 16 ) to "1" before writing in this register. note 2: do not set "1" when x in is more than 16 mhz can0/1 clock select register (note 1, note 2) symbol address when reset c01clkr 025f 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: no division mode 0 0 1: division by 2 mode 0 1 0: division by 4 mode 0 1 1: division by 8 mode 1 0 0: division by 16 mode b2 b1 b0 cclk7 cclk5 cclk4 cclk3 cclk1 cclk2 cclk0 cclk6 can0 clock select bit reserved bit w r can1 clock select bit 0 0 0: no division mode 0 0 1: division by 2 mode 0 1 0: division by 4 mode 0 1 1: division by 8 mode 1 0 0: division by 16 mode b6 b5 b4 always set to "0" reserved bit always set to "0" note2: change the register value only when the can module is in reset/initialization mode (the bit 0 of the can control register (address 0210 16 and 0230 16 ) is"1"). note1: set bit 0 of the protect register (address 000a 16 ) to "1" before writing in this register.
43 clock generating circuit under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock output in single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 16 ) enable f 8 , f 32 , or fc to be output from the p5 7 /clk out pin. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1, the output of f 8 and f 32 stops when a wait instruction is executed. stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc remains above 2v. because the oscillation of bclk, f 2 to f 32 , fc, fc 32 , fc an0 , fc an1 and f ad2 stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uarti(i = 0 to 2) functions provided an external clock is selected. table 5-2 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. when shifting to stop mode, the main clock division select bit 0 (bit 6 at 0006 16 ) is set to 1. pin memory expansion mode single-chip mode microprocessor mode address bus, data bus, cs0 to cs3 retains status before stop mode rd, wr, bhe, wrl, wrh h hlda, bclk h ale h port retains status before stop mode retains status before stop mode clk out when fc selected valid only in single-chip mode h when f 8 , f 32 selected valid only in single-chip mode retains status before stop mode table 5-2. port status during stop mode
44 clock generating circuit under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer wait mode wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclk and watchdog timer may be stopped under certain conditions. refer to the section describing the watchdog timer. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power consumption to be reduced. table 5-3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts using as bclk the clock that had been selected when the wait instruction was executed. table 5-3. port status during wait mode pin memory expansion mode single-chip mode microprocessor mode address bus, data bus, cs0 to cs3 retains status before wait mode rd, wr, bhe, wrl, wrh h hlda h bclk h (note) ale h port retains status before wait mode retains status before wait mode clk out when f c selected valid only in single-chip mode does not stop when f 8 , f 32 selected valid only in single-chip mode does not stop when the wait peripheral function clock stop bit is 0. when the wait peripheral function clock stop bit is 1, the status immediately prior to entering wait mode is main- tained. note: bclk is "h" only when the watchdog timer is stopped. refer to the watchdog timer section for more information
45 clock generating circuit under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer status transition of bclk power consumption can be reduced and low-voltage operation achieved by changing the count source for bclk. table 5-4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. after a reset, operation defaults to division by 8 mode. when shifting to stop mode, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is used as bclk. (6) low-speed mode f c is used as bclk. note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power consumption mode f c is the bclk and the main clock is stopped. (8) ring oscillator mode what the ring oscillator generates is the bclk. you can use it by dividing it by 2, 4, 8 or 16, and also no division is possible. status transition of bclk 01000 invalid division by 2 mode 10000 invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 11000 invalid division by 16 mode 00000 invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power consumption mode cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk table 5-4. operating modes dictated by settings of system clock control registers 0 and 1
46 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer power control power control the following is a description of the three available power control modes: modes power control is available in three modes. (1) normal operation mode ? high-speed mode divide-by 1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide by-4 divide-by-8 or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function operates according to its assigned clock. ? low-speed mode fc becomes the bclk. the cpu operates according to the fc clock selected. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. ? ring oscillator mode the ring oscillator replaces x in . no-division-, divide-by-2-, 4-, 8- or 16 mode can be selected by changing the values in cm06, cm16 and cm17. the higher the division ratio is, the lower power consumption. the clock driver of x in can be stopped by changing the value of the main clock stop bit to "0" when the cpu operates using the ring oscillator. through this the power consumption will be still lower. (2) wait mode the cpu operation is stopped. the oscillator does not stop. (3) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in reducing power consumption. figure 5-7 shows the state transition of power control modes.
47 power control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer bclk : f(x in )/8 cm07 = 0 cm06 = 1 main clock is oscillating sub clock is oscillating main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating cm05 = 0 : main clock is oscillating cm04 = 0 : sub clock is stopped cm05 = 0 cm04 = 1 cm05 = 0 cm04 = 0 cm05 = 1 cm04 = 1 bclk : f(x cin ) cm07 = 1 bclk : f(x in )/16 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 1 bclk : f(x in )/4 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 0 bclk : f(x in ) cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 0 bclk : f(x in )/ 2 cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 1 high-speed mode medium-speed mode (divided-by-2) medium-speed mode (divided-by-16) medium-speed mode (divided-by-4) low-speed mode bclk : f(x in )/1 6 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 1 bclk: f(x in )/4 cm07 = 0 cm06 = 0 cm17 = 1 cm16 = 0 bclk : f(x in ) cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 0 bclk : f(x in )/ 2 cm07 = 0 cm06 = 0 cm17 = 0 cm16 = 1 bclk : f( x cin ) cm07 = 1 high-speed mode medium-speed mode (divided-by-2) medium-speed mode (divided-by-16) medium-speed mode (divided-by-4) low power dissipation mode medium-speed mode (divided-by-8 mode) reset medium-speed mode (divided-by-8 mode) high-speed/medium- speed/low-speed/low power dissipation mode stop mode wait mode wait instruction ring oscillator mode interrupt cpu operation stopped cm05 = 0 cm04 = 1 cm21 = 0 cm21 = 1 cm10 = 1 all oscillators stopped interrupt transition of stop mode, wait mode transition of normal mode normal mode switch clocks after oscillation of both is sufficiently stable. change cm06 after changing cm17 and cm16. note 1: note 2: figure 5-7. state transition diagram of power control mode
oscillation stop detection function under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer 48 oscillation stop detection function this function is for detecting an abnormal stop of the clock which is caused by open- and/or short circuit of the xin oscillation circuit. when it detects an oscillation stop, it generates either an internal reset or an oscillation stop detection interrupt. the selection depends on the value in the bit 7 of the oscillation stop detection register (000c 16 ). when an oscillation stop detection interrupt is generated, the ring oscillator which is built in the microcomputer starts oscillation automatically, which is used as the system clock instead of xin. through this an interrupt operation is enabled. you can set the function to valid/invalid by changing the value in the bit 0 of the oscillation stop detection register. the function is valid when the bit is "1". however, the value of the bit after reset release is "0", so the function is invalid. figure 5-8. structure of the oscillation stop detection circuit cm21 internal reset generating cicuit oscillation stop detection interrupt generating circuit charge/discharge cicuit ring oscillator internal reset to the cpu watchdog timer interrupt main clock main clock switch control to the main clock prescaler compulsory discharge when cm20=0 pulse generation circuit for clock edge discharge control detection and charge/ # #: when xin is supplied, this repeats charge and discharge with pulses by xin edge detection. when xin is not supplied, this continues charging. when the charge exceeds a certain level, it regards the oscillation as stopped. xin table 5-5. outline of specification of the oscillation stop detection function item specification clock and frequency xin is 2 mhz or more. condition the oscillation stop detection bit (bit 0 at 000c 16 ) is "1". operation when detected #generates an internal reset (when the bit 7 at 000c 16 is "0") an oscillation stop #generates an oscillation stop detection interrupt (when the bit 7 at 000c 16 is "1") write "0" in the oscillation stop detection bit before setup of the stop- in the stop-mode mode to set the oscillation stop detection function to "invalid". write "1" in the bit after stop-mode release.
49 oscillation stop detection function under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer oscillation stop detection register (note 1) symbol address when reset cm2 000c 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm20 cm21 main clock switch bit cm22 cm23 cm24 cm25 cm26 cm27 oscillation stop 0: the function is invalid. 1: the function is valid. 0: select xin (ring oscillator is stopped.) 1: select ring oscillator. 0: no meaning 1: an oscillation stop is detected. 0: xin is in operation. 0: internal reset on stop detectio 1: xin is stopped. 1: start ring oscillator detection status (note 2) oscillation stop detection bit clock monitor bit (note 3) w r reserved bit always set to "0" operation select bit (when an oscillation stop is detected) note 2: this bit is valid only in an execution program for the oscillation stop detection inter- rupt. use this bit for the purpose of cause judgment(oscillation stop detection- or watchdog timer interrupt) for interrupt execution. you can write in this bit "0" only. note 1: set bit 0 of the protect register (address 000a 16 ) to "1" before writing to this register. note 3: this bit is valid only in an execution program for the oscillation stop detection inter- rupt. use this bit for the purpose of confirming xin operation for interrupt execution. figure 5-9. structure of the oscillation stop detection register
oscillation stop detection function under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer 50 oscillation stop detection bit (cm20) you can start the oscillation stop detection by setting this bit to "1". the detection is not executed when this bit is set to "0" or in reset status. be sure to set this bit to "0" before setting for the stop-mode. set this bit again to "1" after release from stop-mode. this is because it is necessary to cancel the oscillation stop detection function due to a certain period of unstable oscillation after release from stop-mode. set this bit to "0" also before setting the main clock stop bit (bit 5 at 0006 16 ) to "1". do not set this bit to "1" if the frequency of xin is lower than 2 mhz. main clock switch bit (cm21) you can use the ring oscillator as a system clock by setting this bit to "1". when this bit is "0", the ring oscillator is not in operation. for more explanation, see the section of the clock generating circuit. oscillation stop detection status (cm22) you can see the status of the oscillation stop detection. when this bit is "1", an oscillation stop is detected. for usage of this bit, see the explanation on cm27. clock monitor bit (cm23) you can see the operation status of the xin clock. when this bit is "1", xin is operating correctly. you can check the operation status of xin when an oscillation stop detection interrupt is generated. operation select (when an oscillation stop is detected) bit (cm27) (1) operation when internal reset is selected (cm27 is set to "0".) an internal reset is generated when an abnormal stop of xin is detected. the microcomputer stops in reset status and does not operate further. note: release from this status is only possible through an external reset. however, in case of a defect xin clock, further operation cannot be compensated. see table 5-6 for status of each port after an internal reset is generated. (2) operation when oscillation stop detection interrupt is selected (cm27 is set to "1".) an oscillation stop detection interrupt is generated when an abnormal stop of xin is detected. the ring oscillator starts operation instead of the xin clock which stopped abnormally. the operation goes further with the supply from the ring oscillator. for the oscillation stop detection interrupt judgment on the interrupt condition is necessary, because this interrupt shares the vector table with watchdog timer interrupt. use the oscillation stop detection status (cm22) for the judgment. figure 5-10 shows the flow of the judgment.
51 oscillation stop detection function under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 5-10. flow of the judgment table 5-6. port status after an internal reset is generated depends on hold pin input.) depends on hold pin put.) p5 5 input port (floating) hold input (floating) hold input (floating) p5 6 input port (floating) ale output ("l" level output) ale output ("l" level output) p5 7 input port (floating) rdy input (floating) rdy input (floating) p6, p7, p8 0 to p8 4 p8 6 , p8 7 , p9, p10 input port (floating) input port (floating) input port (floating) (pull-up resistance is on.) (pull-up resistance is on.) pin status pin name microprocessor mode/memory expansion mode single-chip mode byte = vss byte = vcc p0 input port (floating) data input (floating) data input (floating) p1 input port (floating) data input (floating) input port (floating) p2, p3, p4 0 to p4 3 input port (floating) address output (undefined) address output (undefined) p4 4 input port (floating) cs0 output ("h" level output) cs0 output ("h" level output) p4 5 to p4 7 input port (floating) input port (floating) input port (floating) p5 0 input port (floating) wr output ("h" level output) wr output ("h" level output) p5 1 input port (floating) bhe output (undefined) bhe output (undefined) p5 2 input port (floating) rd output ("h" level output) rd output ("h" level output) p5 3 input port (floating) bclk output bclk output p5 4 input port (floating) hlda output (output value hlda output (output value p0 input port (floating) data input (floating) data input (floating) p1 input port (floating) data input (floating) input port (floating) p2, p3, p4 0 to p4 3 input port (floating) address output (undefined) address output (undefined) p4 4 input port (floating) cs0 output ("h" level output) cs0 output ("h" level output) p4 5 to p4 7 input port (floating) input port (floating) input port (floating) p0 input port (floating) data input (floating) data input (floating) p1 input port (floating) data input (floating) input port (floating) p2, p3, p4 0 to p4 3 input port (floating) address output (undefined) address output (undefined) p4 4 input port (floating) cs0 output ("h" level output) cs0 output ("h" level output) p4 5 to p4 7 input port (floating) input port (floating) input port (floating) p5 0 input port (floating) wr output ("h" level output) wr output ("h" level output) p5 1 input port (floating) bhe output (undefined) bhe output (undefined) p5 2 input port (floating) rd output ("h" level output) rd output ("h" level output) p5 3 input port (floating) bclk output bclk output p5 4 input port (floating) hlda output (output value hlda output (output value oscillation stop detection interrupt or watchdog timer interrupt is generated read cm22 cm22 = 1 ? jump to the execution program for oscillation stop detection interrupt jump to the execution program for watchdog timer interrupt yes no
52 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer overview of interrupt type of interrupts figure 6-1 lists the types of interrupts. figure 6-1. classification of interrupts ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. interrupt software hardware special peripheral i/o (note) undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction reset _______ nmi ________ dbc watchdog timer/oscillation stop single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system.
53 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to "1". the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral interrupt i/o interrupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to "0" and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt request. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
54 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer hardware interrupts hardware interrupts are classified into two types - special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset reset occurs if an "l" is input to the reset pin. ? nmi interrupt an nmi interrupt occurs if an "l" is input to the nmi pin. ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt/oscillation stop detection interrupt generated by the watchdog timer or upon oscillation stop detection. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to "1", a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". if an address other than the first address of the instruction in the address match interrupt register is no address match interrupt occurs. for address match interrupt, see 2. 11 address match interrupt. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? bus collision detection interrupt this is an interrupt that the serial i/o bus collision detection generates. ? dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ? key-input interrupt a key-input interrupt occurs if an "l" is input to the ki pin. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0, uart1, uart2/nack, can0, can1, si/o3, and si/o4 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0, uart1, uart2/ack, can0, can1, si/o3, and si/o4 reception interrupt these are interrupts that the serial i/o reception generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates. ? timer b0 interrupt through timer b5 interrupt these are interrupts that timer b generates. ? int0 interrupt through timer int5 interrupt an int interrupt occurs if either a rising edge or a falling edge or both edges are input to the int pin.
55 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 6. 2 shows the format for specifying the address. two types of interrupt vector tables are available __ fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. figure 6-2. format for specifying interrupt vector addresses ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 6. 1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. mid address low address 0 0 0 0 high address 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb table 6-1. interrupts assigned to the fixed vector tables and addresses of vector tables interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 oscillation stop detection 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use nmi ffff8 16 to ffffb 16 _______ external interrupt by input to nmi pin reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only.
56 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer table 6-2. interrupt assigned to the variable vector tables and addresses of vector tables ? variable vector tables the addresses in the variable vector table can be modified, according to the user's setting. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the address the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 6-2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. software interrupt number interrupt source vector table address address (l) to address (h) remarks +44 to +47 (note 1) software interrupt number 11 +48 to +51 (note 1) software interrupt number 12 +52 to +55 (note 1) software interrupt number 13 +56 to +59 (note 1,2) software interrupt number 14 +68 to +71 (note 1) software interrupt number 17 +72 to +75 (note 1) software interrupt number 18 +76 to +79 (note 1) software interrupt number 19 +80 to +83 (note 1) software interrupt number 20 +84 to +87 (note 1) software interrupt number 21 +88 to +91 (note 1) software interrupt number 22 +92 to +95 (note 1) software interrupt number 23 +96 to +99 (note 1) software interrupt number 24 +100 to +103 (note 1) software interrupt number 25 +104 to +107 (note 1) software interrupt number 26 +108 to +111 (note 1) software interrupt number 27 +112 to +115 (note 1) software interrupt number 28 +116 to +119 (note 1) software interrupt number 29 +120 to +123 (note 1) software interrupt number 30 +124 to +127 (note 1) software interrupt number 31 +128 to +131 (note 1) software interrupt number 32 +252 to +255 (note 1) software interrupt number 63 to note 1: address relative to address in interrupt table register (intb). note 2: it is selected by interrupt request cause select registers (ifsr0/1). note 3: when iic mode is selected, nack and ack interrupts are selected. cannot be masked i flag +40 to +43 (note 1) software interrupt number 10 +60 to +63 (note 1,3) software interrupt number 15 +64 to +67 (note 1,3) software interrupt number 16 +20 to +23 (note 1) software interrupt number 5 +24 to +27 (note 1) software interrupt number 6 +28 to +31 (note 1) software interrupt number 7 +32 to +35 (note 1,2) software interrupt number 8 +16 to +19 (note 1) software interrupt number 4 +36 to +39 (note 1,2) can1 reception, int5 software interrupt number 9 can1 transm., int4, s i/o3 timer b3 timer b4 timer b5 int3 to dma0 dma1 key input int. a-d conv., uart0 transmission uart0 reception uart1 transmission uart1 reception timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt bus collision detection uart2 transmission uart2 reception +4 to +7 (note 1) software interrupt number 1 +8 to +11 (note 1) software interrupt number 2 +12 to +15 (note 1) software interrupt number 3 +0 to +3 (note 1) brk instr. software interrupt number 0 can0 transmission can0 reception can0,1 wake up can0,1 error int.
57 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer interrupt control descriptions are given here regarding how to enable or disable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority selection bit, or processor interrupt priority level(ipl). whethre an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bie are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 6-3 shows the memory map of the interrupt control registers.
58 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 6-3. interrupt control registers symbol address when reset intiic(i=3) 0044 16 xx00x000 2 c1recic/int5ic (note 3) 0048 16 0049 16 xx00x000 2 intiic(i=0 to 2) 005d 16 to 005f 16 xx00x000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ilvl0 ir pol interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 (note1) interrupt control register (note 2) b7 b6 b5 b4 b3 b2 b1 b0 bit name function bit symbol w r symbol address when reset ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. (note1) 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 tbiic(i=3 to 5) 0045 16 to 0047 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dmiic(i=0, 1) 004b 16 , 004c 16 xxxxx000 2 c01erric, kupic 004e 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0 to 2) 0051 16 , 0053 16 , 004f 16 xxxxx000 2 siric(i=0 to 2) 0052 16 , 0054 16 , 0050 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 c01wkupic, c0recic, c0trmic 0041 16 xxxxx000 2 0042 16 , 0043 16 xxxxx000 2 004d 16, xx00x000 2 c1trmic/s3ic/int4ic (note 3) in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 3: use ifsr0/isfr1 (address 1de/1df) for interrupt request cause selection. note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts.
59 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to "1" enables all maskable interrupts; setting to "0" disables all maskable interrupts. this flag is set to "0" after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1".) interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. table 6-3 shows the settings of interrupt priority levels and table 6-4 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted. ? interrupt enable flag (i flag) = 1 ? interrupt request bit = 1 ? interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 6-3. settings of interrupt priority levels table 6-3. interrupt levels enabled according to the contents of the ipl interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl
60 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: example 1 int_switch1: fclr i ;di sable interrupts. and.b #00h, 0055h ;c lear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ;enable interrupts example 2 int_switch2: fclr i ;di sable interrupts. and.b #00h, 0055h ;c lear ta0ic int. priority level and int. request bit. mov.w mem, r0 ;dummy read fset i ;enable interrupts example 3 int_switch3: pushc flg ;push flag register onto stack fclr i ;di sable interrupts. and.b #00h, 0055h ;c lear ta0ic int. priority level and int. request bit. popcflg ;enable interrupts the reason why two nop instructions (four when using the hold function) or dummy read is inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. when an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions: and, or, bclr, bset
61 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer interrupt sequence an interrupt sequence __ what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed __ is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16 . (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to "0" (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed). (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 6-4 shows the interrupt responce time. figure 6-4. interrupt response time instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated
62 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 6-5. table 6-5. time required for executing the interrupt sequence stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure 6-5. time required for executing the interrupt sequence indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 6-6 is set in the ipl. table 6-6. relation between interrupts without interrupt priority levels and ipl interrupt sources without priority levels 7 value set in the ipl _______ watchdog timer, nmi other not changed 0 reset
63 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 6-6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers ecept the stack pointer (sp). figure 6-6. state of stack before and after acceptance of interrupt request address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m C 1 m C 2 m C 3 m C 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m C 1 m C 2 m C 3 m C 4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m )
64 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 6-7. operation of saving registers the operation of saving registers carried out in the interrupt sequence is dependent whether content of the stack pointer, at the time of acceptance of an interrupt equest, is even or odd. if the counter of the stack pointer (notze) is even, the counter of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 6-7 shows the operation of the saving registers. note: stack pointer indicated by u flag. (2) stack pointer (sp) contains odd number [sp] (odd) [sp] C 1 (even) [sp] C 2(odd) [sp] C 3 (even) [sp] C 4(odd) [sp] C 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] C 1(odd) [sp] C 2 (even) [sp] C 3(odd) [sp] C 4 (even) [sp] C 5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h )
65 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspendedd process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruction befoere executing the reit instruction. interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt aqssigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority),watchdog timer interrupt, etc. are regulated by hardware. figure 6-8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. _______ ________ reset > nmi > dbc > watchdog timer > peripheral i/o > single step > address match figure 6-8. hardware interrupts priorities interrupt resolution circuit when two or more interupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 6-9 shows the circuit that judges the interrupt priority level.
66 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer uart1 reception uart0 reception uart2 reception int2 can0 transmission can0,1 wake up timer a2 uart0 transmission a-d conversion dma1 bus collision detection can1 transm., int4, serial i/o3 timer b4 can0 reception can0,1 error uart2 transmission /key input interrupt dma0 can1 reception, int5 processor interrupt priority level (ipl) interrupt enable flag (i flag) timer a1 timer a4 timer b5 watchdog timer reset dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) int0 timer b1 timer a0 uart1 transmission int3 timer b3 address match timer b2 timer b0 timer a3 int1 figure 6-9. maskable interrupts priorities (peripheral i/o interrupts)
67 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer int interrupt int interrupt int0 to int5 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. of interrupt control registers, 0048 16 is used both as can1 receive and external interrupt int5 input control register, and 0049 16 is used as serial i/o3, can1 transmit and as external interrupt int4 input control register. use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (01df 16 ) - to specify which interrupt request cause to select. after having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. the interrupt control register 0049 16 has the polarity-switching bit. be sure to set this bit to "0" when selecting the serial i/o as the interrupt request cause. as to external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting "1" in the inti interrupt polarity switching bit of the interrupt request cause select register (01df 16 ). to select both edges, set the polarity switching bit of the correponding interrupt control register to 'falling edge' ("0"). figures 6-10 and 6-11 show the interrupt request cause select registers 0 and 1. interrupt request cause select register 0 bit name function bit symbol w r symbol address when reset ifsr0 01de 16 ifsr00 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request cause select bit 0 : c1trmic 1 : sio3 xxxxxx00 16 nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. ifsr01 interrupt request cause select bit 0 : ad converter 1 : key on wake up interrupt request cause select register 1 bit name fumction bit symbol w r symbol address when reset ifsr1 01df 16 ifsr10 b7 b6 b5 b4 b3 b2 b1 b0 int0 interrupt polarity swiching bit 1 : int4 0 : sio3 / c1trmic 1 : int5 0 : c1recic 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges int1 interrupt polarity swiching bit int2 interrupt polarity swiching bit int3 interrupt polarity swiching bit int4 interrupt polarity swiching bit int5 interrupt polarity swiching bit 0 : one edge 1 : two edges interrupt request cause select bit interrupt request cause select bit ifsr11 ifsr12 ifsr13 ifsr14 ifsr15 ifsr16 ifsr17 00 16 figure 6-10. interrupt request cause select register 0 figure 6-11. interrupt request cause select register 1
68 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 6-12. block diagram of key input interrupt nmi interrupt an nmi interrupt is generated when the input to the p8 5 /nmi pin changes from h to l. the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p8 5 register (bit 5 at address 03f0 16 ). this pin cannot be used as a normal port input. key input interrupt if the direction register of any of p10 4 to p10 7 is set for input and a falling edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancel- ling the wait mode or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as a-d input ports. figure 6-12 shows the block diagram of the key input interrupt. note that if an l level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. interrupt control circuit key input interrupt control register (address 004e 16 ) key input interrupt request p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 port p10 4 -p10 7 pull-up select bit port p10 7 direction register pull-up transistor port p10 7 direction register port p10 6 direction register port p10 5 direction register port p10 4 direction register pull-up transistor pull-up transistor pull-up transistor nmi interrupt
69 interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure 6-13 shows the address match interrupt-related registers. address match interrupt figure 6-13. address match interrupt-related registers bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminated. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminated. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23)
70 interrupts under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer precautions for interrupts (1) reading address 00000 16 ? when the maskable interrupt occurs, cpu reads the interrupt information (the interrupt number and inter- rupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to "0". reading address 00000 16 by software sets enabled highest priority interrupt source request bit to "0". though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value for the stack pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point at the begin- ning of a program. concerning the first instruction immediately after reset, generating any interrupt includ- ing the nmi interrupt is prohibited. precautions for interrupts can0/1 wake up interrupt a can wake up interrupt is generated after one of the can buses becomes active. that means the physical bus turns to a dominant level. this interrupt can only be used to wake up the cpu from wait mode or stop mode. the can wake up interrupt can only be used, if the port(s) are configured as can ports. one interrupt signal is generated for both can channels. please note that the wake up message wiil be lost. figure 6-8 shows the principle to generate the corresponding interrupt signal. figure 6-14. can 0/1 wake up interrupt interrupt control circuit can0/1 wake up int. control register (address 0041 16 ) can wake up interrupt request crx 0 crx 1
71 precautions for interrupts under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer set the polarity select bit clear the interrupt request bit to 0 set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to 0 (disable interrupt) set the interrupt enable flag to 1 (enable interrupt) (3) the nmi interrupt ? as for the nmi pin, an interrupt cannot be disabled. connect it to the vcc pin via a resistor (pull-up) if unused. be sure to work on it. ? the nmi pin also serves as p8 5 , which is exclusively for input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time when the nmi interrupt is input. ? do not reset the cpu with the input to the nmi pin being in the "l" state. ? do not attempt to go into stop mode with the input to the nmi pin being in the "l" state. with the input to the nmi pin being in the "l" state, the cm10 is fixed to "0", so attempting to go into stop mode is turned down. ? do not attempt to go into wait mode with the input to the nmi pin being in the "l" state. with the input to the nmi pin being in the "l" state, the cpu stops but the oscillation does not stop, so no power is saved. in this instance, the cpu is returned to the normal state by a later interrupt. ? signals input to the nmi pin require an "l" level of 1 clock or more, from the operation clock of the cpu. (4) external interrupt ? either an "l" level or an "h" level of at least 250 ns width is necessary for the signal input to pins int0 through int5 regardless of the cpu operation clock. ? when the polarity of the int0 to int5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 6-15 shows the procedure for changing the int interrupt generate factor. figure 6-15. switching condition of int interrupt request
72 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) falling edge of int0 or int1 (int0 can be selected by dma0, int1 bydma1) or both edge timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 transmission and reception interrupt requests uart1 transmission and reception interrupt requests uart2 transmission and reception interrupt requests serial i/o3 interrupt request a-d conversion interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer the dma enable bit is cleared and transfer ends when an underflow occurs in the transfer counter ? repeat transfer when an underflow occurs in the transfer counter, the value in the transfer counter reload register is reloaded into the transfer counter and the dma transfer is repeated dma interrupt request generation timing when an underflow occurs in the transfer counter dma startup ? single transfer transfer starts when the dma is requested after 1 is written to the dma enable bit ? repeat transfer transfer starts when the dma is requested after 1 is written to the dma enable bit transfer starts when the dma is requested after an underflow occurs in the transfer counter dma shutdown ? when 0 is written to the dma enable bit ? when, in single transfer mode, an underflow occurs in the transfer counter forward address pointer and when dma transfer starts, the value of whichever of the source or destination pointer reload timing for transfer that is set up as the forward pointer is reloaded into the forward address pointer. the counter value in the transfer counter reload register is reloaded into the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register set up as the forward register is the same as reading the value of the forward address pointer . note: dma transfer is not effective to any interrupt. dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. table 7-1 shows the dmac specifications. figure 7-1 shows the block diagram of the dmac. figures 7-2 to 7-4 show the registers used by the dmac. table 7-1. dmac specifications
73 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer dma0 request cause select register symbol address when reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0. software dma request bit if software trigger is selected, a dma request is generated by setting this bit to 1 (when read, the value of this bit is always 0) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms=0) /two edges of int0 pin (dms=1) 0 1 1 1 : timer b0 (dms=0) timer b3 (dms=1) 1 0 0 0 : timer b1 (dms=0) timer b4 (dms=1) 1 0 0 1 : timer b2 (dms=0) timer b5 (dms=1) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause figure 7-2. dmac register (1) figure 7-1. block diagram of dmac data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits address bus dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request.
74 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 7-3. dmac register (2) dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit rw dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0 . note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to 0 . note 3: source address direction select bit and destination address direction select bit cannot be set to 1 simultaneously. (note 2) dma1 request cause select register symbol address when reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0 . software dma request bit if software trigger is selected, a dma request is generated by setting this bit to 1 (when read, the value of this bit is always 0 ) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3(dms=0) /serial i/o3 (dms=1) 0 1 1 0 : timer a4 (dms=0) 0 1 1 1 : timer b0 (dms=0) /two edges of int1 (dms=1) 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 receive bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause
75 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer b7 b0 b7 b0 (b8) (b15) function rw ? transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ? source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0. symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ? destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0. figure 7-4. dmac register (3)
76 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. in memory expansion mode and microprocessor mode, the number of read and write bus cycles also de- pends on the level of the byte pin. also, the bus cycle itself is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) effect of byte pin level when transferring 16-bit data over an 8-bit data bus (byte pin = h) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. therefore, two bus cycles are required for reading the data and two are required for writing the data. also, in contrast to when the cpu accesses internal memory, when the dmac accesses internal memory (internal rom, internal ram, and sfr), these areas are accessed using the data size selected by the byte pin. (c) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 7-5 shows the example of the transfer cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respec- tive conditions to both the destination write cycle and the source read cycle. for example (2) in figure 7- 5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle.
77 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) one wait is inserted into the source read under the conditions in (1) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd transferring 16-bit data on an 8-bit data bus (in this case, there are also two destination write cycles). bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) (when 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). note: the same timing changes occur with the respective conditions at the destination as at the source. figure 7-5. example of the transfer cycles for a source read
78 dmac under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer single-chip mode memory expansion mode transfer unit bus width access address microprocessor mode no. of read no. of write no. of read no. of write cycles cycles cycles cycles 16-bit even 1 1 1 1 8-bit transfers (byte= l) odd 1 1 1 1 (dmbit= 1) 8-bit even 1 1 (byte = h) odd 1 1 16-bit even 1 1 1 1 16-bit transfers (byte = l) odd 2 2 2 2 (dmbit= 0) 8-bit even 2 2 (byte = h) odd 2 2 table 7-2. no. of dmac transfer cycles internal memory external memory internal rom/ram internal rom/ram sfr area separate bus separate bus multiplex no wait with wait no wait with wait bus 122123 coefficient j, k (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 7-2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k
79 watchdog timer under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer cm07 cm06 cm17 cm16 internal clock f wdc7 period 0 0 0 0 10mhz 0 approx. 52.4ms (note) 1 approx. 419.2ms (note) 0 0 0 1 5mhz 0 approx. 104.9ms (note) 1 approx. 838.8ms (note) 0 0 1 0 2.5mhz 0 approx. 209.7ms (note) 1 approx. 1.68s (note) 0 0 1 1 0.625mhz 0 approx. 838.8ms (note) 1 approx. 6.71s (note) 0 1 invalid invalid 1.25mhz 0 approx. 419.2ms (note) 1 approx. 3.35s (note) 1 invalid invalid invalid 32khz invalid approx. 2s (note) note: error is generated by the prescaler. figure 8-1. block diagram of watchdog timer the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 8-1 shows the block diagram of the watchdog timer. figure 8-2 shows the watchdog timer-related registers. table 8-1. watchdog timer periodic table (x in = 10mhz, x cin = 32khz) watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the internal clock f using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is se- lected for the internal clock f, bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the internal clock f , the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). table 8-1 shows the periodic table for the watchdog timer. internal clock write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to 7fff 16 1/128 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 hold 1/2 prescaler
80 watchdog timer under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 8-2. watchdog timer control and start registers watchdog timer during wait mode the watchdog timer is supplied by the internal clock f . if the internal clock f stops, the watchdog timer stops also. when executing a wait instruction, the internal clock f stops if no interrupt request is pending or any interrupt request that is pending is marked (i.e. the interrupts ipl is set to a value not greater than the cpu's ipl). the internal clock f and the watchdog timer will continue running when at the issuance of the wait instruction any nonmasked interrupt request was pending and the i flag in the flag register was cleared. the same applies to an internal clock f stopped during wait mode: if during wait mode a disabled but not masked interrupt is requested and the i flag is cleared internal clock f restarts. though the cpu remains in wait, the watchdog timer recommences activity where it left off and will in time request an interrupt itself. watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bits of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit reserved bit must always be set to 0 this bit can neither be set nor reset. 0 0
81 timer a under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 9-1. timer a block diagram timer there are eleven 16-bit timers. these timers can be classified by function into timers a (five) and timers b (six). all these timers function independently. figures 9-1 and 9-2 show the block diagram of timers. timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode timer mode one-shot mode pwm mode event counter mode event counter mode event counter mode event counter mode event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 2 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/4 1/4 f pclk0 = 1 2 f 8 f 32 x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to 1 reset clock prescaler timer b2 overflow 1/2
82 timer a u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 9-2. timer b block diagram event counter mode event counter mode event counter mode timer mode pulse width measuring mode timer mode pulse width measuring mode timer mode pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 2 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to 1 reset clock prescaler timer a event counter mode event counter mode timer mode pulse width measuring mode timer mode pulse width measuring mode timer mode pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt 1/4 1/4 f pclk0 = 1 2 f 8 f 32 1/2
83 timer a under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. count start flag (address 0380 16 ) up count/down count tai addresses taj tak timer a0 0387 16 0386 16 timer a4 timer a1 timer a1 0389 16 0388 16 timer a0 timer a2 timer a2 038b 16 038a 16 timer a1 timer a3 timer a3 038d 16 038c 16 timer a2 timer a4 timer a4 038f 16 038e 16 timer a3 timer a0 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits high-order 8 bits clock source selection ? timer (gate function) ? timer ? one shot ? pwm f 2 f 8 f 32 external trigger tai in (i = 0 to 4) tb2 overflow ? event counter f c32 clock selection taj overflow (j = i C 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits up/down flag down count (address 0384 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit timer a figure 9-3 shows the block diagram of timer a. figures 9-4 to 9-6 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: figure 9-3. block diagram of timer a figure 9-4. timer a-related registers (1)
84 timer a u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to 0 symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r ? timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set ? event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow ? one-shot timer mode 0000 16 to ffff 16 counts a one shot width ? pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator ? pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. figure 9-5. timer a-related registers (2)
85 timer a under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr w r nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to 0. ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to 0. w r 1 : timer start when read, the value is 0 figure 9-6. timer a-related registers (3)
86 timer a u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer note 1: the settings of the corresponding port register and port direction register are invalid. note 2: the bit can be 0 or 1. note 3: set the corresponding port direction register to 0. timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held l (note 3) 1 1 : timer counts only when ta iin pin is held h (note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to 0 in timer mode) 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 figure 9-7. timer ai mode register in timer mode table 9-1. specifications of timer mode (1) timer mode in this mode, the timer counts an internally generated count source. (see table 9-1.) figure 9-7 shows the timer ai mode register in timer mode. item specification count source f 2 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pins input signal ? pulse output function each time the timer underflows, the tai out pins polarity is reversed
87 timer a under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification count source ? external signals input to tai in pin (effective edge can be selected by software) ? tb2 overflow, taj overflow count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register con tents before continuing counting (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed note: this does not apply when the free-run function is selected. table 9-2. timer specifications in event counter mode (when not processing two-phase pulse signal) timer ai mode register note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 0383 16 ). note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an l signal is input to the tai out pin, the downcount is activated. when h, the upcount is activated. set the corresponding port direction register to 0. symbol address when reset taimr(i = 0, 1) 0396 16 , 0397 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to 0 in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 invalid in event counter mode can be 0 or 1 tmod1 figure 9-8. timer ai mode register in event counter mode (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 9-2 lists timer specifications when counting a single-phase external signal. figure 9-8 shows the timer ai mode register in event counter mode. table 9-2 lists timer specifications when counting a two-phase external signal. figure 9-9 shows the timer ai mode register in event counter mode.
88 timer a u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer tai out tai in (i=3,4) count up all edges count up all edges count down all edges count down all edges item specification count source ? two-phase pulse signals input to tai in or tai out pin count operation ? up count or down count can be selected by two-phase pulse signal ? when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer ? when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function ? normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ? multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h, the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h, the timer counts down rising and falling edges on the tai out and tai in pins. note: this does not apply when the free-run function is selected. tai out up count up count up count down count down count down count tai in (i=2,3) table 9-3. timer specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3, and a4)
89 timer a under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer note 1: the settings of the corresponding port register and port direction register are invalid. note 2: this bit is valid when only counting an external signal. note 3: set the corresponding port direction register to 0. note 4: this bit is valid for the timer a3 mode register. for timer a2 and a4 mode registers, this bit can be 0 or 1. note 5: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to 1. also, always be sure to set the event/trigger select bit (addresses 0382 16 and 0383 16 ) to 00. timer ai mode register (when not using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (tai out pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 0 : (must always be 0 in event counter mode) tck1 tck0 01 0 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) bit symbol bit name function w r count operation type select bit two-phase pulse signal processing operation select bit (note 4)(note 5) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation note 1: this bit is valid for timer a3 mode register. for timer a2 and a4 mode registers, this bit can be 0 or 1. note 2: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to 1. also, always be sure to set the event/trigger select bit (addresses 0382 16 and 0383 16 ) to 00. timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be 0 when using two-phase pulse signal processing) 0 (must always be 0 when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be 0 when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be 1 when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 figure 9-9. timer ai mode register in event counter mode
90 timer a u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification count source f 2 , f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be 0 in one-shot timer mode) 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be 1 or 0. note 3: set the correspondin g port direction re g ister to 0. w r (3) one-shot timer mode in this mode, the timer operates only once. (see table 9-4.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 9-10 shows the timer ai mode register in one-shot timer mode. table 9-4. timer specifications in one-shot timer mode figure 9-10. timer ai mode register in one-shot timer mode
91 timer a under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer bit name timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be 1 in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be 1 or 0. note 2: set the corresponding port direction register to 0. item specification count source f 2 , f 8 , f 32 , f c32 count operation ? t he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n (m+1) / fi n : values set to timer ai registers high-order address ? cycle time (2 8 - 1) (m+1) / fi m : values set to timer ai registers low-order address count start condition ? external trigger is input ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 9-5.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 9-11 shows the timer ai mode register in pulse width modulation mode. figure 9-12 shows the example of how a 16-bit pulse width modulator operates. figure 9-13 shows the example of how an 8-bit pulse width modulator operates. table 9-5. timer specifications in pulse width modulation mode figure 9-11. timer ai mode register in pulse width modulation mode
92 timer a u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin h h h l l l 1 0 timer ai interrupt request bit cleared to 0 when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 2 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to fe 16 ; n = 00 16 to fe 16 . condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 C 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1) figure 9-13. example of how an 8-bit pulse width modulator operates figure 9-12. example of how a 16-bit pulse width modulator operates 1 / f i x (2 C 1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition: reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal h h l l timer ai interrupt request bit 1 0 cleared to 0 when interrupt request is accepted, or cleared by software f i : frequency of count source (f 2 , f 8 , f 32 , f c32 ) note: n = 0000 16 to fffe 16 . 1 / f i x n
93 timer b under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. timer bi mode register symbol address when reset tbimr(i = 0 to 5) 039b 16 to 039d 16 00xx0000 2 01db 16 to 01dd 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. clock source selection (address 0380 16 ) ? event counter ? timer ? pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 2 f 8 f 32 tbj overflow (j = i C 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 timer b3 01d1 16 01d0 16 timer b5 timer b4 01d3 16 01d2 16 timer b3 timer b5 01d5 16 01d4 16 timer b4 timer b figure 10-1 shows the block diagram of timer b. figures 10-2 and 10-3 show the timer b-related registers. use the timer bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: figure 10-1. block diagram of timer b figure 10-2. timer b-related registers (1)
94 timer b u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate tb3 01d1 16 , 01d0 16 indeterminate tb4 01d3 16 , 01d2 16 indeterminate tb5 01d5 16 , 01d4 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r ? pulse period / pulse width measurement mode measures a pulse period or width ? timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set ? event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. symbol address when reset tbsr 01c0 16 00 16 timer b3, 4, 5 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b5 count start flag timer b4 count start flag timer b3 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0. function figure 10-3. timer b-related registers (2)
95 timer b under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification count source f 2 , f 8 , f 32 , f c32 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 01db 16 to 01dd 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. this bit can neither be set nor reset. when read in timer mode, its content is indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0, 3) nothing is assiigned (i = 1, 2, 4, 5). this bit can neither be set nor reset. when read, its content is indeterminate. (note 1) (note 2) b7 b6 (1) timer mode in this mode, the timer counts an internally generated count source. (see table 10-1.) figure 10-4 shows the timer bi mode register in timer mode. table 10-1. timer specifications in timer mode figure 10-4. timer bi mode register in timer mode
96 timer b u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification count source ? external signals input to tbi in pin ? effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) table 10-2. timer specifications in event counter mode figure 10-5. timer bi mode register in event counter mode timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 01db 16 to 01dd 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 invalid in event counter mode. this bit can neither be set nor reset. when read in event counter mode, its content is indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 nothing is assigned (i = 1, 2, 4, 5). this bit can neither be set nor reset. when read, its content is indeterminate. note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. note 4: set the corresponding port direction register to 0. invalid in event counter mode. can be 0 or 1. event clock select 0 : input from tbi in pin (note 4) 1 : tbj overflow (j = i C 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (fixed to 0 in event counter mode; i = 0, 3) (note 2) (note 3) (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 10-2.) figure 10-5 shows the timer bi mode register in event counter mode.
97 timer b under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification count source f 2 , f 8 , f 32 , f c32 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to table 10-3. timer specifications in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 01db 16 to 01dd 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 nothing is assigned (i = 1, 2, 4, 5). this bit can neither be set nor reset. when read, its content is indeterminate. count source select bit timer bi overflow flag ( note 1) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note 1: the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register. this flag cannot be set to 1 by software. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. 0 (fixed to 0 in pulse period/pulse width measurement mode; i = 0, 3) (note 2) (note 3) (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 10-3.) figure 10-6 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 10- 7 shows the operation timing when measuring a pulse period. figure 10-8 shows the operation timing when measuring a pulse width. figure 10-6. timer bi mode register in pulse period/pulse width measurement mode
98 timer b u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 10-8. operation timing when measuring a pulse width measurement pulse h count source count start flag timer bi interrupt request bit timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) l 0 0 timer bi overflow flag 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to 0 when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing figure 10-7. operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches 0000 16 h 1 transfer (indeterminate value) l 0 0 timer bi overflow flag 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to 0 when interrupt request is accepted, or cleared by software. transfer (measured value) 1 reload register counter transfer timing
99 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer three-phase pwm control register 0 symbol address when reset invc0 01c8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit inv0 0 bit symbol bit name description rw inv0 1 effective interrupt output specification bit inv0 2 mode select bit (note 2) inv0 4 bit to enable the function for concurrent l output disablement of positive and negative phases inv0 7 software trigger bit inv0 6 modulation mode select bit (note 3) inv0 5 flag to detect concurrent l output of positive and negative phases inv0 3 output control bit 0: a timer b2 interrupt occurs when the timer a1 reload control signal is 0 . 1: a timer b2 interrupt occurs when the timer a1 reload control signal is 1 . effective only in three-phase mode 1 0: not specified. 1: selected by the effective interrupt output polarity selection bit. effective only in three-phase mode 1 0: normal mode 1: three-phase pwm output mode 0: output disabled 1: output enabled 0: feature disabled 1: feature enabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode 1: trigger generated the value, when read, is 0 . (note 1) t hree-phase pwm control register 1 symbol address when reset invc1 01c9 16 00 16 bit name description bit symbol w r inv1 0 inv1 1 inv1 2 timer ai start trigger signal select bit timer a1-1, a2-1, a4-1 control bit short circuit timer count source select bit (note 1) 0: timer b2 overflow signal 1: timer b2 overflow signal, signal for writing to timer b2 0: three-phase mode 0 1: three-phase mode 1 0 : inhibited 1 : f 2 /2 b7 b6 b5 b4 b3 b2 b1 b0 noting is assigned. note 1: no value other than 0 can be written. note 2: selecting three-phase pwm output mode causes p8 0 , p8 1 , and p7 2 through p7 5 to output u, u, v, v, w, and w, and works the timer for setting short circuit prevention time, the u, v, w phase output control circuits, and the circuit for setting timer b2 interrupt frequency. note 3: in triangular wave modulation mode: the short circuit prevention timer starts in synchronization with the falling edge of timer ai output. the data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. in sawtooth wave modulation mode: the short circuit prevention timer starts in synchronization with the falling edge of timer a output and with the transfer trig ger signal. the data transfer from the three-phase output buffer register to the three-phase output shift register i s made with respect to every transfer trigger. noting is assigned. these bits can be set nor reset. when read, their contents are indeterminate. reserved bit always set to 0 0 note 1: to use three-phase pwm output mode, write 1 to inv12. note 4: to write 1 both to bit 0 (inv00) and bit 1 (inv01) of the three-phase pwm control register, set in advance the content of the t imer b2 interrupt occurrences frequency set counter. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . figure 11-1. registers related to timers for three-phase motor control timers functions for three-phase motor control use of more than one built-in timer a and timer b provides the means of outputting three-phase motor driving waveforms. figures 11-1 through 11-3 show registers related to timers for three-phase motor control.
100 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer three-phase output buffer register 0 symbol address when reset idb0 01ca 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. du0 dub0 dv0 dw0 dvb0 dwb0 u phase output buffer 0 setting in u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 setting in v phase output buffer 0 setting in w phase output buffer 0 setting in w phase output buffer 0 setting in v phase output buffer 0 setting in u phase output buffer 0 three-phase output buffer register 1 symbol address when reset idb1 01cb 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 du1 dub1 dv1 dw1 dvb1 dwb1 u phase output buffer 1 setting in u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 setting in v phase output buffer 1 setting in w phase output buffer 1 setting in w phase output buffer 1 setting in v phase output buffer 1 setting in u phase output buffer 1 dead time timer symbol address when reset dot 01cc 16 indeterminate function values that can be set w r by by set dead time timer 1 to 255 timer b2 interrupt occurrences frequency set counter symbol address when reset ictb2 01cd 16 indeterminate function values that can be set w r by by set occurrence frequency of timer b2 interrupt request 1 to 15 in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. note: when executing read instruction of this register, the contents of three-phase shift register is read out. nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. note: when executing read instruction of this register, the contents of three-phase shift register is read out. note1: in setting 1 to bit 1 (inv01) - the effective interrupt output specification bit - of three- phase pwm control register 0, do not change the b2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. note2: do not write at the timing of an overflow occurrence in timer b2. figure 11-2. registers related to timers for three-phase motor control
101 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 11-3. registers related to timers for three-phase motor control symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to 0. symbol address when reset ta11 01c3 16 ,01c2 16 indeterminate ta21 01c5 16 ,01c4 16 indeterminate ta41 01c7 16 ,01c6 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r counts an internal count source 0000 16 to ffff 16 @ function values that can be set timer ai-1 register (note) note: read and write data in 16-bit units. symbol address when reset ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta4 038f 16 ,038e 16 indeterminate tb2 0395 16 ,0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r ? timer mode 0000 16 to ffff 16 @ counts an internal count source function values that can be set ? one-shot timer mode 0000 16 to ffff 16 counts a one shot width note: read and write data in 16-bit units. timer ai register (note)
102 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 11-4. timer mode registers in three-phase waveform mode three-phase motor driving waveform output mode (three-phase waveform mode) setting 1 in the mode select bit - bit 2 of three-phase pwm control register 0 (01c8 16 ) shown in fig. 11- 1 - causes three-phase waveform mode that uses four timers a1, a2, a4, and b2 to be selected. as shown in figure 11-4, set timers a1, a2, and a4 in one-shot timer mode, set the trigger in timer b2, and set timer b2 in timer mode using the respective timer mode registers. bit name timer ai mode register symbol address when reset ta1mr 0397 16 00 16 ta2mr 0398 16 00 16 ta4mr 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be 0 in one-shot timer mode) 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be 1 or 0 . note 3: set the corresponding port direction register to 0 . w r timer b2 mode register symbol address when reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. this bit can neither be set nor reset. when read in timer mode, its content is indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0) b7 b6 1 0
103 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 11-5 shows the block diagram for three-phase waveform mode. in three-phase waveform mode, the positive-phase waveforms (u phase, v phase, and w phase) and negative waveforms (u phase, v phase, and w phase), six waveforms in total, are output from p8 0 , p8 1 , p7 2 , p7 3 , p7 4 , and p7 5 as active on the l level. of the timers used in this mode, timer a4 controls the u phase and u phase, timer a1 controls the v phase and v phase, and timer a2 controls the w phase and w phase respectively; timer b2 controls the periods of one-shot pulse output from timers a4, a1, and a2. in outputting a waveform, dead time can be set so as to cause the l level of the positive waveform output (u phase, v phase, and w phase) not to lap over the l level of the negative waveform output (u phase, v phase, and w phase). to set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. a value from 1 through 255 can be set as the count of the timer for setting dead time. the timer for setting dead time works as a one-shot timer. if a value is written to the dead timer (01cc 16 ), the value is written to the reload register shared by the three timers for setting dead time. any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2) of three-phase pwm control register 1 (01c9 16 ). the timer can receive another trigger again before the workings due to the previous trigger are completed. in this instance, the timer performs a down count from the reload registers content after its transfer, provoked by the trigger, to the timer for setting dead time. since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 00 16 , and waits for the next trigger to come. the positive waveforms (u phase, v phase, and w phase) and the negative waveforms (u phase, v phase, and w phase) in three-phase waveform mode are output from respective ports by means of setting 1 in the output control bit (bit 3) of three-phase pwm control register 0 (01c8 16 ). setting 0 in this bit causes the ports to be the state of set by port direction register. this bit can be set to 0 not only by use of the applicable instruction, but by entering a falling edge in the nmi terminal or by resetting. also, if 1 is set in the positive and negative phases concurrent l output disable function enable bit (bit4) of three- phase pwm control register 0 (01c8 16 ) causes one of the pairs of u phase and u phase, v phase and v phase, and w phase and w phase concurrently go to l, as a result, the output control bit become the state of set by port direction register.
104 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer timer b2 (timer mode) overflow counter for setting the frequency of interrupt occurrences interrupt request bit u(p8 0 ) u(p8 1 ) v(p7 2 ) v(p7 3 ) w(p7 4 ) w(p7 5 ) nmi reset r d d t q d t q d t q d t q for short circuit prevention d t q d t q q inv0 3 inv0 5 diagram for switching to p8 0 , p8 1 , and to p7 2 - p7 5 is not shown. inv0 4 timer a4 counter (one-shot timer mode) (one-shot timer mode) (one-shot timer mode) trigger timer a4 reload timer a4-1 timer a1 counter trigger timer a1 reload timer a1-1 timer a2 counter trigger timer a2 reload timer a2-1 inv0 7 t q inv1 1 timer for setting short circuit prevention time (8) inv0 0 1 0 inv0 1 inv1 1 du0 du1 t dq t dq dub0 dub1 t dq t dq u phase output control circuit u phase output signal u phase output signal v phase output control circuit to be set to 0 when timer a4 stops t q inv1 1 to be set to 0 when timer a1 stops t q inv1 1 to be set to 0 when timer a2 stops u phase output control circuit v phase output signal w phase output signal v phase output signal w phase output signal signal to be written to b2 trigger signal for timer ai start trigger signal for transfer inv1 0 circuit for setting the frequency of interrupt occurrences bit 0 of three-phase output buffer register 0 bit 0 of three-phase output buffer register 1 three-phase output shift register (u phase) control signal for timer a4 reload f 2 inv1 2 0 1 1/2 n = 1 to 15 reload register n = 1 to 255 timer for setting short circuit prevention time n = 1 to 255 timer for setting short circuit prevention time (8) n = 1 to 255 n = 1 to 255 figure 11-5. block diagram for three-phase waveform mode
105 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer triangular wave modulation to generate a pwm waveform of triangular wave modulation, set 0 in the modulation mode select bit (bit 6) of three-phase pwm control register 0 (01c816). also, set 1 in the timers a4-1, a1-1, a2-1 control bit (bit 1) of three-phase pwm control register 1 (01c916). in this mode, each of timers a4, a1, and a2 has two timer registers, and alternately reloads the timer registers content to the counter every time timer b2 counters content becomes 000016. if 1 is set to the effective interrupt output specification bit (bit 1) of three-phase pwm control register 0 (01c816), the frequency of interrupt requests that occur every time the timer b2 counters value becomes 000016 can be set by use of the timer b2 counter (01cd16) for setting the frequency of interrupt occurrences. the frequency of occurrences is given by (setting; setting p 0). setting 1 in the effective interrupt output specification bit (bit 1) of three-phase pwm control register 0 provides the means to choose which value of the timer a1 reload control signal to use, 0 or 1, to cause timer b2s interrupt request to occur. to make this selection, use the effective interrupt output polarity selection bit (bit 0) of three-phase pwm control register 0 (01c816). an example of u phase waveform is shown in figure 11-6, and the description of waveform output workings is given below. set 1 in bit 0 (du0) of three-phase output buffer register 0 (01ca16). and set 0 in bit 1 (dub0) of the same register. in addition, set 0 in bit 0 (du1) of three-phase output buffer register 1 (01cb16) and set 1 in bit 1 (dub1) of the same register. also, set 0 in the effective interrupt output specification bit (bit 1) of three-phase pwm control register 0 to set a value in the timer b2 interrupt occurence frequency set counter. by this setting, a timer b2 interrupt occurs when the timer b2 counters content becomes 000016 as many as (setting) times. furthermore, set 1 in the effective interrupt output specification bit (bit 1) of three-phase pwm control register 0, set in the effective interrupt polarity select bit (bit 0) of three-phase pwm control register 0 and set "1" in the interrupt occurence frequency set counter (01cd16). these settings cause a timer b2 interrupt to occur every other interval when the u phase output goes to h. when the timer b2 counters content becomes 000016, timer a4 starts outputting one-shot pulses. in this instance, the content of the three-phase buffer register du1 and that of du0 are set in the three-phase output shift register (u phase), the content of dub1 and that of dub0 are set in the three-phase shift register (u phase). after triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer b2 counters content becomes 000016. the value of du0 and that of dub0 are output to the u terminal (p80) and to the u terminal (p81) respec- tively. when the timer a4 counter counts the value written to timer a4 (038f16, 038e16) and when timer a4 finishes outputting one-shot pulses, the three-phase shift registers content is shifted one position, and the value of du1 and that of dub1 are output to the u phase output signal and to u phase output signal respectively. at the same time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the l level of the u phase waveform doesnt lap over the l level of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift registers content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three- phase shift register goes effective, and the u phase waveform changes to the "l" level. when the timer b2 counters content becomes 000016, the timer a4 counter starts counting the value written to timer a4-1 (01c116, 01c016), and starts outputting one-shot pulses. when timer a4 finishes outputting one-shot pulses, the three-phase shift registers content is shifted one position, but if the three-phase output shift registers content changes from 0 to 1 as a result of the shift, the output level changes from l to h without waiting for the timer for setting dead time to finish outputting one-shot pulses. a u phase waveform
106 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave timber b2 interrupt occurres rewriting timer a4 and timer a4-1. possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit u phase output signal m nn mp o trigger signal: set to triangular wave modulation mode and to three-phase mode 1 control signal for timer a4 reload m the three-phase shift register shifts in synchronization with the falling edge of the a4 output. u phase u phase output signal figure 11-6. timing chart of operation (1) is generated by these workings repeatedly. with the exception that the three-phase output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform . in this way, a waveform can be picked up from the applicable terminal in a manner in which the l level of the u phase waveform doesnt lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying the values of timer b2, timer a4, and timer a4-1. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the u and u phases to generate an intended waveform.
107 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave rewriting timer a4 every timer b2 interrupt occurres. u phase output signal m nn mp o note: set to triangular wave modulation mode and to three-phase mode 1. control signal for timer a4 reload m u phase u phase output signal timer b2 interrupt occurres. rewriting three-phase buffer register. figure 11-7. timing chart of operation (2) assigning certain values to du0 (bit0) of three-phase output buffer register 0 (01ca 16 ) and dub0 (bit1) of the same register, and to du1 (bit0) of three-phase output buffer register 1 (01cb 16 ) and dub1 (bit1) of the same register allows you to output the waveforms as shown in the figure 11-7, that is, to output the u phase alone, to fix u phase to "h", to fix the u phase to "h", or to output the u phase alone.
108 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer sawtooth modulation to generate a pwm waveform of sawtooth wave modulation, set 1 in the modulation mode select bit (bit 6) of three-phase pwm control register 0 (01c8 16 ). also, set 0 in the timers a4, a1, and a2-1 control bit (bit 1) of three-phase pwm control register 1 (01c9 16 ). in this mode, the timer registers of timers a4, a1, and of a2 comprise conventional timers a4, a1, and a2 alone, and reload the corresponding timer registers content to the counter every time the timer b2 counters content becomes 0000 16 . the effective interrupt output specification bit (bit 1) of three-phase pwm control register 0 (01c8 16 ) and the effective interrupt output polarity selection bit (bit 0) turn nullified. an example of u phase waveform is shown in figure 11-8, and the description of waveform output workings is given below. set 1 in bit 0 (du0) of three-phase output buffer register 0 (01ca 16 ), and set 0 in bit 1 (dub0) of the same register. in addition, set 0 in bit 0 (du1) of three-phase output buffer register 1 (01ca 16 ) and set 1 in bit 1 (dub1) of the same register. when the timber b2 counters content becomes 0000 16 , timer b2 generates an interrupt, and timer a4 starts outputting one-shot pulses at the same time. in this instance, the contents of the three-phase buffer registers du1 and du0 are set in the three-phase output shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase output register (u phase). after this, the three-phase buffer registers content is set in the three-phase shift register every time the timer b2 counters content be- comes 0000 16 . the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (038f 16 , 038e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase output shift registers content is shifted one position, and the value of du1 and that of dub1 are output to the u phase output signal and to the u output signal respectively. at the same time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the l level of the u phase waveform doesnt lap over the l level of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift registers content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the l level. when the timer b2 counters content becomes 0000 16 , the contents of the three- phase buffer registers du1 and du0 are set in the three-phase shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase shift register (u phase) again. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the l level of the u phase waveform doesnt lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying the values of timer b2 and timer a4. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the u and u phases to gener- ate an intended waveform. setting 1 both in bit 1 (dub0) of three-phase buffer register 0 (01ca 16 ) and in bit 1 (dub1) of three- phase buffer register 1 (01ca 16 ) provides a means to output the u phase alone and to fix the u phase output to h as shown in figure 11-9.
109 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 11-8. timing chart of operation (3) timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform m n o p note: set to sawtooth modulation mode and to three-phase mode 0. interrupt occurres. rewriting the value of timer a4. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. trigger signal for timer ai start (timer b2 overflow signal)
110 timers functions for three-phase motor control under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 11-9. timing chart of operation (4) timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform mn p note: set to sawtooth modulation mode and to three-phase mode 0. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. trigger signal for timer ai start (timer b2 overflow signal) interrupt occurres. rewriting the value of timer a4. rewriting three-phase output buffer register data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. interrupt occurres. rewriting the value of timer a4.
111 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer serial i/o serial i/o is configured as four channels: uart0, uart1, uart2 and s i/o3. uart0 to 2 uart0, uart1 and uart2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 12-1 shows the block diagram of uart0, uart1 and uart2. figures 12-2 and 12-3 show the block diagram of the transmit/receive unit. uarti (i = 0 to 2) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 , 03a8 16 and 01f8 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0, uart1 and uart2 have almost the same functions. uart0 through uart2 are almost equal in their functions with minor exceptions. uart2, in particular, is compliant with the sim interface with some extra settings added in clock-asynchronous serial i/o mode (note). it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. table 12-1 shows the comparison of functions of uart0 through uart2, and figures 12-4 through 12-8 show the registers related to uarti. note: sim : subscriber identity module note 1: only when clock synchronous serial i/o mode. note 2: only when clock synchronous serial i/o mode and 8-bit uart mode. note 3: only when uart mode. note 4: using for sim interface. uart0 uart1 uart2 function clk polarity selection continuous receive mode selection lsb first / msb first selection impossible transfer clock output from multiple pins selection impossible impossible impossible impossible serial data logic switch impossible sleep mode selection impossible impossible txd, rxd i/o polarity switch impossible possible txd port output format n-channel open-drain /cmos output impossible parity error signal output impossible impossible bus collision detection impossible possible possible (note 1) separate cts/rts pins possible (note 1) possible (note 1) possible (note 3) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 3) possible possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) n-channel open-drain /cmos output n-channel open-drain /cmos output table 12-1. comparison of functions of uart0 through uart2
112 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1/(n 2 +1) 1/16 1/16 1/2 bit rate generator (address 01f9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 cts 2 /rts 2 f 2sio f 8sio f 32sio vcc rts 2 cts 2 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd 0 1/(n 0 +1) 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 /rts 0 f 2sio f 8sio f 32sio reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd 0 transmit/ receive unit rxd 1 1/(n 1 +1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 2sio f 8sio f 32sio reception control circuit transmission control circuit internal external rts 1 cts 1 txd 1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled cts/rts separated clock output pin select switch cts 1 /rts 1 /cts 0 /clks 1 cts/rts disabled cts0 from uart1 cts/rts selected cts/rts disabled v cc cts0 to uart0 cts 0 cts/rts disabled cts/rts separated cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16 figure 12-1. block diagram of uarti (i = 0 to 2)
113 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 12-2. block diagram of uarti (i = 0, 1) transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uartitransmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 data bus high-order bits
114 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 01fe 16 address 01ff 16 address 01fa 16 address 01fb 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit figure 12-3. block diagram of uart2 transmit/receive unit
115 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 12-4. serial i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 01f9 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data (note) nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate u2tb 01fb 16 , 01fa 16 indeterminate w r note: bit 8 is set to 1 when i 2 c mode is used. (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate u2rb 01ff 16 , 01fe 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: bits 15 through 12 are set to 0 when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 , 03a8 16 and 01f8 16 ) are set to 000 2 or the receive enable bit is set to 0. (bit 15 is set to 0 when bits 14 to 12 all are set to 0.) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 03a6 16 , 03ae 16 and 01fe 16 ) is read out. note 2: arbitration lost detecting flag is allocated to u2rb and noting but 0 may be written. nothing is assigned in bit 11 of u0rb and u1rb. these bits can neither be set or reset. when read, the value of this bit is 0. invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0. receive data w r receive data abt arbitration lost detecting flag (note 2) invalid 0 : not detected 1 : detected
116 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = 1 0 : odd parity 1 : even parity invalid invalid must always be 0 function (during uart mode) function (during clock synchronous serial i/o mode) uart2 transmit/receive mode register symbol address when reset u2mr 01f8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : (note) 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to 0 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = 1 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to 0 function (during uart mode) function (during clock synchronous serial i/o mode) note: bit 2 to bit 0 are set to 010 2 when i 2 c mode is used. figure 12-5. serial i/o-related registers (2)
117 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer uart2 transmit/receive control register 0 symbol address when reset u2c0 01fc 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit (note 3) 1 1 : inhibited b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol note 1: set the corresponding port direction register to 0. note 2: the settings of the corresponding port register and port direction register are invalid. note 3: only clock synchronous serial i/o mode and 8-bit uart mode are valid. note 4: for flash chips p7 1 can only be nch open drain output! 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 0 0 : f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 0 0 : f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 0 0 : f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 1 1 : inhibited b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol must always be 0 note 1: set the corresponding port direction register to 0. note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : lsb first 1 : msb first nch data output select bit 0 : txd 2 /rxd 2 pin is cmos output 1 : txd2/rxd2 pin is n-channel open-drain output (note 4) 0 : txd 2 /rxd 2 pin is cmos output 1 : txd2/rxd2 pin is n-channel open-drain output figure 12-6. serial i/o-related registers (3)
118 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 12-7. serial i/o-related registers (4) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. these bits can neither be set nor reset. when read, the value of these bits is 0. uart2 transmit/receive control register 1 symbol address when reset u2c1 01fd 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must be fixed to 0 0 : output disabled 1 : output enabled
119 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 12-8. serial i/o-related registers (5) note: when using multiple pins to output the transfer clock, the following requirements must be met: ? uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = 0. uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 rcsp uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be 0 u0irs u1irs u0rrm u1rrm 0 : cts/rts shared pin 1 : cts/rts separated 0 : cts/rts shared pin 1 : cts/rts separated separate cts/rts bit invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = 1 0 : clock output to clk1 1 : clock output to clks1 uart2 special mode register symbol address when reset u2smr 01f7 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss iic mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : iic mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. note: nothing but "0" may be written. (note)
120 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: maximum 5 mbps. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. clock synchronous serial i/o mode item specification transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 01f8 16 = 0) : fi/ 2(n+1) (note 1) fi = f 2sio , f 8sio , f 32sio ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 01f8 16 = 1) : input from clki pin (note 2) transmission/reception control ? cts function/ rts function/ cts , rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 0 _ when cts function selected, cts input level = l ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 01fc 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 01fc 16 ) = 1: clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 1 _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 01fc 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 01fc 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 01fd 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 01fd 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 12-2 and 12-3 list the specifications of the clock synchronous serial i/o mode. figure 12-9 shows the uarti transmit/receive mode register. table 12-2. specifications of clock synchronous serial i/o mode (1)
121 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item specification select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection (uart1) (note) uart1 transfer clock can be chosen by software to be output from one of the two pins set ? separate cts/rts pins (uart0) (note) uart0 cts and rts pins each can be assigned to separate pins ? switching serial data logic (uart2) whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. ? txd, rxd i/o polarity reverse (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed. note: the transfer clock output from multiple pins and the separate cts/rts pins functions cannot be selected simultaneously. clock synchronous serial i/o mode table 12-3. specifications of clock synchronous serial i/o mode (2)
122 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 12-9. uarti transmit/receive mode register in clock synchronous serial i/o mode clock synchronous serial i/o mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be 0 in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode symbol address when reset u2mr 01f8 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note) 0 : no reverse 1 : reverse note: usually set to 0.
123 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 01f8 16 ) = 0 internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 01f8 16 ) = 1 port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = 0 port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= 0 (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 01fc 16 ) =0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 01fc 16 ) = 0 port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = 0 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 01fc 16) = 0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 01fc 16 ) = 1 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 01fc 16 ) = 1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) clock synchronous serial i/o mode (when transfer clock output from multiple pins and separate cts/rts pins functions are not selected) table 12-4 lists the functions of the input/output pins during clock synchronous serial i/o mode. this table shows the pin functions when the transfer clock output from multiple pins and the separate cts/rts pins functions are not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 12-4. input/output pin functions in clock synchronous serial i/o mode
124 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 12-10. typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) clock synchronous serial i/o mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because transfer enable bit = 0 data is set in uarti transmit buffer register tc = tclk = 2(n + 1) / fi fi: frequency of brgi count source (f 2 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) h l 0 1 0 1 0 1 ctsi the above timing applies to the following settings: ? internal clock is selected. ? cts function is selected. ? clk polarity select bit = 0. ? transmit interrupt cause select bit = 0. transmit interrupt request bit (ir) 0 1 stopped pulsing because cts = h 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi h l 0 1 0 1 0 1 receive enable bit (re) 0 1 receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ? external clock is selected. ? rts function is selected. ? clk polarity select bit = 0. f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. transferred from uarti transmit buffer register to uarti transmit register meet the following conditions are met when the clk input before data reception = h ? transmit enable bit 1 ? receive enable bit 1 ? dummy data write to uarti transmit buffer register shown in ( ) are bit symbols. cleared to 0 when interrupt request is accepted, or cleared by software cleared to 0 when interrupt request is accepted, or cleared by software ? example of receive timing (when external clock is selected)
125 serial i/o under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (a) polarity select function as shown in figure 12-11, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 01fc 16 ) allows selection of the polarity of the transfer clock. figure 12-11. polarity of transfer clock (b) lsb first/msb first select function as shown in figure 12-12, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 , 01fc 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 12-12. transfer format clock synchronous serial i/o mode ? when clk polarity select bit = 1 note 2: the clk pin level when not transferring data is l. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ? when clk polarity select bit = 0 note 1: the clk pin level when not transferring data is h. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first ? when transfer format select bit = 0 d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ? when transfer format select bit = 1 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = 0.
126 serial i/o under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 12-13.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when this function is selected, uart1 cts/rts function cannot be used. figure 12-13. the transfer clock output from the multiple pins function usage microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 , bit 5 at address 01fd 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) separate cts/rts pins function (uart0) this function works the same way as in the clock asynchronous serial i/o (uart) mode. the method of setting and the input/output pin functions are both the same, so refer to select function in the next section, (2) clock asynchronous serial i/o (uart) mode. note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) serial data logic switch function (uart2) when the data logic select bit (bit6 at address 01fd 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 12-14 shows the example of serial data logic switch timing. figure 12-14. serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) h l h l h l ?when lsb first clock synchronous serial i/o mode
127 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. item specification transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 01f8 16 =0) : fi/16(n+1) (note 1) fi = f 2sio , f 8sio , f 32sio ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 01f8 16 =1) : f ext /16(n+1)(note 1) (note 2) transmission/reception control ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 0 - when cts function selected, cts input level = l reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 01fd 16 ) = 1 - start bit detection interrupt request ? when transmitting generation timing - t ransmit interrupt cause select bits (bits 0,1 at address 03b0 16 , bit4 at address 01fd 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 , bit4 at address 01fd 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 13-1 and 13-2 list the specifications of the uart mode. figure 13-1 shows the uarti transmit/receive mode register. table 13-1. specifications of uart mode (1)
128 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode table 13-2. specifications of uart mode (2) item specification select function ? separate cts/rts pins (uart0) uart0 cts and rts pins each can be assigned to separate pins ? sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro- computers ? serial data logic switch (uart2) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ? txd, rxd i/o polarity switch (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed.
129 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode figure 13-1. uarti transmit/receive mode register in uart mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = 1 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit symbol address when reset u2mr 01f8 16 00 16 ckdir uart2 transmit / receive mode register internal / external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = 1 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) note: usually set to 0.
130 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 01f8 16 ) = 0 internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 01f8 16 ) = 1 port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = 0 port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= 0 (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 01fc 16 ) =0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 01fc 16 ) = 0 port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = 0 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 01fc 16) = 0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 01fc 16 ) = 1 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 01fc 16 ) = 1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) (when separate cts/rts pins function is not selected) table 13-3 lists the functions of the input/output pins during uart mode. this table shows the pin func- tions when the separate cts/rts pins function is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 13-3. input/output pin functions in uart mode
131 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : ? parity is enabled. ? one stop bit. ? cts function is selected. ? transmit interrupt cause select bit = 1. 1 0 1 l h 0 1 tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 2sio , f 8sio , f 32sio ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 cleared to 0 when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) 0 1 0 1 0 1 the above timing applies to the following settings : ? parity is disabled. ? two stop bits. ? cts function is disabled. ? transmit interrupt cause select bit = 0. transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 2sio , f 8sio , f 32sio ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = 0 stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is h when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to l. data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. 0 sp cleared to 0 when interrupt request is accepted, or cleared by software ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 13-2. typical transmit timings in uart mode
132 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 13-3. typical receive timing in uart mode (a) separate cts/rts pins function (uart0) with the separate cts/rts bit (bit 6 at address 03b0 16 ) is set to 1, the unit outputs/inputs the cts and rts signals on different pins. (see figure 13-4.) this function is valid only for uart0. note that if this function is selected, the cts/rts function for uart1 cannot be used. (b) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. d 0 start bit sampled l receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit 1 0 0 1 h l the above timing applies to the following settings : ?parity is disabled. ?one stop bit. ?rts function is selected. receive interrupt request bit 0 1 transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to 0 when interrupt request is accepted, or cleared by software microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts0 (p6 4 ) rts0 (p6 0 ) ic figure 13-4. the separate cts/rts pins function usage
133 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode (c) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 01fd 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 13-5 shows the example of timing for switching serial data logic. figure 13-5. timing for switching serial data logic st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) txd 2 (reverse) h l h l h l ? when lsb first, parity enabled, one stop bit (d) txd, rxd i/o polarity reverse function (uart2) this function is to reverse txd pin output and rxd pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. (e) bus collision detection function (uart2) this function is to sample the output level of the txd pin and the input level of the rxd pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 13-6 shows the example of detection timing of a buss collision (in uart mode). figure 13-6. detection timing of a bus collision (in uart mode) st : start bit sp : stop bit st st sp sp transfer clock txd 2 rxd 2 bus collision detection interrupt request signal h l h l h l 1 0 bus collision detection interrupt request bit 1 0
134 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode (3) clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card i/c or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this function. table 13-4 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clk 2 pin. note 3: if an overrun error occurs, the uart2 receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. item specification transfer data format ? transfer data 8-bit uart mode (bit 2 through bit 0 of address 01f8 16 = 101 2 ) ? one stop bit (bit 4 of address 01f8 16 = 0) ? with the direct format chosen set parity to even (bit 5 and bit 6 of address 01f8 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 01fd 16 = 0). set transfer format to lsb (bit 7 of address 01fc 16 = 0). ? with the inverse format chosen set parity to odd (bit 5 and bit 6 of address 01f8 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 01fd 16 = 1) set transfer format to msb (bit 7 of address 01fc 16 = 1) transfer clock ? with the internal clock chosen (bit 3 of address 01f8 16 = 0) : fi / 16 (n + 1) (note 1) : fi=f 2 , f 8 , f 32 ? with an external clock chosen (bit 3 of address 01f8 16 = 1) : f ext / 16 (n+1) (note 1) (note 2) transmission / reception control ? disable the cts and rts function (bit 4 of address 01fc 16 = 1) other settings ? the sleep mode select function is not available for uart2 ? set transmission interrupt factor to transmission completed (bit 4 of address 01fd 16 = 1) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 01fd 16 ) = 1 - transmit buffer empty flag (bit 1 of address 01fd 16 ) = 0 r eceptio n start condition ? to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 01fd 16 ) = 1 - detection of a start bit ? when transmitting when data transmission from the uart2 transfer register is completed (bit 4 of address 01fd 16 = 1) ? when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed error detection ? overrun error (see the specifications of clock-asynchronous serial i/o) (note 3) ? framing error (see the specifications of clock-asynchronous serial i/o) ? parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an l level is output from the txd 2 pin by use of the parity error signal output function (bit 7 of address 01fd 16 = 1) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the rxd 2 pin when a transmission interrupt occurs ? the error sum flag (see the specifications of clock-asynchronous serial i/o) table 13-4. specifications of clock-asynchronous serial i/o mode (compliant with the sim interface)
135 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode figure 13-7. typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : ? parity is enabled. ? one stop bit. ? transmit interrupt cause select bit = 1. 0 1 0 1 0 1 tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 2sio , f 8sio , f 32sio ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uarti transmit buffer register sp the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit txd 2 the above timing applies to the following settings : 0 1 0 1 tc = 16 (n + 1) / fi or 16 (n + 1) / f ext receive interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a l level returns from txd 2 due to the occurrence of a parity error. a l level returns from txd 2 due to the occurrence of a parity error. rxd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 1) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 1) transferred from uarti transmit buffer register to uarti transmit register cleared to 0 when interrupt request is accepted, or cleared by software cleared to 0 when interrupt request is accepted, or cleared by software
136 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode (a) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 01fd 16 ) assigned 1, you can output an l level from the txd 2 pin when a parity error is detected. in step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. figure 13-8 shows the output timing of the parity error signal. figure 13-8. output timing of the parity error signal st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag h l h l h l 1 ? lsb first 0 (b) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d 0 data is output from txd 2 . if you choose the inverse format, d 7 data is inverted and output from txd 2 . figure 13-9 shows the sim interface format. figure 13-9. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p
137 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode figure 13-10 shows the example of connecting the sim interface. connect txd 2 and rxd 2 and apply pull-up. figure 13-10. connecting the sim interface microcomputer sim card txd 2 rxd 2
138 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode uart2 special mode register the uart2 special mode register (address 01f7 16 ) is used to control uart2 in various ways. figure 13-11 shows the special uart2 mode register. uart2 special mode register symbol address when reset u2smr 01f7 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss i c mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration loss detecting flag control bit 0 : normal mode 1 : i c mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. note: nothing but "0" may be written. (note) 2 2 function normal mode i 2 c mode (note 1) factor of interrupt number 15 (note 2) uart2 transmission no acknowledgment detection (nack) factor of interrupt number 16 (note 2) uart2 reception start condition detection or stop condition detection uart2 transmission output delay not delayed delayed p7 0 at the time when uart2 is in use txd 2 (output) sda (input/output) (note 3) p7 1 at the time when uart2 is in use rxd 2 (input) scl (input/output) p7 2 at the time when uart2 is in use clk2 p7 2 dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits uart2 reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p7 1 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when i 2 c mode is in use. set 0 1 0 in bits 2, 1, 0 of the uart2 transmission/reception mode register. disable the rts/cts function. select t x d 2 as nch. choose the lsb first function. note 2: follow the steps given below to switch from a factor to another. 1. disable the interrupt of the corresponding number. 2. switch from a factor to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when serial i/o is invalid. factor of interrupt number 10 (note 2) bus collision detection acknowledgment detection (ack) 10 initial value of uart2 output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p7 0 when the port is selected 11 uart2 special mode register figure 13-11. uart2 special mode register table13-5. features in i 2 c mode
139 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode figure 13-12 shows the functional block diagram for i 2 c mode. setting 1 in the i 2 c mode selection bit (iicm) causes ports p70, p71, and p72 to work as data transmission-reception terminal sda, clock input- output terminal scl, and port p72 respectively. a delay circuit is added to the sda transmission output, so the sda output changes after scl fully goes to l. an attempt to read port p71 (scl) results in getting the terminals level regardless of the content of the port direction register. the initial value of sda trans- mission output in this mode goes to the value set in port p70. the interrupt factors of the bus collision detection interrupt, uart2 transmission interrupt, and of uart2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. the start condition detection interrupt refers to the interrupt that occurs when the falling edge of the sda terminal (p70) is detected with the scl terminal (p71) staying h. the stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the sda terminal (p70) is detected with the scl terminal (p71) staying h. the bus busy flag (bit 2 of the special uart2 mode register) is set to 1 by the in the first place, the control bits related to the i 2 c bus(simplified i 2 c bus) interface are explained. bit 0 of the uart2 special mode register (01f7 16 ) is used as the i 2 c mode selection bit. setting 1 in the i 2 c mode selection bit (bit 0) goes the circuit to achieve the i 2 c bus interface effective. table 13-5 shows the relation between the i 2 c mode selection bit and respective control workings. in order to configure p7 0 as nch open drain output, set bit 5 (nch) in the uart transmit/receive control register 0 (u2c0). since this function uses clock-synchronous serial i/o mode, be sure to set this bit to 0 in uart mode. figure 13-12. functional block diagram for i 2 c mode uart2 special mode register selector i/o timer delay noize filter timer uart2 selector (port p7 1 output data latch) i/o p7 1 /rxd 2 /scl reception register clk internal clock uart2 external clock selector uart2 i/o timer p7 2 /clk 2 arbitration start condition detection stop condition detection data bus falling edge detection d t q d t q d t q nack ack uart2 uart2 uart2 r uart2 transmission/ nack interrupt request uart2 reception/ack interrupt request dma1 request 9th pulse iicm=1 iicm=0 iicm=1 iicm=0 iicm=1 iicm=0 iicm=0 iicm=1 iicm=0 iicm=1 iicm=1 iicm=0 port reading * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. l-synchronous output enabling bit s r q bus busy iicm=1 iicm=0 bus collision/start, stop condition detection interrupt request bus collision detection noize filter transmission register to dma0, dma1 q noize filter to dma0 p7 0 through p7 2 conforming to the simplified i c bus 2 p7 0 /txd 2 /sda nch open drain/cmos port select signal
140 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode start condition detection, and set to 0 by the stop condition detection. the acknowledgment non- detection interrupt refers to the interrupt that occurs when the sda terminal level is detected still staying h at the rising edge of the 9th transmission clock. the acknowledgment detection interrupt refers to the interrupt that occurs when sda terminals level is detected already went to l at the 9th transmission clock. also, assigning 1 1 0 1 (uart2 reception) to the dma request factor selection bits provides the means to start up the dma transfer by the effect of acknowledgment detection. bit 1 of the special uart2 mode register (01f716) is used as the arbitration loss detection flag control bit. arbitration means the act of detecting the nonconformity between transmission data and sda terminal data at the timing of the scl rising edge. this detecting flag is located at bit 3 of the uart2 reception buffer register (01ff16), and 1 is set in this flag when nonconformity is detected. use the arbitration loss detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. when setting this bit to 1 and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock. if updated the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. bit 3 of the special uart2 mode register is used as scl- and l-synchronous output enabling bit. setting this bit to 1 resets the p71 data register to 0 in synchronization with the scl terminal level going to l. uart2 special mode register
141 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode some other functions added are explained here. figure 13-13 shows their workings. bit 4 of the uart2 special mode register is used as the bus collision detect sampling clock select bit. the bus collision detect interrupt occurs when the rxd2 level and txd2 level do not match, but the nonconfor- mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to 0. if this bit is set to 1, the nonconformity is detected at the timing of the overflow of timer a0 rather than at the rising edge of the transfer clock. bit 5 of the uart2 special mode register is used as the auto clear function select bit of transmit enable bit. setting this bit to 1 automatically resets the transmit enable bit to 0 when 1 is set in the bus collision detect interrupt request bit (nonconformity). bit 6 of the uart2 special mode register is used as the transmission start condition select bit. setting this bit to 1 starts the txd transmission in synchronization with the falling edge of the rxd terminal. 1. bus collision detect sampling clock select bit (bit 4 of the uart2 special mode register) 0: rising edges of the transfer clock clk timer a0 1: timer a0 overflow 2. auto clear function select bit of transmt enable bit (bit 5 of the uart2 special mode register) clk txd/rxd bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uart2 special mode register) clk txd enabling transmission clk txd rxd with "1: falling edge of rxd 2 " selected 0: in normal state txd/rxd figure 13-13. other functions controlled by uart2 special mode register uart2 special mode register uart2 special mode register
142 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode uart2 special mode register 2 the uart2 special mode register 2(address 01f6 16 ) is used to further control uart2 in i 2 c mode. figure 13-14 shows the special uart2 mode register. figure 13-14. uart2 special mode register 2 uart2 special mode register 2 symbol address when reset u2smr2 01f6 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function stac swc2 sdhi i c mode selection bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart2 initialization bit clock-synchronous bit refer to table 1.19.10 0 : disabled 1 : enabled iicm2 csc swc asl 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: uart2 clock 1: 0 output (note) 2 shtc start/stop condition control bit set this bit to "1" in i 2 c mode (refer to table 1.19.11) uart2 special mode register 2
143 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode bit 0 of the uart2 special mode register 2(address 01f6 16 ) is used as the i 2 c mode selection bit 2. table 13-6 shows the types of control to be changed by i 2 c mode selection bit 2 when the i 2 c mode selection bit is set to "1". table 13-7 shows the timing characteristics of detecting the start condition and the stop condition. set the start/stop condition control bit (bit 7 of uart2 special mode register 2) to "1" in i 2 c mode. table 13-6. functions changed by i 2 c mode selection bit 2 function iicm2 = 1 iicm2 = 0 factor of interrupt number 15 no acknowledgment detection (nack) uart2 transmission (the rising edge of the final bit of the clock) factor of interrupt number 16 acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) timing for transferring data from the uart2 reception shift register to the reception buffer. the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock timing for generating a uart2 reception/ack interrupt request the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock 1 2 3 4 5 table 13-7. timing characteristics of detecting the start condition and the stop condition 3 to 6 cycles < duration for setting-up (note2) 3 to 6 cycles < duration for holding (note2) note 1 : when the start/stop condition count bit is "1" . note 2 : "cycles" is in terms of the input oscillation frequency f(x in ) of the main clock. duration for setting up duration for holding scl sda (start condition) sda (stop condition) uart2 special mode register 2
144 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode functions available in i2c mode are shown in figure 13-15 a functional block diagram. bit 3 of the uart2 special mode register 2 (address 01f6 16 )is used as the sda output stop bit. setting this bit to "1" causes an arbitration loss to occur, and the sda pin turns to high-impedance state the instant when the arbitration loss detecting flag is set to "1". bit 1 of the uart2 special mode register 2 (address 01f6 16 ) is used as the clock synchronization bit. with this bit set to "1" at the time when the internal scl is set to "h", the internal scl turns to "l" if the falling edge is found in the scl pin; and the baus rate generator reloads the set value, and start counting within the "l" interval. when the internal scl changes from "l" to "h" with the scl pin set to "l", stops counting the baud rate generator, and starts counting it again when the scl pin turns to "h". due to this function, the uart2 transmission-reception clock becomes the logical product of the signal flowing through the internal scl and that flowing through the scl pin. this function operates over the period from the moment earlier by a half cycle than falling edge of the uart2 first clock to the rising edge of the ninth bit. to use this function, choose the internal clock for the transfer clock. bit 2 of the uart2 special mode register 2 (01f6 16 ) is used as the scl wait output bit. setting this bit to "1" causes the scl pin to be fixed to "l" at the falling edge of the ninth bit of the clock. setting this bit to "0" frees the output fixed to "l". figure 13-15. functional block diagram for i 2 c mode iicm=1 and iicm2=0 iicm=1 and iicm2=0 iicm=0 or iicm2=1 iicm=0 or iicm2=1 to dma0, dma1 to dma0 i/0 noize filter p7 1 /rxd 2 /scl reception register clk control uart2 noize filter uart2 p7 2 /clk 2 d t q d t q uart2 uart2 r iicm=1 iicm=0 iicm=0 iicm=1 iicm=1 iicm=0 s r q r s swc falling of 9th pulse swc2 start condition detection stop condition detection falling edge detection l-synchronous output enabling bit data register selector internal clock external clock selector i/0 timer port reading bus busy uart2 transmission/ nack interrupt request uart2 reception/ack interrupt request dma1 request nack ack iicm=1 iicm=0 * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. bus collision detection 9th pulse bus collision/start, stop condition detection interrupt request i/0 delay noize filter uart2 d t q uart2 iicm=1 iicm=0 als sdhi selector timer arbitration transmission register p7 0 /txd 2 /sda nch open drain/cmos port select signal uart2 special mode register 2
145 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode bit 4 of the uart2 special mode register 2(address 01f6 16 ) is used as the uart2 initialization bit. setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows: (1) the transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. this starts transmission by dealing with the clock entered next as the first bit. the uart2 output value, however, does not change until the first bit data is output after the entrance ofr the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) the reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) the scl wait output bit turns to "1". this turns the scl pin to "l" at the falling edge of the ninth bit of the clock. starting to transmit/receive signals to/from uart2 using this function does not change the value of the transmission buffer empty flag. to use this function, choose the external clock for the tansfer clocl. bit 5 of the uart2 special mode register 2 (01f6 16 ) is used as the scl pin wait output bit 2. setting this bit to "1" with the serial i/o specified allows the user to forcibly output an "l" from the scl pin even if uart2 is in operation. setting this bit to "0" frees the "l" output from the scl pin, and the uart2 clock is input/output. bit 6 of the uart special mode register 2 (01f6 16 ) is used as the sda output enable bit. setting this bit to "1" forces the sda pin to turn to the high-impedance state. refrain from changing the value of this bit at the rising edge of the uart2 transfer clock. there can be instances in which arbitration loss detecting flag is turned on. uart2 special mode register 2
146 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer s i/o3 s i/o3 s i/o3 is exclusive clock-synchronous serial i/o. figure 14-1 shows the s i/o3 block diagram, and figure 14-2 shows the s i/o3 control register. table 14-1 shows the specifications of s i/o3. figure 14-1. s i/o3 block diagram figure 14-2. s i/o3 control register s i/o3 transmission/reception register (8) s i/o3 counter (3) synchronous circuit f 2 sio f 8 sio f 32 sio data bus 8 s i/o3 interrupt request sm35 lsb msb sm32 sm33 sm33 sm36 sm31 sm30 p9 0/ clk 3 p9 2/ s out3 p9 1/ s in3 transfer rate register (8) sm36 n: a value set in the s i/o3 transfer rate register (01e3 16 ) 1/(n+1) 1/2 s i/o3 control register (note 1) symbol address when reset s3c 01e2 16 40 16 b7 b6 b5 b4 b3 b2 b1 b0 w r description sm35 sm31 sm30 sm33 sm36 sm37 internal synchronous clock select bit transfer direction select bit s i/o3 port select bit (note 2) s out3 initial value set bit 0 0 : selecting f 2sio 0 1 : selecting f 8sio 1 0 : selecting f3 2sio 1 1 : not to be used b1 b0 0 : external clock 1 : internal clock effective when sm33 = 0 0 : l output 1 : h output 0 : input-output port 1 : s out3 output, clk function output, bit name bit symbol synchronous clock select bit 0 : lsb first 1 : msb first sm32 s out3 high impedance control bit 0 : s out3 output 1 : s out3 high impedance note 1: set "1" in bit 2 of the protection register (000a 16 ) in advance to write to the s i/o3 control register. nothing is assigned. this bit can neither be set nor read. when read, the value of this bit is 0. note 2: when set "0" to sm33 and select input - output port, set "1" to sm36 and select internal clock, or input "h" to p9 0 and p9 5 .
147 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer s i/o3 table 14-1. specifications of s i/o3 note 1: n is a value from 00 16 through ff 16 set in the s i/o3 transfer rate register. note 2: with the external clock selected: ? to write to the s i/o3 transmission/reception register (01e2 16 ), enter the h level to the clk3 terminal. also, to write to the bit 7 (s out3 initial value set bit) of si/o3 control register (01e2 16 ), enter the h level to the clk3 terminal. ? the s i/o3 circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. the internal clock, if selected, automatically stops. note 3: if the internal clock is used for the synchronous clock, the transfer clock signal stops at the h state. figure 14-3. si/o3 related register si/o3 bit rate generator b7 b0 symbol address when reset s3brg 01e3 16 indeterminate indeterminate assuming that set value = n, brg3 divides the count source by n + 1 00 16 to ff 16 values that can be set w r si/o3 transmit/receive register b7 b0 symbol address when reset s3trr 01e0 16 indeterminate indeterminate transmission/reception starts by writing data to this register. after transmission/reception finishes, reception data is input. w r item transfer data format transfer clock conditions for transmission/ reception start interrupt request generation timing select function specifications ? transfer data length: 8 bits ? with the internal clock selected (bit 6 of 01e2 16 = 1): f2sio/2(n+1), f8sio/2(n+1), f32sio/2(n+1) (note 1) ? with the external clock selected (bit 6 of 01e2 16 ): input from the clk3 terminal (note 2) ? to start transmit/reception, the following requirements must be met: - select the synchronous clock (use bit 6 of 01e2 16 ). select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 01e2 16 ). - s out 3 initial value set bit (use bit 7 of 01e2 16 )= 1. - s i/o3 port select bit (bit 3 of 01e2 16 ) = 1. - select the transfer direction (use bit 5 of 01e2 16 ) ? to use s i/o3 interrupts, the following requirements must be met: - s i/o3 interrupt request bit (bit 3 of 0049 16 ) = 0. ? an interrupt occurs after counting eight transfer clock either in transmitting or receiving data. (note 3) - in transmitting: at the time data transfer from the s i/o3 transmission/reception register finishes. - in receiving: at the time data reception to the s i/o3 transmission/reception register finishes. ? lsb first or msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected.
148 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer s i/o3 functions for setting an s out3 initial value in carrying out transmission, the output level of the sout3 terminal as it is before transmitting 1-bit data can be set either to h or to l. figure 14-4 shows the timing chart for setting an sout3 initial value and how to set it. figure 14-4. timing chart for setting sout3s initial value and how to set it s i/o3 operation timing figure 14-5 shows the s i/o3 operation timing d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) s i/o3 output s out 3 s i/o3 input s in 3 signal written to the s i/o3 register (note 2) setting the s i/o3 interrupt request bit note 1: with the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the s i/o3 control register. (2-division frequency, 8-division frequency, 32-division frequency) note 2: with the internal clock selected for the transfer clock, the s out 3 terminal becomes to the high-impedance state after the transfer finishes. figure 14-5. s i/o3 operation timing chart signal written to the s i/o3 transmission/reception register s out3 (internal) s out3 's initial value setting bit (sm37) s out3 terminal output s i/o 3 port select bit (sm33) setting the s out3 initial value to h port selection (normal port -> s out3 ) d0 initial value = h (note) port output d0 (example) with h selected for s out3 note: the set value is output only when the external clock has been selected. if the internal clock has been selected or if s out high impedance has been set, this output goes to the high-impedance state. s i/o3 port select bit sm33 = 0 s out 3 initial value select bit sm37 = 1 (s out 3: internal -> h level) s i/o3 port select bit sm33 = 0 -> 1 (port select: normal port -> s out 3) s out 3 terminal = h output signal written to the s i/o3 register =l -> h -> l (falling edge) s out 3 terminal = outputting stored data in the s i/o3 transmission/reception register
149 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter note 1: does not depend on use of sample and hold function. note 2: without sample and hold function, set the f ad frequency to 250khz min. with the sample and hold function, set the f ad frequency to 1mhz min. in either case, the f ad frequency may not exceed 10 mhz. table 15-1. performance of a-d converter a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p0 0 to p0 7 , p2 0 to p2 7 , p10 0 to p10 7 , p9 5 , and p9 6 function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the 8 bits are stored in the even addresses. table 15-1 shows the performance of the a-d converter. figure 15-1 shows the block diagram of the a-d converter, and figures 15-2 and 15-3 show the a-d converter-related registers. item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating condition (note 2) v cc = 5v, f ad2 divided by 1, 2, or 4, f ad2 =f(x in ) divided by 1 or 2 resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? with sample and hold function (10-bit resolution) an 0 to an 7 input : 3lsb anex0 and anex1 input (including mode in which external operation amp is connected) : 7lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 24 pins (an 0 to an 7 , an 00 to an 07 and an 20 to an 27 ) + 2 pins (anex0 and anex1) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 ? external trigger (can be retriggered) a-d conversion starts when the a-d conversion start flag is 1 and the ad trg /p9 7 input changes from h to l conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles , 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles , 10-bit resolution: 33 f ad cycles
150 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter figure 15-1. block diagram of a-d converter 1/2 ad 1/2 f ad2 a-d conversion rate selection (03c1 16 , 03c0 16 ) (03c3 16 , 03c2 16 ) (03c5 16 , 03c4 16 ) (03c7 16 , 03c6 16 ) (03c9 16 , 03c8 16 ) (03cb 16 , 03ca 16 ) (03cd 16 , 03cc 16 ) (03cf 16 , 03ce 16 ) cks1=1 cks0=0 0 0 : normal operation 0 1 : anex0 1 0 : anex1 1 1 : external op-amp mode a-d register 0(16) a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) resistor ladder anex1 anex0 successive conversion register opa1,opa0=0,1 opa0=1 opa1=1 opa1,opa0=1,1 a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) v ref v in data bus high-order data bus low-order v ref opa1,opa0=0,0 vcut=0 av ss vcut=1 cks0=1 cks1=0 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 decoder comparator opa1, opa0 addresses adgsel1,0 00 2 10 2 11 2 an0 an00 an20 an1 an01 an21 an2 an02 an22 an3 an03 an23 an4 an04 an24 an5 an05 an25 an6 an06 an26 an7 an07 an27
151 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad2 /4 is selected 1 : f ad2 /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected external op-amp connection mode bit w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad2 /2 or f ad2 /4 is selected 1 : f ad2 is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. figure 15-2. a-d converter-related registers (1)
152 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter figure 15-3. a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 xxxx0000 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. nothing is assigned. these bits can neither be set nor reset. when read, their content is 0. a-d register i symbol address when reset adi(i=0 to 7) 03c0 16 to 03cf 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) ? during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. these bits can neither be set nor reset. when read, their content is 0. ? during 8-bit mode when read, the content is indeterminate smp reserved bit always set to 0 0 0 0 : port p10 group select 0 1 : inhibited 1 0 : port p0 group select 1 1 : port p2 group select b2 b1 a-d group select bit adgsel0 adgsel1
153 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter figure 15-4. a-d conversion register in one-shot mode (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. table 15-2 shows the specifications of one-shot mode. figure 15-4 shows the a-d control register in one-shot mode. table 15-2. one-shot mode specifications item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 w r 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected external op-amp connection mode bit 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 0 : one-shot mode (note 2) b4 b3 ch0 b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit1 0 : f ad2 /2 or f ad2 /4 is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 1 : f ad2 is selected 0 : f ad2 /4 is selected 0 : f ad2 /2 is selected
154 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure 15-5. a-d conversion register in repeat mode (2) repeat mode i n repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 15-3 shows the specifications of repeat mode. figure 15-5 shows the a-d control register in repeat mode. table 15-3. repeat mode specifications a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad2 /4 is selected 1 : f ad2 /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 1 : repeat mode (note 2) b4 b3 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 0 : f ad2 /2 or f ad2 /4 is selected 1 : f ad2 is selected
155 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad2 /4 is selected 1 : f ad2 /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 0 invalid in single sweep mode 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither 01 nor 10 can be selected with the external op-amp connection mode bit b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad2 /2 or f ad2 /4 is selected 1 : f ad2 is selected cks1 item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (3) single sweep mode i n single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 15-4 shows the specifications of single sweep mode. figure 15-6 shows the a-d control register in single sweep mode. table 15-4. single sweep mode specifications figure 15-6. a-d conversion register in single sweep mode
156 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad2 /4 is selected 1 : f ad2 /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 0 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither 01 nor 10 can be selected with the external op-amp connection mode bit. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad2 /2 or f ad2 /4 is selected 1 : f ad2 is selected cks1 item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 15-5 shows the specifications of repeat sweep mode 0. figure 15-7 shows the a- d control register in repeat sweep mode 0. table 15-5. repeat sweep mode 0 specifications figure 15-7. a-d conversion register in repeat sweep mode 0
157 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad2 /4 is selected 1 : f ad2 /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 1 : repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 1 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither 01 nor 10 can be selected with the external op-amp connection mode bit. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad2 /2 or f ad2 /4 is selected 1 : f ad2 is selected cks1 (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 15-6 shows the specifications of repeat sweep mode 1. figure 15-8 shows the a-d control register in repeat sweep mode 1. table 15-6. repeat sweep mode 1 specifications figure 15-8. a-d conversion register in repeat sweep mode 1
158 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer a-d converter analog input external op-amp an 0 an 7 an 1 an 2 an 3 an 4 an 5 an 6 anex1 anex0 resistor ladder successive conversion register comparator (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved with 8-bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. (b) extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex0 and anex1 can also be converted from analog to digital. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 1 and bit 7 is 0, input via anex0 is converted from analog to digital. the result of conversion is stored in a-d register 0. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 0 and bit 7 is 1, input via anex1 is converted from analog to digital. the result of conversion is stored in a-d register 1. (c) external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex0 and anex1, can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 1 and bit 7 is 1, input via an 0 to an 7 is output from anex0. the input from anex1 is converted from analog to digital and the result stored in the corresponding a-d register. the speed of a-d conversion depends on the response of the external opera- tion amp. do not connect the anex0 and anex1 pins directly. figure 15-9 is an example of how to connect the pins in external operation amp mode. figure 15-9. example of external op-amp connection mode
159 d-a converter under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 16-1 lists the performance of the d-a converter. figure 16-1 shows the block diagram of the d-a converter. figure 16-2 shows the d-a control register. figure 16-1. block diagram of d-a converter table 16-1. performance of d-a converter p9 3 /da 0 p9 4 /da 1 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 )
160 d-a converter under developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 16-2. d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0 d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion figure 16-3. d-a converter equivalent circuit v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: the same circuit as this is also used for d-a1. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d- a register to 00 16 so that no current flows in the resistors rs and 2rs.
161 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer crc figure 17-2. crc-related registers crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcomputer uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is completed in two machine cycles. figure 17-1 shows the block diagram of the crc circuit. figure 17-2 shows the crc-related registers. figure 17-3 shows the calculation example using the crc calculation circuit. figure 17-1. block diagram of crc circuit eight low-order bits eight high-order bits data bus high-order bits data bus low-order bits crc data register (16) crc input register (8) crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 03bd 16 , 03bc 16 ) (address 03be 16 ) symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16
162 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer crc figure 17-3. calculation example using the crc calculation circuit b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1
163 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can module 0/1 the can module provides the can (controller area network) serial-bus data communication interface. this asynchronous communication protocol is used in distributed systems, such as automotive and industrial control systems and where high-speed processing and data exchange are required w ith a very high level of security. this module supports data transfer rates up to 1 mbps. according to the bosch 2.0b can protocol specification, the can module can handle and process both the standard and extended identifier message formats. for more details, refer to the bosch can specifi- cation 2.0b, hereinafter referred to as can specification. can configu ration register can con trol register can extid register interrupt control logic messag e mailbox slot 0 - 15 message id dlc message data tim e stamp wake up logic protocol controller ctx crx can global mask register can local mask a register can local mask b register recsuc int trmsuc int can error int can wake-up int data bus data bus can time stamp register 16 bit time r acceptance filter can slot status register can int co ntrol register can status register can rec register can tec register can message control register 0 -15 mailbox 0 - 15 figure 18-1. block diagram of one can module figure 18-1 shows a block diagram of the m16c can module. the main functional blocks in this description are: protocol controller: this controller handles the bus arbitration and the can serial communication protocol message transmission and reception services, i.e. bit stuffing, crc, error status etc. message mailbox: this memory block consists of several message slots which can be configured to act either as a transmit- or receive message box. each slot consists of a relevant identi- fier, data length code, a data field (8 bytes) and a communication time stamp. this message slot time stamp value corresponds to the instant of time (event) when the protocol controller indicates a successful can message reception. acceptance filter: this block performs the comparison between the identifier of the received message and the key identifier of all receive slots. for this acceptance filter, users can define the content of special mask registers to filter a range of identifier for the correspond- ing message slot. 16 bit timer: this 16 bit timer is used for a time stamp function. the timer provides the counter status which will be stored together with the received message in the message mail- box.
164 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer interrupts ? 6 interrupts can0 - successful transmission interrupt can0 - successful reception interrupt can1 - successful transmission interrupt can1 - successful reception interrupt can0/1 - error interrupt - error passive state - error busoff state - bus error (this feature could be disabled separately) can0/1 - wake up interrupt when the cpu detects an successful transmission/reception interrupt, the can status register must be read to determine which mailbox has issued the interrupt. memory map of the can0/1 special function registers this memory map is valid for both can channels (can0 and can1) ? can mailboxes - 16 message slots (each mailbox comprises 16 bytes (8 words)) - fixed mailbox-organization - 'basic can'-feature is composed of two regular can slots (#14/15) - this feature is implemented as an option. ? can mask registers - 3 masks for the acceptance filter (refer to section 'mask register and acceptance filter') (each mask comprises 6 bytes) ? can sfr registers - 9 can special function registers control register (16 bits): controls the can module. status register (16 bits): displays the status of the can module. slot status register (16 bits): for each slot, the current content status is monitored. interrupt control register (16 bits): for each slot, the interrupts can be disabled. extended id register (16 bits): distinguishes between extendedid and standardid mailboxes. configuration register (16 bits): configuration of the bus timing rec register (8 bits) : receive error counter of the can module tec register (8 bits) : transmit error counter of the can module time stamp register (16 bits): time stamp counter wake up logic: the mcu can be set to stop- or wait mode to reduce power consumption. this module provides the possibility to wake up the mcu from sleep mode via the can bus (refer to section can wake up interrupt). interrupt generation: the can module signals the cpu different events via 6 interrupts. four interrupt channels are used for successful can message transmission and re- ception indication, i.e. 'message receive successful' interrupt (c0recic/c1recic) and 'message transmit successful' interrupt (c0trmic/ c1trmic). one interrupt signals if the can module enters an error operating state (c01erric), i.e. 'error passive', 'bus off' and if any can bus error occurred in the communication process. the can bus error interrupt generation can be individually disabled in the can control register. the wake up case will also be flagged to the cpu by an additional interrupt line (c01wkpic).
165 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer memory map of a message object table 18-2. message object overview (can1) to access the message memory, either linear address order (byte access) or crossed address order (word access), which supports word access especially for even addresses, can be selected. the location of the message object bytes depends on the message order control bit (msgorder), which selects byte- or word address order. refer also to section 'can control register'. table 18-1. message object overview (can0) address content byte order (8 bits) word order (16 bits) 0060 16 + x16 + 0 stdid [10 to 6] stdid [5 to 0] 0060 16 + x16 + 1 stdid [5 to 0] stdid [10 to 6] 0060 16 + x16 + 2 extid [17 to 14] extid [13 to 6] 0060 16 + x16 + 3 extid [13 to 6] extid [17 to 14] 0060 16 + x16 + 4 extid [5 to 0] dlc 0060 16 + x16 + 5 dlc extid [5 to 0] 0060 16 + x16 + 6 data byte 0 data byte 1 0060 16 + x16 + 7 data byte 1 data byte 0 ... ... ... 0060 16 + x16 + 13 data byte 7 data byte 6 0060 16 + x16 + 14 time stamp upper byte time stamp lower byte 0060 16 + x16 + 15 time stamp lower byte time stamp upper byte note: x: number of message slot (x = 0 to 15) address content byte order (8 bits) word order (16 bits) 0260 16 + x16 + 0 stdid [10 to 6] stdid [5 to 0] 0260 16 + x16 + 1 stdid [5 to 0] stdid [10 to 6] 0260 16 + x16 + 2 extid [17 to 14] extid [13 to 6] 0260 16 + x16 + 3 extid [13 to 6] extid [17 to 14] 0260 16 + x16 + 4 extid [5 to 0] dlc 0260 16 + x16 + 5 dlc extid [5 to 0] 0260 16 + x16 + 6 data byte 0 data byte 1 0260 16 + x16 + 7 data byte 1 data byte 0 ... ... ... 0260 16 + x16 + 13 data byte 7 data byte 6 note: x: number of message slot (x = 0 to 15) 0260 16 + x16 + 14 time stamp upper byte time stamp lower byte 0260 16 + x16 + 15 time stamp lower byte time stamp upper byte
166 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 18-3. bit organization of the message objects for word access bit 15 bit 0 stdid[10 to 6] stdid[5 to 0] extid[17 to 14] extid[13 to 6] extid[5 to 0] dlc[3 to 0] data 0[7 to 0] data 1[7 to 0] can data frame: data 7[7 to 0] sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 bit 8 bit 7 eid 17 eid 16 eid 15 eid 14 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 dlc 3 dlc 2 dlc 1 dlc 0 data byte 0 data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 time stamp [15 to 8] time stamp [7 to 0] figure 18-2. bit organization of the message objects for byte access bit 7 bit 0 sid 10 sid 9 sid 8 sid 7 sid 6 stdid [10 to 6] sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 stdid [5 to 0] eid 17 eid 16 eid 15 eid 14 extid [17 to 14] eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 extid [13 to 6] eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 extid [5 to 0] dlc 3 dlc 2 dlc 1 dlc 0 dlc data byte 0 data byte 1 data byte 7 ... stdid[10 to 6] stdid[5 to 0] extid[17 to 14] extid[13 to 6] extid[5 to 0] dlc[3 to 0] data 0[7 to 0] data 1[7 to 0] can data frame: data 7[7 to 0] time stamp [15 to 8] time stamp upper byte time stamp [7 to 0] time stamp lower byte can message objects data can be written in the grey shaded bits in the identifier bytes. but in the case of read-process, the value of these bits will be set to "0" if a successful receive process is performed for the corresponding slot. in case of no message storage by the can module, these bits contain their previous values (written by the cpu). please note the meaning of byte order in the message object. this order corresponds directly with the data field on the bus in chronological order (see figures. 18-2/18-3 can data frames).
167 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can configuration register a programmable clock prescaler is used to derive the can module basic clock from the clock frequency f (can0/1) /2. bit 0 to bit 3 of the can configuration register represent the prescaler, allowing a division ratio of 1 to 1/16 to be selected. so the can module basic clock frequency f canb can be calculated as follows: f canb f (can0/1) 2 x (brp + 1) ---------------------------------------- - = where brp is the value of the prescaler (selectable from 0 to 15). the effective baud rate of the can bus communication depends on the can bus timing control parameters and will be explained below. figure 18-5. bit timing the first segment (ss) is fixed to one time quantum, the segments pr, ph1 and ph2 can be programmed from 1 to 8 time quanta by the can configuration register. the whole bit-time has to consist of minimum 8 and maximum 25 time quanta. the duration of one time quantum is the cycle time of f canb . baudrate f (can0/1) 2 x (brp + 1) x num(quanta ) ------------------------------------------------------------------------- = for example: assuming f(x in )=16mhz and brp=0, one time quantum will be 125ns long. this allows a maximum transmission rate of 1mbps (assuming 8 time quanta per bit-time). can bus timing control each bit-time consists of four different segments: figure 18-4. generation of can basic clock frequency ss pr ph1 ph2 sample point bit-time synchronization segment (ss), propa gation time segment (pr), phase buffer se gment 1 (ph1) and phase buffer se gment 2 (ph2). f canb 0 f can0 1/2 1/brp0 f canb1 f can1 1/2 1/brp1
168 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 18-6. description of can configuration register (settings for can bus timing) symbol address when reset c0conr 021a indeterminate c1conr 023a indeterminate b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function r w brp prescaler divider oo sam sampling control bit 0: 1: one sample per bit three samples per bit oo propagation time prescaler division ratio selection 0 0 0 0 : 1 0 0 0 1 : 1/2 0 0 1 0 : 1/3 ... 1 1 1 1 : 1/16 duration control bits 0 0 0 : one time quantum 0 0 1 : two time quanta ... 1 1 0 : seven time quanta 1 1 1 : eight time quanta oo (b15) (b8) b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function r w ph1 phase buffer segment 1 duration control bits oo ph2 phase buffer segment 2 oo sjw synchronization jump width 0 0 0 : one time quantum 0 0 1 : two time quanta ... 1 1 0 : seven time quanta 1 1 1 : eight time quanta duration control bits 0 0 0 : one time quantum 0 0 1 : two time quanta ... 1 1 0 : seven time quanta 1 1 1 : eight time q uanta control bits 0 0 : one time quantum 0 1 : two time quanta 1 0 : three time quanta 1 1 : four time quanta oo can configuration registers symbol address when reset c0conr 021b 16 indeterminate c1conr 023b 16 16 16 indeterminate b3 b2 b1 b0 b7 b6 b5 b2 b1b0 b5 b4 b3 b7 b6 pr
169 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 18-7. structure of can control register can control register bit symbol bit name function r w reset can module reset 0: 1: operation mode reset / initialization mode oo loopback loop back mode for can module 0: 1: normal operation mode loop back mode (read back and store the transmitted message) oo msgorder message order 0: 1: the address order is adapted to word access (16bit) for the message objects and also the mask memory. the address order is byte linear(8bit access). oo basiccan basic can feature 0: 1: normal operation mode: slot #14/15 receive messages according to the 'first fit' system. the can module switches between the two active receive-slots #14 and #15 in case of successive messages fitting into both slots. oo buserren bus error enable 0: 1: bus-errors will not be visible for icu/cpu. bus-errors will be flagged for the icu via the can error interrupt signal. oo sleep local sleep mode for can module 0: 1: operation mode clock of the can module will be stopped. oo porten can port enable 0: 1: port serves as i/o port. port serves as can terminal (crx/ctx). oo when read, its content is indeterminate. -- can control register (b15) (b8) b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function r w tsprescale bit1, bit0 timestamp (ts) prescaler prescaler value for ts counting source (basic source is the can bit-clock.) 0 0: bit-clock 0 1: (bit-clock)/2 1 0: (bit-clock)/4 1 1: (bit-clock)/8 oo tsreset timestamp (ts) reset 0: 1: ts counter counts bit cycles (s. the divider stages is activated by tsprescale setting.) reset (counter value is cleared to $0000.) oo retbusoff return from 'error busoff' state 0: 1: normal operation mode reset only for the can module to return from 'error busoff' state oo nothing is assigned. it is not allowed to write '1' to these bit locations. nothing is assigned. it is not allowed to write '1' to this bit location. when read, their contents are indeterminate. -- *) note: if the ts reset/retbusoff (write '1') is activated, the control bit will be cleared automatically by the can module after performing the reset for the ts counter or the return from 'busoff' state. symbol address when reset c0ctlr 0210 16 01 16 c1ctlr 0230 16 01 16 symbol address when reset c0ctlr 0211 16 00 16 c1ctlr 0231 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 (note) (note)
170 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer after leaving the mcu 'reset'-state, the can module starts in 'reset/initialization' mode. all module setup parameters should be written in the relevant registers to enable the can module to take part in the can bus communication with the correct transfer rate , bit timing etc. (can configuration register). after finishing the initialization stage, the 'reset' bit (can control register) has to be cleared by the user and the can module will start the bus participation according to the can specification. in order to change the existing setting of the protocol configuration, activate 'reset/initialization' mode also during normal operation. in this case, the can module will leave the can bus communication in conformity with the protocol. this means, a just started transmit process has to be finished before entering the 'reset' state. in case the protocol engine enters the 'error busoff' state, the system can be restarted in 'error active' mode by setting the 'retbusoff' bit in the can control register. this 'reset' for the 'protocol controller' has no effect on the can-interface configuration. the entire slot-configuration, slot contents and all sfr set- tings will be kept without changes.
171 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer basic can feature some applications for the can network operate with more than 16 message types (identifiers), so an original can approach (one slot corresponds to one message type) is not a feasible way for these systems. the first approach to give system support for these applications is the sophisticated mask concept implemented in this can module (refer to section 'mask register and acceptance filter'). in case there is the requirement to receive most or all messages from the can bus (performing further acceptance filter by software), the can module provides a special slot configuration to support this kind of system solution. in the normal operation mode, the received message is stored in the first fitting message slot. the slots under consideration for this decision will be determined in the acceptance filter phase. in this case many messages will be received by one slot, the cpu is heavily loaded to serve this slot without loosing a message because of 'overwriting' (receiving the next fitting message). by activating the 'basic can' feature, the slot scheduling in 'receive' case changes for slot #14 and #15. received messages are stored alternately in these two message boxes. the can module uses two different slot addresses to build the basic can feature (no shadow buffer concept). the 'lock/unlock' function will be controlled exclusively by the can module without any influence of the cpu. there is no 'message protection mechanism' implemented, so the message n+2 will overwrite the content of message n (figure 18-7). the following restrictions have to be kept in case of using the 'basic can' feature: - the module configuration ('basic can' on/off) should be selected before leaving the 'reset/initializa- tion' state. the can module will store the first fitting message into slot #14 (in case the filtering failed for all preceding slots). in case the 'basic can' feature will be enabled or disabled 'on the fly', the slot where the first message will be stored is undetermined. - the can module never checks, whether or not the received message will be accepted by slot #15 when slot #14 is locked (last message is stored in slot #14). therefore it is recommended to use the same identifier for the message slots #14 and #15 (building the 'basic can' channel) and the same mask values for both local masks. otherwise a received message might be dropped by the can module, although slot #14 could accept this message. figure 18-8. receive slot scheduling for implementing the 'basic can' feature slot 14 slot 15 msg n msg n+1 msg n+2 empty locked (empty) locked (empty) msg n locked msg n + 1 msg n+2 (lost msg n) locked (msg n+1 ) etc. (msg n)
172 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer in the 'basic can' mode, two exceptions regarding the message control register and the general configura- tion concept exist: 1. can frame type tolerance in the 'normal operation mode', decide if an activated slot should handle 'data' or 'remote' frames. it is not possible to receive 'data' frames and 'remote' frames in the same slot without a reconfiguration process by the cpu. in case of the operation with a 'basic can' channel, this behavior is not tolerable, because both frame types must be handled without cpu interaction. therefore, the 'basic can' feature enables message slots #14 and #15 to receive both types of can frames, 'data'- and 'remote' frames. 2. can frame type indication in the 'normal operation mode', the extended id register (c0idr/c1idr) dictates the type of frames, i.e. extended or standard, which can be handled by the message box. as described in the upper section for the 'basic can' slots, it is possible to receive both frame types irrespective of the slot configuration. therefore, the can module provides the frame type information in the corresponding message control register. because the 'remactive' information is not needed for the 'basic can' slot function, the frame type informa- tion is mapped to this location (refer to section 'can message control register'). the content of this bit corresponds to the frame type stored last in this slot location . can extended id register figure 18-9. structure of can extended id register (b15) (b8) b7 b6 b0 b7 b0 function values that can be set for each bit rw extid bits each bit corresponds with the appropriate message mailbox. id-format assignment for each message mailbox 0: 1: mailbox handles standard identifiers. mailbox handles extended identifiers. oo can extid register symbol address when reset c0idr 0219 16 , 0218 16 0000 16 c1idr 0239 16 , 0238 16 0000 16 note: these bits can not be set in reset/initialization mode.
173 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can message control register figure 18-10. structure of can message control register b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function r w newdata new data 0: 1: - receive mailbox the content of the message slot is read or still under processing by the cpu. the can module has stored new data in the corresponding mailbox. oo sentdata sent data 0: 1: - transmit mailbox transmission is not started/finished yet. frame is transmitted successfully. invaldata invalid data 0: 1: - receive mailbox the content of the message slot is valid. message slot contains invalid data (update of the message content is in progress). oo trmactive transmission active 0: 1: - transmit mailbox slot is waiting for bus free and passing internal transmit arbitration. transmit process for this message is active. msglost message lost 0: 1: - receive mailbox no message was overwritten in this slot. this mailbox already contained a message, but it was overwritten by a newer one. oo remactive remote active 0: 1: the module handles data frames; transmit/ receive case depends on the slot configuration (basiccan mode: data frame is stored). remote part of the auto-switch modes (trans- mit remote frame / receive remote frame) is active (basiccan mode: remote frame is stored). oo rsplock response locked 0: 1: - transmission remote mailbox after a remote frame is received, it will be answered automatically. after a remote frame is received, no transmis- sion will be started as long as this bit is set to 1. oo remote remote mailbox 0: 1: mailbox is remote mailbox (s. also table 18-3) oo recreq receive mailbox 0: 1: mailbox is receive mailbox (s. also table 18-3) oo trmreq transmit mailbox 0: 1: mailbox is transmission mailbox (s. also table 18-3) oo note: the write access on cpu side is limited to 'write only 0'. if the cpu tries to set these bits to 1, it will not have any influence to the content of these bits. in this case, the values of these bits are forced to their 'status meaning' defined by the current state of the can module. can message control register i symbol address when reset c0mctli 0200 to 020f 00 16 c1mctli 0220 to 022f 00 16 16 16 16 16 (i = 0 to 15) (note) (note) (note) (note)
174 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer reception- and transmission modes table 18-3. table of all reception- and transmission modes notes - reception mode ? a received message, which fulfills the comparison conditions of several mailboxes, will be stored in the first suitable mailbox starting with the message mailbox slot0 (special case for the 'basic can' feature). this means the message will be stored only one time. ? when the can module transmits a message, the can module receives its own message. however, the can module does not store that message in the normal operation mode, even if there is a receive box with a fitting identifier. in case the can module operates in the 'loop back' mode (can control register), the transmitted message is stored in a prepared mailbox (receivebox with corresponding identifier). notes - transmission mode ? overwrite procedure of an activated transmission mailbox - in order to activate a transmission mailbox, set the configuration bits according to table 18-3. - in order to overwrite the content of a transmission mailbox, deactivate the transmission mailbox. this means, the cpu must clear the trmreq-bit (together with the recreq-bit!). - the cpu has to read the trmactive-bit to check its current status. when the trmactive-bit is '0', the abort request is successful and the cpu can overwrite the data of the transmission mailbox. - after this check, the cpu has the possibility to determine whether the message is transmitted or not. the abort request by cpu side is executed (successful), in case the sentdata-bit is not set. otherwise the message is transmitted successfully in spite of the abort request. trmreq recreq remote rsplock description 00- - configuration mode cpu could configure new transfer mode for this mailbox. 0 1 0 - mailbox is configured as a receivebox for dataframes . 1010 1. step: mailbox transmits remoteframe (remact-bit is 1) 2. step: mailbox becomes a receivebox for dataframes - remactive-bit is set to 0. exception: when the matching dataframe is already detected on the busline before the remoteframe can be sent, the mailbox becomes immediately a receivebox for dataframes . 1000 mailbox is configured as a transmissionbox for dataframes . 0111/0 1. step: mailbox receives a remoteframe (remact-bit is 1). 2. step: mailbox becomes a transmissionbox for dataframes - remactive-bit will be set to 0. remark: as long as rsplock=1, no transmission can be started. this means that remoteframes are not answered automatically.
175 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can slot interrupt control register figure 18-11. structure of can slot interrupt control register (b15) (b8) b7 b6 b0 b7 b0 function values that can be set for each bit rw interrupt enable bits each bit corresponds with the appropriate message mailbox. the transfer interrupts ('successful reception' / 'successful transmission') for each message mailbox can be enabled and disabled. 0: 1: after a successful transmission or reception operation no interrupt request bit is set. oo can slot interrupt control register symbol address when reset c0sicr 0217 16 , 0216 16 0000 16 c1sicr 0237 16 , 0236 16 0000 16 note: these bits can not be set in reset/initialization mode. after a successful transmission or reception operation the interrupt request bit in the corre- sponding mcu interrupt control register is set.
176 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 18-13. structure of acceptance filter figure 18-13 and 18-14 show the memory location of these three filter masks and their bitmap. the structure of the bit organization is adapted to the identifier format in every message slot (refer to figure 18-2/18-3). after mcu reset condition, the content of the mask registers is undefined. the mask registers provide the possibility to filter a range of identifier. they can mask the identifier by setting each bit to '0'. the acceptance filter can be performed either for 29 or for 11 bit identifier length, determined by the extended id register setting for the corresponding mailbox. the mailbox itself contains the identifier for the filtering process. together with the relevant mask, the filtering is performed as shown in the figure below. mask register and acceptance filter for the acceptance filter, three 29-bit mask registers are provided. one global mask is assigned to the mailboxes 0 to 13 and two local masks belong to mailbox 14 and 15 respectively. if the mailbox is configured as a receive slot, the standard id and the extended id of the message object act as the local id mask. figure 18-12. mask assignment mailbox #0 mailbox #1 mailbox #2 mailbox #3 mailbox #4 mailbox #5 mailbox #6 mailbox #7 mailbox #8 mailbox #9 mailbox #10 mailbox #11 mailbox #12 mailbox #14 mailbox #15 global mask local mask a local mask b mailbox #13 received identifier identifier stored in the mailbox mask re g ister acceptance si g nal mask bit values 0:the corresponding incoming id bit is do not care . 1: the corresponding id bit is checked against the incoming id bit. acceptance signal values 0:the can module ignores the current incoming message. 1:the can module stores the incoming message; the relevant bits (determined by the mask) of received id and mailbox id are equal.
177 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 18-14. acceptance filter masks (byte address order) figure 18-15. acceptance filter masks (word address order) bit 7 bit 0 sid 10 sid 9 sid 8 sid 7 sid 6 0160 16 0360 16 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 0161 16 0361 16 eid 17 eid 16 eid 15 eid 14 0162 16 0362 16 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 0163 16 0363 16 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 0164 16 0364 16 global mask sid 10 sid 9 sid 8 sid 7 sid 6 0166 16 0366 16 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 0167 16 0367 16 eid 17 eid 16 eid 15 eid 14 0168 16 0368 16 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 0169 16 0369 16 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 016a 16 036a 16 local mask a sid 10 sid 9 sid 8 sid 7 sid 6 016c 16 036c 16 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 016d 16 036d 16 eid 17 eid 16 eid 15 eid 14 016e 16 036e 16 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 016f 16 036f 16 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 0170 16 0370 16 local mask b addresses can0 can1 bit 15 bit 0 sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 bit 8 bit 7 eid 17 eid 16 eid 15 eid 14 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 global mask 0160 16 /0360 16 local mask a local mask b 0162 16 /0362 16 0164 16 /0364 16 0166 16 /0366 16 0168 16 /0368 16 016a 16 /036a 16 016c 16 /036c 16 016e 16 /036e 16 0170 16 /0370 16 sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 eid 17 eid 16 eid 15 eid 14 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 eid 17 eid 16 eid 15 eid 14 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 addresses can0 / can1 n n+1
178 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 18-16. structure of can status register can status register (b15) (b8) b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function r w reset reset acknowledge bit 0: 1: operation mode reset o- loopback loop back acknowledge 0: 1: normal operation mode loop back mode o- msgorder message order 0: 1: the address order for the message objects is adapted to word access. the address order is byte linear (8 bit access only). o- basiccan basiccan feature 0: 1: normal operation mode basiccan feature (slot #14/15) o- buserror bus error 0: 1: no error occurred. can bus-error occurred. o- errpass can module is in error passive state 0: 1: can module is not error passive and bus off. can module is error passive or bus off. o- busoff can module is in error busoff state 0: 1: can module is not bus off. can module is bus off. o- nothing is assigned. it is not allowed to write '1' to this bit location. when read, their contents are indeterminate. -- can status register b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function r w mbox bit3..bit0 mailbox number number of the mailbox which transmitted/ received a message successfully 0 0 0 0 : mailbox 0 0 0 0 1 : mailbox 1 ... 1 1 1 1 : mailbox 15 o- trmsucc transmission successful 0: 1: no [successful] transmission can module transmitted a message successfully. o- recsucc receive successful 0: 1: no [successful] reception can module received a message successfully. o- trmstate transmitter 0: 1: can module is idle or receiver. can module is transmitter. o- recstate receiver 0: 1: can module is idle or transmitter. can module is receiver. o- symbol address when reset c0str 0212 16 00 16 c1str 0232 16 00 16 symbol address when reset c0str 0213 16 01 16 c1str 0233 16 01 16 b3 b2 b1 b0
179 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can slot status register figure 18-17. structure of can slot status register (b15) (b8) b7 b6 b0 b7 b0 function values that can be set for each bit rw slot status bits each bit corresponds with the appropriate message mailbox. 0: - receive mailbox slot contains no unread mes- sage. - transmit mailbox message is not sent yet slot contains unread message. message was sent success- fully. o- can slot status register symbol address when reset c0sstr 0215 16 , 0214 16 0000 16 c1sstr 0235 16 , 0234 16 0000 16 1: - receive mailbox - transmit mailbox
180 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can time stamp register ? the cpu can read out the content of the 16 bit timer responsible for the time stamp function of the can module. figure 18-18. can time stamp register the basic clock for this timer is the bit clock derived from the can bus bit timing. the content of the timer is increased by one when received or transmitted frame bits. when the can bus is idle, the timer is increased by the nominal bit rate, which is defined in the can configuration register. by help of an additional prescaler structure, the basic clock can be divided by the scale factor 1/1, 1/2, 1/4 or 1/8 (refer to the description of the can control register). for the 'time stamp' function the content of the counter is captured after the current message on the bus is declared to be valid. this decision is made in conformity to the definition of a 'successful receive process' based on the can specification. this 'time stamp' is stored in the message buffer which corresponds to the successful receive process. (b15) (b8) b7 b0 b7 b0 function values that can be read rw time stamp (16 bit) counts the can bus bit cycles 0000 16 to ffff 16 o- can time stamp register symbol address when reset c0tsr 021f , 021e 0000 16 c1tsr 023f , 023e 0000 16 16 16 16 16
181 can module under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer can rec- and can tec-register ? the rec- and tec-register can be used for the analysis of the can bus transmit and receive error occurrences. figure 18-19. structure of can rec register (receive error counter) figure 18-20. structure of can tec register (transmit error counter) b7 b0 function values that can be read rw receive error counter increment and decrement according to the can specification 00 16 to ff 16 o- can rec register symbol address when reset c0recr 021c 00 16 c1recr 023c 00 16 16 16 b7 b0 function values that can be read rw transmit error counter increment and decrement according to the can specification 00 16 to ff 16 o- can tec register symbol address when reset c0tecr 021d 16 00 00 16 c1tecr 023d 16 16
182 can module u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer acceptance filter support register ? the acceptance filter support register can be used for the implementation of efficient acceptance filter rooutines. figure 18-21. acceptance filter support register when writing the first two bytes of a received message object to the acceptance filter support register, the bits are modified as illustrated in figure 18-20. therefore, when read, the obtained value can be used for an efficient software acceptance filtering of the most recently written standard identifier. the message order that the acceptance filter support register expects is the message order of the according can module. figure 18-22. write/read of acceptance filter support register (word order) bit 15 bit 0 bit 8 bit 7 when read 242 16 /244 16 sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 bit 15 bit 0 sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 bit 8 bit 7 when write 242 16 /244 16 addresses can0 / can1 3/8 decoder b7 b0 b7 b0 (b15) (b8) function values that can be set rw acceptance filter support register symbol address when reset c0afs 0243 , 0242 16 indeterminate o o indeterminate c1afs 0245 , 0244 16 16 16 at write each bit corresponds to an standard identifier bit of a received message object. at read a modified form of the standard identifier is obtained. standard identifier in word- or byte order can be set.
183 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer programmable i/o ports there are 87 programmable i/o ports: p0 to p10 (excluding p8 5 ). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p7 1 and p9 1 are nch open drain ports and have no built-in pull-up resistance. p8 5 is an input-only port and has no built- in pull-up resistance. figures 19-1 and 19-3 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a converter), they function as outputs regardless of the contents of the direction registers. see the descrip- tions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 19-4 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. note: there is no direction register bit for p8 5 . (2) port registers figure 19-5 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 19-6 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. however, in memory expansion mode and microprocessor mode, p0 to p5 operate as the bus and the pull-up control register setting is invalid. (4) port control register figure 19-7 shows the port control register. the bit 0 of port control register is used to read port p1 as follows: 0 : when port p1 is input port, port input level is read. when port p1 is output port , the contents of port p1 register is read. 1 : the contents of port p1 register is read though port p1 is input/output port. this register is valid in the following: ? external bus width is 8 bits in microprocessor mode or memory expansion mode. ? port p1 can be used as a port in multiplexed bus for the entire space.
184 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-1. programmable i/o ports (1) data bus direction register pull-up selection port latch p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 4 , p5 6 p0 0 to p0 7 , p2 0 to p2 7 , data bus direction register pull-up selection analog input port latch p1 0 to p1 4 data bus direction register pull-up selection port latch port p1 control register p1 5 to p1 7 direction register port latch port p1 control register pull-up selection data bus input to respective peripheral functions p5 7 , p6 0 , p6 1 , p6 4 , p6 5 , p7 2 to p7 6 , p8 0 , p8 1 , p9 0 , p9 2 direction register port latch pull-up selection data bus input to respective peripheral functions "1" output
185 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-2. programmable i/o ports (2) p8 2 to p8 4 data bus direction register pull-up selection port latch input to respective peripheral functions p5 5 , p6 2 , p6 6 , p7 7 , p9 7 data bus direction register pull-up selection port latch input to respective peripheral functions p6 3 , p6 7 "1" output nch data bus note 1: p6 3 and p6 7 can be n-channel open drain only when used as t x d0/t x d1 pin. direction register pull-up selection port latch p8 5 data bus nmi interrupt input p7 0 "1" output nch data bus note 2: p70 can be n-channel open drain only when used as t x d2 pin. if used as input port it is only usable as cmos port. direction register pull-up selection port latch input to respective peripheral functions p7 1 , p9 1 "1" output direction register port latch input to respective peripheral functions note 3: symbolizes a parasitic diode. (note 3)
186 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-3. programmable i/o ports (3) p9 3 , p9 4 p9 6 p9 5 data bus direction register pull-up selection port latch analog input input to respective peripheral functions p10 0 to p10 3 (inside dotted-line not included) p10 4 to p10 7 (inside dotted-line included) d-a output enabled direction register pull-up selection port latch data bus input to respective peripheral functions d-a output enabled analog output "1" output direction register pull-up selection port latch data bus analog input "1" output direction register pull-up selection port latch data bus analog input input to respective peripheral functions
187 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer p8 7 p8 6 fc rf rd data bus direction register pull-up selection port latch "1" output direction register pull-up selection port latch data bus byte byte signal input cnv ss cnv ss signal input reset reset signal input figure 19-4. programmable i/o ports (4) figure 19-5. i/o pins
188 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-6. direction register port pi direction register (note) symbol address when reset pdi (i = 0 to 10, except 8) 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 , 03ea 16 00 16 03eb 16 , 03ee 16 , 03ef 16 , 03f3 16 , 03f6 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 10 except 8) port p8 direction register symbol address when reset pd8 03f2 16 00x00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 direction register pd8_1 port p8 1 direction register pd8_2 port p8 2 direction register pd8_3 port p8 3 direction register pd8_4 port p8 4 direction register nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. pd8_6 port p8 6 direction register pd8_7 port p8 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note: set bit 2 of protect register (address 000a 16 ) to 1 before rewriting to the port p7 and p9 direction register.
189 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-7. port register port pi register symbol address when reset pi (i = 0 to 10, except 8) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : l level data 1 : h level data (i = 0 to 10 except 8) port p8 register symbol address when reset p8 03f0 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 p8_0 port p8 0 register p8_1 port p8 1 register p8_2 port p8 2 register p8_3 port p8 3 register p8_4 port p8 4 register p8_5 port p8 5 register p8_6 port p8 6 register p8_7 port p8 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for p8 5 ) 0 : l level data 1 : h level data
190 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-8. pull-up control register pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up pu12 p5 0 to p5 3 pull-up pu13 p5 4 to p5 7 pull-up pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up (note 1) pu17 p7 4 to p7 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high note 1: since p7 0 is n-channel open drain port, pull-up is not available for it. note 2: when the v note 3: since p9 1 is n-channel open drain port, pull-up is not available for it. cc level is being impressed to the cnv ss terminal, this register becomes to 02 16 when reset (pu11 becomes to 1 ). pull-up control register 2 symbol address when reset pur2 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up (except p8 5 ) pu22 p9 0 to p9 3 pull-up (note 3) pu23 p9 4 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. theses bits can neither be set nor reset. when read, their contents are 0 . the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high
191 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 19-9. port control register port control register symbpl address when reset pcr 03ff 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control register 0 : when input port, read port input level. when output port, read the contents of port p1 register. 1 : read the contents of port p1 register though input/output port. nothing is assigned. theses bits can neither be set nor reset. when read, their contents are 0 .
192 programmable i/o port under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer table 19-1. example connection of unused pins in single-chip mode p8 2 to p8 4 data bus direction register pull-up selection port latch input to respective peripheral functions p5 5 , p6 2 , p6 6 , p7 7 , p9 7 data bus direction register pull-up selection port latch input to respective peripheral functions p6 3 , p6 7 "1" output nch data bus note 1: p6 3 and p6 7 can be n-channel open drain only when used as t x d0/t x d1 pin. direction register pull-up selection port latch p8 5 data bus nmi interrupt input p7 0 "1" output nch data bus note 2: p70 can be n-channel open drain only when used as t x d2 pin. if used as input port it is only usable as cmos port. direction register pull-up selection port latch input to respective peripheral functions p7 1 , p9 1 "1" output direction register port latch input to respective peripheral functions note 3: symbolizes a parasitic diode. (note 3) figure 19-10. example connection of unused pins pin name connection ports p0 to p10 (excluding p8 5 ) x out (note) av ss , v ref , byte av cc after setting for input mode, connect every pin to v ss or v cc via a resistor; or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note: with external clock input to x in pin. nmi connect via resistor to v cc (pull-up) table 19-2. example connection of unused pins in memory expansion mode and microprocessor mode port p0 to p10 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc byte av ss v ref microcomputer v cc v ss in single-chip mode port p6 to p10 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc av ss v ref open microcomputer v cc v ss in memory expansion mode or in microprocessor mode hold rdy ale bclk bhe hlda open open open
193 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer usage precaution timer a (timer mode) usage precaution timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 by underflow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 . reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs l level. ? the interrupt request generated and the timer ai interrupt request bit goes to 1. (2) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. timer a (one-shot timer mode) (1) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the tai out pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1. timer a (pulse width modulation mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. timer b (timer mode, event counter mode)
194 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer usage precaution (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. stop mode and wait mode a-d converter (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. timer b (pulse period/pulse width measurement mode) interrupts external rom version the external rom version is operated only in microprocessor mode, so be sure to perform the following: ? connect cnvss pin to vcc. ? fix the processor mode bit to 11 2 (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning the first instruction immediately after reset, generating any interrupts including the nmi interrupt is prohibited. (3) the nmi interrupt ? as for the nmi interrupt pin, an interrupt cannot be prohibited. connect it to the v cc pin if unused. be sure to work on it. ? do not get either into stop mode or into wait mode with the nmi pin set to l. (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a-d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as internal cpu clock.
195 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics table 21-1. absolute maximum ratings note 1: specify a product of -40 to 85 c to use it. v ref , x in x out v o -0.3 to vcc+0.3 -0.3 to vcc+0.3 p d ta=25 -0.3 to 6.5 -0.3 to 6.5 v v v v i avcc vcc t stg t opr mw v -65 to 150 700 -40 to 85 (note 1) p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 7 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 ,p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4, p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , reset, p9 0 to p9 7 , p10 0 to p10 7 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p7 1 , p9 1 p7 0 , p7 1 , -0.3 to 6.5 -0.3 to 6.5 v v cnv ss , byte, v cc =av cc v cc =av cc c c c symbol parameter condition rated value unit supply voltage analog supply voltage input voltage output voltage power dissipation operating ambient temperature storage temperature
196 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics table 21-2. recommended operating conditions (referenced to vcc = 4.5 v to 5.5v at ta = -40 to 85 c (note 3) unless otherwise specified) note 1: the mean output current is the mean value within 100ms. note 2: the total i ol (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, and p10 must be 80ma max. the total i oh (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, and p10 must be 80ma max. the total i ol (peak) for ports p3, p4, p5, p6, p7, and p8 0 to p8 4 must be 80ma max. the total i with wait, program/erase of flash memory by vcc = 4.2v to 5.5v and f(bclk) 12.5 mhz. oh (peak) for ports p3, p4, p5, p6, p7 2 to p7 7 , and p8 0 to p8 4 must be 80ma max. note 3: specify a product of -40 to 85 c to use it. note 4: relationship between main clock oscillation frequency and supply voltage. note 5: execute case without wait, program/erase of flash memory by vcc = 4.2v to 5.5v and f(bclk) 6.25 mhz. execute case main clock input oscillation frequency (mask rom, no wait) 16.0 5.0 0.0 2.7 4.2 5.5 operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) 7.33 x v cc - 14.791mh z main clock input oscillation frequency (eprom, one-time prom, no wait) 16.0 3.5 0.0 2.7 4.5 5.5 operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) 6.95 x v cc - 15.275mh z main clock input oscillation frequency (eprom, one-time prom, with wait) 16.0 7.0 0.0 2.7 4.5 5.5 operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) 5 x v cc - 6.5mh z main clock input oscillation frequency (mask rom, with wait) 16.0 10.0 0.0 2.7 4.2 5.5 operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) 4 x v cc - 0.8mh z 4.2 5.5 vcc 5.0 vcc avcc v v 0 0 v ih i oh (avg) ma ma vss avss 0.8vcc v v v v v v v 0.8vcc 0.5vcc vcc vcc vcc 0.2vcc 0.2vcc 0 0 0 (data input function during memory expansion and microprocessor modes) 0.16vcc i oh (peak) p7 2 to p7 7 , p8 0 to p8 7 , p9 0 2 , p9 to p9 7 , p10 0 to p10 7 , -5.0 -10.0 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 (during single-chip mode) p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 p0 0 to p0 7 , p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 ,p7 0 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 2 p9 to p9 7, 0, p10 0 to p10 7 p3 1 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7, 0, 0, p6 0 to p6 7 , p7 10.0 5.0 ma f (x in ) mhz i ol (peak) ma i ol (avg) 16 f (xc in ) khz 50 32.768 v x in , reset, cnv ss , byte p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p3 1 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7, p6 0 to p6 7 , x in , reset, cnv ss , byte (data input function during memory expansion and microprocessor modes) p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 (during single-chip mode) p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 vcc=4.2v to 5.5v p9 1 , 0.8vcc 6.5 v p7 1 v il 0 mask rom, flash mask rom, flash vcc=4.2v to 5.5v 0 mhz 20 symbol parameter unit standard min typ. max. supply voltage analog supply voltage supply voltage analog supply voltage high input voltage low input voltage high peak output current high average output current low peak output current low average output current main clock input oscillation frequency subclock oscillation frequency with wait no wait mhz 16 vcc=4.2v to 5.5v 0 vcc=4.2v to 5.5v 0 mhz 20
197 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics table 21-3. electrical characteristics (referenced to vcc = avcc = vref = 5v, vss = avss = 0 v at ta = 25 c, f(xin) = 16mhz unless otherwise specified) v oh v oh v oh v ol v ol v ol v v 4.7 v x out 3.0 3.0 v 2.0 0.45 v v x out 2.0 2.0 3.0 i oh =-5ma i oh =-1ma i oh =-200a i oh =-0.5ma i ol =5ma i ol =1ma i ol =200a i ol =0.5ma p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , highpower lowpower p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , , p7 0 , p7 2 to p7 p6 0 to p6 77 , 0 , p9 , p8 0 to p8 4 p8 6 , p8 7 p9 2 , to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , , p7 0 , p7 2 to p7 p6 0 to p6 77 , 0 , p9 , p8 0 to p8 4 p8 6 , p8 7 p9 2 , to p9 7 , p10 0 to p10 7 highpower lowpower p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 highpower lowpower x cout 3.0 1.6 v p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 v t+ - v t- v t+ - v t- clk 1 ,ta2 out to ta4 out ,nmi, 0.2 0.8 v tb0 in to tb2 in , int 0 to int 5, ad trg , cts 0 , cts 1 , clk 0 , hold, rdy, ta0 in to ta4 in , v x cout 0 0 highpower lowpower symbol parameter unit standard min typ. max. high output voltage high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage low output voltage hysteresis with no load applied with no load applied with no load applied with no load applied i ih i il v ram icc 0.2 1.8 v 5.0 a 2.0 v ma ma ma reset p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7, x in , reset, cnvss, byte v i =5v v i =0v -5.0 50.0 80.0 f(x in )=16mhz p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7, x in , reset, cnvss, byte 4.0 9.0 a f(x mask rom version flash memory 5v version cin )=32khz 200.0 a r fxin r fcxin x in x cin 6.0 8.0 1.0 r pullup 50.0 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 v i =0v 30.0 167.0 hysteresis high input current low input current pull-up resistance feedback resistance feedback resistance ram retention voltage power supply current a when clock is stopped in single-chip mode, the output pins are open and other pins are v ss square wave, no division square wave f(x cin )=32khz square wave square wave timer a operates with fc32 f(x ring oscillation cin )=32khz 1.0 a 20.0 ta=85 ?c when clock is stopped ta=25 ? c when clock is stopped measuring condition ki 0 to ki 3 k m m when a wait instruction is executed m w m w k w
198 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v table 21-4. a-d conversion characteristics (referenced to vcc = avcc = v ref = 5v, vss = avss = 0 v at ta = 25 c, f(x in ) = 16mhz unless otherwise specified) table 21-5. d-a conversion characteristics (referenced to vcc = 5 v, v ref = 5v, vss = avss = 0 v at ta = 25 c, f(x in ) = 16mhz unless otherwise specified) min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20 10 4 s ( note ) standard k w s standard min. typ. max. resolution absolute accuracy bits lsb v ref = v cc 3 10 symbol parameter measuring condition unit v ref = v cc = 5v r ladder t conv ladder resistance conversion time (10bit) (note 1) reference voltage analog input voltage v v ia v ref v 0 2 10 v cc v ref 40 33 conversion time (8bit) (note 1) 28 t conv t samp sampling time 0.3 v ref = v cc sample & hold function disabled sample & hold function enabled10bit) an 0 to an 7 input an 00 to an 07 input an 20 to an 27 input anex0, anex1 input, external op-amp connection mode v ref =v cc = 5v lsb lsb 7 sample & hold function enabled8bit) v ref = v cc = 5v 2 lsb cycles cycles 3 k w note 1: the conversion times are given in cycles of fad. fad is derived from f(xin) divided by 1, 2, 4, or 8 and may not exceed 10 mhz. minimal conversion times are achieved with an f(xin) of 10 mhz or 20 mhz. note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to "00 16 ". the a-d converter's ladder resistance is not included. also, when the v ref is unconnected at the a-d control register, i vref is sent.
199 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v timing requirements (referenced to vcc = 5 v, vss = 0 v at ta = 25 c unless otherwise specified) table 21-6. external clock input max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 15 62.5 25 25 15 table 21-7. memory expansion- and microprocessor modes f(bclk) x 2 (note) (note) (note) 40 30 0 0 40 0 note: calculated according to the bclk frequency as follows: 40 min. data input setup time ns t su(db-rd) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (with wait) data input access time (when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time t ac1(rd C db) = f(bclk) x 2 C 45 10 9 [ns] t ac2(rd C db) = f(bclk) x 2 C 45 3 x 10 9 [ns] t ac3(rd C db) = C 45 3 x 10 9 [ns]
200 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v timing requirements (referenced to vcc = 5 v, vss = 0 v at ta = 25 c unless otherwise specified) table 21-8. timer a input (counter input in event counter mode) table 21-10. timer a input (gating input in timer mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 table 21-9. timer a input (gating input in timer mode) standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 table 21-11. timer a input (external trigger input in one-shot timer mode) standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 table 21-12. timer a input (up/down input in event counter mode) standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400
201 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v timing requirements (referenced to vcc = 5 v, vss = 0 v at ta = 25 c unless otherwise specified) table 21-13. timer b input (counter input in event counter mode) standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) 100 40 40 80 80 200 table 21-14. timer b input (pulse period measurement mode) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width 400 200 200 table 21-15. timer b input (pulse width measurement mode) standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width 400 200 200 table 21-16. a-d trigger input standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width 1000 125 table 21-17. serial i/o ns ns ns ns ns ns ns standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 200 100 100 0 30 90 80 table 21-18. external interrupt inti inputs standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width 250 250
202 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v switching characteristics (referenced to vcc = 5 v, vss = 0 v at ta = 25 c, cm15 ="1" unless otherwise specified) table 21-19. memory expansion mode and microprocessor mode (no wait) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (bclk standard) 4 ns t h(bclk-cs) chip select output hold time (bclk standard) 4 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time C 4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (bclk standard) 40 ns t h(bclk-db) data output hold time (bclk standard) 4 ns t h(wr-db) data output hold time (wr standard)(note2) 0 ns t d(db-wr) data output delay time (wr standard) ns (note1) note 1: calculated according to the bclk frequency as follows: td(db C wr) = f(bclk) x 2 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) 0 ns note 2: this is standard value shows the timing when the output is off, and doesn't show hold time of data bus. hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = Ccr x ln (1 C v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2v cc , c = 30pf, r = 1k w , hold time of output l level is t = C 30pf x 1k w x ln (1 C 0.2v cc / v cc ) = 6.7ns. dbi r c figure 1.26.1
203 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v switching characteristics (referenced to vcc = 5 v, vss = 0 v at ta = -25 c, cm15 ="1" unless otherwise specified) table 21-20. memory expansion mode and microprocessor mode (with wait, accessing external memory) figure 1.26.1 symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (bclk standard) 4 ns t h(bclk-cs) chip select output hold time (bclk standard) 4 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time C 4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (bclk standard) 40 ns t h(bclk-db) data output hold time (bclk standard) 4 ns t h(wr-db) data output hold time (wr standard)(note2) 0 ns t d(db-wr) data output delay time (wr standard) ns (note1) note 1: calculated according to the bclk frequency as follows: td(db C wr) = f(bclk) 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) 0 ns note 2: this is standard value shows the timing when the output is off, and doesn't show hold time of data bus. hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = Ccr x ln (1 C v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2v cc , c = 30pf, r = 1k w , hold time of output l level is t = C 30pf x 1k w x ln (1 C 0.2v cc / v cc ) = 6.7ns. dbi r c
204 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics vcc = 5 v switching characteristics (referenced to vcc = 5 v, vss = 0 v at ta = -25 c, cm15 ="1" unless otherwise specified) table 21-21. memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (bclk standard) 4 ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (bclk standard) 4 ns ns t h(rd-ad) address output hold time (rd standard) (note) t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns ns t h(wr-ad) address output hold time (wr standard) (note) t d(bclk-wr) wr signal output delay time 25 ns t d(bclk-db) data output delay time (bclk standard) 40 ns t h(bclk-db) data output hold time (bclk standard) 4 ns t d(db-wr) data output delay time (wr standard) (note) ns t d(bclk-ale) ale signal output delay time (bclk standard) 25 ns t h(bclk-ale) ale signal output hold time (bclk standard) C 4 ns t h(ale-ad) ale signal output hold time (adderss standard) 50 ns t h(bclk-wr) wr signal output hold time 0 ns ns t h(rd-cs) chip select output hold time (rd standard) (note) t h(wr-cs) chip select output hold time (wr standard) (note) ns t d(ad-rd) post-address rd signal output delay time ns 0 t d(ad-wr) post-address wr signal output delay time ns 0 t dz(rd-ad) address output floating start time ns 8 t h(wr-db) data output hold time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: th(rd C ad) = f(bclk) x 2 10 9 [ns] th(wr C ad) = f(bclk) x 2 10 9 [ns] th(rd C cs) = f(bclk) x 2 10 9 [ns] th(wr C cs) = f(bclk) x 2 10 9 [ns] td(db C wr) = f(bclk) x 2 10 9 C 40 [ns] x 3 td(ad C ale) = f(bclk) x 2 10 9 C 25 [ns] th(wr C db) = f(bclk) x 2 10 9 [ns] t d(ad-ale) ale signal output delay time (address standard) ns (note) figure 1.26.1
205 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf figure 21-1. port p0 to p10 measurement circuit
206 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics figure 21-2. vcc = 5v timing diagram v cc = 5v t su(dCc) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(cCq) t h(cCd) t h(cCq) t h(t in Cup) t su(upCt in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input
207 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics figure 21-3. vcc = 5v timing diagram v cc = 5v measuring conditions : ? v cc =5v ? input timing voltage : determined with v il =1.0v, v ih =4.0v ? output timing voltage : determined with v ol =2.5v, v oh =2.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with or without wait) note: the above pins are set to high-impedance regardless of the input level of the byte pin and bit (pm06) of processor mode register 0 selects the function of ports p4 0 to p4 3 . t h(bclkChold) t su(holdCbclk) (valid only with wait) t d(bclkChlda) t d(bclkChlda) hiCz rdy input tsu(rdyCbclk) th(bclkCrdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus)
208 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics figure 21-4. vcc = 5v timing diagram bclk csi ale C4ns.min rd 25ns.max 0ns.min 4ns.min 4ns.min hiCz db 0ns.min adi bhe read timing bclk csi ale 25ns.max 0ns.min 4ns.min 4ns.min hi-z db 40ns.max 4ns.min (tcyc/2C40)ns.min adi bhe write timing t d(bclkCad) t d(bclkCale) t h(bclkCale) t su(dbCrd) t h(bclk-ad) t d(bclkCwr) t h(bclkCdb) t d(bclkCrd) t d(bclkCale) 40ns.min t ac1(rdCdb) memory expansion mode and microprocessor mode (with no wait) wr, wrl, wrh t d(bclkCcs) 25ns.max tcyc t h(bclkCcs) t h(rdCcs) 0ns.min 25ns.max t h(bclkCad) t h(rdCad) 0ns.min t h(bclkCrd) 25ns.max t h(rdCdb) t d(bclkCcs) 25ns.max t h(bclkCcs) tcyc t h(wrCcs) 0ns.min t d(bclkCad) 25ns.max 25ns.max t h(bclkCale) C4ns.min t h(wrCad) 0ns.min t h(bclkCwr) t d(bclkCdb) t d(dbCwr) t h(wrCdb) 0ns.min v cc = 5v
209 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics figure 21-5. vcc = 5v timing diagram bclk csi ale rd 4ns.min hiCz db 40ns.min 0ns.min adi bhe read timing bclk csi ale 4ns.min t h(wrCad) adi bhe (tcycC40)ns.min 0ns.min dbi write timing t d(bclkCrd) 0ns.min 0ns.min t h(rdCad) memory expansion mode and microprocessor mode (when accessing external memory area with wait) measuring conditions : ? v cc =5v ? input timing voltage : determined with: v il =0.8v, v ih =2.5v ? output timing voltage : determined with: v ol =0.8v, v oh =2.0v wr, wrl, wrh t d(bclkCcs) 25ns.max tcyc t h(bclkCcs) 4ns.min t h(rdCcs) 0ns.min t h(bclkCad) t d(bclkCad) 25ns.max t d(bclkCale) 25ns.max t h(bclkCale) C4ns.min t h(bclkCrd) 0ns.min 25ns.max t ac2(rdCdb) t h(rdCdb) t su(dbCrd) t d(bclkCcs) 25ns.max tcyc t h(bclkCcs) 4ns.min t h(wrCcs) 0ns.min t h(bclkCad) t d(bclkCad) 25ns.max t d(bclkCale) 25ns.max t h(bclkCale) C4ns.min t h(bclkCwr) 0ns.min t d(bclkCwr) 25ns.max t h(bclkCdb) 4ns.min t d(bclkCdb) 40ns.max t d(dbCwr) t h(wrCdb) v cc = 5v
210 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer electrical characteristics figure 21-6. vcc = 5v timing diagram memory expansion mode and microprocessor mode (when accessing external memory area with wait, and select multiplexed bus) bclk csi ale rd 4ns.min tcyc adi bhe adi /dbi t d(adCale) read timing 0ns.min bclk csi ale C4ns.min 4ns.min 4ns.min tcyc adi bhe adi /dbi write timing address measuring conditions : ? v cc =5v ? input timing voltage : determined with v il =0.8v, v ih =2.5v ? output timing voltage : determined with v ol =0.8v, v oh =2.0v (tcyc/2)ns.min address data input (tcyc/2)ns.min t d(bclkCale) (tcyc/2)ns.min t h(wrCcs) address (tcyc*3/2C40)ns.min t d(bclkCale) (tcyc/2)ns.min (tcyc/2-25)ns.min address 25ns.max t su(dbCrd) tac3(rdCdb) (tcyc/2)ns.min t h(aleCad) 50ns.min t d(adCrd) 0ns.min t dz(rdCad) 8ns.max t d(adCwr) 0ns.min data output wr, wrl, wrh t d(bclkCcs) 25ns.max t h(rdCcs) t h(bclkCcs) 4ns.min t h(bclkCad) t h(rdCdb) 0ns.min 40ns.min 25ns.max t d(bclkCad) C4ns.min t h(bclkCale) t d(bclkCrd) 25ns.max t h(rdCad) t h(bclkCrd) 0ns.min t d(bclkCcs) 25ns.max t h(bclkCcs) t h(bclkCdb) 4ns.min t h(wrCdb) t d(dbCwr) t h(bclkCad) t d(adCale) (tcyc/2C25)ns.min t d(bclkCad) 25ns.max 25ns.max t h(bclkCale) 25ns.max t d(bclkCwr) t h(bclkCwr) t h(wrCad) t d(bclkCdb) 40ns.max v cc = 5v
211 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer flash chip memory description outline performance table 22-1 shows the outline performance of the m16c/6n (with on-chip flash memory). table 22-1. outline performance of the m16c/6n (with on-chip flash memory) item power supply voltage program/erase voltage flash memory mode erase block division program method erase method program/erase control method protect method number of commands program/erase count rom code protect performance 5v version: 4.5 to 5.5 v (f(x in )=16mhz, without wait, 4.2 to 5.5v) 5v version: 4.5 to 5.5 v (f(x in )=12.5mhz, with one wait) three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 22-3. one division (8 kbytes) (note 1) in units of pages (in units of 256 bytes) collective erase/block erase program/erase control by software command protected for each block by lock bit 8 commands 100 times parallel i/o and standard serial modes are supported. note 1: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area parameter 5 v power supply current (5 v version) f(xin)=16 mhz, without wait, no division division by 4 in program/erase 35 ma 28 ma 25 ma measuring condition remark read program erase standard (typ.) table 22-2. power supply current (typ.) of the m16c/6n (flash memory version)
212 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer flash chip memory description figure 22-1. rom expansion the following shows mitsubishi plans to develop a line of m16c/6n products (with on-chip flash memory). (1) rom size (2) package 100p6s-a ... plastic molded qfp rom size (bytes) M306N0FGTFP flash memory version external rom 256k 128k 96k 64k 32k the following lists the m16c/6n products to be supported in the future. parameter 5 v power supply current (5 v version) f(xin)=16 mhz, without wait, no division division by 4 in program/erase 35 ma 28 ma 25 ma measuring condition remark read program erase standard (typ.) table 22-3. product list figure 22-2. type names, memory sizes and package package type: fp : package 100p6s-a rom no. omitted for flash version rom capacity: 1 : 8k bytes 7 : 56k bytes 2 : 16k bytes 8 : 64k bytes 3 : 24k bytes 9 : 80k bytes 4 : 32k bytes a : 96k bytes 5 : 40k bytes c : 128k bytes 6 : 48k bytes g : 256k bytes memory type: m : mask rom version f : flash rom version type no. m 3 0 6 n 0 m c t C x x x f p m16c/6n group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning) temperature range t : automotive 85 o c version
213 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer flash chip memory description flash memory modes the m16c/6n (with on-chip flash memory) contains the dinor (divided bit line nor) type of flash memory that can be rewritten with a single voltage of 5 v or 3.3 v. for this flash memory, three flash memory modes are available in which to read, program and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and a cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). each mode is detailed in the pages to follow. the flash memory is divided into several blocks as shown in figure 22-3, so that memory can be erased one block at a time. each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. in addition to ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to rewriting in cpu rewrite and standard serial i/o mode. this boot rom area has a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user's application system. this boot rom area can be rewritten in parallel i/o mode only. 0c0000 16 0d0000 16 block 6 : 64k byte block 5 : 64k byte 0e0000 16 block 4 : 64k byte 0f0000 16 block 3 : 32k byte 0f8000 16 block 2 : 8k byte 0fa000 16 block 1 : 8k byte block 0 : 16k byte 0fc000 16 user rom area 8k byte 0fe000 16 0fffff 16 0fffff 16 boot rom area note 1: the boot rom area can be rewritten in only parallel input/output mode. (access to any other areas is inhibited.) note 2: to specify a block, use the maximum address in the block that is an even address. type no. flash memory start address m306n0fg 0c0000 16 figure 22-3. block diagram of on-chip flash memory
214 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program or erase) under control of the central processing unit (cpu). in cpu rewrite mode, it is possible to write only in the user rom area in figure 22-3; in the boot rom area not possible. make sure the program and block erase commands are issued only for the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom- or boot rom area. in cpu rewrite mode, since the flash memory cannot be accessed for read by the cpu, use the rewrite control program except in the internal flash memory. boot mode the control program for cpu rewrite mode must be rewritten into the user rom- or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 23-3 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnvss pin low. in this case, the cpu starts operating, using the control program in the user rom area. when the microcomputer is reset by pulling the p5 5 (epm) pin low, the cnvss pin high, and the p5 0 (ce) pin high, the cpu start operating, using the control program in the boot rom area. this mode is called the "boot" mode. the control program in the boot rom area can also be used to rewrite the user rom area. block address block addresses refer to the maximum even address of each block. these addresses are used in the block erase command, erase all unlock blocks command, lock bit program command and read lock status command.
215 cpu rewrite mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer outline performance (cpu rewrite mode) the cpu rewrite mode can be executed in single-chip mode, memory expansion mode and boot mode, allowing for only the user rom area to be rewritten. in cpu rewrite mode, the on-chip flash memory is operated on for erase, program or read operation by the cpu by writing a software command. note that in this case the control program may not be located in the internal flash memory. for example, in single-chip mode, transferred into internal ram. when the cpu rewrite mode select bit (bit 1 at address 03b7 16 ) is set to 1, transition to cpu rewrite mode occurs and software commands can be accepted. in cpu rewrite mode, all software commands and data are written into and read from even addresses (address a0 of byte address = 0) 16 bits at a time. therefore, make sure 8-bit software commands are always written into even addresses. data at odd addresses have no effect. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 23-1 shows the flash memory control register. bit 0 is the ry/by status flag, a read-only bit indicat- ing the operating status of the flash memory. this flag is 0 (busy) during auto write and auto erase opera- tion; otherwise, it is 1 (ready). (its function is equivalent to that of the ry/by pin in parallel i/o mode.) bit 1 is the cpu rewrite mode select bit. the cpu rewrite mode is entered by setting this bit to 1, so that software commands become acceptable. in cpu rewrite mode, the cpu becomes unable to access the on-chip flash memory directly. therefore, use the control program except in the internal flash memory to set this bit to 0. for this bit to be set to 1, the user needs to write a 0 and then a 1 in it in succession. the bit can be set to 0 by writing a 0 only. bit 2 is a lock bit disable bit. by setting this bit to 1, it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. (this function is equivalent to that of the wp pin in parallel i/o mode.) the lock bit disable bit only disables the function of the lock bit and cannot set the lock bit itself. however, if an erase operation is performed when this bit is 1, the lock bit data that is 0 (locked) is set to 1 (unlocked) after erasure. for this bit to be set to 1, it is necessary to write a 0 and then a 1 in it in succession when the cpu rewrite mode select bit is 1. this bit can be manipulated only when the cpu rewrite mode select bit is 1. bit 3 is a flash memory reset bit, provided to reset the control circuit of the on-chip flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. if this bit is set to 1 when the cpu rewrite mode select bit is 1, the flash memory is reset. to deassert this reset, the bit needs to be cleared to 0 after being set to 1. bit 5 is a user rom area select bit which is effective in boot mode only. if this bit is set to 1 in boot mode, the area to access is switched from the boot rom area to the user rom area. when the cpu rewrite mode needs to be used in boot mode, set this bit to 1. note that if the microcomputer is booted from the user rom area, it is always the user rom area that can be accessed and this bit has no effect. when in boot mode, the function of this bit is effective regardless of whether the cpu rewrite mode is on or off. use the control program outside the internal flash memory to rewrite this bit. figure 23-2 shows a flowchart to set and reset the cpu rewrite mode. always be sure to follow this flowchart.
216 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 23-1. flash memory control register flash memory control register symbol address when reset fmcr 03b7 16 xx000001 2 w r b7 b6 b5 b4 b3 b2 b1 b0 ry/by status flag f mc r0 bit symbol bit name function rw 0: busy (being written or erased) 1: ready cpu rewrite mode select bit (note 2) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) f mc r1 0: boot rom area is accessed 1: user rom area is accessed this bit must always be set to 0. lock bit disable bit (note 3) 0: block lock by lock bit data is enabled 1: block lock by lock bit data is disabled flash memory reset bit (note 3) 0: normal operation 1: reset nothing is assigned. when write, set "0". when read, values are indeterminate. user rom area select bit ( note 5) (effective in only boot mode) f mc r2 f mc r3 f mc r5 0 note 1: the value of the flash memory control register after a reset is "--000001". note 2: for this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession. use the control program except in the internal flash memory for write to this bit. note 3: for this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession when the cpu rewrite mode select bit = 1. note 4: effective only when the cpu rewrite mode select bit = 1. set this bit to 0 subsequently after setting it to 1 (reset). note 5: use the control program except in the internal flash memory for write to this bit. flash memory control register 2 symbol address when reset fmcr2 03b6 16 xx000001 2 w r b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function rw flash memory power supply-off bit (note) 0: flash memory power supply must always be set to "0". is connected. 1: flash memory power supply-off reserved bits f mc r22 00 00 0 0 0 note: for this bit to be set to "1", the user needs to write a 0"" and then a 1 to it in succession. when this procedure is not taken, it is not enacted in "1". this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. during parallel i/o mode, programming, erase, or read of flash memory is not controlled by this bit, only by external pins. must always be set to "0". reserved bits figure 23-2. flash memory control register 2
217 cpu rewrite mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 23-3 cpu rewrite mode set/reset flowchart end start execute read array command or reset flash memory by setting flash memory reset bit (by writing 1 and then 0 in succession) (note 2) single-chip mode, memory expansion mode, or boot mode set processor mode register (note 1) using software command execute erase, program, or other operation (set lock bit disable bit as required) jump to transferred control program in ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram note 1: set bit 7 (internal rom access wait bit) of the processor mode register 1 (address 0005 16 ) to 1 (1 wait state). note 2: before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. note 3: 1 can be set. however, when this bit is 1, user rom area is accessed. (boot mode only) write 0 to user rom area select bit (note 3) write 0 to cpu rewrite mode select bit (boot mode only) set user rom area select bit to 1 set cpu rewrite mode select bit to 1 (by writing 0 and then 1 in succession) set the bit 2 of fmcr2 (address 03b6 16 ) in order to reduce power consumption.although setting this bit to "1" helps to reduce the device's power consumption, programs cannot be read from the internal flash memory. make sure the operation to saet this bit to "1" and other operations to be performed while this bit remains "1" are executed in areas outside flash memory.
218 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer precautions on cpu rewrite mode described below are the precautions to observe when rewriting the flash memory in cpu rewrite mode. (1) operation speed when in cpu rewrite mode, set the main clock frequency as shown below, using the main clock divide ratio select bit (bit 6 at address 0006 16 and bits 6 and 7 at address 0007 16 ): 6.25 mhz or less when wait bit (bit 7 at address 0005 16 ) is 0 (without internal access wait state) 12.5 mhz or less when wait bit (bit 7 at address 0005 16 ) is 1 (with internal access wait state) (2) instructions inhibited the instructions listed below cannot be used when in cpu rewrite mode, because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction and brk instruction (when using fixed vector table only) (3) interrupts inhibited the nmi interrupt and address match interrupt cannot be used in cpu rewrite mode because they refer to the internal flash memory. if interrupts have their in the intb register, they can be used by transferring the vector into the ram area. the wdt interrupt can be used because the operation mode is forcibly changed to normal mode when the interrupt is generated. since the rewrite operation is halted when the wdt interrupt occurs, the erase/program operation needs to be performed over again. (4) internal reserved expansion bit (bit 3 at address 0005 16 ) the reserved area of the internal memory can be changed by using the internal reserved expansion bit (bit 3 at address 0005 16 ). however, if the cpu rewrite mode select bit (bit 1 at address 03b7 16 ) is set to 1, the internal reserved expansion bit (bit 3 at address 0005 16 ) is also set to 1 automatically. similarly, if the cpu rewrite mode select bit (bit 1 at address 03b7 16 ) is set to 0, the internal reserved bit (bit 3 at address 0005 16 ) also is set to 0 automatically. (5) reset reset input is always accepted. after a reset, the address 0c0000 16 through 0cffff 16 are made a reserved area and cannot be accessed. therefore, if your product has this area in the user rom area, do not write any address of this area into the reset vector. this area is made accessible by changing the internal reserved expansion bit (bit 3 at address 0005 16 ) in a program.
219 cpu rewrite mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer table 23-1. list of software commands (cpu rewrite mode) software commands table 23-1 lists the software commands available with the m16c/6nt (with on-chip flash memory). after setting the cpu rewrite mode select bit to 1, write a software command to specify an erase or program operation. note that when entering a software command, the upper byte (d 8 to d 15 ) is ignored. the content of each software command is explained below. command page program clear status register read array read status register x x x x (note 3) first bus cycle second bus cycle third bus cycle ff 16 70 16 50 16 41 16 write write write write x srd read write lock bit program x 77 16 write ba d0 16 write erase all unlock block x a7 16 write x d0 16 write wa1 wd1 write (note 2) wa0 (note 3) wd0 (note 3) block erase x 20 16 write d0 16 write ba (note 4) read lock bit status x 71 16 write ba d 6 read (note 5) mode address mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) data (d 0 to d 7 ) (note 6) note 1: when a software command is input, the high-order byte of data (d 8 to d 15 ) is ignored. note 2: srd = status register data note 3: wa = write address, wd = write data wa and wd must be set sequentially from 00 16 to fe 16 (byte address; however, an even address). the page size is 256 bytes. note 4: ba = block address (enter the maximum address of each block that is an even address.) note 5: d 6 corresponds to the block lock status. block not locked when d 6 = 1, block locked when d 6 = 0. note 6: x denotes a given address in the user rom area (that is an even address). read array command (ff 16 ) the read array mode is entered by writing the command code "ff 16 " in the first bus cycle. when an even address to read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 to d 15 ), 16 bits at a time. the read array mode is retained intact until another command is written. read status register command (70 16 ) when the command code "70 16 " is written in the first bus cycle, the content of the status register is read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr3 to 5 of the status register after they are set. these bits indicate that operation has ended in an error. to use this command, write the command code "50 16 " in the first bus cycle.
220 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer page program command (41 16 ) page program allows for high-speed programming in units of 256 bytes. page program operation starts when the command code "41 16 " is written in the first bus cycle. in the second cycle through the 129th bus cycle, the write data are sequentially written 16 bits at a time. at this time, the addresses a 0 to a 7 need to be increased by 2 from "00 16 " to "fe 16 ". when the system finishes loading the data it starts an auto write operation (data program and verify operation). whether or not the auto write operation is completed can be confirmed by reading the status register or the flash memory control register. at the same time the auto write operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon completion of the auto write operation. in this case, the read status register mode remains active until the read array command (ff 16 ) or read lock bit status command (71 16 ) is written or the flash memory is reset using its reset bit. the ry/by status flag of the flash memory control register is 0 during the auto write operation and 1 when the auto write operation is completed as is the status register bit 7. after the auto write operation is completed, the status register can be read out to know the result of the auto write operation. for details, refer to the section where the status register is detailed. figure 23-3 shows an example of a page program flowchart. each block of the flash memory can be write protected by using a lock bit. for details, refer to the section where the data protect function is detailed. additional writes in the already programmed pages are prohibited. figure 23-4. page program flowchart n = fe 16 start write 41 16 n = 0 write address n and data n sr7 = 1? read status register check full status page program completed n = n + 2 no yes no yes
221 cpu rewrite mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer block erase command (41 16 ) by writing the command code "20 16 " in the first bus cycle, the confirmation command code "d0 16 " and the block address of a flash memory block in the second bus cycle that follows, the system initiates an auto erase (erase and erase verify) operation. whether or not the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register. at the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) or read lock bit status command (71 16 ) is written or the flash memory is reset using its reset bit. the ry/by status flag of the flash memory control register is 0 during the auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. after the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. for details, refer to the section where the status register is detailed. figure 23-4 shows an example of a block erase flowchart. each block of the flash memory can be protected against erasure by using a lock bit. for details, refer to the section where the data protect function is detailed. figure 23-5. block erase flowchart write 20 16 write d0 16 block address read status register sr7 = 1? check full status check block erase completed no yes start
222 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer erase all unlock blocks command (a7 16 /d0 16 ) by writing the command code "a7 16 " in the first bus cycle and the confirmation command code "d0 16 " in the second bus cycle that follows, the system starts erasing blocks successively. whether or not the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register, in the same way as for block erase. also, the status register can be read out to know the result of the auto erase operation. when the lock bit disable bit of the flash memory control register is 1, all blocks are erased no matter how the lock bit is set. on the other hand, when the lock bit disable bit is 0, the function of the lock bit is effective and only nonlocked blocks (when lock bit data is 1) are erased. lock bit program command (77 16 /d0 16 ) by writing the command code "77 16 " in the first bus cycle, the confirmation command code "d0 16 " and the block address of a flash memory block in the second bus cycle that follows, the system sets the lock bit for the specified block to 0 (locked). figure 23-5 shows an example of a lock bit program flowchart. the status of the lock bit (lock bit data) can be read out by a read lock bit status command. whether or not the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register, in the same way as for page program. for details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. figure 23-6. lock bit program flowchart sr7 = 1? write 77 16 write d0 16 block address no yes sr4 = 0? no lock bit program completed lock bit program in error yes start
223 cpu rewrite mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer figure 23-7. read lock bit status flowchart read lock bit status command (71 16 ) by writing the command code "71 16 " in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data (d6). figure 23-6 shows an example of a read lock bit program flowchart. write 71 16 enter block address d6 = 0? no blocks locked blocks not locked yes start
224 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer data protect function (block lock) each block in figure 23-1 has a nonvolatile lock bit to specify that the block should be protected (locked) against erase/write. the lock bit program command is used to set the lock bit to 0 (locked). the lock bit of each block can be read out using the read lock bit status command. whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register's lock bit disable bit is set. (1) when the lock bit disable bit is 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). blocks whose lock bit data are 0 are locked, so they are disabled against erase/write. on the other hand, the blocks whose lock bit data are 1 are not locked, so they are enabled for erase/write. (2) when the lock bit disable bit is 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. in this case, the lock bit data that are 0 (locked) are set to 1 (nonlocked) after erasure, so the lock bit-actuated lock is removed. status register the status register indicates the operating status of the flash memory and whether an erase- or a program operation has terminated normally or in error. the content of this register can be read out only by writing the read status register command (70 16 ). table 23-2 details the status register. the status register is cleared by writing the clear status register command (50 16 ). after a reset, the status register is set to "80 16 ". each bit in this register is explained below. write state machine (wsm) status (sr7) after power-on, the write status machine (wsm) status is set to 1. the write state machine (wsm) status indicates the operating status of the device, as for output on the ry/by pin. this status bit is set to 0 during the auto write- or the auto erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status informs the operating status of the auto erase operation to the cpu. when an erase error occurs, it is set to 1. the erase status is reset to 0 when cleared.
225 cpu rewrite mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer program status (sr4) the program status informs the operating status of the auto write operation to the cpu. when a write error occurs, it is set to 1. the program status is reset to 0 when cleared. when an erase command is in error (which occurs if the command entered after the block erase command (20 16 ) is not the confirmation command (d0 16 )), both the program status and erase status (sr5) are set to 1. when the program status or erase status is 1, the following commands entered by command write are not accepted. also, in one of the following cases, both sr4 and sr5 are set to 1 (command sequence error): (1) when the valid command is not entered correctly. (2) when the data entered in the second bus cycle of the lock bit program (77 16 /d0 16 ), block erase (20 16 /d0 16 ), or erase all unlock blocks (a7 16 /d0 16 ) is not the d0 16 or ff 16 . however, if ff 16 is entered, read array is assumed and the command that has been set up in the first bus cycle is cancelled. block status after program if excessive data are written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), "1" is set for the program status after-program at the end of the page write operation. in other words, when writing ends successfully, "80 16 " is output; when writing fails, "90 16 " is output; and when excessive data are written, "88 16 " is output. table 23-2. definition of each bit in status register each bit of srd sr4 (bit4) sr5 (bit5) sr7 (bit7) sr6 (bit6) status name definition sr1 (bit1) sr2 (bit2) sr3 (bit3) sr0 (bit0) "1" "0" program status erase status write state machine (wsm) status reserved reserved reserved block status after program reserved ready busy terminated in error terminated in error terminated in error terminated normally terminated normally terminated normally - - - - - - - -
226 cpu rewrite mode u nder developm ent preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer full status check by performing full status check, it is possible to know the execution results of erase- and program operations. figure 23-7 shows a full status check flowchart and the action to take when each error occurs. figure 23-8. full status check flowchart and reemedial procedure for errors read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer 226 functions to inhibit rewriting on-chip flash memory functions to inhibit rewriting on-chip flash memory to prevent the contents of the on-chip flash memory from being read out or rewritten easily, the device incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. rom code protect function the rom code protect function reading out or modifying the contents of the on-chip flash memory by using the rom code protect address (0fffff 16 ) when in parallel i/o mode. figure 23-8 shows the rom code protect control address (0fffff 16 ). (this address exists in the user rom area.) if one of the pair of rom code protect bits is set to 0, rom code protect is turned on, so that the contents of the on-chip flash memory are protected against readout and modification. rom code protect is implemented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to "00", rom code protect is turned off, so that the contents of the on-chip flash memory can be read out or modified. once rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o- or some other mode to rewrite the contents of the rom code protect reset bits. figure 23-9. rom code protect control address symbol address when reset romcp 0fffff 16 ff 16 rom code protect level 2 set bit (note 1, 2) 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: protect removed 01: protect set bit effective 10: protect set bit effective 11: protect set bit effective 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect reset bit (note 3) rom code protect level 1 set bit (note 1) romcp2 romcr romcp1 b3 b2 b5 b4 b7 b6 note 1: when rom code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. note 2: when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. note 3: the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode. reserved bit always set this bit to 1.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer 228 functions to inhibit rewriting on-chip flash memory id code check function use this function in standard serial i/o mode. when the contents of the flash memory is not blank, the id code sent from the serial programmer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the serial programmer are not accepted. the id code consists of 8-bit data, the area of which, beginning with the first byte, are 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 and 0ffffb 16 . write a program which has the id code preset at these addresses to the flash memory. figure 23-10. id code store addresses reset watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 6 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address
229 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode description of pin function (flash memory parallel i/o mode) pin name signal name i/o function v cc ,v ss power supply input apply 3.3 0.3 v to the vcc pin (for both 5v and 3.3v versions) and 0 v to the vss pin. cnv ss cnv ss connect this pin to v cc . i reset reset input reset input pin. when reset is held low, more than 20 cycles of clock are required at the x in pin. i x in clock input connect a ceramic or crystal resonator between the x in and x out pins. when entering an externally derived clock, enter it from x in and leave x out open. i x out clock output o byte byte connect this pin to vcc or vss. i av cc , av ss analog power supply input v ref reference voltage input o connect avss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 data i/o d 0 to d 7 these are data d 0 Cd 7 input/output pins. i/o p1 0 to p1 7 address input a 0 to a 6 these are address a 0 Ca 6 (word address) input pins. address ai in parallel input/output mode is equivalent to ai + 1 in microcomputer mode. i p2 0 to p2 7 these are address a 7 Ca 14 (word address) input pins. i p3 0 to p3 7 p4 0 to p4 2 i ce input this is a ce input pin. i p5 1 this is a oe input pin. i p5 2 we input this is a we input pin. i p7 0 to p7 7 p9 2 p9 1 p9 0 to p9 7 input port p9 enter high or low signals to these pins or leave these pins open. i input port p9 enter high or low signals to these pins or leave these pins open. i p10 0 to p10 7 input port p10 enter high or low signals to these pins or leave these pins open. i data i/o d 8 to d 15 i/o these are data d 8 Cd 15 input/output pins. address input a 7 to a 14 p4 3 to p4 7 input port p4 enter high signals to these pins. i address input a 15 to a 17 these are address a 15 Ca 17 (word address) input pins. oe input p5 0 p5 3 wp input this is a wp input pin. i p5 4 bsel input this is a bsel input pin. i p5 5 epm input i enter a low signal to this pin. p5 6 to p5 7 input port p5 i enter high signals to these pins. p6 0 to p6 7 input port p6 enter high signals to these pins. i input port p7 enter high signals to these pins. i p8 0 to p8 1 i p8 5 rp input this is a rp input pin. i input port p8 enter high signals to these pins. i p8 2 to p8 4 input port p8 enter low signals to these pins. p8 6 to p8 7 input port p8 enter high signals to these pins. i ry/by output this is a ry/by output pin. o
230 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode table 24-1. differences from the m5m29fb800 parallel i/o mode the parallel i/o mode is entered by making connections shown in figure 24-2 and then turning the vcc power supply (3.3 v) on. in this mode, the m16c/6n (with on-chip flash memory) operates in a manner similar to the dinor flash memory m5m29fb800 by mitsubishi. note, however, that there are some differences in regard to the functions not available with the microcomputer and matters related to memory size, as shown in table 24-1. only in parallel i/o mode, the m16c/6n (with on-chip flash memory), either 5v- or 3.3v version, needs to be operated with a supply voltage of 3.3 v + 0.3 v. table 24-2 shows pin relationship between the m16c/6n and m5m29fb800 in parallel i/o mode. functions not available with microcomputer differences in matters related to memory capacity ? device id code readout ? suspend/resume functions ? sleep function ? additional write function note: do not apply v hh (12 v) to the a9 and rp pins. ? flash memory capacity ? block arrangement (see figure cc-1) functions only available with microcomputer ? boot rom area selection table 24-2. pin relationship in parallel i/o mode m16c/62(on-chip flash memory) m5m29fb800 v cc v ss v cc v ss v cc v ss address input data i/o oe input ce input wp input p2 1 to p2 7 , p3 0 to p3 7 , p4 0 , p4 1 , p4 2 p0 0 to p0 7 , p1 0 to p1 7 p5 1 p5 0 p5 3 a 0 to a 16 d 0 to d 15 oe ce wp we input byte input rp input ry/by output bsel input (note) p5 2 byte nmi p7 0 p5 4 we byte rp ry/by note: bsel is used to choose between the user rom and boot rom areas and has no equivalent pin in the m5m29fb800.
231 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode address the m16c/6n (with on-chip flash memory) has word- and byte modes which are switched over by the byte pin. when the byte pin is high, the 16-bit data bus is selected and the memory is accessed in 16 bits. in this case, addresses must always be specified by an even address. when the byte pin is low, the 8-bit data bus is selected and the memory is accessed in 8 bits. the user rom is divided into blocks as shown in figure 24-1. the block address referred to in this manual is the maximum even address of each block. figure 24-1. block diagram of on-chip flash memory 0c0000 16 0d0000 16 block 6 : 64k byte block 5 : 64k byte 0e0000 16 block 4 : 64k byte 0f0000 16 block 3 : 32k byte 0f8000 16 block 2 : 8k byte 0fa000 16 block 1 : 8k byte block 0 : 16k byte 0fc000 16 user rom area 8k byte 0fe000 16 0fffff 16 0fffff 16 boot rom area note 1: the boot rom area can be rewritten in only parallel input/output mode. (access to any other areas is inhibited.) note 2: to specify a block, use the maximum address in the block that is an even address. type no. flash memory start address m306n0fgt 0c0000 16
232 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode figure 24-2. pin connection diagram in parallel i/o mode signal value cnvss vcc epm vss reset vss mode setup method reset p5 0 /wrl/ wr 123 456 78910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0 0 /d 0 p0 1 /d 1 p0 2 /d 2 p0 3 /d 3 p0 4 /d 4 p0 5 /d 5 p0 6 /d 6 p0 7 /d 7 p1 0 /d 8 p1 1 /d 9 p1 2 /d 10 p1 3 /d 11 p1 4 /d 12 p1 5 /d 13 /int3 v ref av ss p1 6 /d 14 /int4 p1 7 /d 15 /int5 v c c x in x o ut v ss reset cnvss p8 7 /x c in p8 6 /x co ut byte p2 0 /a 0 (/d 0 /-) p2 1 /a 1 (/d 1 /d 0 ) p2 2 /a 2 (/d 2 /d 1 ) p2 3 /a 3 (/d 3 /d 2 ) p2 4 /a 4 (/d 4 /d 3 ) p2 5 /a 5 (/d 5 /d 4 ) p2 6 /a 6 (/d 6 /d 5 ) p2 7 /a 7 (/d 7 /d 6 ) p3 0 /a 8 (/-/d 7 ) p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 p4 3 /a 19 p7 4 /ta2 o ut /w p7 5 /ta2 in /w p7 6 /ta3 o ut p5 6 /ale p7 7 /ta3 in p5 5 /hold p5 4 /hlda p5 3 /bclk p5 2 /rd vcc vss p5 7 /rdy/clk out p4 5 /cs1 p4 6 /cs2 p4 7 /cs3 avcc p6 3 /t x d 0 p6 5 /clk 1 p6 6 /rxd 1 p6 7 /t x d 1 p6 1 /clk 0 p6 2 /rxd 0 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p10 4 /an 4/ ki 0 p10 5 /an 5 /ki 1 p10 6 /an 6 /ki 2 p10 7 /an 7 /ki 3 p9 3 /da 0 /tb3 in p9 4 /da 1 /tb4 in p9 5 /anex0/clk4 p9 6 /anex1/s o ut 4 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s o ut 3 p9 7 /ad trg /s in 4 p8 2 /int 0 p8 3 /int 1 p8 1 /ta4 in /u p8 4 /int 2 p8 0 /ta4 o u t /u p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p7 3 /cts 2 /rts 2 /ta1 in /v p7 2 /clk 2 /ta1 o ut /v p7 1 /rxd 2 /scl/ta0 in /tb5 in nmi p4 4 /cs0 p5 1 /wrh/bhe p9 0 /tb0 in /clk3 p7 0 /t x d 2 /sda/ta0 o ut p8 5 / M306N0FGTFP (100p6s) vcc vss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d14 d15/a-1 d12 d13 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bsel ce oe we epm wp rp ry/by cnvss byte connect oscillator circuit.
233 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode user rom and boot rom areas in parallel i/o mode, the user rom- and boot rom areas shown in figure 24-1 can be rewritten. bsel pin is used to select between these two areas. the user rom area is selected by pulling the bsel input low; the boot rom area is selected by driving the bsel input high. both areas of flash memory can be operated on in the same way. program- and block erase operations can be performed in the user rom area. the user rom area and its blocks are shown in figure 24-1. the boot rom area is 8 kbytes in size. in parallel i/o mode, it is located at address 0fe000 16 through 0fffff 16 . make sure program- and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 8 kbyte block. the boot rom area has a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, if the device is going to be used in standard serial i/o mode, do not rewrite the boot rom area. functional outline (parallel i/o mode) in parallel i/o mode, bus operation modes read, output disable, standby, write and deep power down are selected by the status of the ce-, oe-, we- and rp input pins. the contents of erase-, program- and other operations are selected by writing a software command. the data, status register, etc. in memory can be read out only by a read after software command input. program- and erase operations are controlled using software commands. table 24-3. relationship between control signals and bus operation modes read write stand by array deep power down output disabled status register lock bit status program erase other data output status register data output lock bit data (d 6 ) output hi-z command/data input command input command input hi-z hi-z v il v il v il v il v ih v il v il v il v il v il v il v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v ih v il v il v il v il x x x x x mode pin name ce oe we rp d 0 to d 15 note: x can be v il or v ih .
234 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode bus operation modes read the read mode is entered by pulling the oe pin low when the ce pin is low and the we- as well as rp pins are high. there are three read modes: array, status register and lock bit status which are selected by software command input. in read mode, the data corresponding to each software command entered are output from the data i/o pins d 0 C d 15 . the read array mode is automatically selected when the device is powered on after it exits deep power down mode. output disable the output disable mode is entered by pulling the ce pin low and the we-,oe- and rp pins high. also, the data i/o pins are placed in the high-impedance state. standby the standby mode is entered by driving the ce pin high when the rp pin is high. also, the data i/o pins are placed in the high-impedance state. however, if the ce pin is set high during erase- or program operation, the internal control circuit does not halt immediately and normal power consumption is required until the operation under way is completed. write the write mode is entered by pulling the we pin low when the ce pin is low and the oe- as well as rp pins are high. in this mode, the device accepts the software commands or write data entered from the data i/o pins. a program-, erase- or some other operation is initiated depending on the content of the software command entered here. the input data such as addresses and software command are latched at the rising edge of we or ce whichever occurs earlier. deep power down the deep power down is entered by pulling the rp pin low. also, the data i/o pins are placed in the high- impedance state. when the device is freed from deep power down mode, the read array mode is selected and the content of the status register is set to "80 16 ". if the rp pin is pulled low during erase- or program operation, the operation under way is cancelled and the data in the relevant block becomes invalid.
235 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode software commands table 24-4 lists the software commands available with the m16c/6nt (with on-chip flash memory). by entering a software command from the data i/o pins (d 0 C d 7 ) in write mode, specify the content of the operation, such as erase- or program operation, to be performed. when entering a software command, the upper byte (d 8 C d 15 ) is ignored. read array command (ff 16 ) the read array mode is entered by writing the command code "ff 16 " in the first bus cycle. when an address to read is input in one of the bus cycles that follow, the content of the specified address is output from the data bus (d 0 C d 15 ). the address entered here must be an even address when the byte pin is high (16-bit mode). the read array mode is retained intact until another command is written. the read array mode is also selected automatically when the device is powered on and after it exits deep power down mode. read status register command (70 16 ) when the command code "70 16 " is written in the first bus cycle, the content of the status register is output from the data bus (d 0 C d 7 ) by a read in the second bus cycle. since the content of the status register is updated at the falling edge of oe or ce, the oe- or ce signal must be asserted each time the status is read. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr3 to 5 of the status register after they are set. these bits indicate that operation has ended in an error. to use this command, write the command code "50 16 " in the first bus cycle. table 24-4. software command list (parallel i/o mode) command page program clear status register read array read status register x x x x (note 3) first bus cycle second bus cycle third bus cycle ff 16 70 16 50 16 41 16 write write write write x srd read write lock bit program x 77 16 write ba d0 16 write erase all unlock block x a7 16 write x d0 16 write wa1 wd1 write (note 2) wa0 (note 3) wd0 (note 3) block erase x 20 16 write d0 16 write ba (note 4) read lock bit status x 71 16 write ba d 6 read (note 5) mode address mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) data (d 0 to d 7 ) (note 6) note 1: when a software command is input, the upper byte of data (d 8 to d 15 ) is ignored. note 2: srd = status register data note 3: wa = write address, wd = write data wa and wd must be set sequentially from 00 16 to fe 16 (an even address). the page size is 256 bytes. note 4: ba = block address (enter the maximum address of each block that is an even address.) note 5: d 6 corresponds to the block lock status. block not locked when d 6 = 1, block locked when d 6 = 0.
236 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode page program command (41 16 ) page programming enables high-speed programming in blocks of 256 bytes. the page programming operation is started when the "41 16 " command code is written for the first bus cycle. write data are then written sequentially from the second bus cycle to the 129th bus cycle. in this case, when the byte pin is "h" level, the address must be odd and increased by two from "00 16 " to "ff 16 ". when the byte pin is "l" level, the address must increase from "00 16 " to "ff 16 ". when data loading ends, the auto write (data program and verify) operation starts. auto write end can be verified by reading the status register or the status of the ry/by signal. at the start of the auto write operation, the read status register mode is automatically engaged, so the contents of the status register can be read from the data i/o pins (d 0 C d 7 ). status register bit 7 (sr7) becomes "0" when the auto write operation starts and returns to "1" when it ends. in this way, the read status register mode is maintained until the next read array command (ff 16 ) or read lock bit status command (71 16 ) is written. similar to the status register bit 7, the ry/by pin is "l" level during the auto write period and becomes "h" level when auto write ends. after the auto write operation ends, the result of the operation can be known by reading the status register. for more information, see the section on the status register. figure 24-3 shows a flowchart of the page program. for the operation timing of the page program, see the time chart in the section on electric characteristics. each block can be write-protected with the lock bit. for more information, see the section on the data protection. additional writing is not allowed with already programmed pages. figure 24-3. page program flowchart n=ff 16 n=fe 16 start write 41 16 n=0 write address n and data n sr7=1? read status register run full status check if needed page program end n=n+1/n=n+2 no yes no yes
237 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode block erase command (20 16 /d0 16 ) writing the "20 16 " command code for the first bus cycle and, after that, the "d0 16 " verify command code and the block address of a block for the second bus cycle starts the auto erase (erase and erase verify) operation for the specified block. auto erase end can verified by reading the status register or the status of the ry/by signal. at the start of the auto erase operation, the read status register mode is automatically engaged, so the contents of the status register can be read from the data i/o pins (d 0 C d 7 ). status register bit 7 (sr7) becomes "0" when the auto erase operation starts and returns to "1" when it ends. in this way, the read status register mode is maintained until the next read array command (ff 16 ) or read lock bit status command (71 16 ) is written. similar to the status register bit 7, the ry/by pin is "l" level during auto erase operations and becomes "h" level when auto erase ends. after the block erase operation ends, the result of the operation can be known by reading the status register. for more information, see the section on the status register. figure 24-4 shows a flowchart of block erasing. for the block erase operation timing, see time chart in the section on electric characteristics. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. write 20 16 write d0 16 and block address read status register sr7=1? run full status check if needed block erase end no yes start figure 24-4. block erase flowchart
238 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode erase all unlocked blocks command (a7 16 /d0 16 ) writing the "a7 16 " command code for the first bus cycle and the "d0 16 " verify command code for the second bus cycle continuously executes the block erase operation for all the blocks. in this case, it is not necessary to specify an address in the second bus cycle. even after the erase all unlock blocks operation ends, as with block erase, the end of the operation can be verified by reading the status register or the status of the ry/by signal. also, the result of the erase operation can be known by reading the status register. when the wp pin is "h" level, all blocks are erased regardless of lock bit status. when the wp pin is "l" level, the lock pin is enabled and only unlocked blocks (lock bit data are "1") are erased. lock bit program command (77 16 /d0 16 ) writing the "77 16 " command code for the first bus cycle and, after that, the "d0 16 " verify command code as well as the block address of a block for the second bus cycle writes "0" (lock) for the lock bit of the specified block. figure 24-5 shows an example of flowchart of the lock bit program. the lock bit status (lock bit data) can be read with the read lock bit status command. as with the page program, the end of the lock bit program auto write operation can be verified by reading the status register or the status of the ry/by signal. for information on the lock bit function, reset procedure and so on, see the section on the data protection function. sr7=1? write 77 16 write d0 16 and block address no yes sr4=0? no lock bit program end lock bit program error yes start figure 24-5. lock bit program flowchart
239 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode read lock bit status command (71 16 ) after the "71 16 " command code is written for the first bus cycle and the address block of a given block is specified in the second bus cycle, the lock status of the specified block is output as data i/o pin bit 6 (d6). figure 24-6 shows an example of flowchart of the read lock bit status. d6 = 0? block locked no yes write block address block unlocked (note) note: data bus bit 6. write 71 16 star t figure 24-5. lock bit program flowchart
240 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode data protection function (block lock ) each of the blocks in figure 24-1 has a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. a block is locked (writing "0" for the lock bit) with the lock bit program command. also, the lock bit of any block can be read with the read lock bit status command. block lock enable/disable is determined by the status of the lock bit itself and the status of the rp- and wp pins. this relationship is given in table 24-5. (1) when the rp pin is "l" level, the deep power down mode is engaged and all blocks are locked. (2) when the rp pin is "h" level and the wp pin "l" level, the specified block can be locked/unlocked using the lock bit (lock bit data). blocks with "0" lock bit data are locked and cannot be erased or written in. on the other hand, blocks with "1" lock bit data are unlocked and can be erased or written in. (3) when the rp pin and the wp pin are both "h" level, all blocks are unlocked regardless of lock bit data status and can be erased or written in. in this case, lock bit data that were "0" before the block was erased are set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. table 24-5. block lock conditions locks all blocks (deep power down mode) locks block using lock bit data unlocks block using lock bit data unlocks all blocks (note 2) v il v ih v ih v ih x v il v il v ih x 0 1 x rp wp lock bit (internal) block lock (note 1) note 1: during read/write operations or when the write state machine (wsm) status is busy (sr7 = "0"), do not switch wp pin state. note 2: in this case, the lock bit is set to "1" after the block is erased.
241 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode status register the status register indicates status such as whether an erase operation or a program ended successfully or in error. it can be read under the following conditions. (1) in the read array mode or lock bit status mode, when the read status register command (70 16 ) is written and the block address is subsequently read. (2) in the period from when the page program auto write or auto erase starts to when the read array command (ff 16 ) or the read lock bit status command (71 16 ) is input. the status register is cleared in the following situations. (1) when the clear status register command (50 16 ) is written (2) when in the deep power down mode (3) when power is turned off table 24-6 gives the definition of each status register bit. when power is turned on or returning from the deep power down mode, the status register outputs "80 16 ". table 24-6. status register symbol sr4 (d 4 ) sr0 (d 0 ) sr5 (d 5 ) sr7 (d 7 ) sr6 (d 6 ) sr3 (d 3 ) sr2 (d 2 ) sr1 (d 1 ) status definition write state machine (wsm) status "0" reserved erase status program status program status after-program reserved reserved reserved "1" ready ended in error ended in error ended in error busy ended successfully ended successfully ended successfully write state machine (wsm) status (sr7) the write state machine (wsm) status indicates the operating status of the flash memory. when power is turned on or returning from deep power down mode, it is set to "1". this bit is "0" (busy) during the auto write- or erase operation and becomes "1" when the operation ends. erase status (sr5) the erase status reports the operating status of the auto erase operation. if an erase error occurs, it is set to "1". when the erase status is cleared, it is set to "0". program status (sr4) the program status reports the operating status of the auto write operation. if a write error occurs, it is set to "1". when the program status is cleared, it is set to "0".
242 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode block status after program (sr3) if excessive data are written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), the block status after-program is set to "1" at the end of the page write operation. in other words, when writing ends successfully, "80 16 " is output; when writing fails, "90 16 " is output; and when excessive data are written, "88 16 " is output. if "1" is written for any of sr5-, sr4- or sr3 bits, the page program-, block erase-, erase all unlocked blocks- and lock bit program commands are not accepted. before executing these commands,, execute the clear status register command (50 16 ) and clear the status register. also in the following cases, both sr4 and sr5 are set to "1" (command sequence error). (1) if data other than "d0 16 " or "ff 16 " are input for the second bus cycle data of the lock bit program command (77 16 /d0 16 ). (2) if data other than "d0 16 " or "ff 16 " are input for the second bus cycle data of the block erase command (20 16 /d0 16 ). (3) if data other than "d0 16 " or "ff 16 " are input for the second bus cycle data of the erase all unlocked blocks command (a7 16 /d0 16 ). however, inputting "ff 16 " engages the read array mode and cancels the setup command in the first bus cycle. full status check results of executed erase- and program operations can be known by running a full status check. figure 24-7 shows a flowchart of the full status check and explains how to remedy errors which may occur. figure 24-7. full status flowchart and remedial procedure for errors read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands.
243 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer parallel i/o mode ready/busy (ry/by) pin the ry/by pin is an output pin which, like the write state machine (wsm) status (sr7), indicates the operating status of the flash memory. it is "l" level during the auto write- or the auto erase operation and becomes to the high-impedance state (ready state) when the operation ends. the ry/by pin requires an external pull-up.
244 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode pin functions (flash memory standard serial i/o mode) pin description v cc ,v ss apply program/erase protection voltage to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out byte connect this pin to vcc or vss. av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p2 0 to p2 7 input "h" or "l" level signal or open. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 7 input "h" or "l" level signal or open. p5 1 to p5 4, p5 6, p5 7 input "h" or "l" level signal or open. p5 0 input "h" level signal. p5 5 input "l" level signal. p6 0 to p6 3 input "h" or "l" level signal or open. p6 4 busy signal output pin p6 5 serial clock input pin p6 6 serial data input pin p6 7 serial data output pin p7 0 to p7 7 input "h" or "l" level signal or open. p8 0 to p8 7 input "h" or "l" level signal or open. p9 to p9 7 input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output byte analog power supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 input port p5 ce input epm input input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 input port p10 i/o i i i o i o i i i i i i i i i o i i o i i i i
245 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode 12345678 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0 0 /d 0 p0 1 /d 1 p0 2 /d 2 p0 3 /d 3 p0 4 /d 4 p0 5 /d 5 p0 6 /d 6 p0 7 /d 7 p1 0 /d 8 p1 1 /d 9 p1 2 /d 10 p1 3 /d 11 p1 4 /d 12 p1 5 /d 13 /int3 v ref av ss p1 6 /d 14 /int4 p1 7 /d 15 /int5 v cc x in x out v ss reset cnvss p8 7 /x cin p8 6 /x cout byte p2 0 /a 0 (/d 0 /-) p2 1 /a 1 (/d 1 /d 0 ) p2 2 /a 2 (/d 2 /d 1 ) p2 3 /a 3 (/d 3 /d 2 ) p2 4 /a 4 (/d 4 /d 3 ) p2 5 /a 5 (/d 5 /d 4 ) p2 6 /a 6 (/d 6 /d 5 ) p2 7 /a 7 (/d 7 /d 6 ) p3 0 /a 8 (/-/d 7 ) p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 p4 3 /a 19 p7 4 /ta2 out /w p7 5 /ta2 in /w p7 6 /ta3 out p5 6 /ale p7 7 /ta3 in p5 5 /hold p5 4 /hlda p5 3 /bclk p5 2 /rd vcc vss p5 7 /rdy/clk out p4 5 /cs1 p4 6 /cs2 p4 7 /cs3 avcc p6 3 /t x d 0 p6 5 /clk 1 p6 6 /rxd 1 p6 7 /t x d 1 p6 1 /clk 0 p6 2 /rxd 0 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p10 4 /an 4/ ki 0 p10 5 /an 5 /ki 1 p10 6 /an 6 /ki 2 p10 7 /an 7 /ki 3 p9 3 /da 0 /tb3 in p9 4 /da 1 /tb4 in p9 5 /anex0/clk4 p9 6 /anex1/s out 4 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s out 3 p9 7 /ad trg /s in 4 p8 2 /int 0 p8 3 /int 1 p8 1 /ta4 in /u p8 4 /int 2 p8 0 /ta4 out /u p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p7 3 /cts 2 /rts 2 /ta1 in /v p7 2 /clk 2 /ta1 out /v p7 1 /rxd 2 /scl/ta0 in /tb5 in p8 5 /nmi p4 4 /cs0 p5 0 /wrl/wr p5 1 /wrh/bhe p9 0 /tb0 in /clk3 p7 0 /t x d 2 /sda/ta0 out vcc vss rxd txd sclk cnvss ce epm busy reset M306N0FGTFP (100p6s) cnvss vcc epm vss reset vss to vcc ce vcc connect oscillator circuit. signal value mode setup method figure 25-1. pin connections for serial i/o mode
246 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode standard serial i/o mode the standard serial i/o mode serially inputs and outputs the software commands, addresses and data neces- sary for operating (read, program, erase, etc.) the internal flash memory. it uses a purpose-specific serial programmer. the standard serial i/o mode differs from the parallel i/o mode in that the cpu controls operations like rewriting (uses the cpu rewrite mode) in the flash memory or serial input for rewriting data. the standard serial mode is started by clearing the reset with an "h" level signal at the p5 0 (ce) pin, an "l" signal at the p5 5 (epm) pin and an "h" level at the cnvss pin. (for the normal microprocessor mode, set cnvss to "l".) this control program is written in the boot rom area when shipped from mitsubishi electric. therefore, if the boot rom area is rewritten in the parallel i/o mode, the standard serial i/o mode cannot be used. figure 25-1 shows the pin connections for the standard serial i/o mode. serial data i/o uses four uart1 pins: clk1, r x d1, t x d1 and rts1 (busy). the clk1 pin is the transfer clock input pin and it transfers the external transfer clock. the t x d1 pin outputs the cmos signal. the rts1 (busy) pin outputs an "l" level when reception setup ends and an "h" level when the reception operation starts. transmission- and reception data are transferred serially in 8-byte blocks. in the standard serial i/o mode, only the user rom area shown in 24-1 can be rewritten, the boot rom area cannot. the standard serial i/o mode has a 7-byte id code. when the flash memory is not blank and the id code does not match the content of the flash memory, the command sent from the programmer is not accepted. function overview (standard serial i/o mode) in the standard serial i/o mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a 4-wire clock-synchronized serial i/o (uart1). in reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the clk1 pin and input into the flash memory via the r x d1 pin. in transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the t x d1 pin. the t x d1 pin is cmos output. transmission is in 8-bit blocks and lsb first. when busy, either during transmission or reception, or while executing an erase operation or program the r t s1 (busy) pin is "h" level. accordingly, do not start the next transmission until the rts1 (busy) pin is "l" level. also, data in memory and the status register can be read after inputting a software command. it is possible to check flash memory operating status or whether a program- or erase operation ended successfully or in error by reading the status register. software commands and the status register are explained here following.
247 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode table 25-1. software commands (standard serial i/o mode) software commands table 25-1 lists software commands. in the standard serial i/o mode, erase operation, programs and reading are controlled by transferring software commands via the r x d pin. software commands for the serial i/o mode are basically the same as those for the parallel i/o mode, but there are six additional commands to make up for wp pin functions used in the parallel i/o mode. these commands are lock bit disable, lock bit enable, id check, download, version information output and boot area output. control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lockbit status 8 lockbit program 9 lockbit enable 10 lockbit disable 11 id check function 12 download function 13 version data output function 14 boot area output function ? shading indicates transfer from flash memory microcomputer to serial programmer. all other data is transferred from the serial programmer to the flash memory microcomputer. ? srd refers to status register data. srd1 refers to status register 1 data. ? all commands can be accepted when the flash memory is totally blank. when id is not verificate not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable version data output to 9th byte data output to 259th byte data output to 259th byte data input to 259th byte to id7 data output data input id1 to required number of times version data output data output data output data input id size data input version data output data output data output data input d0 16 lock bit data output d0 16 address (high) check- sum version data output data output address (high) address (high) address (high) srd1 output address (high) address (high) address (middle) size (high) version data output address (high) address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (middle) address (low) size (low) version data output address (middle) ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 77 16 7a 16 75 16 f5 16 fa 16 fb 16 fc 16
248 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode figure 25-2. timing for reading array read array command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the read array command as explained below. (1) send the "ff 16 " command code in the first byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the second and the third bytes of the transmission respectively. (3) from the fourth byte onward, data (d0 to d7) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smaller address first in synchronization with the rise of the clock. data0 data255 clk1 txd1 rxd1 rts1(busy) a 8 to a 15 a 16 to a 23 ff 16 read status register command this command reads status information. when the "70 16 " command code is sent in the first byte of the transmission, the contents of the status register (srd) specified in the second byte of the transmission and the contents of status register 1 (srd1) specified in the third byte of the transmission are read. srd output srd1 output clk1 txd1 rxd1 rts1(busy) 70 16 figure 25-3. timing for reading the status register
249 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode clear status register command this command clears the bits (sr3 C sr5) which are set when the status register operation ends in error. when the "50 16 " command code is sent in the first byte of the transmission, the abovementioned bits are cleared. when the clear status register operation ends, the rts1 (busy) signal changes from the "h" to the "l" level. figure 25-4. timing for clearing the status register clk1 txd1 rxd1 (rts1)busy 50 16 page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained below. (1) send the "41 16 " command code in the first byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the second and the third bytes of the transmission respectively. (3) from the fourth byte onward, as write data (d0 C d7) for the page (256 bytes) specified with addresses a 8 to a 23 are input sequentially from the smallest address first, that page is automati- cally written. when reception setup for the next 256 bytes ends, the rts1 (busy) signal changes from the "h" to the "l" level. the result of the page program can be known by reading the status register. for more informa- tion, see the section on the status register. each block can be write-protected with the lock bit. for more information, see the section on the data protection function. additional writing is not allowed in the already programmed pages. clk1 txd1 rxd1 rts1(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255 figure 25-5. timing for the page program
250 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode block erase command this command erases the data in the specified block. execute the block erase command as explained below. (1) send the "20 16 " command code in the first byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the second and the third bytes of the transmission respectively. (3) send the verify command code "d016" in the fourth byte of the transmission. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . when the block ease ends, the rts1 (busy) signal changes from the "h" to the "l" level. after the block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. a 8 to a 15 a 16 to a 23 20 16 d0 16 clk1 txd1 rxd1 rts1(busy) figure 25-6. timing for block erase
251 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode figure 25-7. timing for erasing all unlocked blocks erase all unlocked blocks command this command erases the content of all the blocks. execute the erase all unlocked blocks command as explained below. (1) send the "a7 16 " command code in the first byte of the transmission. (2) send verify command code "d0 16 " in the second byte of the transmission. with the verify com- mand code, the erase operation will start and continue for all the block in the flash memory. when the block erase ends, the rts1 (busy) signal changes from the "h" to the "l" level. the result of the erase operation can be known by reading the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. clk1 txd1 rxd1 rts1(busy) a7 16 d0 16 lock bit program command this command writes "0" (lock) for the lock bit of the specified block. execute the lock bit program command as explained below. (1) send the "77 16 " command code in the first byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the second and the third bytes of the transmission respectively. (3) send verify command code "d0 16 " in the fourth byte of the transmission. with the verify command code, "0" is written for the lock bit of the specified block. write the highest address of the specified block for the addresses a 8 to a 23 . when the writing ends, the rts1 (busy) signal changes from the "h" to the "l" level. lock bit status can be read with the read lock bit status command. for information on the lock bit function, see the section on the data protection function. clk1 txd1 rxd1 rts1(busy) a 8 to a 15 a 16 to a 23 77 16 d0 16 figure 25-8. timing for lock bit program
252 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status command as explained below. (1) send the "71 16 " command code in the first byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the second and the third bytes of the transmission respectively. (3) the lock bit data of the specified block are output in the fourth byte of the transmission. write the highest address of the specified block for the addresses a 8 to a 23 . clk1 txd1 rxd1 rts1(busy) a 8 to a 15 a 16 to a 23 71 16 dq6 figure 25-9. timing for reading lock bit status lock bit enable command this command enables the lock bit in blocks whose bit has been disabled with the lock bit disable command. it functions in the same way as the wp pin in the parallel i/o mode. the command code "7a 16 " is sent in the first byte of the serial transmission. this command enables the lock bit function only; it does not set the lock bit itself. 7a 16 clk1 txd1 rxd1 rts1(busy) figure 25-10. timing for enabling the lock bit
253 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode lock bit disable command this command disables the lock bit. it functions in the same way as the wp pin in the parallel i/o mode. the command code "7a 16 " is sent in the first byte of the serial transmission. this command enables the lock bit function only; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data will be set to "1" (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. 75 16 clk1 txd1 rxd1 rts1(busy) figure 25-11. timing for disabling the lock bit download command this command downloads a program into the ram for execution. execute the download command as explained below. (1) send the "fa 16 " command code in the first byte of the transmission. (2) send the program size in the second and the third bytes of the transmission. (3) send the check sum in the fourth byte of the transmission. the check sum is added to all the data in the fifth byte onward. (4) the program to execute is sent in the fifth byte onward. when all the data are transmitted, if the check sum matches, the download program is executed. the size of the program may vary according to the internal ram. fa 16 program data program data data size (high) data size (low) check sum clk1 txd1 rxd1 rts1(busy) figure 25-12. timing for download
254 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained below. (1) send the "fb 16 " command code in the first byte of the transmission. (2) the version information will be output from the second byte onward. these data are composed of 8 ascii code characters. fb 16 'x' 'v' 'e' 'r' clk1 txd1 rxd1 rts1(busy) figure 25-13. timing for version information output boot area output command this command outputs the control program stored in the boot area in one page blocks (256 bytes). execute the boot area output command as explained below. (1) send the "fc 16 " command code in the first byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the second and the third bytes of the transmission respectively. (3) from the fourth byte onward, data (d0 C d7) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in synchronization with the rise of the clock. data0 data255 clk1 txd1 rxd1 rts1(busy) a 8 to a 15 a 16 to a 23 fc 16 figure 25-14. timing for boot area output
255 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode id check this command checks the id code. execute the boot id check command as explained below. (1) send the "f5 16 " command code in the first byte of the transmission. (2) send addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the first byte of the id code in the second, the third and the fourth bytes of the transmission respectively. (3) send the number of data sets of the id code in the fifth byte. (4) the id code is sent in the sixth byte onward, starting with the first byte of the code. when all the data are transmitted, if the check sum matches, the download program is executed. the size of the program may vary according to the internal ram. figure 25-15. timing for id check id size id1 id7 clk1 txd1 rxd1 rts1(busy) f5 16 df 16 ff 16 0f 16 id code when the flash memory is not blank, the id code sent from the serial programmer and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the serial programmer is not accepted. an id code contains 8 bits of data. its area is, from the first byte, 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 and 0ffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. reset watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 6 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address figure 25-16. id code storage addresses
256 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode data protection (block lock) each of the blocks in figure 24-1 has a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. a block is locked (writing "0" for the lock bit) with the lock bit program command. also, the lock bit of any block can be read with the read lock bit status command. block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable- and lock enable bit commands. (1) after the reset is cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). blocks with "0" lock bit data are locked and cannot be erased or written in. on the other hand, blocks with "1" lock bit data are unlocked and can be erased or written in. (2) after the lock bit enable command is executed, all the blocks are unlocked regardless of lock bit data status and can be erased or written in. in this case, lock bit data that were "0" before the block was erased will be set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. 0c0000 16 0d0000 16 block 6 : 64k byte block 5 : 64k byte 0e0000 16 block 4 : 64k byte 0f0000 16 block 3 : 32k byte 0f8000 16 block 2 : 8k byte 0fa000 16 block 1 : 8k byte block 0 : 16k byte 0fc000 16 user rom area 0fffff 16 type no. flash memory start address M306N0FGTFP 0c0000 16 figure 25-17. blocks in the user area
257 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 25-2 gives the definition of the status register bits. after clearing the reset, the status register outputs "80 16 ". table 25-2. status register (srd) each bit of srd sr4 (bit4) sr5 (bit5) sr7 (bit7) sr6 (bit6) status name definition sr1 (bit1) sr2 (bit2) sr3 (bit3) sr0 (bit0) "1" "0" program status erase status write state machine (wsm) status reserved reserved reserved block status after program reserved ready busy terminated in error terminated in error terminated in error terminated normally terminated normally terminated normally - - - - - - - - write state machine (wsm) status (sr7) the write status machine (wsm) status indicates the operating status of the flash memory. when power is turned on, it is set to "1" (ready). the bit is set to "0" (busy) during an auto write- or an auto erase operation, but it is set back to "1" when the operation ends. erase status (sr5) the erase status reports the operating status of the auto erase operation. it is set to "1" if an erase error occurs. when the erase status is cleared, it is set to "0". program status (sr4) the program status reports the operating status of the auto write operation. it is set to "1" if a write error occurs. when the program status is cleared, it is set to "0".
258 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode program status after program (sr3) if excessive data are written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), the block status after-program is set to "1" at the end of the page write operation. in other words, when writing ends successfully, "80 16 " is output; when writing fails, "90 16 " is output; and when excessive data are written, "88 16 " is output. if "1" is written for any of sr5-, sr4- or sr3 bits, the page program-, block erase-, erase all unlocked blocks- and lock bit program commands are not accepted. before executing these commands, ex- ecute the clear status register command (50 16 ) and clear the status register. also in the following cases, both sr4 and sr5 are set to "1" (command sequence error). (1) if data other than "d0 16 " or "ff 16 " are input for the second bus cycle data of the lock bit program command (77 16 /d0 16 ). (2) if data other than "d0 16 " or "ff 16 " are input for the second bus cycle data of the block erase command (20 16 /d0 16 ). (3) if data other than "d0 16 " or "ff 16 " are input for the second bus cycle data of the erase all unlocked blocks command (a7 16 /d0 16 ). however, inputting "ff 16 " engages the read array mode and cancels the setup command in the first bus cycle. figure 25-17. blocks in the user area 0c0000 16 0d0000 16 block 6 : 64k byte block 5 : 64k byte 0e0000 16 block 4 : 64k byte 0f0000 16 block 3 : 32k byte 0f8000 16 block 2 : 8k byte 0fa000 16 block 1 : 8k byte block 0 : 16k byte 0fc000 16 user rom area 0fffff 16 type no. flash memory start address M306N0FGTFP 0c0000 16
259 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode status register 1 (srd1) the status register 1 indicates status of serial communication, results of id checks and those of check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 25-4 gives the definition of each status register bit. "00 16 " is output when power is turned on and the flag status is maintained even after the reset. table 25-3. status register 1 (srd 1) srd1 bits sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) status name boot update completed bit reserved reserved checksum match bit id check completed bits data receive time out reserved definition "1" "0" - - - match 00 01 10 11 - - - mismatch normal operation - not verified verification mismatch reserved verified time out block update completed bit (sr15) this flag indicates whether or not the control program was downloaded to the ram, using the download function. check sum consistency bit (sr12) this flag indicates whether or not the check sum matches when a program is downloaded for execution using the download function. id check completed bits (sr11 and sr 10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state.
260 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode full status check results of executed erase- and program operations can be known by running a full status check. figure 25- 18 shows a flowchart of the full status check and explains how to remedy errors which may occur. read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands. figure 25-18. full status check flowchart and remedial procedure for errors
261 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode example circuit application for the standard serial i/o mode the figure blow shows a circuit application for the standard serial i/o mode. control pins may vary accord- ing to programmer, therefore see the programmer manual for more information. figure 25-19. example circuit application for the standard serial i/o mode rts1(busy) clk1 r x d1 t x d1 cnvss nmi clock input rts1 output data input data output p5 0 (ce) p5 5 (epm) m16c/62 flash memory (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch.
262 under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c / 6n group single-chip 16-bit cmos microcomputer standard serial i/o mode mitsubishi semiconductors m16c/6n group data sheet rev.b second edition march1999 editioned by committee of editing of mitsubishi semiconductor data sheet published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1998 mitsubishi electric corporation

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