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general description the max3952 16:1 serializer is optimized for 10.3gbps and 9.95gbps ethernet applications. a serial clock out- put is provided for retiming the data at the latch input of the laser driver. both the high-speed data and clock are cml outputs. the serializer operates from a single +3.3v supply, consuming only 1.15w typical power. the clock multiplier reference clock frequency can be either 1/16 or 1/64 the serial output clock rate. a fifo aligns the phase between the parallel clock input and the internally synthesized clock. in addition, a 1/16 counterdirectional clock output (lvds) is provided for use as the clock signal of the xaui codec ic or framer. the operating temperature range is from -40? to +85?. the max3952 is available in a 10mm ? 10mm 68-pin qfn package. applications 10gbps ethernet lan 10gbps ethernet wan features operates at 9.953gbps and 10.3125gbps 16-bit lvds interface single +3.3v supply 1.15w power dissipation lvds source clock output built-in 2 7 - 1 prbs pattern generator deterministic jitter: 9ps (max) at 0? to +85? operating temperature range: -40? to +85? 68-pin qfn package (10mm ? 10mm) max3952 10gbps 16:1 serializer ________________________________________________________________ maxim integrated products 1 ordering information max3952 max3930 gnd ttl sclken fifoerr 644.53mhz refclk input pdio+ refclk+ refclk- v cc _vco v cc ckset lock prbsen reset 3.3v mac pclko- pclko+ pclki- pclki+ pdi15- pdi15+ pdio- this symbol represents a transmission line of characteristic impedance (z 0 = 50 ? ). fil 0.1 f 5v sdo+ sdo- sclko- sclko+ 100 ? typical application circuit 19-2405; rev 0; 4/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max3952egk -40 c to +85 c 68 qfn pin configuration appears at end of data sheet.
max3952 10gbps 16:1 serializer 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3v to +3.6v, t a = -40 c to +85 c. typical values are at v cc = +3.3v, differential lvds load = 100 ? , t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power supply (v cc )....................................................-0.5 to +5v cml output current (sdo, sclko)..............................22ma lvds input voltage levels (pdi_, pclki).....................................-0.5v to (v cc + 0.5v) lvds output voltage (pclko)................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85 c) qfn (derate 30.3mw/ c above 70 c) .......................2424mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +160 c voltage levels at fil, reset, ckset........-0.5v to (v cc + 0.5v) lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units supply current i cc (note 1) 350 500 ma lvds input specifications (pdi [15 0], pclki ) input voltage range v i 0 2400 mv differential input voltage |v id | 100 mv input common-mode current input, v os = 1.2v 100 a threshold hysteresis 70 mv differential input impedance r in 85 100 115 ? lvds output specifications (pclko ) output high voltage v oh 1.475 v output low voltage v ol 0.925 v differential output voltage |v od | 250 400 mv change in magnitude of differential outputs for complementary inputs ? |v od | 25 mv offset output voltage 1.125 1.275 v change in magnitude of output offset voltage for complementary states ? |v os | 25 mv differential output impedance 80 140 ? short together 12 output current short to ground 40 ma
max3952 10gbps 16:1 serializer _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3v to +3.6v, t a = -40 c to +85 c. typical values are at v cc = +3.3v, differential lvds load = 100 ? , t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units cml output specifications (sdo , sclko ) differential output r l = 50 ? to v cc 640 800 1000 mv p-p differential output impedance 85 100 115 ? output common-mode voltage r l = 50 ? to v cc v cc - 0.2 v lvttl specifications (reset, fifo_error, lock, prbsen) lvttl input high voltage v ih 2.0 v lvttl input low voltage v il 0.8 v lvttl input high current i ih -28 10 a lvttl input low current i il -50 10 a lvttl output high voltage v oh i oh = 20a 2.4 v cc v lvttl output low voltage v ol i ol = 1ma 0.4 v lvpecl input specifications (refclk ) lvpecl input high voltage v ih v cc - 1.16 v cc - 0.88 v lvpecl input low voltage v il v cc - 1.81 v cc - 1.48 v lvpecl input bias voltage v cc - 1.3 v lvpecl single-ended impedance 1.4 k ? lvpecl differential input voltage swing 300 1900 mv p-p note 1: cml outputs ac-coupled to 100 ? differential load, prbsen = gnd, and sclken = gnd.
max3952 10gbps 16:1 serializer 4 _______________________________________________________________________________________ ac electrical characteristics (v cc = +3v to +3.6v, t a = -40 c to +85 c. typical values are at v cc = +3.3v, differential lvds and cml load = 100 ? , t a = +25 c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units tx data input specifications (pdi [15 0], pclki ) parallel input setup time t su (figure 1) 200 ps parallel input hold time t h (figure 1) 200 ps tx source clock output specifications (pclko ) parallel clock output rise/fall time t r , t f 20% to 80% 100 250 ps parallel clock output duty cycle 45 55 % serial data output specifications (sdo , sclko ) bit-error rate 1 ? 10 -12 serial data output rise/fall time t r , t f 20% to 80% 28 ps serial output clock-to-data delay t ck-q (note 3) -15 +15 ps serial data or clock output random jitter t rj 0.9 ps rms 0 c to +85 c (note 4) 9 serial data output deterministic jitter t dj -40 c to +85 c (note 4) 15 ps p-p 100khz to 10ghz 17 10ghz to 13ghz 10 serial clock or data output return loss rl = -20log|s 22 | 13ghz to 15ghz 7 db tx reference clock input specifications (refclk ) reference clock frequency tolerance -100 +100 ppm reference clock input duty cycle 30 70 % reset input (reset) minimum pulse width of fifo reset ui is pclko period 4 ui tolerated drift between pclki and pclko after reset u i i s p c lko p er i od ; d r i ft i s p c lko cr ossi ng - p c lki cr ossi ng -1 +1 ui note 2: see table 1 for valid operating clock frequencies. ac characteristics are guaranteed by design and characterization. note 3: relative to the falling edge of the sclko. note 4: deterministic jitter includes pattern-dependent jitter and pulse-width distortion. measured with a pattern equivalent to 2 23 - 1 prbs.
max3952 10gbps 16:1 serializer _______________________________________________________________________________________ 5 rclki to sclko jitter transfer max3952 toc01 jitter frequency (hz) jitter transfer (db) 1k 100 -20 -15 -10 -5 0 5 -25 10 10k serial clock output random jitter max3952 toc02 f refclk = 155.52mhz, random jitter = 513fs rms serial clock and data outputs max3952 toc03 sclko sdo 20ps/div supply current vs. temperature max3952 toc04 temperature ( c) supply current (ma) 60 10 310 330 350 370 390 410 430 450 290 -40 110 typical operating characteristics (t a = +25 c, v cc = +3.3v, unless otherwise noted.)
max3952 10gbps 16:1 serializer 6 _______________________________________________________________________________________ pin description pin name function 1, 4, 5, 13, 17, 18, 26, 34, 35, 51, 52, 68 gnd ground 2 refclk+ positive reference clock input, lvpecl 3 refclk- negative reference clock input, lvpecl 6, 9, 12, 25, 43, 60 v cc positive power supply 7 sclko- negative serial clock output, cml. 9.95328ghz or 10.3125ghz 8 sclko+ positive serial clock output, cml. 9.95328ghz or 10.3125ghz 10 sdo- negative serial data output, cml. 9.95328gbps or 10.3125gbps 11 sdo+ positive serial data output, cml. 9.95328gbps or 10.3125gbps 14 sclken control input for disabling sclko output: sclken = gnd ? sclko off sclken = v cc ? sclko active 15 pclko+ positive source clock output. lvds, 622mhz or 644mhz. clocks the mac. 16 pclko- negative source clock output. lvds, 622mhz or 644mhz. clocks the mac. 19, 21, 23, 27, 29, 31, 36, 38, 40, 44, 46, 48, 54, 56, 58, 61 pdi15+ to pdi0+ positive parallel data inputs, lvds. pdi15+ is msb 20, 22, 24, 28, 30, 32, 37, 39, 41, 45, 47, 49, 55, 57, 59, 62 pdi15- to pdi0- negative parallel data inputs, lvds. pdi15- is msb 33 reset 16 x 4-bit fifo reset input, ttl, active high 42 prbsen prbs pattern generator enable input, ttl, active high 50 fifo_error fifo error, ttl, active high 53 lock pll lock indicator, ttl, active high 63 pclki+ positive parallel clock input, lvds 64 pclki- negative parallel clock input, lvds 65 ckset reference clock programming pin. programming instructions in table 1. 66 fil filter capacitor input pin 67 v cc_ vco loop filter and vco positive power supply
detailed description the max3952 converts 16-bit-wide, 622mbps/644mbps data to 9.95gbps/10.3gbps serial data (figures 3 and 4). data is loaded into the 16:1 mux through a 16 x 4 fifo buffer for wide tolerance to clock skew. clock and data inputs are lvds levels, and high-speed serial out- puts are current-mode logic (cml). an internal pll fre- quency synthesizer generates a serial clock from a low-speed reference clock. low-voltage differential-signal inputs and outputs the max3952 has lvds inputs for interfacing with high-speed digital circuitry. this technology uses 250mv to 400mv differential low-voltage swings to achieve fast transition times, minimal power dissipation, and noise immunity. for proper operation, the parallel clock lvds outputs (pclko) require 100 ? differential dc terminations between the positive and negative out- puts. do not terminate these outputs to ground. the parallel data and parallel clock lvds inputs (pdi_+, pdi_-, pclki+, pclki-) are internally terminated with a 100 ? differential input resistance and therefore do not require external termination. lvpecl inputs the reference clock (refclk) has lvpecl inputs for interfacing to a crystal oscillator using ac- or dc-coupling. the refclk inputs are self-biasing to v cc - 1.3v for ac-coupled inputs. only a 100 ? differ- ential termination resistance must be added when inputs are ac-coupled. current-mode logic outputs the high-speed data and clock outputs (sdo, sclko) of the max3952 are designed using cml. the cml outputs include internal 50 ? back termination to v cc . these outputs are intended to drive a 50 ? transmission line terminated with a matched load impedance. for detailed instructions on how to inter- face with lvds, pecl, and cml, refer to hfan-01.0: introduction to lvds, pecl, and cml. fifo buffer data is latched into the max3952 by the parallel input clock (pclki). the parallel input clock is the fifo write clock. the parallel output clock (pclko) is the fifo read clock that loads the 16:1 mux. the fifo allows the read and write clock to vary by up to 1ui (unit interval). this specification makes the max3952 noncompliant with the ieee802.3ae standard, as this standard requires a tolerance of 14ui. conditions that result in the read and write clock accessing the same fifo address are indicated by fifo_error. to clear this condition, assert reset high for at least 4ui. fifo_error can be connected directly to the reset input to clear timing errors. after reset, the full elastic range of the fifo is available again. frequency synthesizer the pll synthesizes a 9.95ghz/10.31ghz clock from an external reference clock. the pll reference clock (refclk) can be programmed as 622mhz/644mhz or 155mhz/161mhz using the ckset pin. see table 1 for ckset settings. the parallel output clock (pclko) is derived from the synthesizer and is sclko 16. a ttl-compatible loss-of-lock indicator (lock), asserts low when the vco is unable to lock to the refer- ence frequency. this pin can be used to directly drive an led. if jitter on the refclk input is present, an error with respect to the divided down sclko frequen- cy of 500ppm will be indicated by a low state on lock. internal pattern generator the max3952 includes a sonet-compliant internal pat- tern generator capable of a 2 7 - 1 prbs pattern. connecting the prbsen pin to v cc enables the pattern generator. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies and keep ground connections short. use multiple vias where possible. use controlled impedance transmission lines to inter- face with the max3952 clock and data inputs and out- puts. give special consideration to filtering the v cc _vco pin; all other power supplies can be con- nected through a common filter. exposed pad (ep) package the ep 68-pin qfn incorporates features that provide a very low thermal resistance path for heat removal from the ic to a pc board. the max3952 s exposed paddle must be soldered directly to a ground plane with good thermal conductance. refer to hfan-08.1: thermal considerations of qfn and other exposed-paddle packages. max3952 10gbps 16:1 serializer _______________________________________________________________________________________ 7 reference clock frequency (mhz) ckset pin setting serial clock frequency (ghz) 622.08 open 9.95 644.53 v cc 10.3 155.52 gnd 9.95 161.13 30k ? to gnd 10.3 table 1. setting refclk frequency
max3952 chip information transistor count:8400 process: sige bipolar 10gbps 16:1 serializer 8 _______________________________________________________________________________________ 1.608ns t su t h 622mhz clock (pclki) 622mbps data (pdi) figure 1. setup and hold time max3952 pclki+ lvds cml cml lvpecl lock sclken ckset fil vcc_vco 0 1 16 16 clk data 16-bit reg pclki- pdi+[15...0] lvds pdi-[15...0] prbsen sis refclk+ refclk- 16 x 4-bit fifo write read 16:1 mux reset fifo-error prbs generator frequency generator sdo+ sdo- sclko+ sclko- pclko+ pclko- lvds 16 16 16 figure 3. functional diagram 100.47ps t clk-q 9.953ghz clock (sclko) 9.953gbps data (sdo) figure 2. definition of clock to q
max3952 10gbps 16:1 serializer _______________________________________________________________________________________ 9 62 63 64 65 66 58 59 60 61 67 41 42 43 44 45 46 47 48 49 50 sdo+ pdi15- v cc _vco qfn* top view fil ckset pclki- pclki+ v cc pdio- pdio+ pdi1- pdi1+ 56 57 52 53 54 55 pdi2- pdi2+ pdi3- pdi3+ lock gnd pdi15+ pdi14- pdi14+ pdi13- pdi13+ gnd v cc pdi12- pdi12+ pdi11- pdi11+ pdi10- pdi10+ gnd reset fifo_error pdi4- pdi4+ pdi5- pdi5+ pdi6- pdi6+ pdi7- pdi7+ pdi8- 35 36 37 38 39 40 pdi8+ pdi9- pdi9+ v cc prbsen gnd sdo- sclko+ sclko- gnd v cc pclko+ pclko- sclken gnd vcc v cc refclk- refclk+ 51 gnd gnd gnd gnd 68 gnd gnd 24 23 22 21 20 28 27 26 25 19 30 29 34 33 32 31 18 11 10 9 8 7 6 5 4 3 2 17 16 *exposed pad is connected to gnd. 15 14 13 12 1 max3951 pin configuration serial output data (sdo) note: signals shown are differential. for example, pclko = (pclko+) - (pclko-). *pdi15 = d15; pdi14 = d14 ... pdio = do. this figure is not intended to show a specific timing relationship between parallel input data and serial output data. parallel input data (pdi_) valid parallel data* pclki pclko t su t h d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 d12 d13 d14 *d15 figure 4. parallel and serial data timing
max3952 10gbps 16:1 serializer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max3952 part number table notes: see the max3952 quickview data sheet for further information on this product family or download the max3952 full data sheet (pdf, 304kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis MAX3952EGK-Td -40c to +85c rohs/lead-free: no max3952egk-d qfn;68 pin;10x10x0.9mm dwg: 21-0103d (pdf) use pkgcode/variation: g6800-1f * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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