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agilent HDMP-0422 single port bypass circuit with cdr & data valid detection capability for fibre channel arbitrated loops data sheet features ? supports 1.0625 gbd fibre channel operation ? supports 1.25 gbd gigabit ethernet (ge) operation ? single pbc/cdr in one package ? cdr location determined by choice of cable input/output ? amplitude valid and data valid detection (fibre channel rate only) on fm_node[0] input ? equalizers on all inputs ? high-speed lvpecl i/o ? buffered line logic (bll) outputs (no external bias resistors required) ? 0.46 w typical power at v cc = 3.3 v ? 24 pin, low-cost ssop package applications ? raid, jbod, bts cabinets ? one 2:1 muxes ? one 1:2 buffers ?1 3 n gigabit serial buffer ?n 3 1 gigabit serial mux description the HDMP-0422 is a single port bypass circuit (pbc) with clock and data recovery (cdr) capability included. this integrated circuit provides a low-cost, low- power physical-layer solution for fibre channel arbitrated loop (fc-al) disk array configurations. by using a pbc such as the hdmp- 0422, hard disks may be pulled out or swapped while other disks in the array are available to the system. a pbc consists of multiple 2:1 multiplexers daisy chained along with a cdr. each port has two modes of operation: disk in loop and disk bypassed. when the disk in loop mode is selected, the loop goes into and out of the disk drive at that port. for example, data goes from the HDMP-0422s to_node[n] differential output pins to the disk drive transceiver ics (e.g. an hdmp-1636a) rx differential input pins. data from the disk drive transceiver ics tx differential outputs goes to the HDMP-0422s fm_node[n] differential input pins. figures 2 and 3 show connection diagrams for disk drive array applications. when the disk bypassed mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. the disk bypassed mode is enabled by pulling the bypass[n]- pin low. leave bypass[n]- floating to enable the disk in loop mode. HDMP-0422s may be cascaded with other members of the hdmp-04xx/hdmp-05xx family through the appropriate fm_node[n] and to_node[n] pins to accommodate any number of hard disks (see figure 4). the unused cells in the HDMP-0422 may be bypassed by using pulldown resistors on the bypass[n]- pins for these cells. an HDMP-0422 may also be used as two 1:1 buffers, one with a cdr and one without. for example, an HDMP-0422 may be placed in front of a cmos asic to clean the jitter of the outgoing signal (cdr path) and to better read the incoming signal (non-cdr paths). in addition, the HDMP-0422 may be configured as one 2:1 multiplexers or as one 1:2 buffers. caution: as with all semiconductor ics, it is advised that normal static precautionsb be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (esd). HDMP-0422
2 figure 1. block diagram of HDMP-0422. training controls. it does this by continually frequency locking onto the 106.25 mhz reference clock (refclk) and then phase locking onto the input data stream. once bit locked, the cdr generates a high-speed sampling clock. this clock is used to sample or repeat the incoming data to produce the cdr output. the cdr jitter specifications listed in this data sheet assume an input that has been 8b/10b encoded. the cdr will also lock onto data encoded using other algorithms as long as there is dc balance and a sufficient number of transitions. refclk input the lvttl refclk input provides a reference oscillator for frequency acquisition of the cdr. the refclk frequency should be within 100 ppm of one-tenth of the incoming data rate in baud (106.25 mhz 100 ppm for fc- al running at 1.0625 gbd). bll output all to_node[n] high-speed differential outputs are driven by a buffered line logic (bll) circuit that has on-chip source termination, so no external bias resistors are required. the bll outputs on the HDMP-0422 are of equal strength and can drive lengthy fr-4 pcb trace. unused outputs should not be left unconnected. ideally, unused outputs should have their differential pins shorted together with a short pcb trace. if longer traces or transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate the HDMP-0422 design allows for cdr placement at any location with respect to a hard disk slot. for example, if hard disk a is connected to pbc cell 1, while bypass[0]- is left to float high (see figure 2), the cdr function will be performed before entering the hard disk at slot a. to obtain a cdr function after slot a (see figure 3), connect hard disk a to pbc cell 0, while floating bypass[1]- high. refer to table 1 for both pin connections. cdr the clock and data recovery (cdr) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. an automatic locking feature allows the cdr to lock onto the input data stream without external av cdr cpll 1 0 bypass[0] 1 0 to_node[0] fm_node[0] bll equ ttl bypass[1] to_node[1] fm_node[1] bll equ ttl 0 1 ttl fm_node[0]_av dv fm_node[0]_dv ttl refclk ttl mode_dv ttl
3 resistor. the value of the termination resistor should match the pcb trace differential impedance. equ input all fm_node[n] high-speed differential inputs have an equalization (equ) buffer to offset the effects of skin loss and dispersion on pcbs. an external termination resistor is required across all high-speed inputs. the value of the termination resistor should match the pcb trace differential impedance. alternatively, instead of a single resistor, two resistors in series, with an ac ground between them, can be connected differentially across the fm_node[n] inputs. the latter configuration attenuates high-frequency common mode noise. bypass[n]- input the active low bypass[n]- inputs control the data flow through the HDMP-0422. all bypass pins are lvttl and contain internal pull-up circuitry. to bypass a port, the appropriate bypass[n]- pin should be connected to gnd through a 1 k w resistor. otherwise, the bypass[n]- inputs should be left to float, as the internal pull-up circuitry will force them high. fm_node[0]_dv output the data valid (dv) block detects if the incoming data at fm_node[0] is valid fibre channel data. the dv block checks for sufficient k28.5+ characters (per fibre channel framing rules) and for run length violations (per 8b/10b encoding) on the data coming out of the cdr. the fm_node[0]_dv output is pulled low if a run length violation (rlv) occurs, or if there are no commas detected (ncd) over a specific time interval. it is pulled high if no errors are detected. a rlv error is defined as any consecutive sequence of 1s or 0s greater than five in the serial bit stream. an ncd error indicates the absence of the seven-bit pattern (0011111) present in the positive disparity comma (k28.5+) character. a k28.5+ character should occur at the beginning of every fibre channel frame of 2148 bytes (or 21480 serial bits), as well as many times within and between frames. if this seven-bit pattern is not found within a 215 bit (~31 m s) interval, an ncd error is generated. a counter within the chip tracks the 2 15 bit intervals. any rlv and ncd errors are stored during the 2 15 bit interval. the fm_node[0]_dv output is pulled low at the start of the 2 15 bit interval after errors are detected. once low, fm_node[0]_dv remains in that state until an entire 2 15 bit interval has no rlv or ncd errors. at the start of the 2 15 bit interval subsequent to no rlv or ncd errors being detected, fm_node[0]_dv is pulled high. mode_dv input the active high data valid mode input selects fibre channel data checking of the fm_node[0] inputs. this is accomplished by having mode_dv override the bypass[0]- control (see figure 1), thereby forcing the data into the cdr to come from the fm_node[0] inputs. the mode_dv pin is an lvttl input and contains internal pull-up circuitry. to select data valid mode, float mode_dv high. otherwise, mode_dv should be connected to gnd through a 1 k w resistor. when mode_dv is high, the user is able to use the bypass[0]- input to bypass invalid fibre channel data from the rest of the loop. for example, if fm_node[0]_dv is connected to the bypass[0]- input, data from the cdr will only be routed to to_node[1] if the data has no rlv or ncd errors. if the dv block detects errors, the signal at to_node[0] will be routed to the to_node[1] outputs (see figure 5). fm_node[0]_av output the amplitude valid (av) block detects if the incoming data on fm_node[0] is valid by examining the differential amplitude of that input. the incoming data is considered valid, and fm_node[0]_av is driven high, as long as the amplitude is greater than 400 mv (differential peak-to-peak). fm_node[0]_av is driven low as long as the amplitude of the input signal is less than 100 mv (differential peak-to-peak). when the amplitude of the input signal is between 100-400 mv (differential peak-to-peak), the fm_node[0]_av output is undefined. table 1. pin connection diagram to achieve desired cdr location (see figures 2, 3) hard disks a a connection to pbc cells 1 0 cdr position (x) xa ax cell connected to cable 0 1 x denotes cdr position with respect to hard disks.
4 figure 2. connection diagram for cdr at first cell. figure 3. connection diagram for cdr at last cell. av cdr cpll 1 0 bypass[0]?= high (float) 1 0 bll equ ttl bll equ ttl 0 1 ttl fm_node[0]_av dv fm_node[0]_dv ttl refclk ttl mode_dv = low ttl to_node[0] = to_loop fm_node[0] = fm_loop bypass[1] to_node[1] fm_node[1] hard disk a serdes av cdr cpll 1 0 bypass[0]? 1 0 bll equ ttl bll equ ttl 0 1 ttl fm_node[0]_av dv fm_node[0]_dv ttl refclk ttl mode_dv = low ttl to_node[0] fm_node[0] bypass[1]?= high (float) to_node[1] = to_loop fm_node[1] = fm_loop hard disk a serdes
5 figure 4. connection diagram for multiple HDMP-0422s. cdr cpll 1 0 bypass[0]? 1 0 bll equ ttl bll equ ttl 0 1 dv fm_node[0]_dv ttl refclk ttl mode_dv = low ttl to_node[0] fm_node[0] bypass[1]?= high (float) to_node[1] = to_loop fm_node[1] hard disk a serdes cdr cpll 1 0 bypass[0]?= high (float) 1 0 bll equ ttl bll equ ttl 0 1 dv fm_node[0]_dv ttl refclk ttl mode_dv = low ttl to_node[0] fm_node[0] = fm_loop bypass[1] to_node[1] fm_node[1] hard disk a serdes
6 figure 5. connection diagram for bypassing invalid fibre channel data. i/o type definitions i/o type definition i-lvttl lvttl input o-lvttl lvttl output hs_out high speed output, lvpecl compatible hs_in high speed input c external circuit node s power supply or ground av cdr cpll 1 0 bypass[0]? 1 0 bll equ ttl bll equ ttl 0 1 ttl fm_node[0]_av dv fm_node[0]_dv ttl refclk ttl mode_dv = high (float) ttl to_node[0] = to_loop fm_node[0] = fm_loop bypass[1] to_node[1] fm_node[1] hard disk a serdes
7 pin definitions pin name pin pin type pin description to_node[0]+ 20 hs_out serial data outputs: high-speed outputs to a hard disk drive or to a cable. to_node[0]- 21 to_node[1]+ 05 to_node[1]- 04 fm_node[0]+ 23 hs_in serial data inputs: high-speed inputs from a hard disk drive or from a cable. fm_node[0]- 24 fm_node[1]+ 02 fm_node[1]- 01 bypass[0]- 17 i-lvttl bypass inputs: for disk bypassed mode, connect bypass[n]- to gnd through bypass[1]- 08 a 1 k w resistor. for disk in loop mode, float high. refclk 14 i-lvttl reference clock: a user-supplied clock reference used for frequency acquisition in the clock and data recovery (cdr) circuit. cpll1 12 c loop filter capacitor: a loop filter capacitor for the internal clock and data cpll0 13 recovery (cdr) circuit must be connected across the cpll1 and cpll0 pins. recommended value is 0.1 m f. fm_node[0]_dv 09 o-lvttl data valid: indicates fibre channel compliant data on fm_node[n] inputs when high. indicates either a run length violation or a no comma detected error when low. mode_dv 11 i-lvttl data valid mode: to allow data valid detection, float mode_dv high. otherwise, connect to gnd through a 1 k w resistor. fm_node[0]_av 16 o-lvttl amplitude valid: indicates acceptable signal amplitude on the fm_node[n] inputs. if (fm_node[n]+ C fm_node[n]-) >= 400 mv peak-to-peak, fm_node[0]_av = 1 if 400 mv > (fm_node[n]+ C fm_node[n]-) > 100 mv, fm_node[0]_av = undefined if 100 mv >= (fm_node[n]+ C fm_node[n]-), fm_node[0]_av = 0 gnd 06 s ground: normally 0 v. see figure 13 for recommended power supply filtering. 07 18 19 v cc a15s analog power supply: normally 3.3 v. used to provide a clean supply to the clock and data recovery (cdr) circuit. see figure 13 for recommended power supply filtering. v cc hs[0] 22 s high speed supply: normally 3.3 v. used only for high-speed outputs v cc hs[1] 03 s (to_node[n]). see figure 13 for recommended power supply filtering. v cc 10 s logic power supply: normally 3.3 v. used for internal logic. see figure 13 for recommended power supply filtering.
8 dc electrical specifications v cc = 3.15 v to 3.45 v. symbol parameter units min. typ. max. v ih,lvttl lvttl input high voltage range v 2.0 v il,lvttl lvttl input low voltage range v 0.8 v oh,lvttl lvttl output high voltage range, i oh = -400 m a v 2.2 v cc v ol,lvttl lvttl output low voltage level, i ol = 1 ma v 0 0.6 i ih,lvttl input high current (magnitude), v in = 2.4 v, v cc = 3.45 v m a40 i il,lvttl input low current (magnitude), v in = 0.4 v, v cc = 3.45 v m a C600 i cc total supply current, t a = 25 c ma 140 ac electrical specifications v cc = 3.15 v to 3.45 v. symbol parameter units min. typ. max. t loop_lat total loop latency from fm_node[0] to to_node[0] ns 3.0 t cell_lat per cell latency from fm_node[1] to to_node[0] ns 2.0 t r,lvttlin input lvttl rise time requirement, 0.8 v to 2.0 v ns 2.0 t f,lvttlin input lvttl fall time requirement, 2.0 v to 0.8 v ns 2.0 t r,lvttlout output ttl rise time, 0.8 v to 2.0 v, 10 pf load ns 1.7 3.3 t f,lvttlout output tll fall time, 2.0 v to 0.8 v, 10 pf load ns 1.7 2.4 t rs,hs_out hs_out single-ended rise time, 20% to 80% ps 200 300 t fs,hs_out hs_out single-ended fall time, 20% to 80% ps 200 300 t rd,hs_out hs_out differential rise time, 20% to 80% ps 200 300 t fd,hs_out hs_out differential fall time, 20% to 80% ps 200 300 v ip,hs_in hs_in required pk-pk differential input voltage mv 200 1200 2000 v op,hs_out hs_out pk-pk differential output voltage (z0 = 75 w , figure 10) mv 1100 1400 2000 absolute maximum ratings t a = 25oc, except as specified. operation in excess of any of these conditions may result in permanent damage to this device. continuous operation at these minimum or maximum ratings is not recommended. symbol parameter units min. max. v cc supply voltage v C0.5 4.0 v in,lvttl lvttl input voltage v C0.5 v cc + 0.5 [1] v in,hs_in hs_in input voltage (differential) mv 200 2000 i o,lvttl lvttl output sink/source current ma 13 t stg storage temperature c C65 +150 t j junction temperature c 0 +125 note: 1. must remain less than or equal to absolute maximum v cc voltage of 4.0 v.
9 guaranteed operating rates v cc = 3.15 v to 3.45 v. fc serial clock rate (mbd) ge serial clock rate (mbd) min. max. min. max. 1,040 1,080 1,240 1,260 cdr reference clock requirements v cc = 3.15 v to 3.45 v. symbol parameter units min. typ. max. f nominal frequency (fibre channel) mhz 106.25 f nominal frequency (gigabit ethernet) mhz 125 f tol frequency tolerance ppm C100 +100 symm symmetry (duty cycle) % 40 60 locking characteristics v cc = 3.15 v to 3.45 v. parameter units max. bit sync time (phase lock) bits 2500 frequency lock at powerup m s 500 figure 6. eye diagram of to_node[1] high speed differential output (50 w termination). note: measurement taken with a 2 7 -1 prbs input to fm_node[0] output jitter characteristics v cc = 3.15 v to 3.45 v. symbol parameter units typ. max. rj [1] random jitter at to_node pins (1 sigma rms) ps 5 dj [1] deterministic jitter at to_node pins (pk-pk) ps 20 note: 1. please refer to figures 7 and 8 for jitter measurement setup information.
10 figure 7. setup for measurement of random jitter. figure 8. setup for measurement of deterministic jitter. jitter measurement configurations hp 70841b pattern generator HDMP-0422 hp 83480a digital communication analyzer hp 70311a clock source clock k28.7 refclk trigger 106.25 mhz 1062.5 mhz ?data 2 ?fm_node[0] bypass-[0] bypass-[1] ?to_node[1] ch 1/2 2 1/10 1.4 v bias tee n/c 106.25 mhz 1 k w hp 70841b pattern generator HDMP-0422 hp 83480a digital communication analyzer hp 70311a clock source clock +k28.5 ?28.5 refclk trigger 106.25 mhz 1062.5 mhz ?data 2 ?fm_node[0] bypass-[0] bypass-[1] ?to_node[1] ch 1/2 2 1/10 1.4 v bias n/c 106.25 mhz 1/2 53.125 mhz 1 k w
11 figure 10. hs_out and hs_in simplified circuit schematic. figure 9. o-lvttl and i-lvttl simplified circuit schematic. simplified i/o cells v bb 1.4 v gnd v cc esd protection gnd v cc o_lvttl i_lvttl gnd esd protection v cc v cc hs_out 0.01 ? 0.01 ? v cc hs gnd esd protection to_node[n] to_node[n]+ gnd fm_node[n]+ fm_node[n] esd protection + + hs_in 2*z0 = 150 w v cc gnd gnd v cc note: 1. fm_node[n] inputs should never be connected to ground as permanent damage to the device may result. z0 = 75 w z0 = 75 w 75 w
12 package information power dissipation and thermal resistance. v cc = 3.15 v to 3.45 v. symbol parameter units typ. max. p d power dissipation mw 460 q jc [1] thermal resistance, junction to case c/w 14 item details package material plastic shrink small outline (ssop) per jesd pub 95, mo-150, var ag lead finish material 85% tin, 15% lead lead finish thickness 200-800 micro-inches lead skew 0.15 mm max lead coplanarity (seating plane) 0.10 mm max mechanical dimensions note: 1. based on independent package testing by agilent. q ja for this device is 57oc/w. q ja is measured on a standard 3x3 fr4 pcb in a still air environment. to determine the actual junction temperature in a given application, use the following equation: t j = t c + ( q ja x p d ), where t c is the case temperature measured on the top center of the package and p d is the power being dissipated. e1 d b pin #1 id e a a1 e dimension a a1 de e1 e b HDMP-0422 2.13 8.20 7.80 5.30 0.65 0.22/ 0.38 tolerance max. ?.30 ?.40 ?.30 bsc min./ max. all dimensions are in millimeters a2 0.25 gage plane c top view 2 3 4 5 6 7 8 9 10 11 12 1 23 22 21 20 19 18 17 16 15 14 13 24 l +0.13/ ?.27 0.90 c 0.09/ 0.20 min./ max. a2 1.75 ?.13 0.05/ 0.25 min./ max. seating plane l figure 11. HDMP-0422 package drawing.
13 figure 12. HDMP-0422 package layout and marking, top view. figure 13. recommended power supply filtering. pin diagram and recommended supply filtering HDMP-0422 2 3 4 5 6 7 8 9 10 11 12 1 23 22 21 20 19 18 17 16 15 14 13 24 gnd gnd v cc v cc v cc capacitors = 0.1 ?, resistor = 10 w (except where noted). gnd gnd gnd v cc 10 ? cpll1 cpll0 HDMP-0422 rz.zz nnnn-nnn s yyww country 2 3 4 5 6 7 8 9 10 11 12 1 23 22 21 20 19 18 17 16 15 14 13 24 mode_dv gnd cpll1 v cc fm_node [1] fm_node [1]+ v cc hs[1] to_node [1] to_node [1]+ gnd bypass[1] fm_node[0]_dv refclk gnd cpll0 v cc a fm_node [0] fm_node [0]+ v cc hs[0] to_node [0] to_node [0]+ bypass[0] fm_node[0]_av sd[0] nnnn-nnn = wafer lot ?build number rz.zz = die revision s = supplier code yyww = date code ( yy = year, ww = work week) country = country of manufacture
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philip- pines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2003 agilent technologies, inc. obsoletes 5988-8561en june 17, 2003 5988-9759en

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