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hd66204 (dot matrix liquid crystal graphic display column driver with 80-channel outputs) description the hd66204f/hd66204fl/hd66204tf/hd 66204tfl, the column driver for a large liquid crystal graphic display, features as many as 80 lcd outputs powered by 80 internal lcd drive circuits. this device latches 4-bit parallel data sent from an lcd controller, and generates lcd drive signals. in standby mode provided by its internal standby function, only one drive circuit operates, lowering power dissipation. the hd66204 has a complete line-up: the hd66204f, a standard device powered by 5 v 10%; the hd66204fl, a 2.7 to 5.5 v, low power dissipation device suitable for battery-driven portable equipment such as ?otebook?personal computers and palm-top personal computers; and the hd66204tf and hd66204tfl, thin package devices powered by 5 v 10% and 2.7 to 5.5 v, respectively. features duty cycle: 1/64 to 1/240 high voltage lcd drive: 10 to 28 v high clock speed 8 mhz max under 5-v operation (hd66204f/hd66204tf) 4 mhz max under 3-v operation (hd66204fl/hd66204tfl) display off function internal automatic chip enable signal generator various lcd controller interfaces lctc series: hd63645, hd64645, hd64646 lvic series: hd66840, hd66841 cline: hd66850 ordering information type no. voltage range package hd66204f 5 v 10% 100-pin plastic qfp (fp-100) hd66204tf 5 v 10% 100-pin thin plastic qfp (tfp-100) HCD66204 5 v 10% chip hd66204fl 2.7 to 5.5 v 100-pin plastic qfp (fp-100) hd66204tfl 2.7 to 5.5 v 100-pin thin plastic qfp (tfp-100) HCD66204l 2.7 to 5.5 v chip
pin arrangement 984 hd66204 hd66204f hd66204fl (fp-100) (top view) y30 y29 y28 y27 y26 y25 y24 y23 y22 y21 y20 y19 y18 y17 y16 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y51 y52 y53 y54 y55 y56 y57 y58 y59 y60 y61 y62 y63 y64 y65 y66 y67 y68 y69 y70 y71 y72 y73 y74 y75 y76 y77 y78 y79 y80 y50 y49 y48 y47 y46 y45 y44 y43 y42 y41 y40 y39 y38 y37 y36 y35 y34 y33 y32 y31 e v1 v3 v4 v ee m cl1 gnd dispoff v cc shl nc nc nc d3 d2 d1 d0 cl2 car 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
hd66204 985 y52 y51 y50 y49 y48 y47 y46 y45 y44 y43 y42 y41 y40 y39 y38 y37 y36 y35 y34 y33 y32 y31 y30 y29 y28 y27 y26 y25 y24 y23 y22 y21 y20 y19 y18 y17 y16 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y53 y54 y55 y56 y57 y58 y59 y60 y61 y62 y63 y64 y65 y66 y67 y68 y69 y70 y71 y72 y73 y74 y75 y76 y77 y78 y79 y80 e v1 v3 v4 v ee m cl1 gnd dispoff v cc shl d3 d2 d1 d0 cl2 nc nc nc car y1 y2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 hd66204tf hd66204tfl (tfp-100) (top view)
pin description symbol pin no. (fp-100/tfp-100) pin name input/output classification v cc 40/38 v cc power supply gnd 38/36 gnd power supply v ee 35/33 v ee power supply v1 32/30 v1 input power supply v3 33/31 v3 input power supply v4 34/32 v4 input power supply cl1 37/35 clock 1 input control signal cl2 49/44 clock 2 input control signal m 36/34 m input control signal d0?3 48?5/43?0 data 0?ata 3 input control signal shl 41/39 shift left input control signal e 31/29 enable input control signal car 50/48 carry output control signal dispoff 39/37 display off input control signal y1?80 51?00, 1?0/49?00, 1?8 y1?80 output lcd drive output nc 42, 43, 44/45, 46, 47 no connection 986 hd66204
pin functions power supply v cc , v ee , gnd: v cc ?nd supplies power to the internal logic circuits. v cc ? ee supplies power to the lcd drive circuits. v1, v3, v4: supply different levels of power to drive the lcd. v1 and v ee are selected levels, and v3 and v4 are non-selected levels. see figure 1. control signal cl1: inputs display data latch pulses for the line data latch circuit. the line data latch circuit latches display data input from the 4-bit latch circuit, and outputs lcd drive signals corresponding to the latched data, both at the falling edge of each cl1 pulse. cl2: inputs display data latch pulses for the 4-bit latch circuit. the 4-bit latch circuit latches display data input via d0?3 at the falling edge of each cl2 pulse. m: changes lcd drive outputs to ac. d0?3: input display data. high-voltage level of data corresponds to a selected level and turns an lcd pixel on, and low-voltage level data cor- responds to a non-selected level and turns an lcd pixel off. shl: shifts the destinations of display data output. see figure 2. e : a low e enables the chip, and a high e disables the chip. car : outputs the e signal to the next hd66204 if hd66204s are connected in cascade. dispoff : a low dispoff sets lcd drive outputs y1?80 to v1 level. lcd drive output y1?80: each y outputs one of the four voltage levels v1, v3, v4, or v ee , depending on a combination of the m signal and display data levels. see figure 3. nc: must be open. hd66204 987 figure 1 different power supply voltage levels for lcd drive circuits v1 v3 v4 v ee
figure 2 selection of destinations of display data output figure 3 selection of lcd drive output level 988 hd66204 y1 y2 y3 y4 y5 y6 y7 y8 y73 y74 y75 y76 y77 y78 y79 y80 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d0 d1 d2 d3 1st 2nd last shl = high y1 y2 y3 y4 y5 y6 y7 y8 y73 y74 y75 y76 y77 y78 y79 y80 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 last 1st shl = low 2nd 10 0 11 0 v ee v4 v1 v3 m d y output level
block functions lcd drive circuit controller: the controller generates the latch signal at the falling edge of each cl2 pulse for the 4-bit latch circuit. 4-bit latch circuit the 4-bit latch circuit latches 4-bit parallel data input via the d 0 to d 3 pins at the timing generated by the control circuit. line data latch circuit the 80-bit line data latch circuit latches data input from the 4-bit latch circuit, and outputs the latched data to the level shifter, both at the falling edge of each clock 1 (cl1) pulse. level shifter the level shifter changes 5-v signals into high- voltage signals for the lcd drive circuit. lcd drive circuit the 80-bit lcd drive circuit generates four volt- age levels v1, v3, v4, and v ee , for driving an lcd panel. one of the four levels is output to the corresponding y pin, depending on a combination of the m signal and the data in the line data latch circuit. hd66204 989 block diagram lcd drive circuit level shifter line data latch circuit 4-bit latch circuit 4-bit latch circuit controller y1?80 d0?3 cl1 m dispoff cl2 shl e car v1 v3 v4 v ee
comparison of the hd66204 with the hd61104 item hd66204 hd61104 clock speed 8.0 mhz max. 3.5 mhz max. display off function provided not provided lcd drive voltage range 10 to 28 v 10 to 26 v relation between shl and see figure 4 see figure 4 lcd output destinations relation between lcd output see figure 5 see figure 5 levels, m, and data lcd drive v pins v1, v3, v4 v1, v2, v3, v4 (v2 level is the same as v ee level) figure 4 relation between shl and lcd output destinations for the hd66204 and hd61104 figure 5 relation between lcd output levels, m, and data for the hd66204 and hd61104 990 hd66204 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 y1 y2 y3 y4 y5 y6 y7 y8 2nd 1st shl = low d0 d1 d2 d3 d0 d1 d2 d3 y73 y74 y75 y76 y77 y78 y79 y80 last d0 d1 d2 d3 d3 d2 d1 d0 d3 d2 d1 d0 y1 y2 y3 y4 y5 y6 y7 y8 2nd last shl = low d3 d2 d1 d0 d3 d2 d1 d0 y73 y74 y75 y76 y77 y78 y79 y80 1st d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 y1 y2 y3 y4 y5 y6 y7 y8 2nd 1st shl = high d0 d1 d2 d3 d0 d1 d2 d3 y73 y74 y75 y76 y77 y78 y79 y80 last d0 d1 d2 d3 d3 d2 d1 d0 d3 d2 d1 d0 y1 y2 y3 y4 y5 y6 y7 y8 2nd last shl = high d3 d2 d1 d0 d3 d2 d1 d0 y73 y74 y75 y76 y77 y78 y79 y80 1st hd61104 hd66204 note the exact reverse relation for the two devices. hd61104 m d 1 0 1 0 1 0 v ee v4 v1 v3 y output level hd66204 v1 v3 v2 v4 y output level m d 1 0 1 0 1 0
operation timing hd66204 991 123 192021 cl2 hd66204 no. 1 latches data hd66204 no. 2 latches data hd66204 no. 3 latches data hd66204 no. n latches data data 0 data 3 cl1 car (no. 1) car (no. 2) car (no. 3) car (no. n) line y1Cy80
application example 992 hd66204 car dispoff d0Cd3 m cl2 cl1 v4 v3 v1 v ee gnd v cc e shl hd66204 (8) v cc car dispoff d0Cd3 m cl2 cl1 v1 gnd v cc e shl hd66204 (2) v cc car y1Cy80 dispoff d0Cd3 m cl2 cl1 v4 v3 v1 shl hd66204 (1) v cc hd66205 (1) x1Cx80 shl di do m v cc gnd cl v ee v6 v5 v1 dispoff hd66205 (3) shl di do m v cc gnd cl v ee v6 v5 v1 dispoff com1 com2 com3 com239 com240 lcd panel of 640 240 dots; 1/240 duty cycle seg640 seg639 seg638 seg3 seg2 seg1 + e + e + e + e v ee r1 r1 r2 r1 r1 v cc gnd m dispoff d0Cd3 cl2 cl1 flm lcd controller v ee gnd v cc e the resistances of r1 and r2 depend on the type of the lcd panel used. for example, for an lcd panel with a 1/15 bias, r1 and r2 must be 3 k w and 33 k w , respectively. that is, r1/(4r1 + r2) should be 1/15. to stabilize the power supply, place two 0.1- m f capacitors near each lcd driver: one between the v cc and gnd pins, and the other between the v cc and v ee pins. notes: 1. 2. v cc v cc x1ex80 y1ey80 v4 v3 v ee y1ey80
absolute maximum ratings item symbol rating unit notes power supply voltage for logic circuits v cc ?.3 to +7.0 v 1 power supply voltage for lcd drive circuits v ee v cc ?30.0 to v cc + 0.3 v input voltage 1 v t1 ?.3 to v cc + 0.3 v 1, 2 input voltage 2 v t2 v ee ?0.3 to v cc + 0.3 v 1, 3 operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? notes: 1. the reference point is gnd (0 v). 2. applies to pins cl1, cl2, m, shl, e , d 0 ? 3 , dispoff . 3. applies to pins v1, v3, and v4. 4. if the lsi is used beyond its absolute maximum ratings, it may be permanently damaged. it should always be used within its electrical characteristics in order to prevent malfunctioning or degradation of reliability. electrical characteristics dc characteristics for the hd66204f/hd66204tf (v cc = 5 v 10%, gnd = 0 v, v cc ?v ee = 10 to 28 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min typ max unit condition notes input high voltage v ih 1 0.7 v cc ? cc v input low voltage v il 1 0 0.3 v cc v output high voltage v oh 2v cc ?0.4 v i oh = ?.4 ma output low voltage v ol 2 0.4 v i ol = 0.4 ma vi?j on resistance r on 3 4.0 k w i on = 100 m a1 input leakage current 1 i il1 1 ?.0 1.0 m av in = v cc to gnd input leakage current 2 i il2 4 ?5 25 m av in = v cc to v ee current consumption 1 i gnd 3.0 ma f cl2 = 8.0 mhz 2 f cl1 = 20 khz v cc ?v ee = 28 v current consumption 2 i ee 150 500 m a same as above 2 current consumption 3 i st 200 m a same as above 2, 3 pins and notes on next page. hd66204 993
dc characteristics for the hd66204fl/hd66204tfl (v cc = 2.7 to 5.5 v, gnd = 0 v, v cc ?v ee = 10 to 28 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min max unit condition notes input high voltage v ih 1 0.7 v cc v cc v input low voltage v il 1 0 0.3 v cc v output high voltage v oh 2v cc ?0.4 v i oh = ?.4 ma output low voltage v ol 2 0.4 v i ol = 0.4 ma vi?j on resistance r on 3 4.0 k w i on = 100 m a1 input leakage current 1 i il1 1 ?.0 1.0 m av in = v cc to gnd input leakage current 2 i il2 4 ?5 25 m av in = v cc to v ee current consumption 1 i gnd 1.0 ma f cl2 = 4.0 mhz 2 f cl1 = 16.8 khz f m = 35 hz v cc = 3.0 v v cc ?v ee = 28 v checker-board pattern current consumption 2 i ee 500 m a same as above 2 current consumption 3 i st 50 m a same as above 2, 3 pins: 1. cl1, cl2, m, shl, e , d 0 ? 3 , dispoff 2. car 3. y1?80, v1, v3, v4 4. v1, v3, v4 notes: 1. indicates the resistance between one pin from y1?80 and another pin from v1, v3, v4, and v ee , when load current is applied to the y pin; defined under the following conditions. v cc ?gnd = 28 v v1, v3 = v cc ?{2/10(v cc ?v ee )} v4 = v ee + {2/10(v cc ?v ee )} v1 and v3 should be near v cc level, and v4 should be near v ee level (figure 6). all voltage must be within d v. d v is the range within which r on , the lcd drive circuits?output impedance, is stable. note that d v depends on power supply voltage v cc ? ee (figure 7). 2. input and output current is excluded. when a cmos input is floating, excess current flows from the power supply through the input circuit. to avoid this, v ih and v il must be held to v cc and gnd levels, respectively. 3. applies to standby mode. 994 hd66204
figure 6 relation between driver output waveform and level voltages figure 7 relation between v cc ?v ee and d v hd66204 995 d v d v v cc v1 v3 v4 v ee 5.6 2.0 10 28 d v (v) v cc e v ee (v) level voltage range
ac characteristics for the hd66204f/hd66204tf (v cc = 5 v 10%, gnd = 0 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min max unit notes clock cycle time t cyc cl2 125 ns clock high-level width t cwh cl1, cl2 45 ns clock low-level width t cwl cl2 45 ns clock setup time t scl cl1, cl2 80 ns clock hold time t hcl cl1, cl2 80 ns clock rise time t r cl1, cl2 * 1ns1 clock fall time t f cl1, cl2 * 1ns1 data setup time t ds d0?3, cl2 20 ns data hold time t dh d0?3, cl2 20 ns enable ( e ) setup time t esu e , cl2 30 ns carry ( car ) output delay time t car car , cl2 80 ns 2 m phase difference time t cm m, cl2 300 ns cl1 cycle time t cl1 cl1 t cyc 50 ns disp off ( dispoff ) rise time t r2 dispoff 200 ns disp off ( dispoff ) fall time t f2 dispoff 200 ns 996 hd66204
ac characteristics for the hd66204fl/hd66204tfl (v cc = 2.7 to 5.5v, gnd = 0 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min max unit notes clock cycle time t cyc cl2 250 ns clock high-level width t cwh cl1, cl2 95 ns clock low-level width t cwl cl2 95 ns clock setup time t scl cl1, cl2 80 ns clock hold time t hcl cl1, cl2 80 ns clock rise time t r cl1, cl2 * 1ns1 clock fall time t f cl1, cl2 * 1ns1 data setup time t ds d0?3, cl2 50 ns data hold time t dh d0?3, cl2 50 ns enable ( e ) setup time t esu e , cl2 65 ns carry ( car ) output delay time t car car , cl2 155 ns 2 m phase difference time t cm m, cl2 300 ns cl1 cycle time t cl1 cl1 t cyc 50 ns disp off ( dispoff ) rise time t r2 dispoff 200 ns disp off ( dispoff ) fall time t f2 dispoff 200 ns notes: 1. t r , t f < (t cyc ?t cwh ?t cwl )/2 and t r , t f 50 ns 2. the load circuit shown in figure 8 is connected. hd66204 997
figure 8 load circuit figure 9 lcd controller interface timing 998 hd66204 30 pf test point cl2 d0?3 cl1 cl2 t r t cwh t f t cwl t cyc t ds t dh t cwh t scl t hcl last data t car t esu 0.8v cc car e 0.7v cc 0.3v cc 0.7v cc 0.3v cc 0.7v cc 0.3v cc 0.7v cc 0.3v cc t cm m 0.3v cc 0.7v cc 0.3v cc t car t cl1 0.2v cc t r2 t f2 0.7v cc 0.3v cc 0.7v cc 0.3v cc dispoff

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