t echnical manual cmos 4 - bit single chip microcomputer s1c63654 technical hardware s1c63654
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revisions and additions for this manual section 1.1 1.5 2.1.5 2.2.2 4.1 4.8.1 4.8.2 4.8.3 4.11.1 4.14.3 4.14.4 4.14.5 4.14.6 (4.15.2) 4.15.2 4.15.3 4.16.1 4.16.4 5.2 7.1 7.2 7.3 a.4.2 page 1 5?8 11 13 18, 21, 23, 24 52 52 57 78 113?114 116?117 118, 120 121 122 122 123 126 128?129 135 140 140 140 160 item features mask option lcd system voltage circuit simultaneous high input to terminals k00?k03 memory map configuration of lcd driver power supply for lcd driving control of lcd display and drive waveform configuration of programmable timer operation of r/f conversion interrupt function i/o memory of r/f converter programming notes mask option svd operation i/o memory of svd circuit interrupt factor i/o memory of interrupt summary of notes by function absolute maximum rating recommended operating conditions dc characteristics differences with the actual ic contents explanation was revised. explanation was revised. figure 2.1.5.1 was revised. explanation was revised. tables 4.1.1(a), (d), (f), (g) were revised. explanation was revised. explanation was revised. explanation was revised. a note was added. explanation was revised. explanation was revised. figures 4.14.3.1?4.14.3.2 were revised. explanation was revised. figures 4.14.4.1?4.14.4.4 were revised. table 4.14.5.1 was revised. explanation was revised. explanation was revised. the section was deleted. explanation was revised. table 4.15.3.1 was revised. explanation was revised. table 4.16.1.1 was revised. tables 4.16.4.1(a), (b) were revised. explanation was revised. table was revised. table was revised. table was revised. explanation was revised. figure was deleted. chapter 1 2 4 5 7 appendix
devices s1 c 63158 f 0a01 packing specifications 00 : besides tape & reel 0a : tcp bl 2 directions 0b : tape & reel back 0c : tcp br 2 directions 0d : tcp bt 2 directions 0e : tcp bd 2 directions 0f : tape & reel front 0g : tcp bt 4 directions 0h : tcp bd 4 directions 0j : tcp sl 2 directions 0k : tcp sr 2 directions 0l : tape & reel left 0m : tcp st 2 directions 0n : tcp sd 2 directions 0p : tcp st 4 directions 0q : tcp sd 4 directions 0r : tape & reel right 99 : specs not fixed specification package d: die form; f: qfp, b: bga model number model name c: microcomputer, digital products product classification s1: semiconductor development tools s5u1 c 63000 a1 1 packing specifications 00: standard packing version 1: version 1 tool type hx : ice ex : eva board px : peripheral board wx : flash rom writer for the microcomputer xx : rom writer peripheral board cx : c compiler package ax : assembler package dx : utility tool by the model qx : soft simulator corresponding model number 63000: common to s1c63 family tool classification c: microcomputer use product classification s5u1: development tool for semiconductor products 00 00 configuration of product number
s1c63654 technical manual epson i contents c ontents chapter 1o utline ________________________________________________ 1 1.1 featur es ......................................................................................................... 1 1. 2b loc k di agram .............................................................................................. 2 1.3 pin layout diagram ..................................................................................... 3 1.4 pin description ............................................................................................. 4 1.5 mask option .................................................................................................. 5 chapter 2p o wer s upply and i nitial r eset ____________________________ 9 2.1 power supply ................................................................................................ 9 2.1.1 voltage regulator for osc1 oscillation cir cuit ......................................... 10 2.1.2 low-speed operation volta ge regul ator .................................................... 10 2.1.3 high-speed operati on voltage re gulator ................................................... 10 2.1.4 internal operating voltage v d1 ....................................................................................... 10 2.1.5 lcd system volta ge circuit ....................................................................... 10 2.1.6 halver mode and saving power ................................................................ 11 2.1.7 analog system power supply ..................................................................... 11 2.2 initial reset .................................................................................................. 12 2.2.1 reset terminal (reset) ............................................................................ 12 2.2.2 simultaneous high input to term inals k00? 03 ...................................... 13 2.2.3 internal register at initial r esetting ........................................................... 13 2.2.4 terminal settings at initial r esetting ......................................................... 14 2.3 test t erminal (test) ................................................................................... 14 chapter 3 cpu, rom, ram ________________________________________ 15 3. 1 cpu .............................................................................................................. 15 3.2 code ro m .................................................................................................... 15 3. 3 ram ............................................................................................................. 15 3.4 data ro m .................................................................................................... 16 chapter 4p eripheral c ircuits and o peration __________________________ 17 4.1 memory map ................................................................................................ 17 4.2 power contr ol .............................................................................................. 25 4.2.1 configuration of pow er supply cir cuit ...................................................... 25 4.2.2 power control procedure ........................................................................... 26 4.2.3 i/o memory for power control .................................................................. 27 4.2.4 progr amming notes ................................................................................... 29 4. 3w at ch do g ti me r ........................................................................................... 30 4.3.1 configuration of watchdog timer .............................................................. 30 4.3.2 interrupt function ...................................................................................... 30 4.3.3 i/o memory of w atchdog tim er ................................................................. 31 4.3.4 progr amming notes ................................................................................... 31 4.4 oscillation ci rc uit ....................................................................................... 32 4.4.1 configuration of oscillation ci r cuit .......................................................... 32 4.4.2 osc1 oscillation cir cuit ............................................................................ 32 4.4.3 osc3 oscillation cir cuit ............................................................................ 33 4. 4. 4 sw itc hi ng of ope ra ti ng vo lta ge ................................................................. 34 4.4.5 clock frequency and instruction execution tim e ....................................... 34 4.4.6 i/o memory of oscillation cir cuit .............................................................. 35 4.4.7 progr amming notes ................................................................................... 36
ii epson s1c63654 technical manual contents 4.5 input ports (k00? 03 and k10? 13) ......................................................... 37 4.5.1 configuration of input ports ..................................................................... 37 4.5.2 interrupt function ...................................................................................... 37 4.5.3 mask option ............................................................................................... 38 4.5.4 i/o memory of input ports ......................................................................... 39 4.5.5 progr amming notes ................................................................................... 41 4.6 output p orts (r00?03) .............................................................................. 42 4.6.1 configuration of output ports ................................................................... 42 4.6.2 mask option ............................................................................................... 42 4.6.3 high impedance control ............................................................................ 43 4.6.4 special output ............................................................................................ 43 4. 6. 5 i/o me mo ry of out put po rts ....................................................................... 45 4.6.6 progr amming notes ................................................................................... 46 4.7 i/o ports (p00?03 and p10?13) ............................................................. 47 4.7.1 configuration of i/o ports ........................................................................ 47 4.7.2 mask option ............................................................................................... 48 4.7.3 i/o control register s and input/out put mode ............................................ 48 4.7.4 pull-down during input mode ................................................................... 48 4.7.5 i/o memory of i/o ports ............................................................................ 49 4.7.6 progr amming not e ..................................................................................... 51 4.8 lcd driver (com0?om5, seg0?eg31) ............................................. 52 4.8.1 configuration of lcd driver .................................................................... 52 4.8.2 power supply for lcd driving .................................................................. 52 4.8.3 control of lcd display and drive waveform ........................................... 52 4.8.4 display memory ......................................................................................... 58 4.8.5 segment option .......................................................................................... 58 4.8.6 lcd contrast adjustment .......................................................................... 60 4.8.7 i/o memory of lcd d river ........................................................................ 61 4.8.8 progr amming not e ..................................................................................... 62 4.9 clock t imer .................................................................................................. 63 4.9.1 configuration of clock tim er ..................................................................... 63 4.9.2 data reading and hold function ................................................................ 63 4.9.3 interrupt function ...................................................................................... 64 4.9.4 i/o memory of clock tim er ........................................................................ 65 4.9.5 progr amming notes ................................................................................... 66 4.10 stopwatch ti mer ........................................................................................... 67 4.10.1 configuration of stopwatc h timer ........................................................... 67 4.10.2 counter and pr escaler ............................................................................. 67 4.10.3 capture buffer and hold func tion ............................................................ 68 4.10.4 stopwatch timer run /stop and r eset ................................................... 69 4.10.5 direct input function and ke y mask ........................................................ 69 4.10.6 interrupt function .................................................................................... 72 4.10.7 i/o memory of stopwatch timer .............................................................. 74 4.10.8 programm ing notes ................................................................................. 77 4.11 programm able time r ................................................................................... 78 4.11.1 configuration of programmabl e timer .................................................... 78 4.11.2 basic count oper ation ............................................................................. 79 4.11.3 setting the input clock ............................................................................. 80 4.11.4 event counter mode (timer 0) ................................................................. 80 4.11.5 pwm mode (timer 0, timer 1) ................................................................. 81 4.11.6 16-bit timer (timer 0 + timer 1) .............................................................. 82 4.11.7 interrupt function .................................................................................... 82 4.11.8 control of t out output .......................................................................... 83 4.11.9 transfer rate setting for serial in terface ................................................ 84 4.11.10 i/o memory of prog r ammable timer ..................................................... 85 4.11.11 programm ing notes ............................................................................... 91
s1c63654 technical manual epson iii contents 4.12 serial interface (sin, sout , sclk, srd y) ................................................ 93 4.12.1 configuration of serial interface ............................................................ 93 4.12.2 mask option ............................................................................................. 94 4.12.3 master mode and slave mode of serial interface .................................... 94 4.12.4 data input/output and interrupt f unction ............................................... 95 4.12.5 i/o memory of seri al int erface ................................................................ 98 4.12.6 program ming notes ................................................................................ 101 4.13 sound g enerator ......................................................................................... 102 4.13.1 configuration of sound gener ator ......................................................... 102 4.13.2 control of b uzzer output ......................................................................... 102 4.13.3 setting of buzzer frequency and sound le vel .......................................... 103 4. 13. 4 di g ita l en vel ope ..................................................................................... 104 4.13.5 one-shot output ...................................................................................... 105 4.13.6 i/o memory of sound gener ator ............................................................. 106 4.13.7 program ming notes ................................................................................ 108 4.14 r/f con verter ............................................................................................... 109 4.14.1 configuration of r/f conve rter ............................................................... 109 4.14.2 connection terminals and cr oscillation circui t .................................. 110 4.14.3 operation of r/f conversion ................................................................... 113 4.14.4 interrupt function ................................................................................... 116 4.14.5 i/o memory of r/f con verter .................................................................. 118 4.14.6 program ming notes ................................................................................ 121 4.15 svd (supply voltage detection) cir cuit ..................................................... 122 4.15.1 configuration of svd circuit ................................................................. 122 4.15.2 svd oper ation ........................................................................................ 122 4.15.3 i/o memory of svd cir cuit ..................................................................... 123 4.15.4 program ming notes ................................................................................ 123 4.16 interrupt and halt .................................................................................... 124 4.16.1 interrupt factor ....................................................................................... 126 4.16.2 interrupt mask ........................................................................................ 127 4.16.3 interrupt vector ...................................................................................... 127 4.16.4 i/o memo ry of interrupt ......................................................................... 128 4.16.5 program ming notes ................................................................................ 130 chapter 5s ummary of n o tes ______________________________________ 131 5.1 notes for low curre nt consump tion .......................................................... 131 5.2 summary of notes by function ................................................................... 132 5.3 precautions on mounting ........................................................................... 137 chapter 6b asic e xternal w iring d iagram ___________________________ 139 chapter 7e lectrical c haracteristics _______________________________ 140 7.1 absolute maximum rating .......................................................................... 140 7.2 recommended operati ng conditi ons ......................................................... 140 7.3 dc char acteristics ..................................................................................... 140 7.4 analog circuit characteris tics and power current consumptio n ............ 141 7.5 oscillation char acteristics ......................................................................... 142 7.6 serial interface ac characteristics ........................................................... 144 7.7 timing chart ............................................................................................... 145 7.8 r/f converter characteristics ..................................................................... 146
iv epson s1c63654 technical manual contents chapter 8p a ckage _______________________________________________ 147 8.1 plastic pack age ........................................................................................... 147 8.2 ceramic packag e for test samples ............................................................. 148 chapter 9p ad l ay out ____________________________________________ 149 9.1 diagram of p ad layout ............................................................................... 149 9.2 pad coordi nates .......................................................................................... 150 appendix p eripheral c ircuit b o ards for s1c63654 ____________________ 151 a.1 names and functions of each p art ............................................................ 151 a.1.1 s5u1c63000p1 ........................................................................................ 151 a.1.2 s5u1c63658p2 ........................................................................................ 154 a.2 connecting to the ta rg et system ................................................................ 155 a.3 downloading to s5u1c63000p1 ............................................................... 158 a.3.1 downloading circuit data 1 ?when new ice (s5u1c63000h2) is used ............................................ 158 a.3.2 downloading circuit data 2 ?when pre vious ice (s5u1c630 00h1) is u sed .................................... 158 a.4 usage precautions ...................................................................................... 159 a.4.1 operational precautions .......................................................................... 159 a.4.2 differences with the actual ic ................................................................. 159 a.5 product specifications ................................................................................ 163 a.5.1 specifications of s5u1c63000p1 ........................................................... 163 a.5.2 specifications of s5u1c63658p2 ........................................................... 163
s1c63654 technical manual epson 1 chapter 1: outline chapter 1o utline the s1c63654 is a microcomputer which has a high-performance 4-bit cpu s1c63000 as the core cpu, rom (4,096 words 13 bits), ram (512 words 4 bits), serial interface, watchdog timer, programmable timer, time base counters (2 systems), an lcd driver that can drive a maximum 32 segments 6 commons, sound generator and r/f converter built-in. the s1c63654 features low current consumption, this makes it suitable for battery driven portable equipment with r/f converter. 1.1 features osc1 oscillation circui t ...................... 32.768 khz (typ.) crystal oscillation circuit osc3 oscillation circui t ...................... 4 mhz (max.) ceramic (2 mhz max. when osc3 is used as the r/f converter operating clock) or 1.1 mhz (typ.) cr oscillation circuit ( ? 1) i nst r uc ti on set ..................................... basic instruction: 46 types (411 instructions with all) addressing mode: 8 types instruction execution time ................... during operation at 32.768 khz: 61 ?ec 122 ?ec 183 ?ec during operation at 4 mhz: 0.5 ?ec 1 ?ec 1.5 ?ec r om capac ity ..................................... code rom: 4,096 words 13 bits data rom: 1,024 words 4 bits ram capacity ...................................... data memory: 512 words 4 bits display memory: 48 words 4 bits input por t ............................................. 8 bits (pull-down resistors may be supplemented ? 1) out put por t .......................................... 4 bits (it is possible to switch the 2 bits to special output ? 2) i/o por t ................................................ 8 b its ( it is possible to switch the 4 bits to serial i/f input/output ? 2) ser ia l in te rf ace .................................... 1 port (8-bit clock synchronous system) lcd driv er ........................................... 32 segments 6, 5, 4 or 3 commons ( ? 2) time base counter .............................. clock timer stopwatch timer (1/1000 sec, with direct key input function) p rog rammable timer ........................... 8-bit pwm 2 ch. or 16-bit pwm 1 ch. ( ? 2) w atchdog tim er ................................... built-in sound gener ator ................................. w ith envelope and 1-shot output functions r /f con ve r ter ....................................... 2 ch., cr oscillation type, 20-bit counter supports resistive humidity sensors supply voltage detection (svd) circuit .. criteria voltage is selectable from 8 types (1.85 to 2.90 v ? 2) e xte r nal in te rr upt ................................ input port interrupt: 2 systems in te r nal in te rr upt ................................. clock timer interrupt: 4 systems stopwatch timer interrupt: 4 systems programmable timer interrupt: 4 systems serial interface interrupt: 1 system r/f converter interrupt: 2 systems po w er supply v oltage .......................... 2.4 to 3.6 v: max. 4 mhz operation in normal mode 2.4 to 3.6 v: 32 khz operation in halver mode 1.8 to 3.6 v: 32 khz operation in normal mode operating temper ature r ange ............. -20 to 70? current consumpti on (typ .) ................ low-speed operation (osc1 = 32 khz crystal oscillation): during halt 3.0 v (lcd on, halver mode) 0.65 ? during operation 3.0 v (lcd on, halver mode) 2.5 ? high-speed operation (osc3 = 4 mhz ceramic oscillation): during operation 3.0 v (lcd on) 800 ? pa ckage .............................................. qfp15-100pin (plastic) or chip ? ?
2 epson s1c63654 technical manual chapter 1: outline 1.2 block diagram osc1 osc2 osc3 osc4 com0~5 seg0~31 v dd v dda v c1 ~ 3 v d1 ~ 2 v osc ca~cd v ss v ssa k00~k03 k10~k13 test bz sen0, sen1, hud ref0, ref1 rfin0, rfin1 rfout reset p00~p03 p10~p13 r00~r03 core cpu s1c63000 rom 4,096 words
s1c63654 technical manual epson 3 chapter 1: outline 1.3 pin layout diagram qfp15-100pin 51 75 26 50 index 25 1 100 76 no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pin name ca cb v c1 v c2 v c3 v ssa rfout rfin0 rfin1 ref0 sen0 ref1 sen1 hud v dda cc cd v d2 v dd v osc osc1 osc2 v d1 osc3 osc4 pin name v ss test reset n.c. n.c. seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 n.c. n.c. n.c. com3 pin name com4 com5 v dd k00 k01 k02 k03 k10 k11 k12 k13 p00 p01 p02 p03 p10 p11 p12 p13 r00 r01 r02 r03 bz v ss pin name n.c. n.c. n.c. n.c. seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 n.c. n.c. com0 com1 com2 n.c. : no connection fi g. 1.3.1 pin layout diagram
4 epson s1c63654 technical manual chapter 1: outline 1.4 pin description t able 1.4.1 pin description pin name v dd v ss v dda v ssa v d1 v d2 v osc v c1 ? c3 ca, cb cc, cd osc1 osc2 osc3 osc4 k00?03 k10?13 p00?03 p10 p11 p12 p13 r00 r01 r02 r03 com0?om5 seg0?eg31 sen0 sen1 ref0 ref1 hud rfin0 rfin1 rfout bz reset test function power (+) supply pin power (? supply pin analog system power (+) supply pin (=v dd ) analog system power (? supply pin (=v ss ) internal logic system regulated voltage output pin 1/2v dd voltage halver output pin oscillation system regulated voltage output pin lcd system power supply pin lcd system voltage booster capacitor connecting pin voltage halver capacitor connecting pin crystal oscillation input pin crystal oscillation output pin ceramic or cr oscillation input pin (selected by mask option) ceramic or cr oscillation output pin (selected by mask option) input port pins input port pins i/o port pins i/o port or serial i/f data input pin (selected by software) i/o port or serial i/f data output pin (selected by software) i/o port or serial i/f clock i/o pin (selected by software) i/o port or serial i/f ready signal output pin (selected by software) output port pin output port pin output port or tout output pin (selected by software) output port or fout output pin (selected by software) lcd common output pin (1/3, 1/4, 1/5 or 1/6 duty is selectable by software) lcd segment output pin r/f converter ch. 0 cr oscillation output pin r/f converter ch. 1 cr oscillation output pin r/f converter ch. 0 reference resistor cr oscillation output pin r/f converter ch. 1 reference resistor cr oscillation output pin r/f converter ac-bias oscillation output pin for humidity sensor r/f converter ch. 0 cr oscillation input pin r/f converter ch. 1 cr oscillation input pin r/f converter oscillation frequency output pin sound output pin initial reset input pin testing input pin i/o i o i o i i i/o i/o i/o i/o i/o o o o o o o o o o o o i i o o i i pin no. 19, 53 26, 75 15 6 23 18 20 3? 1, 2 16, 17 21 22 24 25 54?7 58?1 62?5 66 67 68 69 70 71 72 73 98?00, 50?2 80?5, 31?6 11 13 10 12 14 8 9 7 74 28 27
s1c63654 technical manual epson 5 chapter 1: outline 1.5 mask option mask options shown below are provided for the s1c63654. several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. the function option generator winfog and segment option generator winsog, that have been prepared as the development software tool of s1c63654, are used for this selection. mask pattern of the ic is finally generated based on the data created by winfog and winsog. refer to the "s5u1c63000a manual" for winfog and winsog. (1) osc1 oscillation circuit the osc1 oscillation circuit is fixed at crystal oscillation. refer to section 4.4.2, "osc1 oscillation circuit", for details. (2) osc3 oscillation circuit the osc3 oscillator type can be selected from ceramic oscillation, cr oscillation (external r) and cr oscillation (built-in r). refer to section 4.4.3, "osc3 oscillation circuit", for details. (3) input port pull-down resistor the mask option is used to select whether the pull-down resistor is supplemented to the input ports or not. it is possible to select for each bit of the input ports. refer to section 4.5.3, "mask option", for details. (4) reset terminal pull-down resistor the mask option is used to select whether the pull-down resistor is supplemented to the reset terminal or not. refer to section 2.2.1, "reset terminal (reset)", for details. (5) i/o port pull-down resistor the mask option is used to select whether the pull-down resistor working in the input mode is supplemented to the i/o ports or not. it is possible to select for each bit of the input ports. refer to section 4.7.2, "mask option", for details. (6) output specification of the output port either complementary output or p-channel open drain output can be selected as the output specifica- tion for the output ports r00?03. the selection is done in 1-bit units. refer to section 4.6.2, "mask option", for details. (7) output specification of the i/o port for the output specification when the i/o ports p00?03 and p10?13 are in the output mode, either complementary output or p-channel open drain output can be selected in 1-bit units. refer to section 4.7.2, "mask option", for details. (8) external reset by simultaneous high input to the input port (k00?03) this function resets the ic when several keys are pressed simultaneously. the mask option is used to select whether this function is used or not. further when the function is used, a combination of the input ports (k00?03), which are connected to the keys to be pressed simultaneously, can be selected. refer to section 2.2.2, "simultaneous high input to terminals k00?03", for details. (9) time authorize circuit for the simultaneous high input reset function when the external reset function (shown in 8 above) is used, the time authorize circuit is enabled. the r eset function works only when the input time of simultaneous low is more than the rule time if the time authorize circuit is being used. when the external reset function is not used, the time authorize circuit cannot be used. refer to section 2.2.2, "simultaneous high input to terminals k00?03", for details.
6 epson s1c63654 technical manual chapter 1: outline (10) synchronous clock polarity in the serial interface the polarity of the synchronous clock sclk and the srdy signal in slave mode of the serial interface is selected by mask option. either positive polarity or negative polarity can be selected. refer to section 4.12.2, "mask option", for details. (11) lcd drive power either the internal power supply or an external power supply can be selected for driving lcd. refer to section 4.8.2, "power supply for lcd driving", for details. (12) lcd segment specification the display memory can be allocated to the optional seg terminal. it is also possible to set the optional seg terminal for dc output. refer to section 4.8.5, "segment option", for details.
s1c63654 technical manual epson 7 chapter 1: outline the following is the option list for the s1c63654. multiple selections are available in each option item as indicated in the option list. select the specifica- tions that meet the target system and check the appropriate box. be sure to record the specifications for unused functions too. 1. osc1 system clock 1. crystal 2. osc3 system clock 1. cr (built-in r) 2. cr (external r) 3. ceramic 3. input port pull down resistor ?k00 1. with resistor 2. gate direct ?k01 1. with resistor 2. gate direct ?k02 1. with resistor 2. gate direct ?k03 1. with resistor 2. gate direct ?k10 1. with resistor 2. gate direct ?k11 1. with resistor 2. gate direct ?k12 1. with resistor 2. gate direct ?k13 1. with resistor 2. gate direct 4. reset port pull down resistor ?reset 1. with resistor 2. gate direct 5. i/o port pull down resistor ?p00 1. with resistor 2. gate direct ?p01 1. with resistor 2. gate direct ?p02 1. with resistor 2. gate direct ?p03 1. with resistor 2. gate direct ?p10 1. with resistor 2. gate direct ?p11 1. with resistor 2. gate direct ?p12 1. with resistor 2. gate direct ?p13 1. with resistor 2. gate direct 6. output port output specification ?r00 1. complementary 2. pch-opendrain ?r01 1. complementary 2. pch-opendrain ?r02 1. complementary 2. pch-opendrain ?r03 1. complementary 2. pch-opendrain 7. i/o port output specification ?p00 1. complementary 2. pch-opendrain ?p01 1. complementary 2. pch-opendrain ?p02 1. complementary 2. pch-opendrain ?p03 1. complementary 2. pch-opendrain ?p10 1. complementary 2. pch-opendrain ?p11 1. complementary 2. pch-opendrain ?p12 1. complementary 2. pch-opendrain ?p13 1. complementary 2. pch-opendrain 8. multiple key entry reset combination 1. not use 2. use (k00, k01) 3. use (k00, k01, k02) 4. use (k00, k01, k02, k03) 9. multiple key entry reset time authorize 1. not use 2. use
8 epson s1c63654 technical manual chapter 1: outline 10. sio sync clock & srdy 1. negative clock 2. positive clock 11. lcd driving power 1. internal power (3.0 v panel) 2. external power 1/3 bias, v dd =v c2 (4.5 v panel) 3. external power 1/3 bias, v dd =v c3 (3.0 v panel) 4. external power 1/2 bias, v dd =v c3 , v c1 =v c2 (3.0 v panel) 12. segment option h: l: d: ram data high-order address (0?) ram data low-order address (0?) data bit (0?) s: c: n: segment output complementary output nch open drain output pin name seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 h l d com0 address (f0xx) h l d com1 h l d com2 h l d com3 h l d com4 h l d com5 seg output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output output specification
s1c63654 technical manual epson 9 chapter 2: power supply and initial reset chapter 2p o wer s upply and i nitial r eset 2.1 power supply the s1c63654 operating power voltage is as follows: t able 2.1.1 operating voltage operating mode normal mode halver mode normal mode maximum operating frequency 4 mhz (osc3) 32 khz (osc1 only) 32 khz (osc1 only) operating voltage 2.4 v to 3.6 v 2.4 v to 3.6 v 1.8 v to 3.6 v the s1c63654 operates by applying a single power supply within the above range between v dd and v ss . the s1c63654 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in table 2.1.2. t able 2.1.2 power supply circuits circuit osc1 circuit internal circuits (low-speed operation) osc3 and internal circuits (high-speed operation) lcd driver power supply voltage regulator for osc1 oscillation circuit low-speed operation voltage regulator high-speed operation voltage regulator lcd system voltage circuit output voltage v osc v d1l v d3 v c1 ? c3 note: do not drive external loads with the output voltage from the internal power supply circuits. see chapter 7, "electrical characteristics", for voltage values and drive capability. external power supply lcd system voltage regulator lcd driver cc cd v dda v dd v d2 v c1 v c2 v c3 ca cb v osc v d1 v ss v ssa v c1 v c1 v c2 v c3 v d1l v osc v d3 v d2 =1/2 v dd v d1 voltage halver voltage booster lcd system voltage circuit lpwr vdc3 vdc2 vdc0 vdc1 low-speed operation voltage regulator voltage regulator for osc1 oscillation circuit osc1 oscillation circuit cpu, internal circuits r/f converter high-speed operation voltage regulator osc3 oscillation circuit + fi g. 2.1.1 configuration of power supply
10 epson s1c63654 technical manual chapter 2: power supply and initial reset 2.1.1 voltage regulator for osc1 oscillation circuit this voltage regulator generates the v osc voltage (0.98 v typ.) for driving the osc1 oscillation circuit. this regulator always operates to drive the osc1 oscillation circuit. 2.1.2 low-speed operation voltage regulator the low-speed operation voltage regulator generates the v d1l voltage (1.25 v typ.) for driving the internal logic circuits in low-speed mode. this regulator always operates and the output voltage is used as the operating voltage of the cpu and internal logic circuits when they are driven with the osc1 clock (32 khz). 2.1.3 high-speed operation voltage regulator the high-speed operation voltage regulator generates the v d3 voltage (2.0 v typ.) for driving the osc3 oscillation circuit and the internal logic circuits in high-speed mode. since this regulator stops normally, it should be turned it on using software before switching to the high-speed mode. refer to section 4.4, "oscillation circuit", for the control method. 2.1.4 internal operating voltage v d1 the internal operating voltage v d1 is the voltage for driving the cpu and internal logic circuits. the s1c63654 is designed with twin clock specifications; it has two types of oscillation circuits osc1 and osc3 built-in. use osc1 clock for normal operation, and switch to osc3 using software when high- speed operation is necessary. when switching the clock, the operating voltage v d1 must be switched using software to stabilize the operation of the oscillation circuit and internal circuits. in low-speed operation, v d1l generated by the low-speed operation voltage regulator is used as v d1 . in high-speed operation, v d3 generated by the high-speed operation voltage regulator is used as v d1 . refer to section 4.4, "oscillation circuit", for the control method. 2.1.5 lcd system voltage circuit the lcd system voltage circuit generates the lcd drive voltage. this circuit allows the software to turn on and off. turn this circuit on before starting display on the lcd. the lcd system voltage circuit generates v c1 with the voltage regulator built-in, and generates two other voltages (v c2 = 2v c1 , v c3 = 3v c1 ) by boosting v c1 . the v c1 voltage value can be adjusted using software in 16 steps (0.95 to 1.40 v). the lcd system voltage regulator can be disabled by mask option. in this case, external elements can be minimized because the external capacitors for the lcd system voltage regulator are not necessary. however when the lcd system voltage regulator is not used, the display quality of the lcd panel, when the supply voltage fluctuates (drops), is inferior to when the lcd system voltage regulator is used. figure 2.1.5.1 shows the external element configuration when the lcd system voltage regulator is not used.
s1c63654 technical manual epson 11 chapter 2: power supply and initial reset v dd v c1 v c2 v c3 ca cb v ss 3.0 v 4.5 v lcd panel 1/6, 1/5, 1/4 or 1/3 duty, 1/3 bias 3 v lcd panel 1/6, 1/5, 1/4 or 1/3 duty, 1/3 bias 3 v lcd panel 1/6, 1/5, 1/4 or 1/3 duty, 1/2 bias c 2 c 4 c 1 v dd v c1 v c2 v c3 ca cb v ss 3.0 v c 2 c 3 c 1 v dd v c1 v c2 v c3 ca cb v ss 3.0 v c 2 c 1 fi g. 2.1.5.1 external elements when lcd system voltage regulator is not used refer to section 4.8, "lcd driver", for control of the lcd drive voltage. 2.1.6 halver mode and saving power when the supply voltage v dd is 2.4 v or more, the low-speed operation voltage regulator and lcd system voltage circuit can be driven with the v dd voltage halved. this status is the halver mode for r educing current consumption during halt or low-speed operation. at initial reset, the low-speed operation voltage regulator and lcd system voltage circuit are set in the normal mode using v dd . when necessary switch to the halver mode using software. the halver mode supports only low-speed operation using the osc1 clock and cannot be set during high-speed operation using the osc3 clock. the low- speed operation voltage regulator and the lcd system voltage circuit can be set to the halver mode independently. refer to section 4.2, "power control", for control of the halver mode. 2.1.7 analog system power supply the v dda and v ssa power supply terminals are provided only for the r/f converter in order to avoid decreasing the conversion accuracy due to noise. however, the same voltage level as the v dd ? ss must be supplied to the v dda ? ssa . v dda = v dd , v ssa = v ss
12 epson s1c63654 technical manual chapter 2: power supply and initial reset 2.2 initial reset to initialize the s1c63654 circuits, initial reset must be executed. there are two ways of doing this. (1) external initial reset by the reset terminal (2) external initial reset by simultaneous high input to terminals k00?03 (mask option setting) the circuits are initialized by either (1) or (2). when the power is turned on, be sure to initialize using the r eset function. it is not guaranteed that the circuits are initialized by only turning the power on. figure 2.2.1 shows the configuration of the initial reset circuit. reset k00 k01 k02 k03 osc2 osc1 osc1 oscillation circuit noise reject circuit rq s internal initial reset time authorize circuit divider mask option 1 hz 2 hz v ss mask option fi g. 2.2.1 configuration of initial reset circuit 2.2.1 reset terminal (reset) initial reset can be executed externally by setting the reset terminal to a high level (v dd ). after that the initial reset is released by setting the reset terminal to a low level (v ss ) and the cpu starts operation. the reset input signal is maintained by the rs latch and becomes the internal initial reset signal. the rs latch is designed to be released by a 2 hz signal (high) that is divided by the osc1 clock. therefore in normal operation, a maximum of 250 msec (when f osc1 = 32.768 khz) is needed until the internal initial r eset is released after the reset terminal goes to low level. be sure to maintain a reset input of 0.1 msec or more. however, when turning the power on, the reset terminal should be set at a high level as in the timing shown in figure 2.2.1.1. note that a reset pulse shorter than 100 nsec is rejected as noise. v dd reset 2.0 msec or more 1.8 v 0.5? dd 0.9? dd or more (high level) power on fi g. 2.2.1.1 initial reset at power on the reset terminal should be set to 0.9? dd or more (high level) until the supply voltage becomes 1.8 v or more. after that, a level of 0.5 v dd or more should be maintained more than 2.0 msec. the internal pull-down resistor of the reset terminal can be enabled or disabled by mask option.
s1c63654 technical manual epson 13 chapter 2: power supply and initial reset further, the time authorize circuit mask option is selected when this reset function is selected. the time authorize circuit checks the input time of the simultaneous high input and performs initial reset if that time is the defined time (1 to 2 sec) or more. if using this function, make sure that the specified ports do not go high at the same time during ordinary operation. 2.2.3 internal register at initial resetting initial reset initializes the cpu as shown in table 2.2.3.1. the registers and flags which are not initialized by initial reset should be initialized in the program if necessary. in particular, the stack pointers sp1 and sp2 must be set as a pair because all the interrupts including nmi are masked after initial reset until both the sp1 and sp2 stack pointers are set with software. when data is written to the ext register, the e flag is set and the following instruction will be executed in the extended addressing mode. if an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. therefore, do not write data to the ext register for initialization only. refer to the "s1c63000 core cpu manual" for extended addressing and usable instructions. t able 2.2.3.1 initial values name data register a data register b extension register ext index register x index register y program counter stack pointer sp1 stack pointer sp2 zero flag carry flag interrupt flag extension flag queue register cpu core symbol a b ext x y pc sp1 sp2 z c i e q number of bits 4 4 8 16 16 16 8 8 1 1 1 1 16 setting value undefined undefined undefined undefined undefined 0110h undefined undefined undefined undefined 0 0 undefined name ram display memory other peripheral circuits peripheral circuits number of bits 4 4 setting value undefined undefined ? 2.2.2 simultaneous high input to terminals k00?03 another way of executing initial reset externally is to input a high signal simultaneously to the input ports (k00?03) selected with the mask option. since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at high level for at least 1.5 msec (when the oscillation frequency f osc1 is 32.768 khz) during normal operation. the noise reject circuit does not operate immediately after turning the power on until the oscillation circuit starts oscillating. therefore, maintain the specified input port terminals at high level for at least 1.5 msec (when the oscillation frequency f osc1 is 32.768 khz) after oscillation starts. t able 2.2.2.1 shows the combinations of input ports (k00?03) that can be selected with the mask option. t able 2.2.2.1 combinations of input ports not use k00 ? k01 k00 ? k01 ? k02 k00 ? k01 ? k02 ? k03 1 2 3 4 when, for instance, mask option 4 (k00 ? k01 ? k02 ? k03) is selected, initial reset is executed when the signals input to the four ports k00?03 are all high at the same time. when 2 or 3 is selected, the initial reset is done when a key entry including a combination of selected input ports is made. ? see section 4.1, "memory map".
14 epson s1c63654 technical manual chapter 2: power supply and initial reset 2.2.4 terminal settings at initial resetting the output port (r) terminals and i/o port (p) terminals are shared with special output terminals and input/output terminals of the serial interface. these functions are selected by the software. at initial r eset, these terminals are set to the general purpose output port terminals and i/o port terminals. set them according to the system in the initial routine. in addition, take care of the initial status of output terminals when designing a system. t able 2.2.4.1 shows the list of the shared terminal settings. t able 2.2.4.1 list of shared terminal settings terminal name r00 r01 r02 r03 p00?03 p10 p11 p12 p13 terminal status at initial reset r00 (low output) r01 (low output) r02 (low output) r03 (low output) p00?03 (input & pulled down ? ) p10 (input & pulled down ? ) p11 (input & pulled down ? ) p12 (input & pulled down ? ) p13 (input & pulled down ? ) special output tout fout tout fout serial i/f ? when "with pull-down" is selected by mask option (high impedance when "gate direct" is selected) master p00?03 sin(i) sout(o) sclk(o) p13 slave p00?03 sin(i) sout(o) sclk(i) srdy(o) for setting procedure of the functions, see explanations for each of the peripheral circuits. 2.3 test terminal (test) this is the terminal used for the factory inspection of the ic. during normal operation, connect the test terminal to v ss .
s1c63654 technical manual epson 15 chapter 3: cpu, rom, ram chapter 3 cpu, rom, ram 3.1 cpu the s1c63654 has a 4-bit core cpu s1c63000 built-in as its cpu part. refer to the "s1c63000 core cpu manual" for the s1c63000. note: the slp instruction cannot be used because the sleep operation is not assumed in the s1c63654. 3.2 code rom the built-in code rom is a mask rom for loading programs, and has a capacity of 4,096 steps 13 bits. the core cpu can linearly access the program space up to step ffffh from step 0000h, however, the program area of the s1c63654 is step 0000h to step 0fffh. the program start address after initial reset is assigned to step 0110h. the non-maskable interrupt (nmi) vector and hardware interrupt vectors are allocated to step 0100h and steps 0102h?10eh, respectively. 0000h 0fffh 1000h ffffh 0000h 0100h 0102h 010eh 0110h program area nmi vector hardware interrupt vectors program start address program area rom unused area 13 bits s1c63000 core cpu program space s1c63654 program area fi g. 3.2.1 configuration of code rom 3.3 ram the ram is a data memory for storing various kinds of data, and has a capacity of 512 words 4 bits. the ram area is assigned to addresses 0000h to 01ffh on the data memory map. addresses 0100h to 01ffh are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data. when programming, keep the following points in mind. (1) part of the ram area is used as a stack area for subroutine call and register evacuation, so pay attention not to overlap the data area and stack area. (2) the s1c63000 core cpu handles the stack using the stack pointer for 4-bit data (sp2) and the stack pointer for 16-bit data (sp1). 16-bit data are accessed in stack handling by sp1, therefore, this stack area should be allocated to the area where 4-bit/16-bit access is possible (0100h to 01ffh). the stack pointers sp1 and sp2 change cyclically within their respective range: the range of sp1 is 0000h to 03ffh and the range of sp2 is 0000h to 00ffh. therefore, pay attention to the sp1 value because it may be set to 0200h or more exceeding the 4-bit/16-bit accessible range in the s1c63654 or it may be set to 00ffh or less. memory accesses except for stack operations by sp1 are 4-bit data access. after initial reset, all the interrupts including nmi are masked until both the stack pointers sp1 and sp2 are set by software. further, if either sp1 or sp2 is re-set when both are set already, the interrupts including nmi are masked again until the other is re-set. therefore, the settings of sp1 and sp2 must be done as a pair.
16 epson s1c63654 technical manual chapter 3: cpu, rom, ram (3) subroutine calls use 4 words (for pc evacuation) in the stack area for 16-bit data (sp1). interrupts use 4 words (for pc evacuation) in the stack area for 16-bit data (sp1) and 1 word (for f register evacua- tion) in the stack area for 4-bit data. 0000h 00ffh 0100h 01ffh 4 bits 4-bit access area (sp2 stack area) 4/16-bit access area (sp1 stack area) fi g. 3.3.1 configuration of data ram 3.4 data rom the data rom is a mask rom for loading various static data such as a character generator, and has a capacity of 1,024 words 4 bits. the data rom is assigned to addresses 8000h to 83ffh on the data memory map, and the data can be read using the same data memory access instructions as the ram.
s1c63654 technical manual epson 17 chapter 4: peripheral circuits and operation (memory map) chapter 4 p eripheral c ircuits and o peration the peripheral circuits of s1c63654 (timer, i/o, etc.) are interfaced with the cpu in the memory mapped i/o method. thus, all the peripheral circuits can be controlled by accessing the i/o memory on the memory map using the memory operation instructions. the following sections explain the detailed operation of each peripheral circuit. 4.1 memory map the s1c63654 data memory consists of 512-word ram, 1,024-word data rom, 48-word display memory and 85-word peripheral i/o memory. figure 4.1.1 shows the overall memory map of the s1c63654, and t able 4.1.1 the peripheral circuits' (i/o space) memory maps. 0000h 0200h 8000h 8400h f000h ff00h ffffh ram area unused area unused area data rom area i/o memory area display memory area unused area peripheral i/o area f000h f030h ff00h ffffh fi g. 4.1.1 memory map note: memory is not implemented in unused areas within the memory map. further, some non-imple- mentation areas and unused (access prohibition) areas exist in the peripheral i/o area. if the program that accesses these areas is generated, its operation cannot be guaranteed. refer to the i/o memory maps shown in table 4.1.1 for the peripheral i/o area.
18 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (a) i/o memory map (ff00h?f31h) remarks ? 1i nitial value at initial reset ? 2 not set in the circuit ? 3 constantly "0" when being read address comment d3 d2 register d1 d0 name init ? 1 10 ff06h foute swdir fofq1 fofq0 r/w foute swdir fofq1 fofq0 0 0 0 0 enable disable ff05h 00 svddt svdon rr/w 0 ? 3 0 ? 3 svddt svdon ? ? 2 ? ? 2 0 0 low on normal off unused unused svd evaluation data svd circuit on/off ff07h 00 wden wdrst r/w w r 0 ? 3 0 ? 3 wden wdrst ? 3 ? ? 2 ? ? 2 1 reset enable reset disable invalid unused unused watchdog timer enable watchdog timer reset (writing) ff04h 0 svds2 svds1 svds0 rr/w 0 ? 3 svds2 svds1 svds0 ? ? 2 0 0 0 ff01h clkchg oscc 0 0 r/w r clkchg oscc 0 ? 3 0 ? 3 0 0 ? ? 2 ? ? 2 osc3 on osc1 off cpu clock switch osc3 oscillation on/off unused unused ff00h vdc3 vdc2 vdc1 vdc0 r/w vdc3 vdc2 vdc1 vdc0 0 0 0 0 1/2v dd 1/2v dd on v d3 v dd v dd off v d1l lcd system voltage regulator power source switch low-speed operation voltage regulator power source switch high-speed operation voltage regulator on/off logic system power source switch unused svd criteria voltage setting 1 2.00 2 2.15 3 2.30 4 2.45 5 2.60 6 2.75 7 2.90 [svds2?] voltage(v) fout output enable stopwatch direct input switch 0: k00=run/stop, k01=lap 1: k00=lap, k01=run/stop fout frequency selection 0 f osc1 /64 1 f osc1 /8 2 f osc1 3 f osc3 [fofq1, 0] frequency ff20h sik03 sik02 sik01 sik00 r/w sik03 sik02 sik01 sik00 0 0 0 0 enable enable enable enable disable disable disable disable k00?03 interrupt selection register ff21h k03 k02 k01 k00 r k03 k02 k01 k00 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low k00?03 input port data ff22h kcp03 kcp02 kcp01 kcp00 r/w kcp03 kcp02 kcp01 kcp00 1 1 1 1 k00?03 input comparison register ff24h sik13 sik12 sik11 sik10 r/w sik13 sik12 sik11 sik10 0 0 0 0 enable enable enable enable disable disable disable disable k10?13 interrupt selection register ff25h k12 k11 k10 r k13 k12 k11 k10 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low k10?13 input port data ff26h kcp13 kcp12 kcp11 kcp10 r/w kcp13 kcp12 kcp11 kcp10 1 1 1 1 k10?13 input comparison register ff30h r03hiz r02hiz r01hiz r00hiz r/w r03hiz r02hiz r01hiz r00hiz 0 0 0 0 hi-z hi-z hi-z hi-z output output output output r03 (foute=0)/fout (foute=1) hi-z control r02 (ptout=0)/tout (ptout=1) hi-z control r01 hi-z control r00 hi-z control ff31h r03 r02 r01 r00 r/w r03 r02 r01 r00 0 0 0 0 high high high high low low low low r03 output port data ( foute=0 ) fix at "1" when fout is used. r02 output port data ( ptout=0 ) fix at "1" when tout is used. r01 output port data r00 output port data k13 0 1.85
s1c63654 technical manual epson 19 chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (b) i/o memory map (ff40h?f6dh) address comment d3 d2 register d1 d0 name init ? 1 10 ff40h ioc03 ioc02 ioc01 ioc00 r/w ioc03 ioc02 ioc01 ioc00 0 0 0 0 output output output output input input input input p00?03 i/o control register ff41h pul03 pul02 pul01 pul00 r/w pul03 pul02 pul01 pul00 1 1 1 1 on on on on off off off off p00?03 pull-down control register ff42h p03 p02 p01 p00 r/w p03 p02 p01 p00 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low p00?03 i/o port data ff60h lduty1 lduty0 stcd lpwr r/w lduty1 lduty0 stcd lpwr 0 0 0 0 static on dynamic off lcd drive duty switch lcd drive switch lcd power on/off 0 1/4 1 1/5 2 1/6 3 1/3 ff61h 0 aloff alon 0 rr r/w 0 ? 3 aloff alon 0 ? 3 ? ? 2 1 0 ? ? 2 all off all on normal normal unused lcd all off control lcd all on control unused ff62h lc3 lc2 lc1 lc0 r/w lc3 lc2 lc1 lc0 0 0 0 0 0 light 15 dark [lc3?] contrast lcd contrast adjustment [lduty1, 0] duty ff44h ioc13 ioc12 ioc11 ioc10 r/w ioc13 ioc12 ioc11 ioc10 0 0 0 0 output output output output input input input input p13 i/o control register functions as a general-purpose register when sif (slave) is selected p12 i/o control register (esif=0) functions as a general-purpose register when sif is selected p11 i/o control register (esif=0) functions as a general-purpose register when sif is selected p10 i/o control register (esif=0) functions as a general-purpose register when sif is selected ff45h pul13 pul12 pul11 pul10 r/w pul13 pul12 pul11 pul10 1 1 1 1 on on on on off off off off p13 pull-down control register functions as a general-purpose register when sif (slave) is selected p12 pull-down control register (esif=0) functions as a general-purpose register when sif (master) is selected sclk (i) pull-down control register when sif (slave) is selected p11 pull-down control register (esif=0) functions as a general-purpose register when sif is selected p10 pull-down control register (esif=0) sin pull-down control register when sif is selected ff46h p13 (xsrdy) p12 (xsclk) p11 (sout) p10 (sin) r/w p13 p12 p11 p10 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low p13 i/o port data functions as a general-purpose register when sif (slave) is selected p12 i/o port data (esif=0) functions as a general-purpose register when sif is selected p11 i/o port data (esif=0) functions as a general-purpose register when sif is selected p10 i/o port data (esif=0) functions as a general-purpose register when sif is selected ff6ch enrtm enrst enon bze r/w w r/w enrtm enrst ? 3 enon bze 0 reset 0 0 1 sec reset on enable 0.5 sec invalid off disable envelope releasing time selection envelope reset (writing) envelope on/off buzzer output enable ff6dh 0 bzstp bzsht shtpw rw r/w 0 ? 3 bzstp ? 3 bzsht shtpw ? ? 2 0 0 0 stop trigger busy 125 msec invalid invalid ready 31.25 msec unused 1-shot buzzer stop (writing) 1-shot buzzer trigger (writing) 1-shot buzzer status (reading) 1-shot buzzer pulse width setting
20 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (c) i/o memory map (ff6eh?f7bh) address comment d3 d2 register d1 d0 name init ? 1 10 ff6eh 0 bzfq2 bzfq1 bzfq0 rr/w 0 ? 3 bzfq2 bzfq1 bzfq0 ? ? 2 0 0 0 ff6fh 0 bdty2 bdty1 bdty0 rr/w 0 ? 3 bdty2 bdty1 bdty0 ? ? 2 0 0 0 0 4096.0 1 3276.8 2 2730.7 3 2340.6 [bzfq2, 1, 0] frequency (hz) 4 2048.0 5 1638.4 6 1365.3 7 1170.3 [bzfq2, 1, 0] frequency (hz) unused buzzer frequency selection unused buzzer signal duty ratio selection (refer to main manual) wr/w r ff74h 00 tmrst tmrun 0 ? 3 0 ? 3 tmrst ? 3 tmrun ? ? 2 ? ? 2 reset 0 reset run invalid stop unused unused clock timer reset (writing) clock timer run/stop r ff75h tm3 tm2 tm1 tm0 tm3 tm2 tm1 tm0 0 0 0 0 clock timer data (16 hz) clock timer data (32 hz) clock timer data (64 hz) clock timer data (128 hz) r ff76h tm7 tm6 tm5 tm4 tm7 tm6 tm5 tm4 0 0 0 0 clock timer data (1 hz) clock timer data (2 hz) clock timer data (4 hz) clock timer data (8 hz) 0 none 1 k02 2 k02?3 3 k02?3,10 [dkm2, 1, 0] key mask 4 k10 5 k10?1 6 k10?2 7 k10?3 [dkm2, 1, 0] key mask r/w ff78h edir dkm2 dkm1 dkm0 edir dkm2 dkm1 dkm0 0 0 0 0 enable disable direct input enable key mask selection r/w w r ff79h lcurf crnwf swrun swrst lcurf crnwf swrun swrst ? 3 0 0 0 reset request renewal run reset no no stop invalid lap data carry-up request flag capture renewal flag stopwatch timer run/stop stopwatch timer reset (writing) 0 slave 2 osc1/2 1 pt 3 osc1 r/w ff72h sd3 sd2 sd1 sd0 sd3 sd2 sd1 sd0 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low msb serial i/f transmit/receive data (low-order 4 bits) lsb r/w ff73h sd7 sd6 sd5 sd4 sd7 sd6 sd5 sd4 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low msb serial i/f transmit/receive data (high-order 4 bits) lsb [scs1, 0] clock [scs1, 0] clock ff71h sdp scps scs1 scs0 r/w sdp scps scs1 scs0 0 0 0 0 msb first lsb first serial i/f data input/output permutation serial i/f clock phase selection ?egative polarity (mask option) ?ositive polarity (mask option) serial i/f clock mode selection ff70h 0 esout sctrg esif rr/w 0 ? 3 esout sctrg esif ? ? 2 0 0 0 enable trigger run sif disable invalid stop i/o unused sout enable serial i/f clock trigger (writing) serial i/f clock status (reading) serial i/f enable (p1 port function selection) swd7 swd6 swd5 swd4 0 0 0 0 stopwatch timer data bcd (1/100 sec) r ff7bh swd7 swd6 swd5 swd4 r ff7ah swd3 swd2 swd1 swd0 swd3 swd2 swd1 swd0 0 0 0 0 stopwatch timer data bcd (1/1000 sec)
s1c63654 technical manual epson 21 chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (d) i/o memory map (ff7ch?fc0h) address comment d3 d2 register d1 d0 name init ? 1 10 mc3 mc2 mc1 mc0 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc0?c3 lsb r/w r/w ff92h mc3 mc2 mc1 mc0 mc7 mc6 mc5 mc4 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc4?c7 ff93h mc7 mc6 mc5 mc4 ff90h 0 rfclk rfsel sensel rr/w 0 ? 3 rfclk rfsel sensel ? ? 2 0 0 0 osc3 ac ch.1 osc1 dc ch.0 unused r/f conversion clock selection ch.1 sensor type selection conversion channel selection swd11 swd10 swd9 swd8 0 0 0 0 stopwatch timer data bcd (1/10 sec) r ff7ch swd11 swd10 swd9 swd8 mod16 evcnt fcsel plpol 0 0 0 0 16 bits event ct. with nr 8 bits timer no nr 16-bit mode selection timer 0 counter mode selection timer 0 function selection (for event counter mode) timer 0 pulse polarity selection (for event counter mode) r/w ffc0h mod16 evcnt fcsel plpol tc11 tc10 tc9 tc8 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc8?c11 r/w ff99h tc11 tc10 tc9 tc8 tc15 tc14 tc13 tc12 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc12?c15 r/w ff9ah tc15 tc14 tc13 tc12 tc19 tc18 tc17 tc16 ? ? 2 ? ? 2 ? ? 2 ? ? 2 msb time base counter tc16?c19 r/w ff9bh tc19 tc18 tc17 tc16 mc19 mc18 mc17 mc16 ? ? 2 ? ? 2 ? ? 2 ? ? 2 msb measurement counter mc16?c19 r/w ff96h mc19 mc18 mc17 mc16 tc3 tc2 tc1 tc0 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc0?c3 lsb r/w ff97h tc3 tc2 tc1 tc0 tc7 tc6 tc5 tc4 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc4?c7 r/w ff98h tc7 tc6 tc5 tc4 r/w mc11 mc10 mc9 mc8 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc8?c11 ff94h mc11 mc10 mc9 mc8 r/w mc15 mc14 mc13 mc12 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc12?c15 ff95h mc15 mc14 mc13 mc12 ff91h ovtbc ovmc rfrunr rfruns r/w ovtbc ovmc rfrunr rfruns 0 0 0 0 overflow overflow run run non-ov non-ov stop stop time base counter overflow flag measurement counter overflow flag reference oscillation run control/status (writing "0" is ineffective) sensor oscillation run control/status (writing "0" is ineffective)
22 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (e) i/o memory map (ffc1h?fd3h) address comment d3 d2 register d1 d0 name init ? 1 ptps01 ptps00 ptrst0 ? 3 ptrun0 0 0 ? ? 2 0 reset run invalid stop prescaler 0 division ratio selection timer 0 reset (reload) timer 0 run/stop wr/w r/w ffc3h ptps01 ptps00 ptrst0 ptrun0 0 1/1 1 1/4 2 1/32 3 1/256 [ptps01, 00] division ratio 10 0 ? 3 0 ? 3 chsel0 ptout ? ? 2 ? ? 2 0 0 timer 1 on timer 0 off unused unused tout output selection tout output control rr/w ffc1h 00 chsel0 ptout 0 ? 3 0 ? 3 cksel1 cksel0 ? ? 2 ? ? 2 0 0 osc3 osc3 osc1 osc1 unused unused prescaler 1 source clock selection prescaler 0 source clock selection rr/w ffc2h 00 cksel1 cksel0 ptps11 ptps10 ptrst1 ? 3 ptrun1 0 0 ? ? 2 0 reset run invalid stop prescaler 1 division ratio selection timer 1 reset (reload) timer 1 run/stop wr/w r/w ffc4h ptps11 ptps10 ptrst1 ptrun1 0 1/1 1 1/4 2 1/32 3 1/256 [ptps11, 10] division ratio rld03 rld02 rld01 rld00 0 0 0 0 msb programmable timer 0 reload data (low-order 4 bits) lsb r/w ffc6h rld03 rld02 rld01 rld00 rld07 rld06 rld05 rld04 0 0 0 0 msb programmable timer 0 reload data (high-order 4 bits) lsb r/w ffc7h rld07 rld06 rld05 rld04 rld13 rld12 rld11 rld10 0 0 0 0 msb programmable timer 1 reload data (low-order 4 bits) lsb r/w ffc8h rld13 rld12 rld11 rld10 rld17 rld16 rld15 rld14 0 0 0 0 msb programmable timer 1 reload data (high-order 4 bits) lsb r/w ffc9h rld17 rld16 rld15 rld14 ptd03 ptd02 ptd01 ptd00 0 0 0 0 msb programmable timer 0 data (low-order 4 bits) lsb r ffcch ptd03 ptd02 ptd01 ptd00 ptd07 ptd06 ptd05 ptd04 0 0 0 0 msb programmable timer 0 data (high-order 4 bits) lsb r ffcdh ptd07 ptd06 ptd05 ptd04 ptd13 ptd12 ptd11 ptd10 0 0 0 0 msb programmable timer 1 data (low-order 4 bits) lsb r ffceh ptd13 ptd12 ptd11 ptd10 ptd17 ptd16 ptd15 ptd14 0 0 0 0 msb programmable timer 1 data (high-order 4 bits) lsb r ffcfh ptd17 ptd16 ptd15 ptd14 cd03 cd02 cd01 cd00 0 0 0 0 msb programmable timer 0 compare data (low-order 4 bits) lsb r/w ffd2h cd03 cd02 cd01 cd00 cd07 cd06 cd05 cd04 0 0 0 0 msb programmable timer 0 compare data (high-order 4 bits) lsb r/w ffd3h cd07 cd06 cd05 cd04
s1c63654 technical manual epson 23 chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (f) i/o memory map (ffd4h?ff2h) address comment d3 d2 register d1 d0 name init ? 1 10 ffe5h eit3 eit2 eit1 eit0 r/w eit3 eit2 eit1 eit0 0 0 0 0 enable enable enable enable mask mask mask mask interrupt mask register (clock timer 1 hz) interrupt mask register (clock timer 2 hz) interrupt mask register (clock timer 8 hz) interrupt mask register (clock timer 32 hz) ffe4h 000ei k1 rr/w 0 ? 3 0 ? 3 0 ? 3 eik1 ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (k10?13) ffe6h eirun eilap eisw1 eisw10 r/w eirun eilap eisw1 eisw10 0 0 0 0 enable enable enable enable mask mask mask mask interrupt mask register (stopwatch direct run) interrupt mask register (stopwatch direct lap) interrupt mask register (stopwatch timer 1 hz) interrupt mask register (stopwatch timer 10 hz) ffe7h 00ei rfb eirfm rr/w 0 ? 3 0 ? 3 eirfb eirfm ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (r/f converter reference oscillate completion) interrupt mask register (r/f converter sensor oscillate completion) fff1h 00i pt1 ipt0 rr/w 0 ? 3 0 ? 3 ipt1 ipt0 ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (programmable timer 1 underflow) interrupt factor flag (programmable timer 0 underflow) ffd8h 00 ptsel1 ptsel0 rr/w 0 ? 3 0 ? 3 ptsel1 ptsel0 ? ? 2 ? ? 2 0 0 pwm pwm normal normal unused unused programmable timer 1 pwm output selection programmable timer 0 pwm output selection ffe0h 00 ectc1 ectc0 rr/w 0 ? 3 0 ? 3 ectc1 ectc0 ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (programmable timer 1 compare match) interrupt mask register (programmable timer 0 compare match) cd17 cd16 cd15 cd14 0 0 0 0 msb programmable timer 1 compare data (high-order 4 bits) lsb r/w ffd5h cd17 cd16 cd15 cd14 cd13 cd12 cd11 cd10 0 0 0 0 msb programmable timer 1 compare data (low-order 4 bits) lsb r/w ffd4h cd13 cd12 cd11 cd10 ffe1h 00ei pt1 eipt0 rr/w 0 ? 3 0 ? 3 eipt1 eipt0 ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (programmable timer 1 underflow) interrupt mask register (programmable timer 0 underflow) ffe3h 000ei k0 rr/w 0 ? 3 0 ? 3 0 ? 3 eik0 ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (k00?03) fff0h 00 ictc1 ictc0 rr/w 0 ? 3 0 ? 3 ictc1 ictc0 ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (programmable timer 1 compare match) interrupt factor flag (programmable timer 0 compare match) fff2h 000is if rr/w 0 ? 3 0 ? 3 0 ? 3 isif ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (serial i/f) ffe2h 000ei sif rr/w 0 ? 3 0 ? 3 0 ? 3 eisif ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (serial i/f)
24 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (memory map) t able 4.1.1 (g) i/o memory map (fff3h?ff7h) address comment d3 d2 register d1 d0 name init ? 1 10 fff5h fff6h irun ilap isw1 isw10 r/w irun ilap isw1 isw10 0 0 0 0 (r) yes (w) reset (r) no (w) invalid interrupt factor flag (stopwatch direct run) interrupt factor flag (stopwatch direct lap) interrupt factor flag (stopwatch timer 1 hz) interrupt factor flag (stopwatch timer 10 hz) fff7h 00i rfb irfm rr/w 0 ? 3 0 ? 3 irfb irfm ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (r/f converter reference oscillate completion) interrupt factor flag (r/f converter sensor oscillate completion) it3 it2 it1 it0 r/w it3 it2 it1 it0 0 0 0 0 (r) yes (w) reset (r) no (w) invalid interrupt factor flag (clock timer 1 hz) interrupt factor flag (clock timer 2 hz) interrupt factor flag (clock timer 8 hz) interrupt factor flag (clock timer 32 hz) fff3h 000ik0 rr/w 0 ? 3 0 ? 3 0 ? 3 ik0 ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (k00?03) fff4h 000ik1 rr/w 0 ? 3 0 ? 3 0 ? 3 ik1 ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (k10?13)
s1c63654 technical manual epson 25 chapter 4: peripheral circuits and operation (power control) 4.2 power control 4.2.1 configuration of power supply circuit the s1c63654 has built-in power supply circuits shown in figure 4.2.1.1 so the voltages to drive the cpu, internal logic circuits, oscillation circuits and lcd driver can be generated on the chip. external power supply lcd system voltage regulator lcd driver cc cd v dda v dd v d2 v c1 v c2 v c3 ca cb v osc v d1 v ss v ssa v c1 v c1 v c2 v c3 v d1l v osc v d3 v d2 =1/2 v dd v d1 voltage halver voltage booster lcd system voltage circuit lpwr vdc3 vdc2 vdc0 vdc1 low-speed operation voltage regulator voltage regulator for osc1 oscillation circuit osc1 oscillation circuit cpu, internal circuits r/f converter high-speed operation voltage regulator osc3 oscillation circuit + fi g. 4.2.1.1 built-in power supply circuit v oltage regulator for osc1 oscillation circuit this voltage regulator always operates to generate the v osc voltage (0.98 v typ.) for driving the osc1 oscillation circuit. low-speed operation voltage regulator the low-speed operation voltage regulator always operates to generate the v d1l voltage (1.25 v typ.) for driving the internal logic circuits. the v d1l voltage is used as the v d1 operating voltage of the cpu and internal logic circuits when they are driven with the osc1 clock (32 khz). v d1 should be switched using software according to the operating clock. high-speed operation voltage regulator the high-speed operation voltage regulator generates the v d3 voltage (2.0 v typ.) for driving the osc3 oscillation circuit and the internal logic circuits in high-speed mode. since this regulator stops normally, turn it on using the vdc1 register (vdc1 = "1") and switch the internal logic operating voltage to v d3 using the vdc0 register before starting the osc3 oscillation. lcd system voltage circuit the lcd system voltage circuit generates the lcd drive voltage. this circuit can be turned on and off using the lpwr register. turn this circuit on (lpwr = "1") before starting display on the lcd. the lcd system voltage circuit generates v c1 with the built-in voltage regulator, and generates two other voltages (v c2 = 2v c1 , v c3 = 3v c1 ) by boosting v c1 . the v c1 voltage value can be adjusted using software in 16 steps (0.95 to 1.40 v). refer to section 4.8, "lcd driver", for control of the v c1 voltage (contrast). this circuit does not operate when an external power supply is selected by mask option for driving the lcd.
26 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (power control) v oltage halver the voltage halver generates v d2 by halving the supply voltage v dd . using this halved supply voltage to drive the low-speed operation voltage regulator and lcd system voltage circuit reduces current consumption during halt or low-speed operation. this status is the halver mode and the vdc2 register is used to set the low-speed operation voltage regulator into the halver mode and the vdc3 register is used to set the lcd system voltage circuit. however, the supply voltage must be 2.4 v or more to set the halver mode. furthermore, the halver mode cannot be set during high-speed operation using the osc3 clock. in the normal mode, the low-speed operation voltage regulator and lcd system voltage circuit operate with the supply voltage v dd directly. at initial reset, the normal mode is set by hardware. the voltage halver always operates regardless of the mode set. 4.2.2 power control procedure at initial reset, the power supply, operating voltage and oscillation circuit are set as follows: ?low-speed operation voltage regulator: on normal mode (vdc2 = "0") ?lcd system voltage circuit: off (lpwr = "0") normal mode (vdc3 = "0") ?high-speed operation voltage regulator: off (vdc1 = "0") ?cpu/internal logic operating voltage: v d1l (vdc0 = "0") ?cpu system clock: osc1 (clkchg = "0") ?osc3 oscillation circuit: off (oscc = "0") setting halver mode the low-speed operation voltage regulator and the lcd system voltage circuit can be set into the halver mode independently. setting the low-speed operation voltage regulator the low-speed operation voltage regulator can be set into the halver mode under the conditions below. ?when the supply voltage v dd is 2.4 v or higher. ?when the cpu/internal circuits operate with the v d1l operating voltage and osc1 operating clock. the following shows the switching procedure from normal mode to halver mode. 1. switch the cpu clock from osc3 to osc1 (clkchg = "0", when osc3 is used as the cpu clock) 2. stop the osc3 oscillation (oscc = "0") 3. switch the internal operating voltage from v d3 to v d1l (vdc0 = "0") 4. turn the high-speed operation voltage circuit off (vdc1 = "0") 5. check that the supply voltage v dd is 2.4 v or higher using the svd circuit 6. set the halver mode (vdc2 = "1") steps 1 to 4 are necessary during high-speed operation. setting the lcd system voltage circuit the lcd system voltage circuit can be set into the halver mode under the conditions below. ?when the supply voltage v dd is 2.4 v or higher. ?when the v c1 setup value for driving the lcd is 1.13 v or lower. the following shows the switching procedure. 1. check that the supply voltage v dd is 2.4 v or higher using the svd circuit 2. set the lcd drive voltage v c1 to 1.13 v or lower (lc3?c0 6) 3. set the halver mode (vdc3 = "1")
s1c63654 technical manual epson 27 chapter 4: peripheral circuits and operation (power control) switching to high-speed operation the s1c63654 is designed with twin clock specifications; it has two types of oscillation circuits osc1 (for low-speed operation) and osc3 (for high-speed operation) built-in. use osc1 clock for normal operation, and switch it to osc3 using software when high-speed operation is necessary. when switching the clock, the operating voltage v d1 must be switched using software to stabilize the operation of the oscillation circuit and internal circuits. the following shows the switching procedure. refer to section 4.4, "oscillation circuit", for control of the oscillation circuit. switching from low-speed operation to high-speed operation 1. set vdc2 to "0". (low-speed operation voltage regulator: halver mode normal mode) 2. set vdc1 to "1". (high-speed operation voltage regulator: off on) 3. set vdc0 to "1". (internal logic operating voltage: v d1l v d3 ) 4. wait 2.5 msec or more. 5. set oscc to "1". (osc3 oscillation: off on) 6. wait 5 msec or more. 7. set clkchg to "1". (cpu clock: osc1 osc3) to switch from high-speed operation to low-speed operation, follow the procedure to set the halver mode (see the previous page). 4.2.3 i/o memory for power control t able 4.2.3.1 shows the i/o address and the control bits for power control. t able 4.2.3.1 power control bits address comment d3 d2 register d1 d0 name init ? 1 10 ff00h vdc3 vdc2 vdc1 vdc0 r/w vdc3 vdc2 vdc1 vdc0 0 0 0 0 1/2v dd 1/2v dd on v d3 v dd v dd off v d1l lcd system voltage regulator power source switch low-speed operation voltage regulator power source switch high-speed operation voltage regulator on/off logic system power source switch ff60h lduty1 lduty0 stcd lpwr r/w lduty1 lduty0 stcd lpwr 0 0 0 0 static on dynamic off lcd drive duty switch lcd drive switch lcd power on/off 0 1/4 1 1/5 2 1/6 3 1/3 [lduty1, 0] duty *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read vdc0: internal logic system power switching register (ff00h?0) it is used to switch the operating voltage for the cpu and internal circuit. when "1" is written: v d3 (for osc3 operation) when "0" is written: v d1l (for osc1 operation) reading: valid when "1" is written to vdc0, the internal operating voltage is switched to v d3 . after switching to v d3 , the osc3 oscillation can be started. when the low-speed operation voltage regulator is in the halver mode, return it to the normal mode before switching to v d3 . when "0" is written to vdc0, the internal operating voltage is switched to v d1l . stop the osc3 oscillation before switching to v d1l . at initial reset, this register is set to "0".
28 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (power control) vdc1: high-speed operation voltage regulator control (on/off) register (ff00h?1) t urns the high-speed operation voltage regulator on and off. when "1" is written: on when "0" is written: off reading: valid when "1" is written to vdc1, the high-speed operation voltage regulator goes to generate the high-speed operation voltage v d3 for the internal logic circuits. when "0" is written to vdc1, the high-speed operation voltage regulator stops operating. do not write "0" to vdc1 while the cpu is operating with the osc3 clock. at initial reset, this register is set to "0". vdc2: low-speed operation voltage regulator power control register (ff00h?2) sets the low-speed operation voltage regulator to the halver mode. when "1" is written: halver mode (driven with 1/2 v dd ) when "0" is written: normal mode (driven with v dd ) reading: valid when "1" is written to vdc2, the low-speed operation voltage regulator enters the halver mode. in this mode, the low-speed operation voltage regulator operates with 1/2 the v dd voltage, this makes it possible to reduce current consumption. however, the supply voltage v dd must be 2.4 v or higher. furthermore, this mode does not allow high-speed operation using the osc3 clock. when "0" is written to vdc2, the low-speed operation voltage regulator enters the normal mode and operates with the supply voltage v dd . at initial reset, the hardware sets the normal mode and this register is set to "0". vdc3: lcd system voltage circuit power control register (ff00h?3) sets the lcd system voltage circuit to the halver mode. when "1" is written: halver mode (driven with 1/2 v dd ) when "0" is written: normal mode (driven with v dd ) reading: valid when "1" is written to vdc3, the lcd system voltage circuit enters the halver mode. in this mode, the lcd system voltage circuit operates with 1/2 the v dd voltage, this makes it possible to reduce current consumption. however, the supply voltage v dd must be 2.4 v or higher and the v c1 setup voltage must be 1.13 v or lower. furthermore, this mode does not allow high-speed operation using the osc3 clock. when "0" is written to vdc3, the lcd system voltage circuit enters the normal mode and operates with the supply voltage v dd . at initial reset, the hardware sets the normal mode and this register is set to "0". lpwr: lcd power control (on/off) register (ff60h?0) tu rns the lcd system voltage circuit on and off. when "1" is written: on when "0" is written: off reading: valid when "1" is written to the lpwr register, the lcd system voltage circuit goes on and generates the lcd drive voltage. when "0" is written, all the lcd drive voltages go to v ss level. it takes about 100 msec for the lcd drive voltage to stabilize after starting up the lcd system voltage circuit by writing "1" to the lpwr register. at initial reset, this register is set to "0".
s1c63654 technical manual epson 29 chapter 4: peripheral circuits and operation (power control) 4.2.4 programming notes (1) when setting the low-speed operation voltage regulator to the halver mode, make sure that the supply voltage is 2.4 v or higher using the svd circuit before writing "1" to vdc2. furthermore, switch the cpu clock to osc1. (2) when setting the lcd system voltage circuit to the halver mode, make sure that the supply voltage is 2.4 v or higher using the svd circuit before writing "1" to vdc3. furthermore, set the v c1 voltage (contrast) to 1.13 v or lower (lc register = 6 or less).
30 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (watchdog timer) 4.3 watchdog timer 4.3.1 configuration of watchdog timer the s1c63654 has a built-in watchdog timer that operates with a 256 hz divided clock from the osc1 as the source clock. the watchdog timer starts operating after initial reset, however, it can be stopped by the software. the watchdog timer must be reset cyclically by the software while it operates. if the watchdog timer is not reset in at least 3? seconds, it generates a non-maskable interrupt (nmi) to the cpu. figure 4.3.1.1 is the block diagram of the watchdog timer. watchdog timer non-maskable interrupt (nmi) osc1 dividing signal 256 hz watchdog timer enable signal watchdog timer reset signal fi g. 4.3.1.1 watchdog timer block diagram the watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the last stage of the counter (0.25 hz) overflows. wa tchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. the watchdog timer operates in the halt mode. if a halt status continues for 3? seconds, the non- maskable interrupt releases the halt status. 4.3.2 interrupt function if the watchdog timer is not reset periodically, the non-maskable interrupt (nmi) is generated to the core cpu. since this interrupt cannot be masked, it is accepted even in the interrupt disable status (i flag = "0"). however, it is not accepted when the cpu is in the interrupt mask state until sp1 and sp2 are set as a pair, such as after initial reset or during re-setting the stack pointer. the interrupt vector of nmi is assigned to 0100h in the program memory.
s1c63654 technical manual epson 31 chapter 4: peripheral circuits and operation (watchdog timer) 4.3.3 i/o memory of watchdog timer t able 4.3.3.1 shows the i/o address and control bits for the watchdog timer. t able 4.3.3.1 control bits of watchdog timer address comment d3 d2 register d1 d0 name init ? 1 10 ff07h 00 wden wdrst r/w w r 0 ? 3 0 ? 3 wden wdrst ? 3 ? ? 2 ? ? 2 1 reset enable reset disable invalid unused unused watchdog timer enable watchdog timer reset (writing) *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read wden: watchdog timer enable register (ff07h?1) selects whether the watchdog timer is used (enabled) or not (disabled). when "1" is written: enabled when "0" is written: disabled reading: valid when "1" is written to the wden register, the watchdog timer starts count operation. when "0" is written, the watchdog timer does not count and does not generate the interrupt (nmi). at initial reset, this register is set to "1". wdrst: watchdog timer reset (ff07h?0) resets the watchdog timer. when "1" is written: watchdog timer is reset when "0" is written: no operation reading: always "0" when "1" is written to wdrst, the watchdog timer is reset and restarts immediately after that. when "0" is written, no operation results. this bit is dedicated for writing, and is always "0" for reading. 4.3.4 programming notes (1) when the watchdog timer is being used, the software must reset it within 3-second cycles. (2) because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (nmi) if it is not used.
32 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (oscillation circuit) 4.4 oscillation circuit 4.4.1 configuration of oscillation circuit the s1c63654 has two oscillation circuits (osc1 and osc3). osc1 is a crystal oscillation circuit that supplies the operating clock to the cpu and peripheral circuits. osc3 is either a cr or a ceramic oscilla- tion circuit. when processing with the s1c63654 requires high-speed operation, the cpu operating clock can be switched from osc1 to osc3 by the software. to stabilize operation of the internal circuits, the operating voltage must be switched according to the oscillation circuit to be used. figure 4.4.1.1 is the block diagram of this oscillation system. v osc v d1 high-speed operation voltage regulator voltage regulator for osc1 oscillation circuit oscillation circuit control signal cpu clock selection signal to cpu to peripheral circuits clock switch osc3 oscillation circuit osc1 oscillation circuit o p eratin g volta g e selection si g nal divider fi g. 4.4.1.1 oscillation system block diagram 4.4.2 osc1 oscillation circuit the osc1 crystal oscillation circuit generates the main clock for the cpu and the peripheral circuits. the oscillation frequency is 32.768 khz (typ.). figure 4.4.2.1 is the block diagram of the osc1 oscillation circuit. v ss c gx x'tal osc2 osc1 r r dx c dx to cpu (and peripheral circuits) fx v ss fi g. 4.4.2.1 osc1 oscillation circuit as shown in figure 4.4.2.1, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (x'tal) of 32.768 khz (typ.) between the osc1 and osc2 terminals and the trimmer capacitor (c gx ) between the osc1 and v ss terminals.
s1c63654 technical manual epson 33 chapter 4: peripheral circuits and operation (oscillation circuit) 4.4.3 osc3 oscillation circuit the s1c63654 has built-in the osc3 oscillation circuit that generates the cpu's sub-clock (max. 4 mhz) for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro- grammable timer, fout output). the mask option enables selection of the oscillator type from cr (external r type), cr (built-in r type) and ceramic oscillation circuit. when cr oscillation (external r type) is selected, only a resistance is required as an external element. when ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are required. when cr oscillation (built-in r type) is selected, no external element is required. figure 4.4.3.1 is the block diagram of the osc3 oscillation circuit. to cpu (and some peripheral circuits) oscillation circuit control signal (b) cr oscillation circuit (built-in r type) (c) ceramic oscillation circuit c cr r cr v ss c gc c dc ceramic osc4 osc3 r r dc to cpu (and some peripheral circuits) oscillation circuit control signal fc to cpu (and some peripheral circuits) oscillation circuit control signal (a) cr oscillation circuit (external r type) c cr osc3 osc4 r cr fi g. 4.4.3.1 osc3 oscillation circuit as shown in figure 4.4.3.1, the cr oscillation circuit (external r type) can be configured simply by connecting the resistor r cr between the osc3 and osc4 terminals when cr oscillation is selected. see chapter 7, "electrical characteristics" for resistance value of r cr . when ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (max. 4 mhz) between the osc3 and osc4 terminals, capacitor c gc between the osc3 and osc4 terminals, and capacitor c dc between the osc4 and v ss terminals. for both c gc and c dc , connect capacitors that are about 30 pf. to reduce current consumption of the osc3 oscillation circuit, oscillation can be stopped by the software (oscc register). t able 4.4.3.1 osc3 oscillation frequency oscillation circuit ceramic oscillation cr oscillation (built-in r type) cr oscillation (external r type) oscillation frequency max. 4 mhz (2 mhz note ) typ. 1.1 mhz 30% 200 khz to 2 mhz note: when selecting osc3 for the time base counter clock of the r/f converter, the maximum frequency of the osc3 clock is limited to 2 mhz.
34 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (oscillation circuit) 4.4.4 switching of operating voltage the cpu system clock is switched to osc1 or osc3 by the software (clkchg register). in this case, to obtain stable operation, the operating voltage for the internal circuits must be switched by the software (vdc0 register). when running with the osc1 clock: operating clock = v d1l (vdc0 = "0", vdc1 = "0") when running with the osc3 clock: operating clock = v d3 (vdc0 = "1", vdc1 = "1") the cpu clock should be switched using the following procedure. pay special attention to the stability waiting time for operating voltage and oscillation. note that the osc3 clock cannot be used as the system clock in the halver mode. when the low-speed operation voltage regulator is in the halver mode, return it to the normal mode before switching the operating voltage. osc1 osc3 1. set vdc2 to "0". (low-speed operation voltage regulator: halver mode normal mode) 2. set vdc1 to "1". (high-speed operation voltage regulator: off on) 3. set vdc0 to "1". (internal logic operating voltage: v d1l v d3 ) 4. wait 2.5 msec or more. 5. set oscc to "1". (osc3 oscillation: off on) 6. wait 5 msec or more. 7. set clkchg to "1". (cpu clock: osc1 osc3) osc3 osc1 1. set clkchg to "0". (cpu clock: osc3 osc1) 2. set oscc to "0". (osc3 oscillation: on off) 3. set vdc0 to "0". (internal logic operating voltage: v d3 v d1l ) 4. set the halver mode if necessary. refer to section 4.2, "power control", for the halver mode. 4.4.5 clock frequency and instruction execution time t able 4.4.5.1 shows the instruction execution time according to each frequency of the system clock. t able 4.4.5.1 clock frequency and instruction execution time clock frequency osc1: 32.768 khz osc3: 1.1 mhz osc3: 2 mhz osc3: 4 mhz instruction execution time ( sec) 1-cycle instruction 2-cycle instruction 3-cycle instruction 61 122 183 1.8 3.6 5.5 123 0.5 1 1.5
s1c63654 technical manual epson 35 chapter 4: peripheral circuits and operation (oscillation circuit) 4.4.6 i/o memory of oscillation circuit t able 4.4.6.1 shows the i/o address and the control bits for the oscillation circuit. t able 4.4.6.1 control bits of oscillation circuit address comment d3 d2 register d1 d0 name init ? 1 10 ff01h clkchg oscc 0 0 r/w r clkchg oscc 0 ? 3 0 ? 3 0 0 ? ? 2 ? ? 2 osc3 on osc1 off cpu clock switch osc3 oscillation on/off unused unused ff00h vdc3 vdc2 vdc1 vdc0 r/w vdc3 vdc2 vdc1 vdc0 0 0 0 0 1/2v dd 1/2v dd on v d3 v dd v dd off v d1l lcd system voltage regulator power source switch low-speed operation voltage regulator power source switch high-speed operation voltage regulator on/off logic system power source switch *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read vdc0: internal logic system power switching register (ff00h?0) it is used to switch the operating voltage for the cpu and internal circuit. when "1" is written: v d3 (for osc3 operation) when "0" is written: v d1l (for osc1 operation) reading: valid when "1" is written to vdc0, the internal operating voltage is switched to v d3 . after switching to v d3 , the osc3 oscillation can be started. when the low-speed operation voltage regulator is in the halver mode, return it to the normal mode before switching to v d3 . when "0" is written to vdc0, the internal operating voltage is switched to v d1l . stop the osc3 oscillation before switching to v d1l . at initial reset, this register is set to "0". oscc: osc3 oscillation control register (ff01h?2) t urns the osc3 oscillation circuit on and off. when "1" is written: osc3 oscillation on when "0" is written: osc3 oscillation off reading: valid when it is necessary to operate the cpu at high speed, set oscc to "1". at other times, set it to "0" to r educe current consumption. furthermore, it is necessary to switch the operating voltage when turning the osc3 oscillation circuit on and off. at initial reset, this register is set to "0". clkchg: cpu system clock switching register (ff01h?3) the cpu's operation clock is selected with this register. when "1" is written: osc3 clock is selected when "0" is written: osc1 clock is selected reading: valid when the cpu clock is to be osc3, set clkchg to "1"; for osc1, set clkchg to "0". after turning the osc3 oscillation on (oscc = "1"), switching of the clock should be done after waiting 5 msec or more. when vdc0 = "0" and oscc = "0" (osc3 oscillation is off), setting of clkchg = "1" becomes invalid and switching to osc3 is not performed. furthermore, do not switch the cpu clock to osc3 in the halver mode. at initial reset, this register is set to "0".
36 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (oscillation circuit) 4.4.7 programming notes (1) when switching the cpu system clock from osc1 to osc3, first set the operating voltage for high- speed operation (v d3 ). after that maintain 2.5 msec or more, and then turn the osc3 oscillation on. when switching from osc3 to osc1, set the operating voltage for low-speed operation (v d1l ) after switching to osc1 and turning the osc3 oscillation off. (2) it takes at least 5 msec from the time the osc3 oscillation circuit goes on until the oscillation stabi- lizes. consequently, when switching the cpu operation clock from osc1 to osc3, do this after a minimum of 5 msec have elapsed since the osc3 oscillation went on. further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (3) when switching the clock form osc3 to osc1, use a separate instruction for switching the osc3 oscillation off. an error in the cpu operation can result if this processing is performed at the same time by the one instruction. (4) when the low-speed operation voltage regulator is in the halver mode (vdc2 = "1"), the system can be operated only in low-speed using the osc1 clock. do not switch the system clock to osc3. (5) do not switch the operating voltage to v d1l while the cpu is operating with the osc3 clock. further- more, do not stop the high-speed operating voltage regulator. (6) when selecting osc3 for the time base counter clock of the r/f converter, the maximum frequency of the osc3 clock is limited to 2 mhz.
s1c63654 technical manual epson 37 chapter 4: peripheral circuits and operation (input ports) 4.5 input ports (k00?03 and k10?13) 4.5.1 configuration of input ports the s1c63654 has eight bits of general-purpose input ports (k00?03, k10?13). each input port termi- nal provides an internal pull-down resistor that can be enabled by mask option. figure 4.5.1.1 shows the configuration of input port. kxx mask option address v dd interrupt request data bus v ss fi g. 4.5.1.1 configuration of input port selection of "with pull-down resistor" with the mask option suits input from the push switch, key matrix, and so forth. when "gate direct" is selected, the port can be used for slide switch input and interfacing with other lsis. the k00 and k01 input ports can also be used as the run/stop and lap direct inputs for the stopwatch timer, and the k13 port can also be used as the event counter input for the programmable timer. 4.5.2 interrupt function all eight bits of the input ports (k00?03, k10?13) provide the interrupt function. the conditions for issuing an interrupt can be set by the software. further, whether to mask the interrupt function can be selected by the software. figure 4.5.2.1 shows the configuration of k00?03 (k10?13) interrupt circuit. input comparison register (kcp00, 10) k00, 10 interrupt request interrupt selection register (sik00, 10) address address address address interrupt factor flag (ik0, 1) k01, 11 k02, 12 k03, 13 interrupt mask register (eik0, 1) address data bus fi g. 4.5.2.1 input interrupt circuit configuration
38 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (input ports) the interrupt selection register (sik) and input comparison register (kcp) are individually set for the input ports k00?03 and k10?13, and can specify the terminals for generating interrupt and interrupt timing. the interrupt selection registers (sik00?ik03, sik10?ik13) select what input of k00?03 and k10?13 to use for the interrupt. writing "1" into an interrupt selection register incorporates that input port into the interrupt generation conditions. the changing the input port where the interrupt selection register has been set to "0" does not affect the generation of the interrupt. the input interrupt timing can select that the interrupt be generated at the rising edge of the input or that it be generated at the falling edge according to the set value of the input comparison registers (kcp00 kcp03, kcp10?cp13). by setting these two conditions, the interrupt for k00?03 or k10?13 is generated when input ports in which an interrupt has been enabled by the input selection registers and the contents of the input com- parison registers have been changed from matching to no matching. the interrupt mask registers (eik0, eik1) enable the interrupt mask to be selected for k00?03 and k10 k13. when the interrupt is generated, the interrupt factor flag (ik0, ik1) is set to "1". figure 4.5.2.2 shows an example of an interrupt for k00?03. interrupt selection register sik03 1 sik02 1 sik01 1 sik00 0 input port (1) (initial value) interrupt generation k03 1 k02 0 k01 1 k00 0 input comparison register kcp03 1 kcp02 0 kcp01 1 kcp00 0 with the above setting, the interrupt of k00?03 is generated under the following condition: (2) k03 1 k02 0 k01 1 k00 1 (3) k03 0 k02 0 k01 1 k00 1 (4) k03 0 k02 1 k01 1 k00 1 because k00 interrupt is set to disable, interrupt will be generated when no matching occurs between the contents of the 3 bits k01?03 and the 3 bits input comparison register kcp01?cp03. fi g. 4.5.2.2 example of interrupt of k00?03 k00 interrupt is disabled by the interrupt selection register (sik00), so that an interrupt does not occur at (2). at (3), k03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the data of the input comparison registers, so that interrupt occurs. as already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison registers from matching to no matching. hence, in (4), when the no matching status changes to another no matching status, an interrupt does not occur. further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. 4.5.3 mask option internal pull-down resistor can be selected for each of the eight bits of the input ports (k00?03, k10 k13) with the input port mask option. when "gate direct" is selected, take care that the floating status does not occur for the input. select "with pull-down resistor" for input ports that are not being used.
s1c63654 technical manual epson 39 chapter 4: peripheral circuits and operation (input ports) 4.5.4 i/o memory of input ports t able 4.5.4.1 shows the i/o addresses and the control bits for the input ports. t able 4.5.4.1 control bits of input ports address comment d3 d2 register d1 d0 name init ? 1 10 ff20h sik03 sik02 sik01 sik00 r/w sik03 sik02 sik01 sik00 0 0 0 0 enable enable enable enable disable disable disable disable k00?03 interrupt selection register ff21h k03 k02 k01 k00 r k03 k02 k01 k00 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low k00?03 input port data ff22h kcp03 kcp02 kcp01 kcp00 r/w kcp03 kcp02 kcp01 kcp00 1 1 1 1 k00?03 input comparison register ff24h sik13 sik12 sik11 sik10 r/w sik13 sik12 sik11 sik10 0 0 0 0 enable enable enable enable disable disable disable disable k10?13 interrupt selection register ff25h k13 k12 k11 k10 r k13 k12 k11 k10 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low k10?13 input port data ff26h kcp13 kcp12 kcp11 kcp10 r/w kcp13 kcp12 kcp11 kcp10 1 1 1 1 k10?13 input comparison register ffe3h 000ei k0 rr/w 0 ? 3 0 ? 3 0 ? 3 eik0 ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (k00?03) ffe4h 000ei k1 rr/w 0 ? 3 0 ? 3 0 ? 3 eik1 ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (k10?13) fff3h 000ik0 rr/w 0 ? 3 0 ? 3 0 ? 3 ik0 ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (k00?03) fff4h 000ik1 rr/w 0 ? 3 0 ? 3 0 ? 3 ik1 ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (k10?13) *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read k00?03: k0 port input port data (ff21h) k10?13: k1 port input port data (ff25h) input data of the input port terminals can be read with these registers. when "1" is read: high level when "0" is read: low level w riting: invalid the reading is "1" when the terminal voltage of the eight bits of the input ports (k00?03, k10?13) goes high (v dd ), and "0" when the voltage goes low (v ss ). these bits are dedicated for reading, so writing cannot be done.
40 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (input ports) sik00?ik03: k0 port interrupt selection register (ff20h) sik10?ik13: k1 port interrupt selection register (ff24h) selects the ports to be used for the k00?03 and k10?13 input interrupts. when "1" is written: enable when "0" is written: disable reading: valid enables the interrupt for the input ports (k00?03, k10?13) for which "1" has been written into the interrupt selection registers (sik00?ik03, sik10?ik13). the input port set for "0" does not affect the interrupt generation condition. at initial reset, these registers are set to "0". kcp00?cp03: k0 port input comparison register (ff22h) kcp10?cp13: k1 port input comparison register (ff26h) interrupt conditions for terminals k00?03 and k10?13 can be set with these registers. when "1" is written: falling edge when "0" is written: rising edge reading: valid the interrupt conditions can be set for the rising or falling edge of input for each of the eight bits (k00 k03 and k10?13), through the input comparison registers (kcp00?cp03 and kcp10?cp13). for kcp00?cp03, a comparison is done only with the ports that are enabled by the interrupt among k00?03 by means of the sik00?ik03 registers. for kcp10?cp13, a comparison is done only with the ports that are enabled by the interrupt among k10?13 by means of the sik10?ik13 registers. at initial reset, these registers are set to "1". eik0: k0 input interrupt mask register (ffe3h?0) eik1: k1 input interrupt mask register (ffe4h?0) masking the interrupt of the input port can be selected with these registers. when "1" is written: enable when "0" is written: mask reading: valid w ith these registers, masking of the input port interrupt can be selected for each of the two systems (k00 k03, k10?13). at initial reset, these registers are set to "0". ik0: k0 input interrupt factor flag (fff3h?0) ik1: k1 input interrupt factor flag (fff4h?0) these flags indicate the occurrence of input interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred when "1" is written: flag is reset when "0" is written: invalid the interrupt factor flags ik0 and ik1 are associated with k00?03 and k10?13, respectively. from the status of these flags, the software can decide whether an input interrupt has occurred. the interrupt factor flag is set to "1" when the interrupt condition is established regardless of the interrupt mask register setting. however, the interrupt does not occur to the cpu when the interrupt is masked. these flags are reset to "0" by writing "1" to them. after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. at initial reset, these flags are set to "0".
s1c63654 technical manual epson 41 chapter 4: peripheral circuits and operation (input ports) 4.5.5 programming notes (1) when input ports are changed from high to low by pull-down resistors, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. hence, when fetching input ports, set an appropriate waiting time. particular care needs to be taken of the key scan during key matrix configuration. make this waiting time the amount of time or more calculated by the following expression. 10 c r c: terminal capacitance 5 pf + parasitic capacitance ? pf r: pull-down resistance 375 k ? (max.) (2) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.
42 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (output ports) 4.6 output ports (r00?03) 4.6.1 configuration of output ports the s1c63654 has four bits of general output ports. output specifications of the output ports can be selected individually with the mask option. two kinds of output specifications are available: complementary output and p-channel open drain output. figure 4.6.1.1 shows the configuration of the output port. v dd v ss rxx data bus address data register address high impedance control register mask option fi g. 4.6.1.1 configuration of output port the r02 and r03 output terminals are shared with special output terminals (tout, fout), and this function is selected by the software. at initial reset, these are all set to the general purpose output port. t able 4.6.1.1 shows the setting of the output terminals by function selection. t able 4.6.1.1 function setting of output terminals terminal name r00 r01 r02 r03 terminal status at initial reset r00 (low output) r01 (low output) r02 (low output) r03 (low output) special output tout fout r00 r00 r01 r01 tout fout when using the output port (r02, r03) as the special output port, the data register must be fixed at "1" and the high impedance control register must be fixed at "0" (data output). 4.6.2 mask option output specifications of the output ports are selected by mask option. either complementary output or p-channel open drain output can be selected individually (in 1-bit units). however, when p-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the output port.
s1c63654 technical manual epson 43 chapter 4: peripheral circuits and operation (output ports) 4.6.3 high impedance control the output ports can be set into a high impedance status. this control is done using the high impedance control registers. the high impedance control registers are provided to correspond with the output ports as shown below. high impedance control register corresponding output port r00hiz r00 (1 bit) r01hiz r01 (1 bit) r02hiz r02 (1 bit) r03hiz r03 (1 bit) when "1" is written to the high impedance control register, the corresponding output port terminal goes into high impedance status. when "0" is written, the port outputs a signal according to the data register. 4.6.4 special output in addition to the regular dc output, special output can be selected for the output ports r02 and r03 as shown in table 4.6.4.1 with the software. figure 4.6.4.1 shows the configuration of the r02 and r03 output ports. t able 4.6.4.1 special output terminal r03 r02 special output fout tout output control register foute ptout data bus register ptout register r02 tout r02 (tout) register foute register r03 register r03hiz register r02hiz fout r03 (fout) fi g. 4.6.4.1 configuration of r02 and r03 output ports at initial reset, the output port data register is set to "0" and the high impedance control register is set to "0". consequently, the output terminal goes low (v ss ). when using the output port (r02, r03) as the special output port, fix the data register (r02, r03) at "1" and the high impedance control register (r02hiz, r03hiz) at "0" (data output). the respective signal should be turned on and off using the special output control register. note: be aware that the output terminal is fixed at a low (v ss ) level the same as the dc output if "0" is written to the r02 and r03 registers when the special output has been selected. be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (r02hiz, r03hiz).
44 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (output ports) ? out (r02) the r02 terminal can output a tout signal. the tout signal is the clock that is output from the programmable timer, and can be used to provide a clock signal to an external device. to output the tout signal, fix the r02 register at "1" and the r02hiz register at "0", and turn the signal on and off using the ptout register. it is, however, necessary to control the programmable timer. refer to section 4.11, "programmable timer" for details of the programmable timer. note: a hazard may occur when the tout signal is turned on and off. figure 4.6.4.2 shows the output waveform of the tout signal. r02hiz register r02 register ptout register tout output fix at "0" fix at "1" "1" "0" "0" fi g. 4.6.4.2 output waveform of tout signal fout (r03) the r03 terminal can output an fout signal. the fout signal is a clock (f osc1 or f osc3 ) that is output from the oscillation circuit or a clock that the f osc1 clock has divided in the internal circuit, and can be used to provide a clock signal to an external device. to output the fout signal, fix the r03 register at "1" and the r03hiz register at "0", and turn the signal on and off using the foute register. the frequency of the output clock may be selected from among 4 types shown in table 4.6.4.2 by setting the fofq0 and fofq1 registers. t able 4.6.4.2 fout clock frequency fofq1 1 1 0 0 fofq0 1 0 1 0 clock frequency f osc3 f osc1 f osc1 1/8 f osc1 1/64 f osc1 : clock that is output from the osc1 oscillation circuit f osc3 : clock that is output from the osc3 oscillation circuit when f osc3 is selected for the fout signal frequency, it is necessary to control the osc3 oscillation circuit before output. refer to section 4.4, "oscillation circuit", for the control and notes. note: a hazard may occur when the fout signal is turned on and off. figure 4.6.4.3 shows the output waveform of the fout signal. r03hiz register r03 register foute register fout output fix at "0" fix at "1" "1" "0" "0" fi g. 4.6.4.3 output waveform of fout signal
s1c63654 technical manual epson 45 chapter 4: peripheral circuits and operation (output ports) 4.6.5 i/o memory of output ports t able 4.6.5.1 shows the i/o addresses and control bits for the output ports. t able 4.6.5.1 control bits of output ports address comment d3 d2 register d1 d0 name init ? 1 10 ff06h foute swdir fofq1 fofq0 r/w foute swdir fofq1 fofq0 0 0 0 0 enable disable fout output enable stopwatch direct input switch 0: k00=run/stop, k01=lap 1: k00=lap, k01=run/stop fout frequency selection 0 f osc1 /64 1 f osc1 /8 2 f osc1 3 f osc3 [fofq1, 0] frequency ff30h r03hiz r02hiz r01hiz r00hiz r/w r03hiz r02hiz r01hiz r00hiz 0 0 0 0 hi-z hi-z hi-z hi-z output output output output r03 (foute=0)/fout (foute=1) hi-z control r02 (ptout=0)/tout (ptout=1) hi-z control r01 hi-z control r00 hi-z control ff31h r03 r02 r01 r00 r/w r03 r02 r01 r00 0 0 0 0 high high high high low low low low r03 output port data ( foute=0 ) fix at "1" when fout is used. r02 output port data ( ptout=0 ) fix at "1" when tout is used. r01 output port data r00 output port data 0 ? 3 0 ? 3 chsel0 ptout ? ? 2 ? ? 2 0 0 timer 1 on timer 0 off unused unused tout output selection tout output control rr/w ffc1h 00 chsel0 ptout *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read r00hiz?03hiz: r0 port high impedance control register (ff30h) controls high impedance output of the output port. when "1" is written: high impedance when "0" is written: data output reading: valid by writing "0" to the high impedance control register, the corresponding output terminal outputs accord- ing to the data register. when "1" is written, it shifts into high impedance status. when the output ports r02 and r03 are used for special output (tout, fout), fix the r02hiz register and the r03hiz register at "0" (data output). at initial reset, these registers are set to "0". r00?03: r0 output port data register (ff31h) set the output data for the output ports. when "1" is written: high level output when "0" is written: low level output reading: valid the output port terminals output the data written in the corresponding data registers without changing it. when "1" is written to the register, the output port terminal goes high (v dd ), and when "0" is written, the output port terminal goes low (v ss ). when the output ports r02 and r03 are used for special output (tout, fout), fix the r02 register and the r03 register at "1". at initial reset, these registers are all set to "0".
46 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (output ports) foute: fout output control register (ff06h?3) controls the fout output. when "1" is written: fout output on when "0" is written: fout output off reading: valid by writing "1" to the foute register when the r03 register has been set to "1" and the r03hiz register has been set to "0", the fout signal is output from the r03 terminal. when "0" is written, the r03 termi- nal goes low (v ss ). when using the r03 output port for dc output, fix this register at "0". at initial reset, this register is set to "0". fofq0, fofq1: fout frequency selection register (ff06h?0, d1) selects a frequency of the fout signal. t able 4.6.5.2 fout clock frequency fofq1 1 1 0 0 fofq0 1 0 1 0 clock frequency f osc3 f osc1 f osc1 1/8 f osc1 1/64 at initial reset, this register is set to "0". ptout: tout output control register (ffc1h?0) controls the tout output. when "1" is written: tout output on when "0" is written: tout output off reading: valid by writing "1" to the ptout register when the r02 register has been set to "1" and the r02hiz register has been set to "0", the tout signal is output from the r02 terminal. when "0" is written, the r02 termi- nal goes high (v dd ). when using the r02 output port for dc output, fix this register at "0". at initial reset, this register is set to "0". 4.6.6 programming notes (1) when using the output port (r02, r03) as the special output port, fix the data register (r02, r03) at "1" and the high impedance control register (r02hiz, r03hiz) at "0" (data output). be aware that the output terminal is fixed at a low (v ss ) level the same as the dc output if "0" is written to the r02 and r03 registers when the special output has been selected. be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (r02hiz, r03hiz). (2) a hazard may occur when the fout signal and the tout signal are turned on and off. (3) when f osc3 is selected for the fout signal frequency, it is necessary to control the osc3 oscillation circuit before output. refer to section 4.4, "oscillation circuit", for the control and notes.
s1c63654 technical manual epson 47 chapter 4: peripheral circuits and operation (i/o ports) 4.7 i/o ports (p00?03 and p10?13) 4.7.1 configuration of i/o ports the s1c63654 has eight bits of general-purpose i/o ports. figure 4.7.1.1 shows the configuration of the i/ o port. address data register data bus pxx address address address i/o control register (ioc) pull-down control register (pul) mask option v ss fi g. 4.7.1.1 configuration of i/o port the i/o port terminals p10 to p13 are shared with the serial interface input/output terminals. the software can select the function to be used. at initial reset, these terminals are all set to the i/o port. t able 4.7.1.1 shows the setting of the input/output terminals by function selection. t able 4.7.1.1 function setting of input/output terminals terminal p00?03 p10 p11 p12 p13 terminal status at initial reset p00?03 (input & pull-down ? ) p10 (input & pull-down ? ) p11 (input & pull-down ? ) p12 (input & pull-down ? ) p13 (input & pull-down ? ) serial i/f master p00?03 sin(i) sout(o) sclk(o) p13 slave p00?03 sin(i) sout(o) sclk(i) srdy(o) ? when "with pull-down resistor" is selected by the mask option (high impedance when "gate direct" is set) when these ports are used as i/o ports, the ports can be set to either input mode or output mode indi- vidually (in 1-bit unit). modes can be set by writing data to the i/o control registers. refer to section 4.12, "serial interface", for control of the serial interface.
48 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (i/o ports) 4.7.2 mask option the output specification of each i/o port during output mode can be selected from either complemen- tary output or p-channel open drain output by mask option. this selection can be done in 1-bit units. when p-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the port. the mask option also permits selection of whether the pull-down resistor is used or not during input mode. this selection can be done in 1-bit units. when "without pull-down" during the input mode is selected, take care that the floating status does not occur. the pull-down resistor for input mode and output specification (complementary output or p-channel open drain output) selected by mask option are effective even when i/o ports are used for input/output of the serial interface. 4.7.3 i/o control registers and input/output mode input or output mode can be set for the i/o ports by writing data into the corresponding i/o control r egisters iocxx. to set the input mode, write "0" to the i/o control register. when an i/o port is set to input mode, it becomes high impedance status and works as an input port. however, when the pull-down explained in the following section has been set by software, the input line is pulled down only during this input mode. to set the output mode, write "1" is to the i/o control register. when an i/o port is set to output mode, it works as an output port, it outputs a high level (v dd ) when the port output data is "1", and a low level (v ss ) when the port output data is "0". if perform the read out in each mode; when output mode, the register value is read out, and when input mode, the port value is read out. at initial reset, the i/o control registers are set to "0", and the i/o ports enter the input mode. the i/o control registers of the ports that are set as input/output for the serial interface can be used as general purpose registers that do not affect the i/o control. (see table 4.7.1.1.) 4.7.4 pull-down during input mode a pull-down resistor that operates during the input mode is built into each i/o port of the s1c63654. mask option can set the use or non-use of this pull-down. the pull-down resistor becomes effective by writing "1" to the pull-down control register pulxx that corresponds to each port, and the input line is pulled down during the input mode. when "0" has been written, no pull-down is done. at initial reset, the pull-down control registers are set to "1". the pull-down control registers of the ports in which "gate direct" has been selected can be used as general purpose registers. even when "with pull-down" has been selected, the pull-down control registers of the ports, that are set as output for the serial interface, can be used as general purpose registers that do not affect the pull-down control. (see table 4.7.1.1.) the pull-down control registers of the port, that are set as input for the serial interface, function the same as the i/o port.
s1c63654 technical manual epson 49 chapter 4: peripheral circuits and operation (i/o ports) 4.7.5 i/o memory of i/o ports t able 4.7.5.1 shows the i/o addresses and the control bits for the i/o ports. t able 4.7.5.1 control bits of i/o ports address comment d3 d2 register d1 d0 name init ? 1 10 ff40h ioc03 ioc02 ioc01 ioc00 r/w ioc03 ioc02 ioc01 ioc00 0 0 0 0 output output output output input input input input p00?03 i/o control register ff41h pul03 pul02 pul01 pul00 r/w pul03 pul02 pul01 pul00 1 1 1 1 on on on on off off off off p00?03 pull-down control register ff42h p03 p02 p01 p00 r/w p03 p02 p01 p00 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low p00?03 i/o port data ff70h 0 esout sctrg esif rr/w 0 ? 3 esout sctrg esif ? ? 2 0 0 0 enable trigger run sif disable invalid stop i/o unused sout enable serial i/f clock trigger (writing) serial i/f clock status (reading) serial i/f enable (p1 port function selection) ff44h ioc13 ioc12 ioc11 ioc10 r/w ioc13 ioc12 ioc11 ioc10 0 0 0 0 output output output output input input input input p13 i/o control register functions as a general-purpose register when sif (slave) is selected p12 i/o control register (esif=0) functions as a general-purpose register when sif is selected p11 i/o control register (esif=0) functions as a general-purpose register when sif is selected p10 i/o control register (esif=0) functions as a general-purpose register when sif is selected ff45h pul13 pul12 pul11 pul10 r/w pul13 pul12 pul11 pul10 1 1 1 1 on on on on off off off off p13 pull-down control register functions as a general-purpose register when sif (slave) is selected p12 pull-down control register (esif=0) functions as a general-purpose register when sif (master) is selected sclk (i) pull-down control register when sif (slave) is selected p11 pull-down control register (esif=0) functions as a general-purpose register when sif is selected p10 pull-down control register (esif=0) sin pull-down control register when sif is selected ff46h p13 (xsrdy) p12 (xsclk) p11 (sout) p10 (sin) r/w p13 p12 p11 p10 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low p13 i/o port data functions as a general-purpose register when sif (slave) is selected p12 i/o port data (esif=0) functions as a general-purpose register when sif is selected p11 i/o port data (esif=0) functions as a general-purpose register when sif is selected p10 i/o port data (esif=0) functions as a general-purpose register when sif is selected *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read
50 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (i/o ports) (1) selection of port function esif: serial interface enable register (ff70h?0) selects function for p10?13. when "1" is written: serial interface input/output port when "0" is written: i/o port reading: valid when using the serial interface, write "1" to this register and when p10?13 are used as the i/o port, write "0". the configuration of the terminals within p10?13 that are used for the serial interface is decided by the mode selected with the scs1 and scs0 registers (see section 4.12). in the slave mode, all the p10?13 ports are set to the serial interface input/output port. in the master mode, p10?12 are set to the serial interface input/output port and p13 can be used as the i/o port. furthermore, when the sout terminal is disabled (esout = "0"), p11 can be used as the i/o port. at initial reset, this register is set to "0". (2) i/o port control p00?03: p0 i/o port data register (ff42h) p10?13: p1 i/o port data register (ff46h) i/o port data can be read and output data can be set through these registers. ?when writing data when "1" is written: high level when "0" is written: low level when an i/o port is set to the output mode, the written data is output unchanged from the i/o port terminal. when "1" is written as the port data, the port terminal goes high (v dd ), and when "0" is written, the terminal goes low (v ss ). port data can be written also in the input mode. ?when reading data when "1" is read: high level when "0" is read: low level the terminal voltage level of the i/o port is read out. when the i/o port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the register value can be read. when the terminal voltage is high (v dd ) the port data that can be read is "1", and when the terminal voltage is low (v ss ) the data is "0". when "with pull-down resistor" has been selected with the mask option and the pul register is set to "1", the built-in pull-down resistor goes on during input mode, so that the i/o port terminal is pulled down. the data registers of the port, which are set for the input/output of the serial interface (p10?13), become general-purpose registers that do not affect the input/output. note: when in the input mode, i/o ports are changed from high to low by pull-down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. hence, when fetching input ports, set an appropriate wait time. pa rt icular care needs to be taken of the key scan during key matrix configuration. make this waiting time the amount of time or more calculated by the following expression. 10 c r c: terminal capacitance 5 pf + parasitic capacitance ? pf r: pull-down resistance 375 k ? (max.)
s1c63654 technical manual epson 51 chapter 4: peripheral circuits and operation (i/o ports) ioc00?oc03: p0 port i/o control register (ff40h) ioc10?oc13: p1 port i/o control register (ff44h) the input and output modes of the i/o ports are set with these registers. when "1" is written: output mode when "0" is written: input mode reading: valid the input and output modes of the i/o ports are set in 1-bit unit. wr iting "1" to the i/o control register makes the corresponding i/o port enter the output mode, and writing "0" induces the input mode. at initial reset, these registers are all set to "0", so the i/o ports are in the input mode. the i/o control registers of the port, which are set for the input/output of the serial interface (p10?13), become general-purpose registers that do not affect the input/output. pul00?ul03: p0 port pull-down control register (ff41h) pul10?ul13: p1 port pull-down control register (ff45h) the pull-down during the input mode are set with these registers. when "1" is written: pull-down on when "0" is written: pull-down off reading: valid the built-in pull-down resistor which is turned on during input mode is set to enable in 1-bit units. (the pull-down resistor is included into the ports selected by mask option.) by writing "1" to the pull-down control register, the corresponding i/o ports are pulled down (during input mode), while writing "0" disables the pull-down function. at initial reset, these registers are all set to "1", so the pull-down function is enabled. the pull-down control registers of the ports in which the pull-down resistor is not included become the general purpose register. the registers of the ports that are set as output for the serial interface can also be used as general purpose registers that do not affect the pull-down control. the pull-down control registers of the port that are set as input for the serial interface function the same as the i/o port. 4.7.6 programming note when in the input mode, i/o ports are changed from high to low by pull-down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci- tance. hence, when fetching input ports, set an appropriate wait time. particular care needs to be taken of the key scan during key matrix configuration. make this waiting time the amount of time or more calculated by the following expression. 10 c r c: terminal capacitance 5 pf + parasitic capacitance ? pf r: pull-down resistance 375 k ? (max.)
52 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (lcd driver) 4.8 lcd driver (com0?om5, seg0?eg31) 4.8.1 configuration of lcd driver the s1c63654 has 6 common terminals (com0?om5) and 32 segment terminals (seg0?eg31), so that it can drive an lcd with a maximum of 192 (32 6) segments. the driving method is 1/6 duty, 1/5 duty, 1/4 duty or 1/3 duty dynamic drive with three voltages (1/3 bias), v c1 , v c2 and v c3 . lcd display on/off can be controlled by the software. 4.8.2 power supply for lcd driving the power supply for driving lcd can be selected from the internal power supply and an external power supply. when the internal power supply is selected, the lcd drive voltages v c1 ? c3 are generated by the built-in lcd system voltage circuit. the lcd system voltage circuit is turned on and off using the lpwr register. when lpwr is set to "1", the lcd system voltage circuit outputs the lcd drive voltages v c1 ? c3 to the lcd driver. the lcd system voltage circuit generates v c1 with the voltage regulator built-in, and generates two other voltages (v c2 = 2v c1 , v c3 = 3v c1 ) by boosting v c1 . when using an external power supply, select the voltage from the following 3 types and supply the lcd drive voltage to the v c1 ? c3 terminals. 1) external power supply 1/3 bias (for 4.5 v panel) v dd = v c2 2) external power supply 1/3 bias (for 3.0 v panel) v dd = v c3 3) external power supply 1/2 bias (for 3.0 v panel) v dd = v c3 , v c1 = v c2 (static drive function is available) note that the power control using the lpwr register is necessary even if an external power supply is used. seg output ports that are set for dc output by the mask option operate same as the output (r) port r egardless of the power on/off control by the lpwr register. 4.8.3 control of lcd display and drive waveform (1) display on/off control the s1c63654 incorporates the alon and aloff registers to blink display. when "1" is written to alon, all the segments go on, and when "1" is written to aloff, all the segments go off. at such a time, an on waveform or an off waveform is output from seg terminals. when "0" is written to these r egisters, normal display is performed. furthermore, when "1" is written to both of the alon and aloff, alon (all on) has priority over the aloff (all off). (2) setting of drive duty in the s1c63654, the drive duty can be set to 1/6, 1/5, 1/4 or 1/3 using the lduty1 and lduty0 r egisters as shown in table 4.8.3.1. t able 4.8.3.1 lcd drive duty setting lduty1 1 1 0 0 lduty0 1 0 1 0 drive duty 1/3 1/6 1/5 1/4 common terminal used com0?om2 com0?om5 com0?om4 com0?om3 maximum segment number 96 (32 3) 192 (32 6) 160 (32 5) 128 (32 4) t able 4.8.3.2 shows the frame frequency corresponding to the drive duty. t able 4.8.3.2 frame frequency osc1 oscillation frequency 32.768 khz when 1/6 or 1/3 duty is selected 42.7 hz when 1/5 duty is selected 25.6 hz when 1/4 duty is selected 32 hz figures 4.8.3.1 to 4.8.3.4 show the dynamic drive waveform according to the duty.
s1c63654 technical manual epson 53 chapter 4: peripheral circuits and operation (lcd driver) com0 com1 com2 com3 com4 com5 seg0 | seg31 v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c2 v c1 not lit lit lcd lighting status com0 com1 com2 com3 com4 com5 seg0~31 frame ?? fi g. 4.8.3.1 dynamic drive waveform for 1/6 duty
54 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (lcd driver) com0 com1 com2 com3 com4 com5 seg0 | seg31 v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c2 v c1 v c2 v c1 not lit lit lcd lighting status com0 com1 com2 com3 com4 seg0~31 frame ?? fi g. 4.8.3.2 dynamic drive waveform for 1/5 duty
s1c63654 technical manual epson 55 chapter 4: peripheral circuits and operation (lcd driver) com0 com1 com2 com3 com4 com5 seg0 | seg31 v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c2 v c1 v c2 v c1 not lit lit lcd lighting status com0 com1 com2 com3 seg0~31 frame ?? fi g. 4.8.3.3 dynamic drive waveform for 1/4 duty
56 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (lcd driver) com0 com1 com2 com3 com4 com5 seg0 | seg31 v c3 v c2 v c1 v ss v c3 v c2 v c1 v ss v c2 v c1 v c2 v c1 not lit lit lcd lighting status com0 com1 com2 seg0~31 frame ?? fi g. 4.8.3.4 dynamic drive waveform for 1/3 duty
s1c63654 technical manual epson 57 chapter 4: peripheral circuits and operation (lcd driver) (3) static drive the s1c63654 provides software setting of the lcd static drive. however, this function is available only when "external power supply 1/2 bias (for 3.0 v panel)" is selected by mask option. to set in static drive, write "1" to the common output signal control register stcd. then, by writing "1" to any one of com0 to com5 (display memory) corresponding to the seg terminal, the seg terminal outputs a static on waveform. when all the com0 to com5 bits are set to "0", the seg terminal outputs a dynamic off waveform. figure 4.8.3.5 shows the static drive waveform. com 0? frame frequency -v c3 -v c2 -v c1 -v ss -v c3 -v c2 -v c1 -v ss -v c3 -v c2 -v c1 -v ss seg 0?1 lcd lighting status com0 com1 : com5 : : seg0?1 not lit lit fi g. 4.8.3.5 static drive waveform note: to use the static drive function, select the "external power supply 1/2 bias (for 3.0 v panel)" mask option. when an option for using the internal power supply or a 1/3 bias external power supply is selected, static drive cannot be set using the stcd register.
58 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (lcd driver) 4.8.4 display memory the display memory is allocated to f000h?02fh in the data memory area and each data bit can be allocated to an segment terminal (seg0?eg31) by mask option. when a bit in the display memory is set to "1", the corresponding lcd segment goes on, and when it is set to "0", the segment goes off. at initial reset, the data memory content becomes undefined hence, there is need to initialize using the software. the display memory has read/write capability, and the addresses that have not been used for lcd display can be used as general purpose registers. 4.8.5 segment option segment allocation the lcd driver has a segment decoder built-in, and the data bit (d0 d3) of the optional address in the display memory area (f000h?02fh) can be allocated to the optional segment. this makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed. figure 4.8.5.1 shows an example of the relationship between the lcd segments (on the panel) and the display memory for the case of 1/4 duty. a f g e d p c seg10 seg11 common 0 common 1 common 2 f020h f021h address d p d3 c g d2 b f d1 a e d0 data display memory allocation seg10 seg11 21, d1 (f) 20, d0 (a) 21, d0 (e) 21, d2 (g) 20, d2 (c) 20, d1 (b) pin address allocation common 0 common 1 common 2 20, d3 (d) 21, d3 (p) common 3 common 3 b fi g. 4.8.5.1 segment allocation output specification 1. the segment terminals (seg0 seg31) can be selected with the mask option in pairs ? for either segment signal output or dc output (v dd and v ss binary output). when dc output is selected, the data corresponding to com0 of each segment terminal is output. 2. when dc output is selected, either complementary output or n-channel open drain output can be selected for each terminal with the mask option. ? the terminal pairs are combination of seg2 n and seg2 n + 1 (where n is an integer from 0 to 15).
s1c63654 technical manual epson 59 chapter 4: peripheral circuits and operation (lcd driver) segment option list h: l: d: ram data high-order address (0?) ram data low-order address (0?) data bit (0?) s: c: n: segment output complementary output nch open drain output pin name seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 h l d com0 address (f0xx) h l d com1 h l d com2 h l d com3 h l d com4 h l d com5 seg output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output s dc output output specification
60 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (lcd driver) 4.8.6 lcd contrast adjustment in the s1c63654, the lcd contrast can be adjusted by the software. it is realized by controlling the voltages v c1 , v c2 and v c3 output from the lcd system voltage circuit. the contrast can be adjusted to 16 levels as shown in table 4.8.6.1. v c1 is changed within the range from 0.95 to 1.40 v (0.03 v step), and other voltages change according to v c1 . t able 4.8.6.1 lcd contrast no. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lc3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 lc2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 lc1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 lc0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 v c1 (v) 0.95 0.98 1.01 1.04 1.07 1.10 1.13 1.16 1.19 1.22 1.25 1.28 1.31 1.34 1.37 1.40 contrast light dark * * * * * * * ? do not set v c1 to 1.16 v or more (lc = 7 or more) when the lcd system voltage regulator is driven in the halver mode. at initial reset, the lc0?c3 are set to 0000b. the software should initialize the register to get the desired contrast. when an external power supply is selected by mask option, the lc0?c3 register becomes invalid.
s1c63654 technical manual epson 61 chapter 4: peripheral circuits and operation (lcd driver) 4.8.7 i/o memory of lcd driver t able 4.8.7.1 shows the i/o addresses and the control bits for the lcd driver. figure 4.8.7.1 shows the display memory map. t able 4.8.7.1 control bits of lcd driver address comment d3 d2 register d1 d0 name init ? 1 10 ff60h lduty1 lduty0 stcd lpwr r/w lduty1 lduty0 stcd lpwr 0 0 0 0 static on dynamic off lcd drive duty switch lcd drive switch lcd power on/off ff61h 0 aloff alon 0 rr r/w 0 ? 3 aloff alon 0 ? 3 ? ? 2 1 0 ? ? 2 all off all on normal normal unused lcd all off control lcd all on control unused ff62h lc3 lc2 lc1 lc0 r/w lc3 lc2 lc1 lc0 0 0 0 0 0 light 15 dark [lc3?] contrast lcd contrast adjustment 0 1/4 1 1/5 2 1/6 3 1/3 [lduty1, 0] duty *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read address base low 0123456789abcde f f000h f010h f020h display memory (48 words 4 bits) r/w fi g. 4.8.7.1 display memory map lpwr: lcd power control (on/off) register (ff60h?0) tu rns the lcd system voltage circuit on and off. when "1" is written: on when "0" is written: off reading: valid when "1" is written to the lpwr register, the lcd system voltage circuit goes on and generates the lcd drive voltage. when "0" is written, all the lcd drive voltages go to v ss level. it takes about 100 msec for the lcd drive voltage to stabilize after starting up the lcd system voltage circuit by writing "1" to the lpwr register. this control does not affect to seg terminals that have been set for dc output. at initial reset, this register is set to "0". lduty0, lduty1: lcd drive duty switching register (ff60h?2, d3) selects the lcd drive duty. t able 4.8.7.2 drive duty setting lduty1 1 1 0 0 lduty0 1 0 1 0 drive duty 1/3 1/6 1/5 1/4 common terminal used com0?om2 com0?om5 com0?om4 com0?om3 maximum segment number 96 (32 3) 192 (32 6) 160 (32 5) 128 (32 4) at initial reset, this register is set to "0".
62 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (lcd driver) stcd: lcd drive switch register (ff60h?1) switches the lcd driving method. when "1" is written: static drive when "0" is written: dynamic drive reading: valid by writing "1" to stcd, static drive is selected, and dynamic drive is selected when "0" is written. at initial reset, this register is set to "0". alon: lcd all on control register (ff61h?1) displays the all lcd segments on. when "1" is written: all lcd segments displayed when "0" is written: normal display reading: valid by writing "1" to the alon register, all the lcd segments go on, and when "0" is written, it returns to normal display. this function outputs an on waveform to the seg terminals, and segments not affect the content of the display memory. alon has priority over aloff. at initial reset, this register is set to "0". aloff: lcd all off control register (ff61h?2) fade outs the all lcd segments. when "1" is written: all lcd segments fade out when "0" is written: normal display reading: valid by writing "1" to the aloff register, all the lcd segments go off, and when "0" is written, it returns to normal display. this function outputs an off waveform to the seg terminals, and does not affect the content of the display memory. alon (ff61h?1) has priority over aloff, so all the lcd segments go on when alon and aloff are set to "1" simultaneously. at initial reset, this register is set to "1". lc3?c0: lcd contrast adjustment register (ff62h) adjusts the lcd contrast. lc3?c0 = 0000b light :: lc3?c0 = 1111b dark when the lcd drive voltage is supplied from outside by mask option selection, this adjustment becomes invalid. at initial reset, lc0?c3 is set to 0000b. 4.8.8 programming note because at initial reset, the contents of display memory are undefined and lc3?c0 (lcd contrast) is set to 0000b, there is need to initialize by the software. furthermore, take care of the registers lpwr and aloff because these are set so that the display goes off.
s1c63654 technical manual epson 63 chapter 4: peripheral circuits and operation (clock timer) 4.9 clock timer 4.9.1 configuration of clock timer the s1c63654 has a built-in clock timer that uses osc1 (crystal oscillator) as the source oscillator. the clock timer is configured of an 8-bit binary counter that serves as the input clock, f osc1 divided clock output from the prescaler. timer data (128?6 hz and 8? hz) can be read out by the software. figure 4.9.1.1 is the block diagram for the clock timer. 128 hz?6 hz data bus 32 hz, 8 hz, 2 hz, 1 hz 256 hz clock timer reset signal divider interrupt request interrupt control 8 hz? hz clock timer run/stop signal clock timer osc1 oscillation circuit (f osc1 ) fig. 4. 9.1.1 block diagram for the clock timer ordinarily, this clock timer is used for all types of timing functions such as clocks. 4.9.2 data reading and hold function the 8 bits timer data are allocated to the address ff75h and ff76h. d0: tm0 = 128 hz d1: tm1 = 64 hz d2: tm2 = 32 hz d3: tm3 = 16 hz d0: tm4 = 8 hz d1: tm5 = 4 hz d2: tm6 = 2 hz d3: tm7 = 1 hz since the clock timer data has been allocated to two addresses, a carry is generated from the low-order data within the count (tm0?m3: 128?6 hz) to the high-order data (tm4?m7: 8? hz). when this carry is generated between the reading of the low-order data and the high-order data, a content combining the two does not become the correct value (the low-order data is read as ffh and the high-order data becomes the value that is counted up 1 from that point). the high-order data hold function in the s1c63654 is designed to operate to avoid this. this function temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point where the low-order data has been read and consequently the time during which the high-order data is held is the shorter of the two indicated here following. 1. period until it reads the high-order data. 2. 0.48?.5 msec (varies due to the read timing.) note: since the low-order data is not held when the high-order data has previously been read, the low- order data should be read first.
64 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (clock timer) 4.9.3 interrupt function the clock timer can cause interrupts at the falling edge of 32 hz, 8 hz, 2 hz and 1 hz signals. software can set whether to mask any of these frequencies. figure 4.9.3.1 is the timing chart of the clock timer. address ff75h ff76h 32 hz interrupt request 8 hz interrupt request 2 hz interrupt request 1 hz interrupt request bit d0 d1 d2 d3 d0 d1 d2 d3 frequency clock timer timing chart 128 hz 64 hz 32 hz 16 hz 8 hz 4 hz 2 hz 1 hz fi g. 4.9.3.1 timing chart of clock timer as shown in figure 4.9.3.1, interrupt is generated at the falling edge of the frequencies (32 hz, 8 hz, 2 hz, 1 hz). at this time, the corresponding interrupt factor flag (it0, it1, it2, it3) is set to "1". selection of whether to mask the separate interrupts can be made with the interrupt mask registers (eit0, eit1, eit2, eit3). however, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal.
s1c63654 technical manual epson 65 chapter 4: peripheral circuits and operation (clock timer) 4.9.4 i/o memory of clock timer t able 4.9.4.1 shows the i/o addresses and the control bits for the clock timer. t able 4.9.4.1 control bits of clock timer address comment d3 d2 register d1 d0 name init ? 1 10 wr/w r ff74h 00 tmrst tmrun 0 ? 3 0 ? 3 tmrst ? 3 tmrun ? ? 2 ? ? 2 reset 0 reset run invalid stop unused unused clock timer reset (writing) clock timer run/stop r ff75h tm3 tm2 tm1 tm0 tm3 tm2 tm1 tm0 0 0 0 0 clock timer data (16 hz) clock timer data (32 hz) clock timer data (64 hz) clock timer data (128 hz) r ff76h tm7 tm6 tm5 tm4 tm7 tm6 tm5 tm4 0 0 0 0 clock timer data (1 hz) clock timer data (2 hz) clock timer data (4 hz) clock timer data (8 hz) ffe5h eit3 eit2 eit1 eit0 r/w eit3 eit2 eit1 eit0 0 0 0 0 enable enable enable enable mask mask mask mask interrupt mask register (clock timer 1 hz) interrupt mask register (clock timer 2 hz) interrupt mask register (clock timer 8 hz) interrupt mask register (clock timer 32 hz) fff5h it3 it2 it1 it0 r/w it3 it2 it1 it0 0 0 0 0 (r) yes (w) reset (r) no (w) invalid interrupt factor flag (clock timer 1 hz) interrupt factor flag (clock timer 2 hz) interrupt factor flag (clock timer 8 hz) interrupt factor flag (clock timer 32 hz) *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read tm0?m7: timer data (ff75h, ff76h) the 128? hz timer data of the clock timer can be read out with these registers. these eight bits are read only, and writing operations are invalid. by reading the low-order data (ff75h), the high-order data (ff76h) is held until reading or for 0.48?.5 msec (one of shorter of them). at initial reset, the timer data is initialized to "00h". tmrst: clock timer reset (ff74h?1) this bit resets the clock timer. when "1" is written: clock timer reset when "0" is written: no operation reading: always "0" the clock timer is reset by writing "1" to tmrst. when the clock timer is reset in the run status, opera- tion restarts immediately. also, in the stop status the reset data is maintained. no operation results when "0" is written to tmrst. this bit is write-only, and so is always "0" at reading. tmrun: clock timer run/stop control register (ff74h?0) controls run/stop of the clock timer. when "1" is written: run when "0" is written: stop reading: valid the clock timer enters the run status when "1" is written to the tmrun register, and the stop status when "0" is written. in the stop status, the timer data is maintained until the next run status or the timer is reset. also, when the stop status changes to the run status, the data that is maintained can be used for resuming the count. at initial reset, this register is set to "0".
66 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (clock timer) eit0: 32 hz interrupt mask register (ffe5h?0) eit1: 8 hz interrupt mask register (ffe5h?1) eit2: 2 hz interrupt mask register (ffe5h?2) eit3: 1 hz interrupt mask register (ffe5h?3) these registers are used to select whether to mask the clock timer interrupt. when "1" is written: enabled when "0" is written: masked reading: valid the interrupt mask registers (eit0, eit1, eit2, eit3) are used to select whether to mask the interrupt to the separate frequencies (32 hz, 8 hz, 2 hz, 1 hz). at initial reset, these registers are set to "0". it0: 32 hz interrupt factor flag (fff5h?0) it1: 8 hz interrupt factor flag (fff5h?1) it2: 2 hz interrupt factor flag (fff5h?2) it3: 1 hz interrupt factor flag (fff5h?3) these flags indicate the status of the clock timer interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred when "1" is written: flag is reset when "0" is written: invalid the interrupt factor flags (it0, it1, it2, it3) correspond to the clock timer interrupts of the respective frequencies (32 hz, 8 hz, 2 hz, 1 hz). the software can judge from these flags whether there is a clock timer interrupt. however, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. these flags are reset to "0" by writing "1" to them. after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. at initial reset, these flags are set to "0". 4.9.5 programming notes (1) be sure to read timer data in the order of low-order data (tm0?m3) then high-order data (tm4 tm7). (2) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.
s1c63654 technical manual epson 67 chapter 4: peripheral circuits and operation (stopwatch timer) 4.10 stopwatch timer 4.10.1 configuration of stopwatch timer the s1c63654 has a 1/1,000 sec stopwatch timer. the stopwatch timer is configured of a 3-stage, 4-bit bcd counter serving as the input clock of a 1,000 hz signal output from the prescaler. data can be read out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software. in addition it has a direct input function that controls the stopwatch timer run/stop and lap using the input ports k00 and k01. figure 4.10.1.1 is the block diagram of the stopwatch timer. data bus 1 hz interrupt request 1,000 / 1,024 prescaler f osc1 /32 (1,024 hz) 1/1,000 sec counter 1/100 sec counter 1/10 sec counter capture buffer swd0? reading swd4? reading swd8?1 reading [swrst] 10 hz interrupt request capture control circuit [swrun] [edir] [crnwf] [dkm2?] [lcurf] direct run interrupt request direct lap interrupt request (1,000 hz) direct input control [swdir] k01 k00 k02?13 fi g. 4.10.1.1 block diagram of stopwatch timer the stopwatch timer can be used as a separate timer from the clock timer. in particular, digital watch stopwatch functions can be realized easily with software. 4.10.2 counter and prescaler the stopwatch timer is configured of four-bit bcd counters swd0?, swd4? and swd8?1. the counter swd0?, at the stage preceding the stopwatch timer, has a 1,000 hz signal generated by the prescaler for the input clock. it counts up every 1/1,000 sec, and generates 100 hz signal. the counter swd4? has a 100 hz signal generated by the counter swd0? for the input clock. it count-up every 1/100 sec, and generated 10 hz signal. the counter swd8?1 has an approximated 10 hz signal gener- ated by the counter swd4? for the input clock. it count-up every 1/10 sec, and generated 1 hz signal. the prescaler inputs a 1,024 hz clock dividing f osc1 (output from the osc1 oscillation circuit), and outputs 1,000 hz counting clock for swd0?. to generate a 1,000 hz clock from 1,024 hz, 24 pulses from 1,024 pulses that are input to the prescaler every second are taken out. when the counter becomes the value indicated below, one pulse (1,024 hz) that is input immediately after to the prescaler will be pulled out. 39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979
68 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (stopwatch timer) figure 4.10.2.1 shows the operation of the prescaler. prescaler input clock (1,024 hz) prescaler output clock counter data start 000 001 002 037 038 039 040 041 fi g. 4.10.2.1 timing of the prescaler operation for the above reason, the counting clock is 1,024 hz (0.9765625 msec) except during pulse correction. consequently, frequency of the prescaler output clock (1,000 hz), 100 hz generated by swd0? and 10 hz generated by swd4? are approximate values. 4.10.3 capture buffer and hold function the stopwatch data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from swd0? (ff7ah), swd4? (ff7bh) and swd8?1 (ff7ch), respectively. the counter data are latched in the capture buffer when r eading, and are held until reading of three words is completed. for this reason, correct data can be read even when a carry from lower digits occurs during reading the three words. further, three counter data are latched in the capture buffer at the same time when swd0? (1/1,000 sec) is read. the data hold is r eleased when swd8?1 (1/10 sec) reading is completed. therefore, data should be read in order of swd0? swd4? swd8?1. if swd4? or swd8?1 is first read when data have not been held, the hold function does not work and data in the counter is directly read out. when data that has not been held is read in the stopwatch timer run status, you cannot judge whether it is correct or not. the stopwatch timer has a lap function using an external key input (explained later). the capture buffer is also used to hold lap data. in this case, data is held until swd8?1 is read. however, when a lap input is performed before completing the reading, the content of the capture buffer is renewed at that point. remaining data that have not been read become invalid by the renewal, and the hold status is not r eleased if swd8?1 is read. when swd8?1 is read after the capture buffer is updated, the capture r enewal flag is set to "1" at that point. in this case, it is necessary to read from swd0? again. the capture r enewal flag is renewed by reading swd8?1. figure 4.10.3.1 shows the timing for data holding and reading. direct lap input (k01/k00) direct lap internal signal capture renewal flag crnwf swd0? reading swd4? reading swd8?1 reading data holding fi g. 4.10.3.1 timing for data holding and reading
s1c63654 technical manual epson 69 chapter 4: peripheral circuits and operation (stopwatch timer) 4.10.4 stopwatch timer run/stop and reset run/stop control and reset of the stopwatch timer can be done by the software. stopwatch timer run/stop the stopwatch timer enters the run status when "1" is written to swrun, and the stop status when "0" is written. in the stop status, the timer data is maintained until the next run status or resets timer. also, when the stop status changes to the run status, the data that was maintained can be used for resuming the count. the run/stop operation of the stopwatch timer by writing to the swrun register is performed in synchronization with the falling edge of the 1,024 hz same as the prescaler input clock. the swrun register can be read, and in this case it indicates the operating status of the stopwatch timer. figure 4.10.4.1 shows the operating timing when controlling the swrun register. f osc1 /32 (1,024 hz) swrun writing swrun register count clock fi g. 4.10.4.1 operating timing when controlling swrun when the direct input function (explained in next section) is set, run/stop control is done by an external key input. in this case, swrun becomes read only register that indicates the operating status of the stopwatch timer. stopwatch timer reset the stopwatch timer is reset when "1" is written to swrst. with this, the counter value is cleared to "000". since this resetting does not affect the capture buffer, data that has been held in the capture buffer is not cleared and is maintained as is. when the stopwatch timer is reset in the run status, counting restarts from count "000". also, in the stop status the reset data "000" is maintained until the next run. 4.10.5 direct input function and key mask the stopwatch timer has a direct input function that can control the run/stop and lap operation of the stopwatch timer by external key input. this function is set by writing "1" to the edir register. when edir is set to "0", only the software control is possible as explained in the previous section. input port configuration in the direct input function, the input ports k00 and k01 are used as the run/stop and lap input ports. the key assignment can be selected using the swdir register. t able 4.10.5.1 run/stop and lap input ports swdir 0 1 k00 run/stop lap k01 lap run/stop direct run when the direct input function is selected, run/stop operation of the stopwatch timer can be controlled by using the key connected to the input port k00/k01 (selected by swdir). k00/k01 works as a normal input port, but the input signal is sent to the stopwatch control circuit. the key input signal from the k00/k01 port works as a toggle switch. when it is input in stop status, the stopwatch timer runs, and in run status, the stopwatch timer stops. run/stop status of the stopwatch timer can be checked by reading the swrun register. an interrupt is generated by direct run input. the sampling for key input signal is performed at the falling edge of 1,024 hz signal same as the swrun control. the chattering judgment is performed at the point where the key turns off, and a chattering less than 46.8?2.5 msec is removed. therefore, more time is needed for an interval be- tween run and stop key inputs.
70 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (stopwatch timer) figure 4.10.5.1 shows the operating timing for the direct run input. f osc1 /32 (1,024 hz) direct run input (k00/k01) direct run internal signal swrun register count clock direct run interrupt fi g. 4.10.5.1 operating timing for direct run input direct lap control for the lap can also be done by key input same as the direct run. when the direct input function is selected, the input port k01/k00 (selected by swdir) becomes the lap key input port. sampling for the input signal and the chattering judgment are the same as a direct run. by entering the lap key, the counter data at that point is latched into the capture buffer and is held. the counter continues counting operation. furthermore, an interrupt occurs by direct lap input. as stated above, the capture buffer data is held until swd8?1 is read. if the lap key is input when data has been already held, it renews the content of the capture buffer. when swd8?1 is read after r enewing, the capture renewal flag is set to "1". in this case, the hold status is not released by reading swd8?1, and it continues. normally the lap data should be read after the interrupt is generated. after that, be sure to check the capture renewal flag. when the capture renewal flag is set, renewed data is held in the capture buffer. so it is necessary to read from swd0? again. the stopwatch timer sets the 1 hz interrupt factor flag isw1 to "1" when requiring a carry-up to 1-sec digit by an swd8?1 overflow. if the capture buffer shifts into hold status (when swd0? is read or when lap is input) while the 1 hz interrupt factor flag isw1 is set to "1", the lap data carry-up r equest flag lcurf is set to "1" to indicate that a carry-up to 1-sec digit is required for the processing of lap input. in normal software processing, lap processing may take precedence over 1-sec or higher digits processing by a 1 hz interrupt, therefore carry-up processing using this flag should be used for time display in the lap processing to prevent the 1-sec digit data decreasing by 1 second. this flag is renewed when the capture buffer shifts into hold status. figure 4.10.5.2 shows the operating timing for the direct lap input, and figure 4.10.5.3 shows the timings for data holding and reading during a direct lap input and reading. f osc1 /32 (1,024 hz) direct lap input (k01/k00) direct lap internal signal data holding direct lap interrupt swd8?1 reading fi g. 4.10.5.2 operating timing for direct lap input direct lap input (k01/k00) capture renewal flag crnwf swd0? reading swd4? reading swd8?1 reading data holding 1 hz interrupt factor flag isw1 lap data carry-up request flag lcurf counter data 999 000 fi g. 4.10.5.3 timing for data holding and reading during direct lap input
s1c63654 technical manual epson 71 chapter 4: peripheral circuits and operation (stopwatch timer) key mask in stopwatch applications, some functions may be controlled by a combination of keys including direct run or direct lap. for instance, the run key can be used for other functions, such as reset and setting a watch, by pressing the run key with another key. in this case, the direct run function or direct lap function must be invalid so that it does not function. for this purpose, the key mask function is set so that it judges concurrence of input keys and invalidates run and lap functions. a combination of the key inputs for this judgment can be selected using the dkm0?km2 registers. t able 4.10.5.2 key mask selection dkm2 0 0 0 0 1 1 1 1 dkm1 0 0 1 1 0 0 1 1 dkm0 0 1 0 1 0 1 0 1 mask key combination none (at initial reset) k02 k02, k03 k02, k03, k10 k10 k10, k11 k10, k11, k12 k10, k11, k12, k13 run or lap inputs become invalid in the following status. 1. the run or lap key is pressed when one or more keys that are included in the selected combina- tion (here in after referred to as mask) are held down. 2. the run or lap key has been pressed when the mask is released. f osc1 /32 (1,024 hz) direct run/lap input key mask valid invalid invalid invalid fig. 4. 10.5.4 operation of key mask run or lap inputs become valid in the following status. 1. either the run or lap key is pressed independently if no other key is been held down. 2. both the run and lap keys are pressed at the same time if no other key is held down. (run and lap functions are effective.) 3. the run or lap key is pressed if either is held down. (run and lap functions are effective.) 4. either the run or lap key and the mask key are pressed at the same time if no other key is held down. 5. both the run and lap keys and the mask key are pressed at the same time if no other key is held down. (run and lap functions are effective.) * simultaneous key input is referred to as two or more key inputs are sampled at the same falling edge of 1,024 hz clock.
72 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (stopwatch timer) 4.10.6 interrupt function 10 hz and 1 hz interrupts the 10 hz and 1 hz interrupts can be generated through the overflow of stopwatch timers swd4? and swd8?1 respectively. also, software can set whether to separately mask the frequencies de- scribed earlier. figure 4.10.6.1 is the timing chart for the counters. 10 hz interrupt request 1 hz interrupt request ff7ch (1/10 sec bcd) ff7bh (1/100 sec bcd) d0 d1 d2 d3 d0 d1 d2 d3 address register stopwatch timer (swd0?) timing chart ff7ah (1/1,000 sec bcd) d0 d1 d2 d3 address register stopwatch timer (swd4?) timing chart address register stopwatch timer (swd8?1) timing chart fi g. 4.10.6.1 timing chart for counters as shown in figure 4.10.6.1, the interrupts are generated by the overflow of their respective counters ("9" changing to "0"). also, at this time the corresponding interrupt factor flag (isw10, isw1) is set to "1". the respective interrupts can be masked separately through the interrupt mask registers (eisw10, eisw1). however, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters.
s1c63654 technical manual epson 73 chapter 4: peripheral circuits and operation (stopwatch timer) direct run and direct lap interrupts when the direct input function is selected, the direct run and direct lap interrupts can be generated. the respective interrupts occur at the rising edge of the internal signal for direct run and direct lap after sampling the direct input signal in the falling edge of 1,024 hz signal. also, at this time the corresponding interrupt factor flag (irun, ilap) is set to "1". the respective interrupts can be masked separately through the interrupt mask registers (eirun, eilap). however, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the inputs of the run and lap. the direct run and lap functions use the k00 and k01 ports. therefore, the direct input interrupt and the k00?03 inputs interrupt may generate at the same time depending on the interrupt condi- tion setting for the input port k00?03. consequently, when using the direct input interrupt, set the interrupt selection registers sik00 and sik01 to "0" so that the input interrupt does not generate by k00 and k01 inputs. f osc1 /32 (1,024 hz) swrst writing edir writing edir register direct run input swrun writing swrun register direct lap input counter data capture buffer swd0? reading swd4? reading swd8?1 reading crnwf 1 hz interrupt factor flag isw1 lcurf direct run interrupt direct lap interrupt 10 hz interrupt 1 hz interrupt 001 002 003 004 005 006 098 099 100 101 102 000 001 002 003 004 005 006 007 993 994 000 995 996 997 998 999 000 001 002 003 004 005 006 007 003 005 995 001 006 fi g. 4.10.6.2 timing chart for stopwatch timer
74 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (stopwatch timer) 4.10.7 i/o memory of stopwatch timer t able 4.10.7.1 shows the i/o addresses and the control bits for the stopwatch timer. t able 4.10.7.1 control bits of stopwatch timer address comment d3 d2 register d1 d0 name init ? 1 10 ff06h foute swdir fofq1 fofq0 r/w foute swdir fofq1 fofq0 0 0 0 0 enable disable fout output enable stopwatch direct input switch 0: k00=run/stop, k01=lap 1: k00=lap, k01=run/stop fout frequency selection 0 f osc1 /64 1 f osc1 /8 2 f osc1 3 f osc3 [fofq1, 0] frequency swd7 swd6 swd5 swd4 0 0 0 0 stopwatch timer data bcd (1/100 sec) r ff7bh swd7 swd6 swd5 swd4 swd11 swd10 swd9 swd8 0 0 0 0 stopwatch timer data bcd (1/10 sec) r ff7ch swd11 swd10 swd9 swd8 r ff7ah swd3 swd2 swd1 swd0 swd3 swd2 swd1 swd0 0 0 0 0 stopwatch timer data bcd (1/1000 sec) 0 none 1 k02 2 k02?3 3 k02?3,10 [dkm2, 1, 0] key mask 4 k10 5 k10?1 6 k10?2 7 k10?3 [dkm2, 1, 0] key mask r/w ff78h edir dkm2 dkm1 dkm0 edir dkm2 dkm1 dkm0 0 0 0 0 enable disable direct input enable key mask selection r/w w r ff79h lcurf crnwf swrun swrst lcurf crnwf swrun swrst ? 3 0 0 0 reset request renewal run reset no no stop invalid lap data carry-up request flag capture renewal flag stopwatch timer run/stop stopwatch timer reset (writing) ffe6h eirun eilap eisw1 eisw10 r/w eirun eilap eisw1 eisw10 0 0 0 0 enable enable enable enable mask mask mask mask interrupt mask register (stopwatch direct run) interrupt mask register (stopwatch direct lap) interrupt mask register (stopwatch timer 1 hz) interrupt mask register (stopwatch timer 10 hz) fff6h irun ilap isw1 isw10 r/w irun ilap isw1 isw10 0 0 0 0 (r) yes (w) reset (r) no (w) invalid interrupt factor flag (stopwatch direct run) interrupt factor flag (stopwatch direct lap) interrupt factor flag (stopwatch timer 1 hz) interrupt factor flag (stopwatch timer 10 hz) *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read swd0?wd3: stopwatch timer data 1/1,000 sec (ff7ah) data (bcd) of the 1/1,000 sec column of the capture buffer can be read out. the hold function of the capture buffer works by reading this data. these 4 bits are read-only, and cannot be used for writing operations. at initial reset, the timer data is set to "0". swd4?wd7: stopwatch timer data 1/100 sec (ff7bh) data (bcd) of the 1/100 sec column of the capture buffer can be read out. these 4 bits are read-only, and cannot be used for writing operations. at initial reset, the timer data is set to "0". swd8?wd11: stopwatch timer data 1/10 sec (ff7ch) data (bcd) of the 1/10 sec column of the capture buffer can be read out. these 4 bits are read-only, and cannot be used for writing operations. at initial reset, the timer data is set to "0". note: be sure to data reading in the order of swd0? swd4? swd8?1.
s1c63654 technical manual epson 75 chapter 4: peripheral circuits and operation (stopwatch timer) edir: direct input function enable register (ff78h?3) enables the direct input (run/lap) function. when "1" is written: enabled when "0" is written: disabled reading: valid the direct input function is enabled by writing "1" to edir, and then run/stop and lap control can be done by external key input. when "0" is written, the direct input function is disabled, and the stopwatch timer is controlled by the software only. further the function switching is actually done by synchronizing with the falling edge of f osc1 /32 (1,024 hz) after the data is written to this register (after 977 ?ec maximum). at initial reset, this register is set to "0". swdir: direct input switch register (ff06h?2) switches the direct-input key assignment for the k00 and k01 ports. when "1" is written: k00 = lap, k01 = run/stop when "0" is written: k00 = run/stop, k01 = lap reading: valid the direct-input key assignment is selected using this register. the k00 and k01 port statuses are input to the stopwatch timer as the run/stop and lap inputs according to this selection. at initial reset, this register is set to "0". dkm0?km2: direct key mask selection register (ff78h?0?2) selects a combination of the key inputs for concurrence judgment with run and lap inputs when the direct input function is set. t able 4.10.7.2 key mask selection dkm2 0 0 0 0 1 1 1 1 dkm1 0 0 1 1 0 0 1 1 dkm0 0 1 0 1 0 1 0 1 mask key combination none (at initial reset) k02 k02, k03 k02, k03, k10 k10 k10, k11 k10, k11, k12 k10, k11, k12, k13 when the concurrence is detected, run and lap inputs cannot be accepted until the concurrence is r eleased. at initial reset, this register is set to "0". swrst: stopwatch timer reset (ff79h?0) this bit resets the stopwatch timer. when "1" is written: stopwatch timer reset when "0" is written: no operation reading: always "0" the stopwatch timer is reset when "1" is written to swrst. when the stopwatch timer is reset in the run status, operation restarts immediately. also, in the stop status the reset data is maintained. since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and is maintained. this bit is write-only, and is always "0" at reading.
76 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (stopwatch timer) swrun: stopwatch timer run/stop (ff79h?1) this register controls the run/stop of the stopwatch timer, and the operating status can be monitored by reading this register. ?when writing data when "1" is written: run when "0" is written: stop the stopwatch timer enters the run status when "1" is written to swrun, and the stop status when "0" is written. in the stop status, the timer data is maintained until the next run status or resets timer. also, when the stop status changes to the run status, the data that was maintained can be used for resuming the count. run/stop control with this register is valid only when the direct input function is set to disable. when the direct input function is set, it becomes invalid. ?when reading data when "1" is read: run when "0" is read: stop reading is always valid regardless of the direct input function setting. "1" is read when the stopwatch timer is in the run status, and "0" is read in the stop status. at initial reset, this register is set to "0". lcurf: lap data carry-up request flag (ff79h?3) this flag indicates a carry that has been generated to 1 sec-digit when the data is held. note that this flag is invalid when the direct input function is disabled. when "1" is read: carry is required when "0" is read: carry is not required w riting: invalid if the capture buffer shifts into hold status while the 1 hz interrupt factor flag isw1 is set to "1", lcurf is set to "1" to indicate that a carry-up to 1-sec digit is required. when performing a processing such as a lap input preceding with 1 hz interrupt processing, read this flag before processing and check whether carry-up is needed or not. this flag is renewed (set/reset) every time the capture buffer shifts into hold status. at initial reset, this flag is set to "0". crnwf: capture renewal flag (ff79h?2) this flag indicates that the content of the capture buffer has been renewed. when "1" is read: renewed when "0" is read: not renewed w riting: invalid the content of the capture buffer is renewed if the lap key is input when the data held into the capture buffer has not yet been read. reading swd8?1 in that status sets this flag to "1", and the hold status is maintained. consequently, when data that is held by a lap input is read, read this flag after reading the swd8?1 and check whether the data has been renewed or not. this flag is renewed when swd8?1 is read. at initial reset, this flag is set to "0". eirun, eilap, eisw1, eisw10: interrupt mask registers (ffe6h) these registers are used to select whether to mask the stopwatch timer interrupt. when "1" is written: enabled when "0" is written: masked reading: valid the interrupt mask registers eirun, eilap, eisw1 and eisw10 are used to separately select whether to mask the direct run, direct lap, 1 hz and 10 hz interrupts. at initial reset, these registers are set to "0".
s1c63654 technical manual epson 77 chapter 4: peripheral circuits and operation (stopwatch timer) irun, ilap, isw1, isw10: interrupt factor flags (fff6h) these flags indicate the status of the stopwatch timer interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred when "1" is written: flag is reset when "0" is written: invalid the interrupt factor flags irun, ilap, isw1 and isw10 correspond to the direct run, direct lap, 1 hz and 10 hz interrupts respectively. the software can judge from these flags whether there is a stopwatch timer interrupt. however, even if the interrupt is masked, the flags are set to "1" when the timing condi- tion is established. these flags are reset to "0" by writing "1" to them. after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. at initial reset, these flags are set to "0". 4.10.8 programming notes (1) the interrupt factor flag should be reset after resetting the stopwatch timer. (2) be sure to data reading in the order of swd0? swd4? swd8?1. (3) when data that is held by a lap input is read, read the capture buffer renewal flag crnwf after r eading the swd8?1 and check whether the data has been renewed or not. (4) when performing a processing such as a lap input preceding with 1 hz interrupt processing, read the lap data carry-up request flag lcurf before processing and check whether carry-up is needed or not. (5) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.
78 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) 4.11 programmable timer 4.11.1 configuration of programmable timer the s1c63654 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in. the timers are composed of 8-bit presettable down counters and they can be used as 8 bits 2 channels or 16 bits 1 channel of programmable timers. timer 0 also has an event counter function using the k13 input port terminal. figure 4.11.1.1 shows the configuration of the programmable timer. each timer has an 8-bit down counter and an 8-bit reload data register. the down counter counts the input clock. when the down counter underflows, the timer outputs the underflow and interrupt signals and resets the counter to its initial value. the reload data register is used to store that initial value. the underflow signal of timer 1 is used as the source clock of the serial interface, this makes it possible to program a flexible transfer rate. each timer has an 8-bit compare data register in addition to the above registers. this register is used to store data to be compared with the contents of the down counter. when the timer is set in the pwm mode, the timer outputs the compare match signal if the contents between the down counter and the compare data register are matched, and an interrupt occurs at the same time. also the compare match signal is used with the underflow signal to generate a pwm waveform. the signal generated by the programmable timer can be output from the r02 output port terminal. interrupt request chsel0 tout (r02) serial interface interrupt control circuit ptout selector output port r02 1/2 1/2 reload data register rld00?ld07 data buffer ptd00?td07 pwm waveform generator compare data register cd00?d07 ptrun0 timer 0 ptps00 ptps01 8-bit down counter prescaler selector cksel0 timer 0 run/stop clock control circuit prescaler setting under- flow signal compare match signal compare match signal data bus selector cksel1 ptsel0 mod16 timer 1 run/stop ptrst0 timer 0 reset pwm output selection 2,048 hz divider osc3 oscillation circuit osc1 oscillation circuit f osc3 f osc1 pwm waveform generator data buffer ptd10?td17 comparator comparator compare data register cd10?d17 ptsel1 pwm output selection timer 1 ptps10 ptps11 8-bit down counter prescaler selector clock control circuit prescaler setting under- flow signal ptrst1 timer 1 reset 16-bit mode selection reload data register rld10?ld17 ptrun1 input port k13 k13 fcsel plpol timer function setting pulse polarity setting evcnt event counter mode setting fi g. 4.11.1.1 configuration of programmable timer
s1c63654 technical manual epson 79 chapter 4: peripheral circuits and operation (programmable timer) 4.11.2 basic count operation this section explains the basic count operation when each timer is used as an individual 8-bit timer. each timer has an 8-bit down counter and an 8-bit reload data register. the reload data register rldx0?ldx7 (x = timer number) is used to set the initial value to the down counter. by writing "1" to the timer reset bit ptrstx, the down counter loads the initial value set in the reload r egister. therefore, down-counting is executed from the stored initial value by the input clock. the ptrunx register is provided to control the run/stop for each timer. by writing "1" to this register after presetting the reload data to the down counter, the down counter starts counting down. writing "0" stops the input count clock and the down counter stops counting. this control (run/stop) does not affect the counter data. the counter maintains its data while stopped, and can restart counting continuing from that data. the counter data can be read via the data buffer ptdx0?tdx7 in optional timing. however, the counter has the data hold function the same as the clock timer, that holds the high-order data (ptdx4?tdx7) when the low-order data (ptdx0?tdx3) is read in order to prevent the borrowing operation between low- and high-order reading, therefore be sure to read the low-order data first. the counter reloads the initial value set in the reload data register when an underflow occurs through the count down. it continues counting down from the initial value after reloading. in addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (tout signal) output and clock supplying to the serial interface. ptrunx ptrstx rldx0?7 input clock ptdx7 ptdx6 ptdx5 ptdx4 ptdx3 ptdx2 ptdx1 ptdx0 a6h f3h preset reload & underflow interrupt fi g. 4.11.2.1 basic operation timing of down counter
80 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) 4.11.3 setting the input clock a prescaler is provided for each timer. the prescaler generates the input clock for the timer by dividing the source clock supplied from the osc1 or osc3 oscillation circuit. the source clock (osc1 or osc3) and the division ratio of the prescaler can be selected with software for each timer individually. the input clock is set in the following sequence. selection of source clock select the source clock input to each prescaler from either osc1 or osc3. this selection is done using the source clock selection register ckselx; when "0" is written to the register, osc1 is selected and when "1" is written, osc3 is selected. when the osc3 oscillation clock is selected for the clock source, it is necessary to turn the osc3 oscillation on, prior to using the programmable timer. however the osc3 oscillation circuit requires a time at least 5 msec from turning the circuit on until the oscillation stabilizes. therefore, allow an adequate interval from turning the osc3 oscillation circuit on to starting the programmable timer. refer to section 4.4, "oscillation circuit", for the control and notes of the osc3 oscillation circuit. at initial reset, the osc3 oscillation circuit is set in off state. selection of prescaler division ratio select the division ratio for each prescaler from among 4 types. this selection is done using the prescaler division ratio selection register ptpsx0/ptpsx1. table 4.11.3.1 shows the correspondence between the setting value and the division ratio. t able 4.11.3.1 selection of prescaler division ratio ptpsx1 1 1 0 0 ptpsx0 1 0 1 0 prescaler division ratio source clock / 256 source clock / 32 source clock / 4 source clock / 1 by writing "1" to the ptrunx register, the prescaler inputs the source clock and outputs the clock divided by the selected division ratio. the counter starts counting down by inputting the clock. 4.11.4 event counter mode (timer 0) ti mer 0 has an event counter function that counts an external clock input to the input port k13. this function is selected by writing "1" to timer 0 counter mode selection register evcnt. at initial reset, evcnt is set to "0" and timer 0 is configured as a normal timer that counts the internal clock. in the event counter mode, the clock is supplied to timer 0 from outside the ic, therefore, the settings of the timer 0 prescaler division ratio selection register ptps00?tps01 and the settings of the timer 0 source clock selection register cksel0 become invalid. count down timing can be selected from either the falling or rising edge of the input clock using the timer 0 pulse polarity selection register plpol. when "0" is written to the plpol register, the falling edge is selected, and when "1" is written, the rising edge is selected. the count down timing is shown in figure 4.11.4.1. k13 input count data n n-1 n-2 n-3 n-4 n-5 n-6 plpol evcnt 01 1 ptrun0 fi g. 4.11.4.1 timing chart in event counter mode
s1c63654 technical manual epson 81 chapter 4: peripheral circuits and operation (programmable timer) the event counter mode also allows use of a noise reject function to eliminate noise such as chattering on the external clock (k13 input signal). this function is selected by writing "1" to the timer 0 function selection register fcsel. when "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98 msec ? or more to count reliably. the noise rejector allows the counter to input the clock at the second falling edge of the internal 2,048 hz ? signal after changing the input level of the k13 input port terminal. consequently, the pulse width of noise that can reliably be rejected is 0.48 msec ? or less. ( ? : f osc1 = 32.768 khz) figure 4.11.4.2 shows the count down timing with noise rejector. counter input clock ? 2 counter data n n-1 n-2 n-3 evin input (k13) 2,048 hz ? 1 ? 1 when f osc1 is 32.768 khz ? 2 when plpol register is set to "0" fi g. 4.11.4.2 count down timing with noise rejector the operation of the event counter mode is the same as the normal timer except it uses the k13 input as the clock. refer to section 4.11.2, "basic count operation" for basic operation and control. 4.11.5 pwm mode (timer 0, timer 1) ti mer 0 and timer 1 can generate a pwm waveform. when using this function, write "1" to the ptsel0 r egister (for timer 0) or ptsel1 register (for timer 1) to set the timer in the pwm mode. the compare data register cdx0?dx7 (x represents a timer number) is provided for timers 0 and 1 to control the pwm waveform. when the timer is set in the pwm mode, the timer compares data between the down counter and the compare data register and outputs the compare match signal if their contents are matched. at the same time a compare match interrupt occurs. furthermore, the timer output signal rises with the underflow signal and falls with the compare match signal. as shown in figure 4.11.5.1, the cycle and duty ratio of the output signal can be controlled using the reload data register and the compare data register, respectively, to generate a pwm signal. note, however, the following condition must be met: rld (reload data) > cd (compare data) and cd 0. if rld cd, the output signal is fixed at "1" after the first underflow occurs and does not fall to "0". the generated pwm signal can be output from the r02 output port terminal (see section 4.11.8). input clock rld register cd register down-counter value compare match signal underflow signal timer output signal compare match interrupt underflow interrupt compare match signal underflow signal timer output signal underflow interrupt 7 6 7 0 6 5 4 3 2 1 0 7 6 5 4 cd register value 3 2 1 0 7 6 5 4 3 2 1 rld register value + 1 pwm mode normal mode fi g. 4.11.5.1 generating pwm waveform
82 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) 4.11.6 16-bit timer (timer 0 + timer 1) ti mers 0 and 1 can be used as a 16-bit timer. to use the 16-bit timer, write "1" to the timer 0 16-bit mode selection register mod16. the 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte as shown in figure 4.11.6.1. reload data register rld00?ld07 data buffer ptd00?td07 comparator ptrun0 fcsel plpol timer 0 + timer 1 timer 0 timer 1 ptps00 ptps01 8-bit down counter 8-bit down counter prescaler selector cksel0 timer 0 run/stop clock control circuit timer function setting pulse polarity setting prescaler setting under- flow signal compare match signal data bus 8 low-order bits 8 high-order bits data buffer ptd10?td17 compare data register cd00?d07 compare data register cd10?d17 divider osc3 oscillation circuit osc1 oscillation circuit f osc3 f osc1 reload data register rld10?ld17 input port k13 evcnt event counter mode setting k13 ptsel1 pwm output selection tout interrupt pwm waveform generator 1/2 ptrst0 timer 0 reset ptrst1 timer 1 reset fi g. 4.11.6.1 configuration of 16-bit timer the registers for timer 0 are used to control the timer. the event counter and pwm output functions can also be used. ti mer 1 operates with the timer 0 underflow signal as the count clock, so the clock and run/stop control registers for timer 1 become invalid. however, reload data (ptrstx) must be preset to timers 0 and 1 separately. the counter data in 16-bit mode must be read in the order below. ptd00?td03 ptd04?dt07 ptd10?td13 ptd14?td17 4.11.7 interrupt function the programmable timer can generate an interrupt due to an underflow of each timer or a compare match of timers 0 and 1. see figures 4.11.2.1 and 4.11.5.1 for the interrupt timing. note: the compare match interrupt can be generated only when timer 0 or 1 is set in pwm mode. an underflow/compare match of timer x sets the corresponding interrupt factor flag iptx/ictcx to "1", and generates an interrupt. the interrupt can also be masked by setting the corresponding interrupt mask r egister eiptx/ectcx. however, the interrupt factor flag is set to "1" by an underflow/compare match of the corresponding timer regardless of the interrupt mask register setting. when timers 0 and 1 are used as a 16-bit timer, an interrupt is generated by an underflow of timer 1. in this case, ipt0 is not set to "1" by a timer 0 underflow. the compare match interrupt uses ictc1 of timer 1.
s1c63654 technical manual epson 83 chapter 4: peripheral circuits and operation (programmable timer) 4.11.8 control of tout output the programmable timer can generate a tout signal from the timer underflow and compare match signals. the tout signal is generated by dividing the underflow signal by 2 in the normal mode. in the pwm mode, the pwm signal generated by timer 0/1 is output as the tout signal. it is possible to select which timer output is to be used by the tout output channel selection register chsel0. t able 4.11.8.1 selecting a timer for tout output chsel0 1 0 tout output timer timer 1 timer 0 select timer 1 when generating the tout signal from the 16-bit timer output. the tout signal can be output from the r02 output port terminal. figure 4.11.8.1 shows the configuration of the output port r02. data bus register ptout register r02 tout r02 (tout) register r02hiz fi g. 4.11.8.1 configuration of r02 the output of a tout signal is controlled by the ptout register. when "1" is written to the ptout r egister, the tout signal is output from the r02 output port terminal and when "0" is written, the terminal goes to a high (v dd ) level. however, the data register r02 must always be "1" and the high impedance control register r02hiz must always be "0" (data output state). since the tout signal is generated asynchronously from the ptout register, a hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register. figure 4.11.8.2 shows the output waveform of the tout signal. r02hiz register r02 register ptout register tout output fix at "0" fix at "1" "1" "0" "0" fi g. 4.11.8.2 output waveform of the tout signal
84 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) 4.11.9 transfer rate setting for serial interface the signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock source for the serial interface. the programmable timer outputs the clock to the serial interface by setting timer 1 into run state (ptrun1 = "1"). it is not necessary to control with the ptout register. ptrun1 timer 1 underflow source clock for serial i/f fi g. 4.11.9.1 synchronous clock of serial interface a setting value for the rld1x register according to a transfer rate is calculated by the following expres- sion: rld1x = fosc / (2 ? bps ? division ratio of the prescaler) - 1 f osc :o scillation frequency (osc1/osc3) bps :t ransfer rate (00h can be set to rld1x) be aware that the maximum clock frequency for the serial interface is limited to 1 mhz when osc3 is used as the clock source.
s1c63654 technical manual epson 85 chapter 4: peripheral circuits and operation (programmable timer) 4.11.10 i/o memory of programmable timer t able 4.11.10.1 shows the i/o addresses and the control bits for the programmable timer. t able 4.11.10.1(a) control bits of programmable timer address comment d3 d2 register d1 d0 name init ? 1 ptps01 ptps00 ptrst0 ? 3 ptrun0 0 0 ? ? 2 0 reset run invalid stop prescaler 0 division ratio selection timer 0 reset (reload) timer 0 run/stop wr/w r/w ffc3h ptps01 ptps00 ptrst0 ptrun0 0 1/1 1 1/4 2 1/32 3 1/256 [ptps01, 00] division ratio mod16 evcnt fcsel plpol 0 0 0 0 16 bits event ct. with nr 8 bits timer no nr 16-bit mode selection timer 0 counter mode selection timer 0 function selection (for event counter mode) timer 0 pulse polarity selection (for event counter mode) ptps11 ptps10 ptrst1 ? 3 ptrun1 0 0 ? ? 2 0 reset run invalid stop prescaler 1 division ratio selection timer 1 reset (reload) timer 1 run/stop wr/w r/w ffc4h ptps11 ptps10 ptrst1 ptrun1 0 1/1 1 1/4 2 1/32 3 1/256 [ptps11, 10] division ratio r/w ffc0h mod16 evcnt fcsel plpol 10 rld03 rld02 rld01 rld00 0 0 0 0 msb programmable timer 0 reload data (low-order 4 bits) lsb r/w ffc6h rld03 rld02 rld01 rld00 rld07 rld06 rld05 rld04 0 0 0 0 msb programmable timer 0 reload data (high-order 4 bits) lsb r/w ffc7h rld07 rld06 rld05 rld04 rld13 rld12 rld11 rld10 0 0 0 0 msb programmable timer 1 reload data (low-order 4 bits) lsb r/w ffc8h rld13 rld12 rld11 rld10 rld17 rld16 rld15 rld14 0 0 0 0 msb programmable timer 1 reload data (high-order 4 bits) lsb r/w ffc9h rld17 rld16 rld15 rld14 ptd03 ptd02 ptd01 ptd00 0 0 0 0 msb programmable timer 0 data (low-order 4 bits) lsb r ffcch ptd03 ptd02 ptd01 ptd00 ptd07 ptd06 ptd05 ptd04 0 0 0 0 msb programmable timer 0 data (high-order 4 bits) lsb r ffcdh ptd07 ptd06 ptd05 ptd04 0 ? 3 0 ? 3 chsel0 ptout ? ? 2 ? ? 2 0 0 timer 1 on timer 0 off unused unused tout output selection tout output control rr/w ffc1h 00 chsel0 ptout 0 ? 3 0 ? 3 cksel1 cksel0 ? ? 2 ? ? 2 0 0 osc3 osc3 osc1 osc1 unused unused prescaler 1 source clock selection prescaler 0 source clock selection rr/w ffc2h 00 cksel1 cksel0 ptd13 ptd12 ptd11 ptd10 0 0 0 0 msb programmable timer 1 data (low-order 4 bits) lsb r ffceh ptd13 ptd12 ptd11 ptd10 ptd17 ptd16 ptd15 ptd14 0 0 0 0 msb programmable timer 1 data (high-order 4 bits) lsb r ffcfh ptd17 ptd16 ptd15 ptd14 cd03 cd02 cd01 cd00 0 0 0 0 msb programmable timer 0 compare data (low-order 4 bits) lsb r/w ffd2h cd03 cd02 cd01 cd00 *1 initial value at initial reset *3 constantly "0" when being read *2 not set in the circuit
86 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) t able 4.11.10.1(b) control bits of programmable timer address comment d3 d2 register d1 d0 name init ? 1 10 ffe0h 00 ectc1 ectc0 rr/w 0 ? 3 0 ? 3 ectc1 ectc0 ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (programmable timer 1 compare match) interrupt mask register (programmable timer 0 compare match) cd07 cd06 cd05 cd04 0 0 0 0 msb programmable timer 0 compare data (high-order 4 bits) lsb r/w ffd3h cd07 cd06 cd05 cd04 cd17 cd16 cd15 cd14 0 0 0 0 msb programmable timer 1 compare data (high-order 4 bits) lsb r/w ffd5h cd17 cd16 cd15 cd14 cd13 cd12 cd11 cd10 0 0 0 0 msb programmable timer 1 compare data (low-order 4 bits) lsb r/w ffd4h cd13 cd12 cd11 cd10 fff0h 00 ictc1 ictc0 rr/w 0 ? 3 0 ? 3 ictc1 ictc0 ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (programmable timer 1 compare match) interrupt factor flag (programmable timer 0 compare match) ffd8h 00 ptsel1 ptsel0 rr/w 0 ? 3 0 ? 3 ptsel1 ptsel0 ? ? 2 ? ? 2 0 0 pwm pwm normal normal unused unused programmable timer 1 pwm output selection programmable timer 0 pwm output selection fff1h 00i pt1 ipt0 rr/w 0 ? 3 0 ? 3 ipt1 ipt0 ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (programmable timer 1 underflow) interrupt factor flag (programmable timer 0 underflow) ffe1h 00ei pt1 eipt0 rr/w 0 ? 3 0 ? 3 eipt1 eipt0 ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (programmable timer 1 underflow) interrupt mask register (programmable timer 0 underflow) *1 initial value at initial reset *3 constantly "0" when being read *2 not set in the circuit cksel0: prescaler 0 source clock selection register (ffc2h?0) cksel1: prescaler 1 source clock selection register (ffc2h?1) selects the source clock of the prescaler. when "1" is written: osc3 clock when "0" is written: osc1 clock reading: valid the source clock for the prescaler is selected from osc1 or osc3. when "0" is written to the ckselx r egister, the osc1 clock is selected as the input clock for the prescaler x (for timer x) and when "1" is written, the osc3 clock is selected. when the event counter mode is selected for timer 0, the setting of cksel0 becomes invalid. when timers 0 and 1 are used as a 16-bit timer, the setting of cksel1 becomes invalid. at initial reset, these registers are set to "0".
s1c63654 technical manual epson 87 chapter 4: peripheral circuits and operation (programmable timer) ptps00, ptps01: timer 0 prescaler division ratio selection register (ffc3h?2, d3) ptps10, ptps11: timer 1 prescaler division ratio selection register (ffc4h?2, d3) sets the division ratio of the prescaler as shown in table 4.11.10.2. t able 4.11.10.2 selection of prescaler division ratio ptpsx1 1 1 0 0 ptpsx0 1 0 1 0 prescaler division ratio source clock / 256 source clock / 32 source clock / 4 source clock / 1 when the event counter mode is selected to timer 0, the setting of ptps00 and ptps01 becomes invalid. when timers 0 and 1 are used as a 16-bit timer, the setting of ptps10 and ptps11 becomes invalid. at initial reset, these registers are set to "0". mod16: 16-bit mode selection register (ffc0h?3) selects whether timers 0 and 1 are used as a 16-bit timer or 2 channels of 8-bit timer. when "1" is written: 16-bit timer when "0" is written: 8-bit timer reading: valid when "1" is written to mod16, a 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte. use the timer 0 registers for control. when "0" is written to mod16, timer 0 and timer 1 are used as independent 8-bit timers. at initial reset, this register is set to "0". evcnt: timer 0 counter mode selection register (ffc0h?2) selects a counter mode for timer 0. when "1" is written: event counter mode when "0" is written: timer mode reading: valid the counter mode for timer 0 is selected from either the event counter mode or timer mode. when "1" is written to the evcnt register, the event counter mode is selected and when "0" is written, the timer mode is selected. at initial reset, this register is set to "0". fcsel: timer 0 function selection register (ffc0h?1) selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode. when "1" is written: with noise rejector when "0" is written: without noise rejector reading: valid when "1" is written to the fcsel register, the noise rejector is used and counting is done by an external clock (k13) with 0.98 msec * or more pulse width. the noise rejector allows the counter to input the clock at the second falling edge of the internal 2,048 hz * signal after changing the input level of the k13 input port terminal. consequently, the pulse width of noise that can reliably be rejected is 0.48 msec * or less. ( ? : f osc1 = 32.768 khz) when "0" is written to the fcsel register, the noise rejector is not used and the counting is done directly by an external clock input to the k13 input port terminal. setting of this register is effective only when timer 0 is used in the event counter mode. at initial reset, this register is set to "0".
88 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) plpol: timer 0 pulse polarity selection register (ffc0h?0) selects the count pulse polarity in the event counter mode. when "1" is written: rising edge when "0" is written: falling edge reading: valid the count timing in the event counter mode (timer 0) is selected from either the falling edge of the external clock input to the k13 input port terminal or the rising edge. when "0" is written to the plpol r egister, the falling edge is selected and when "1" is written, the rising edge is selected. setting of this register is effective only when timer 0 is used in the event counter mode. at initial reset, this register is set to "0". ptsel0: timer 0 pwm mode selection register (ffd8h?0) ptsel1: timer 1 pwm mode selection register (ffd8h?1) sets timer 0 or 1 for pwm output. when "1" is written: pwm output when "0" is written: normal output reading: valid when "1" is written to the ptselx, the compare data register becomes valid and pwm waveform is generated using the underflow and compare match signals. when "0" is written, the timer outputs the normal clock generated from the underflow signal. when timers 0 and 1 are used as a 16-bit timer, the setting of ptsel1 becomes invalid. at initial reset, these registers are set to "0". rld00?ld07: timer 0 reload data register (ffc6h, ffc7h) rld10?ld17: timer 1 reload data register (ffc8h, ffc9h) sets the initial value for the counter. the reload data written in this register is loaded to the respective counters. the counter counts down using the data as the initial value for counting. reload data is loaded to the counter when the counter is reset by writing "1" to the ptrstx register, or when counter underflow occurs. at initial reset, these registers are set to "00h". ptd00?td07: timer 0 counter data (ffcch, ffcdh) ptd10?td17: timer 1 counter data (ffceh, ffcfh) count data in the programmable timer can be read from these latches. the low-order 4 bits of the count data in timer x can be read from ptdx0?tdx3, and the high-order data can be read from ptdx4?tdx7. since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. since these latches are exclusively for reading, the writing operation is invalid. at initial reset, these counter data are set to "00h". cd00?d07: timer 0 compare data register (ffd2h, ffd3h) cd10?d17: timer 1 compare data register (ffd4h, ffd5h) set the compare data for pwm output. when the timer is set in the pwm mode, the compare data set in this register is compared with the counter data and outputs the compare match signal if they are matched. the compare match signal is used for generating an interrupt and controlling the duty ratio of the pwm waveform. at initial reset, these registers are set to "00h".
s1c63654 technical manual epson 89 chapter 4: peripheral circuits and operation (programmable timer) ptrst0: timer 0 reset (reload) (ffc3h?1) ptrst1: timer 1 reset (reload) (ffc4h?1) resets the timer and presets reload data to the counter. when "1" is written: reset when "0" is written: no operation reading: always "0" by writing "1" to ptrstx, the reload data in the reload register rldx0?ldx7 is preset to the counter in timer x. when the counter is preset in the run status, the counter restarts immediately after presetting. in the case of stop status, the reload data is preset to the counter and is maintained. no operation results when "0" is written. since these bits are exclusively for writing, always set to "0" during reading. ptrun0: timer 0 run/stop control register (ffc3h?0) ptrun1: timer 1 run/stop control register (ffc4h?0) controls the run/stop of the counter. when "1" is written: run when "0" is written: stop reading: valid the counter in timer x starts counting down by writing "1" to the ptrunx register and stops by writing "0". in stop status, the counter data is maintained until the counter is reset or is set in the next run status. when stop status changes to run status, the data that has been maintained can be used for r esuming the count. at initial reset, these registers are set to "0". chsel0: tout output channel selection register (ffc1h?1) selects the channel used for tout signal output. when "1" is written: timer 1 when "0" is written: timer 0 reading: valid this register selects which timer's output (timer 0 or timer 1) is used to generate a tout signal. when "0" is written to the chsel0 register, timer 0 is selected and when "1" is written, timer 1 is selected. in the 16- bit mode (mod16 = "1"), timer 1 is always selected regardless of this register setting. at initial reset, this register is set to "0". ptout: tout output control register (ffc1h?0) t urns tout signal output on and off. when "1" is written: on when "0" is written: off reading: valid ptout is the output control register for the tout signal. when "1" is written to the register, the tout signal is output from the output port terminal r02 and when "0" is written, the terminal goes to a high (v dd ) level. however, the data register r02 must always be "1" and the high impedance control register r02hiz must always be "0" (data output state). at initial reset, this register is set to "0".
90 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) eipt0, ectc0: timer 0 interrupt mask registers (ffe1h?0, ffe0h?0) eipt1, ectc1: timer 1 interrupt mask registers (ffe1h?1, ffe0h?1) these registers are used to select whether to mask the programmable timer interrupt or not. when "1" is written: enabled when "0" is written: masked reading: valid eiptx and ectcx are the interrupt mask registers that respectively correspond to the counter underflow and compare match interrupt factors. interrupts set to "1" are enabled and interrupts set to "0" are disa- bled. at initial reset, these registers are set to "0". ipt0, ictc0: timer 0 interrupt factor flags (fff1h?0, fff0h?0) ipt1, ictc1: timer 1 interrupt factor flags (fff1h?1, fff0h?1) these flags indicate the status of the programmable timer interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred when "1" is written: flag is reset when "0" is written: invalid iptx and ictcx are the interrupt factor flags that respectively correspond to the interrupts for counter underflow and compare match, and are set to "1" by generation of each factor. the underflow interrupt factor is generated at the point where the counter underflows. the compare match interrupt factor is generated if the counter data and the compare data are matched when the timer is set in the pwm mode. the software can judge from these flags whether there is a programmable timer interrupt. however, even if the interrupt is masked, the flags are set to "1" by an underflow and compare match of the correspond- ing counter. these flags are reset to "0" by writing "1" to them. after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. at initial reset, these flags are set to "0".
s1c63654 technical manual epson 91 chapter 4: peripheral circuits and operation (programmable timer) 4.11.11 programming notes (1) when reading counter data, be sure to read the low-order 4 bits (ptdx0?tdx3) first. furthermore, the high-order 4 bits (ptdx4?tdx7) are not latched when the low-order 4 bits are read. therefore, the high-order 4 bits should be read within 0.73 msec (when f osc1 is 32.768 khz) from reading the low-order 4 bits. when the cpu is running with the osc1 clock and the programmable timer is r unning with the osc3 clock, stop the timer before reading the counter data. the counter running with osc3 counts down for the value listed in table 4.11.11.1 while the cpu running with osc1 reads the low-order 4 bits and high-order 4 bits of the counter data by two instructions. t able 4.11.11.1 counter change with osc3 between readings low-order and high-order data with osc1 count clock osc3/1 osc3/4 osc3/32 counter change between reading 0200h 001ah 0002h in 16-bit mode, the counter data must be read in the order below. ptd00?td03 ptd04?dt07 ptd10?td13 ptd14?td17 (2) the programmable timer actually enters run/stop status in synchronization with the falling edge of the input clock after writing to the ptrunx register. consequently, when "0" is written to the ptrunx register, the timer enters stop status at the point where the counter is decremented (-1). the ptrunx register maintains "1" for reading until the timer actually stops. figure 4.11.11.1 shows the timing chart for the run/stop control. ptrunx (wr) ptdx0?tdx7 42h 41h 40h 3fh 3eh 3dh ptrunx (rd) input clock "1" (run) writing "0" (stop) writing fi g. 4.11.11.1 timing chart for run/stop control it is the same even in the event counter mode. therefore, be aware that the counter does not enter run/stop status if a clock is not input after setting the run/stop control register (ptrun0). (3) since the tout signal is generated asynchronously from the ptout register, a hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register. (4) when the osc3 oscillation clock is selected for the clock source, it is necessary to turn the osc3 oscillation on, prior to using the programmable timer. however the osc3 oscillation circuit requires a time at least 5 msec from turning the circuit on until the oscillation stabilizes. therefore, allow an adequate interval from turning the osc3 oscillation circuit on to starting the programmable timer. refer to section 4.4, "oscillation circuit", for the control and notes of the osc3 oscillation circuit. at initial reset, the osc3 oscillation circuit is set in the off state. (5) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.
92 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (programmable timer) (6) for the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. the programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as ? in the figure). input clock counter data (continuous mode) (reload data = 25h) 03h 02h 01h 00h 25h 24h counter data is determined by reloading. underflow (interrupt is generated) ? fi g. 4.11.11.2 reload timing for programmable timer to avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ? . be especially careful when using the osc1 (low- speed clock) as the clock source of the programmable timer and the cpu is operating with the osc3 (high-speed clock).
s1c63654 technical manual epson 93 chapter 4: peripheral circuits and operation (serial interface) 4.12 serial interface (sin, sout, sclk, srdy) 4.12.1 configuration of serial interface the s1c63654 has a synchronous clock type 8 bits serial interface built-in. the configuration of the serial interface is shown in figure 4.12.1.1. the cpu, via the 8-bit shift register, can read the serial input data from the sin terminal. moreover, via the same 8-bit shift register, it can convert parallel data to serial data and output it to the sout terminal. the synchronous clock for serial data input/output may be set by selecting by software any one of three types of master mode (internal clock mode: when the s1c63654 is to be the master for serial input/ output) and a type of slave mode (external clock mode: when the s1c63654 is to be the slave for serial input/output). also, when the serial interface is used at slave mode, srdy signal which indicates whether or not the serial interface is available to transmit or receive can be output to the srdy terminal. sd0?d7 sin (p10) sclk or sclk (p12) scs0 scs1 output latch serial i/f interrupt control circuit interrupt request sout (p11) srdy or srdy (p13) sctrg serial i/f activating circuit f osc1 serial clock counter serial clock selector serial clock generator shift register (8 bits) programmable timer 1 underflow signal scps esout fi g. 4.12.1.1 configuration of serial interface the input/output ports of the serial interface are shared with the i/o ports p10?13, and function of these ports can be selected through the software. p10?13 terminals and serial input/output correspondence are as follows: master mode slave mode p10 = sin (i) p10 = sin (i) p11 = sout (o) p11 = sout (o) p12 = sclk (o) p12 = sclk (i) p13 = i/o port (i/o) p13 = srdy (o) the sout output using the p11 port is enabled when "1" is written to the esout register. if esout is "0", p11 functions as a general-purpose i/o port. note: at initial reset, p10?13 are set to i/o ports. when using the serial interface, switch the function (esif = "1", esout = "1") in the initial routine.
94 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (serial interface) 4.12.2 mask option t erminal specification since the input/output terminals of the serial interface is shared with the i/o ports (p10?13), the mask option that selects the output specification for the i/o port is also applied to the serial interface. the output specification of the terminals sout, sclk (during the master mode) and srdy (during the slave mode) that are used as output in the input/output port of the serial interface is respectively selected by the mask options of p11, p12 and p13. either complementary output or p-channel open drain output can be selected as the output specification. however, when p-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the terminal. furthermore, the pull-down resistor for the sin terminal and the sclk terminal (during slave mode) that are used as input terminals can be selected by mask option. the pull-down register can be added by the mask options of p10 and p12. when "without pull-down" is selected, take care that the floating status does not occur. p olarity of synchronous clock and ready signal polarity of the synchronous clock and the ready signal that is output in the slave mode can be selected _________ from either positive polarity (high active, sclk & srdy) or negative polarity (low active, sclk & _________ srdy). when operating the serial interface in the slave mode, the synchronous clock is input from a external device. be aware that the terminal specification is pull-down only and a pull-up resistor cannot be built in if negative polarity is selected. in the following explanation, it is assumed that positive polarity (sclk, srdy) has been selected. 4.12.3 master mode and slave mode of serial interface the serial interface of the s1c63654 has two types of operation mode: master mode and slave mode. the master mode uses an internal clock as the synchronous clock for the built-in shift register, and outputs this internal clock from the sclk (p12) terminal to control the external (slave side) serial device. in the slave mode, the synchronous clock output from the external (master side) serial device is input from the sclk (p12) terminal and it is used as the synchronous clock for the built-in shift register. the master mode and slave mode are selected by writing data to the scs1 and scs0 registers. when the master mode is selected, a synchronous clock may be selected from among 3 types as shown in t able 4.12.3.1. t able 4.12.3.1 synchronous clock selection scs1 1 1 0 0 scs0 1 0 1 0 mode master mode slave mode synchronous clock osc1 osc1 /2 programmable timer ? external clock ? ? the maximum clock is limited to 1 mhz. when the programmable timer is selected, the signal that is generated by dividing the underflow signal of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. in this case, the program- mable timer must be controlled before operating the serial interface. refer to section 4.11, "programmable ti mer" for the control of the programmable timer. at initial reset, the slave mode (external clock mode) is selected. moreover, the synchronous clock, along with the input/output of the 8-bit serial data, is controlled as follows: ? n the master mode, after output of 8 clocks from the sclk (p12) terminal, clock output is automati- cally suspended and the sclk (p12) terminal is fixed at low level (or high level when negative polarity is selected by mask option). ? n the slave mode, after input of 8 clocks to the sclk (p12) terminal, subsequent clock inputs are masked.
s1c63654 technical manual epson 95 chapter 4: peripheral circuits and operation (serial interface) a sample basic serial input/output portion connection is shown in figure 4.12.3.1. s1c63654 sclk sout sin input terminal external serial device clk sout sin ready s1c63654 sclk sout sin srdy external serial device clk sout sin input terminal (a) master mode (b) slave mode fi g. 4.12.3.1 sample basic connection of serial input/output section 4.12.4 data input/output and interrupt function the serial interface of s1c63654 can input/output data via the internal 8-bit shift register. the shift r egister operates by synchronizing with either the synchronous clock output from the sclk (p12) termi- nal (master mode), or the synchronous clock input to the sclk (p12) terminal (slave mode). the serial interface generates an interrupt on completion of the 8-bit serial data input/output. detection of serial data input/output is done by counting of the synchronous clock sclk; the clock completes input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an interrupt. the serial data input/output procedure is explained below: serial data output procedure and interrupt the s1c63654 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. by setting the parallel data to the data registers sd0?d3 (ff72h) and sd4?d7 (ff73h) and writing "1" to sctrg bit (ff70h?1), it synchronizes with the synchronous clock and the serial data is output to the sout (p11) terminal. the synchronous clock used here is as follows: in the master mode, internal clock which is output to the sclk (p12) terminal while in the slave mode, external clock which is input from the sclk (p12) terminal. shift timing of serial data is as follows: when positive polarity is selected for the synchronous clock (mask option): the serial data output to the sout (p11) terminal changes at the rising edge of the clock input or output from/to the sclk (p12) terminal. the data in the shift register is shifted at the rising edge of the sclk signal when the scps register is "1" and is shifted at the falling edge of the sclk signal when the scps register is "0". when negative polarity is selected for the synchronous clock (mask option): the serial data output to the sout (p11) terminal changes at the falling edge of the clock input or _________ output from/to the sclk (p12) terminal. the data in the shift register is shifted at the falling edge of _________ the sclk signal when the scps register (ff71h?2) is "1" and is shifted at the rising edge of the _________ sclk signal when the scps register is "0". when the output of the 8-bit data from sd0 to sd7 is completed, the interrupt factor flag isif (fff2h?0) is set to "1" and an interrupt occurs. moreover, the interrupt can be masked by the interrupt mask register eisif (ffe2h?0). however, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" after output of the 8-bit data.
96 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (serial interface) serial data input procedure and interrupt the s1c63654 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. the serial data is input from the sin (p10) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8-bit shift register. the synchronous clock used here is as follows: in the master mode, internal clock which is output to the sclk (p12) terminal while in the slave mode, external clock which is input from the sclk (p12) terminal. shift timing of serial data is as follows: when positive polarity is selected for the synchronous clock (mask option): the serial data is read into the built-in shift register at the rising edge of the sclk signal when the scps register is "1" and is read at the falling edge of the sclk signal when the scps register is "0". the shift register is sequentially shifted as the data is fetched. when negative polarity is selected for the synchronous clock (mask option): _________ the serial data is read into the built-in shift register at the falling edge of the sclk signal when the _________ scps register is "1" and is read at the rising edge of the sclk signal when the scps register is "0". the shift register is sequentially shifted as the data is fetched. when the input of the 8-bit data from sd0 to sd7 is completed, the interrupt factor flag isif is set to "1" and an interrupt is generated. moreover, the interrupt can be masked by the interrupt mask r egister eisif. however, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" after input of the 8-bit data. the data input in the shift register can be read from data registers sd0?d7 by software. serial data input/output permutation the s1c63654 allows the input/output permutation of serial data to be selected by the sdp register (ff71h?3) as to either lsb first or msb first. the block diagram showing input/output permutation in case of lsb first and msb first is provided in figure 4.12.4.1. the sdp register should be set before setting data to sd0?d7. sin sin address [ff73h] address [ff72h] address [ff73h] address [ff72h] output latch output latch sout sout sd3 sd2 sd1 sd0 sd4 sd5 sd6 sd7 sd7 sd6 sd5 sd4 sd0 sd1 sd2 sd3 (lsb first) (msb first) fi g. 4.12.4.1 serial data input/output permutation srdy signal when the s1c63654 serial interface is used in the slave mode (external clock mode), srdy signal is used to indicate whether the internal serial interface is available to transmit or receive data for the master side (external) serial device. srdy signal is output from the srdy (p13) terminal. output timing of srdy signal is as follows: ? hen positive polarity is selected (mask option): srdy signal goes "1" (high) when the s1c63654 serial interface is available to transmit or receive data; normally, it is at "0" (low). srdy signal changes from "0" to "1" immediately after "1" is written to sctrg and returns from "1" to "0" when "1" is input to the sclk (p12) terminal (i.e., when the serial input/output begins transmit- ting or receiving data). moreover, when high-order data is read from or written to sd4?d7, the srdy signal returns to "0". ? hen negative polarity is selected (mask option): _________ srdy signal goes "0" (low) when the s1c63654 serial interface is available to transmit or receive data; normally, it is at "1" (high). _________ srdy signal changes from "1" to "0" immediately after "1" is written to sctrg and returns from "0" to _________ "1" when "0" is input to the sclk (p12) terminal (i.e., when the serial input/output begins transmit- _________ ting or receiving data). moreover, when high-order data is read from or written to sd4?d7, the srdy signal returns to "1".
s1c63654 technical manual epson 97 chapter 4: peripheral circuits and operation (serial interface) timing chart the s1c63654 serial interface timing charts are shown in figures 4.12.4.2 and 4.12.4.3. sctrg (w) sctrg (r) sclk sin 8-bit shift register sout isif srdy (slave mode) sctrg (w) sctrg (r) sclk sin 8-bit shift register sout isif srdy (slave mode) (b) when scps = "0" fi g. 4.12.4.2 serial interface timing chart (when synchronous clock is positive polarity sclk) sctrg (w) sctrg (r) sclk sin 8-bit shift register sout isif srdy (slave mode) sctrg (w) sctrg (r) sclk sin 8-bit shift register sout isif srdy (slave mode) (b) when scps = "0" fi g. 4.12.4.3 serial interface timing chart (when synchronous clock is negative polarity sclk) (a) when scps = "1" (a) when scps = "1"
98 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (serial interface) 4.12.5 i/o memory of serial interface t able 4.12.5.1 shows the i/o addresses and the control bits for the serial interface. t able 4.12.5.1 control bits of serial interface address comment d3 d2 register d1 d0 name init ? 1 10 ff45h pul13 pul12 pul11 pul10 r/w pul13 pul12 pul11 pul10 1 1 1 1 on on on on off off off off p13 pull-down control register functions as a general-purpose register when sif (slave) is selected p12 pull-down control register (esif=0) functions as a general-purpose register when sif (master) is selected sclk (i) pull-down control register when sif (slave) is selected p11 pull-down control register (esif=0) functions as a general-purpose register when sif is selected p10 pull-down control register (esif=0) sin pull-down control register when sif is selected 0 slave 2 osc1/2 1 pt 3 osc1 r/w ff72h sd3 sd2 sd1 sd0 sd3 sd2 sd1 sd0 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low msb serial i/f transmit/receive data (low-order 4 bits) lsb r/w ff73h sd7 sd6 sd5 sd4 sd7 sd6 sd5 sd4 ? ? 2 ? ? 2 ? ? 2 ? ? 2 high high high high low low low low msb serial i/f transmit/receive data (high-order 4 bits) lsb [scs1, 0] clock [scs1, 0] clock ff71h sdp scps scs1 scs0 r/w sdp scps scs1 scs0 0 0 0 0 msb first lsb first serial i/f data input/output permutation serial i/f clock phase selection ?egative polarity (mask option) ?ositive polarity (mask option) serial i/f clock mode selection ff70h 0 esout sctrg esif rr/w 0 ? 3 esout sctrg esif ? ? 2 0 0 0 enable trigger run sif disable invalid stop i/o unused sout enable serial i/f clock trigger (writing) serial i/f clock status (reading) serial i/f enable (p1 port function selection) fff2h 000is if rr/w 0 ? 3 0 ? 3 0 ? 3 isif ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (serial i/f) ffe2h 000ei sif rr/w 0 ? 3 0 ? 3 0 ? 3 eisif ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (serial i/f) *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read esif: serial interface enable register (p1 port function selection) (ff70h?0) sets p10?13 to the input/output port for the serial interface. when "1" is written: serial interface when "0" is written: i/o port reading: valid when "1" is written to the esif register, p10, p11, p12 and p13 function as sin, sout, sclk, srdy, r espectively. in the slave mode, the p13 terminal functions as srdy output terminal, while in the master mode, it functions as the i/o port terminal. at initial reset, this register is set to "0".
s1c63654 technical manual epson 99 chapter 4: peripheral circuits and operation (serial interface) esout: sout enable register (ff70h?2) enables serial data output from the p11 port. when "1" is written: enabled (sout) when "0" is written: disabled (i/o port) reading: valid when serial data output is not used, the sout output can be disabled to use p11 as an i/o port. when performing serial output, write "1" to esout to set p11 as the sout output port. at initial reset, this register is set to "0". pul10: sin (p10) pull-down control register (ff45h?0) pul12: sclk (p12) pull-down control register (ff45h?2) sets the pull-down of the sin terminal and the sclk terminals (in the slave mode). when "1" is written: pull-down on when "0" is written: pull-down off reading: valid enables or disables the pull-down resistor built into the sin (p10) and sclk (p12) terminals. (pull-down r esistor is only built in the port selected by mask option.) sclk pull-down is effective only in the slave mode. in the master mode, the pul12 register can be used as a general purpose register. at initial reset, these registers are set to "1" and pull-down goes on. scs0, scs1: clock mode selection register (ff71h?0, d1) selects the synchronous clock (sclk) for the serial interface. t able 4.12.5.2 synchronous clock selection scs1 1 1 0 0 scs0 1 0 1 0 mode master mode slave mode synchronous clock osc1 osc1 /2 programmable timer ? external clock ? ? the maximum clock is limited to 1 mhz. synchronous clock (sclk) is selected from among the above 4 types: 3 types of internal clock and external clock. when the programmable timer is selected, the signal that is generated by dividing the underflow signal of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. in this case, the program- mable timer must be controlled before operating the serial interface. refer to section 4.11, "programmable ti mer" for the control of the programmable timer. at initial reset, external clock is selected. scps: clock phase selection register (ff71h?2) selects the timing for reading in the serial data input from the sin (p10) terminal. ?when positive polarity is selected: when "1" is written: rising edge of sclk when "0" is written: falling edge of sclk reading: valid ?when negative polarity is selected: when "1" is written: _________ falling edge of sclk when "0" is written: _________ rising edge of sclk reading: valid select whether the fetching for the serial input data to registers (sd0?d7) at the rising edge or falling edge of the synchronous signal.
100 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (serial interface) pay attention to the polarity of the synchronous clock selected by the mask option because the selection content is different. the input data fetch timing may be selected but output timing for output data is fixed at the rising edge _________ of sclk (when positive polarity is selected) or at the falling edge of sclk (when negative polarity is selected). at initial reset, this register is set to "0". sdp: data input/output permutation selection register (ff71h?3) selects the serial data input/output permutation. when "1" is written: msb first when "0" is written: lsb first reading: valid select whether the data input/output permutation will be msb first or lsb first. at initial reset, this register is set to "0". sctrg: clock trigger/status (ff70h?1) this is a trigger to start input/output of synchronous clock (sclk). ?when writing when "1" is written: trigger when "0" is written: no operation when this trigger is supplied to the serial interface activating circuit, the synchronous clock (sclk) input/output is started. as a trigger condition, it is required that data writing or reading on data registers sd0?d7 be performed prior to writing "1" to sctrg. (the internal circuit of the serial interface is initiated through data writ- ing/reading on data registers sd0?d7.) in addition, be sure to enable the serial interface with the esif re gister before setting the trigger. supply trigger only once every time the serial interface is placed in the run state. refrain from perform- ing trigger input multiple times, as leads to malfunctioning. moreover, when the synchronous clock sclk is external clock, start to input the external clock after the trigger. ?when reading when "1" is read: run (during input/output the synchronous clock) when "0" is read: stop (the synchronous clock stops) when this bit is read, it indicates the status of serial interface clock. after "1" is written to sctrg, this value is latched till serial interface clock stops (8 clock counts). there- fore, if "1" is read, it indicates that the synchronous clock is in input/output operation. when the synchronous clock input/output is completed, this latch is reset to "0". at initial reset, this bit is set to "0". sd0?d3, sd4?d7: serial interface data register (ff72h, ff73h) these registers are used for writing and reading serial data. ?when writing when "1" is written: high level when "0" is written: low level w rite data to be output in these registers. the register data is converted into serial data and output from the sout (p11) terminal; data bits set at "1" are output as high (v dd ) level and data bits set at "0" are output as low (v ss ) level.
s1c63654 technical manual epson 101 chapter 4: peripheral circuits and operation (serial interface) ?when reading when "1" is read: high level when "0" is read: low level the serial data input from the sin (p10) terminal can be read from these registers. the serial data input from the sin (p10) terminal is converted into parallel data, as a high (v dd ) level bit into "1" and as a low (v ss ) level bit into "0", and is loaded to these registers. perform data reading only while the serial interface is not running (i.e., the synchronous clock is neither being input or output). at initial reset, these registers are undefined. eisif: interrupt mask register (ffe2h?0) masking the interrupt of the serial interface can be selected with this register. when "1" is written: enabled when "0" is written: masked reading: valid w ith this register, it is possible to select whether the serial interface interrupt is to be masked or not. at initial reset, this register is set to "0". isif: interrupt factor flag (fff2h?0) this flag indicates the occurrence of serial interface interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred when "1" is written: flag is reset when "0" is written: invalid from the status of this flag, the software can decide whether the serial interface interrupt. this flag is set to "1" after an 8-bit data input/output even if the interrupt is masked. this flag is reset to "0" by writing "1" to it. after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. at initial reset, this flag is set to "0". 4.12.6 programming notes (1) perform data writing/reading to the data registers sd0?d7 only while the serial interface is not r unning (i.e., the synchronous clock is neither being input or output). (2) as a trigger condition, it is required that data writing or reading on data registers sd0?d7 be performed prior to writing "1" to sctrg. (the internal circuit of the serial interface is initiated through data writing/reading on data registers sd0?d7.) in addition, be sure to enable the serial interface with the esif register before setting the trigger. supply trigger only once every time the serial interface is placed in the run state. refrain from performing trigger input multiple times, as leads to malfunctioning. moreover, when the synchronous clock sclk is external clock, start to input the external clock after the trigger. (3) setting of the input/output permutation (msb first/lsb first) with the sdp register should be done before setting data to sd0?d7. (4) be aware that the maximum clock frequency for the serial interface is limited to 1 mhz when osc3 is used as the clock source of the programmable timer or in the slave mode. (5) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.
102 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (sound generator) 4.13 sound generator 4.13.1 configuration of sound generator the s1c63654 has a built-in sound generator for generating a buzzer signal. hence, the generated buzzer signal can be output from the bz terminal. aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control. it also has a one-shot output function for outputting key operated sounds. figure 4.13.1.1 shows the configuration of the sound generator. f osc1 bz terminal programmable dividing circuit 256 hz one-shot buzzer control circuit duty ratio control circuit bzfq0?zfq2 bdty0?dty2 buzzer output control circuit envelope addition circuit enon bze enrtm enrst bzstp bzsht shtpw fi g. 4.13.1.1 configuration of sound generator 4.13.2 control of buzzer output the bz signal generated by the sound generator is output from the bz terminal by setting "1" for the buzzer output enable register bze. when "0" is set to bze register, the bz terminal goes low (v ss ). bze register bz output (bz terminal) "1" "0" "0" fi g. 4.13.2.1 buzzer signal output timing chart note: since it generates the buzzer signal that is out of synchronization with the bze register, hazards may at times be produced when the signal goes on/off due to the setting of the bze register.
s1c63654 technical manual epson 103 chapter 4: peripheral circuits and operation (sound generator) 4.13.3 setting of buzzer frequency and sound level the divided signal of the osc1 oscillation clock (32.768 khz) is used for the buzzer signal and it is set up such that 8 types of frequencies can be selected by changing this division ratio. frequency selection is done by setting the buzzer frequency selection registers bzfq0?zfq2 as shown in table 4.13.3.1. t able 4.13.3.1 buzzer signal frequency setting buzzer frequency (hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 bzfq0 0 1 0 1 0 1 0 1 bzfq1 0 0 1 1 0 0 1 1 bzfq2 0 0 0 0 1 1 1 1 the buzzer sound level is changed by controlling the duty ratio of the buzzer signal. the duty ratio can be selected from among the 8 types shown in table 4.13.3.2 according to the setting of the buzzer duty selection registers bdty0?dty2. t able 4.13.3.2 duty ratio setting bdty0 0 1 0 1 0 1 0 1 bdty1 0 0 1 1 0 0 1 1 bdty2 0 0 0 0 1 1 1 1 level level 1 (max.) level 2 level 3 level 4 level 5 level 6 level 7 level 8 (min.) 4096.0 2048.0 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 3276.8 1638.4 8/20 7/20 6/20 5/20 4/20 3/20 2/20 1/20 2730.7 1365.3 12/24 11/24 10/24 9/24 8/24 7/24 6/24 5/24 2340.6 1170.3 12/28 11/28 10/28 9/28 8/28 7/28 6/28 5/28 duty ratio by buzzer frequency (hz) when the high level output time has been made th and when the low level output time has been made tl due to the ratio of the pulse width to the pulse synchronization, the duty ratio becomes th/(th+tl). when bdty0?dty2 have all been set to "0", the duty ratio becomes maximum and the sound level also becomes maximum. conversely, when bdty0?dty2 have all been set to "1", the duty ratio becomes minimum and the sound level also becomes minimum. the duty ratio that can be set is different depending on the frequency that has been set, so see table 4.13.3.2. level 1 (max.) level 2 level 3 level 4 level 5 level 6 level 7 level 8 (min.) tl th fi g. 4.13.3.1 duty ratio of the buzzer signal waveform note: when a digital envelope has been added to the buzzer signal, the bdty0?dty2 settings will be invalid due to the control of the duty ratio.
104 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (sound generator) 4.13.4 digital envelope a digital envelope for duty control can be added to the buzzer signal. the envelope can be controlled by staged changing of the same duty envelope as detailed in table 4.13.3.2 in the preceding item from level 1 (maximum) to level 8 (minimum). the addition of an envelope to the buzzer signal can be done by writing "1" into enon, but when "0" has been written it is not added. when a buzzer signal output is begun (writing "1" into bze) after setting enon, the duty ratio shifts to level 1 (maximum) and changes in stages to level 8. when attenuated down to level 8 (minimum), it is retained at that level. the duty ratio can be returned to maximum, by writing "1" into register enrst during output of a envelope attached buzzer signal. the envelope attenuation time (time for changing of the duty ratio) can be selected by the register enrtm. the time for a 1 stage level change is 62.5 msec (16 hz), when "0" has been written into enrtm and 125 msec (8 hz), when to "1" has been written. however, there is also a max. 4 msec error from envelope on, up to the first change. figure 4.13.4.1 shows the timing chart of the digital envelope. bzfq0? enon enrst enrtm bze t 01 t 02 t 03 t 04 t 05 t 06 t 07 t 01 t 11 t 12 t 13 t 14 t 15 t 16 t 17 level 1 (max.) 2 3 4 5 6 7 8 (min.) bz signal duty ratio no change of duty level t 01 t 02?7 = 62.5 msec = 62.5 msec +0 ? t 11 t 12?7 = 125 msec = 125 msec +0 ? fi g. 4.13.4.1 timing chart for digital envelope
s1c63654 technical manual epson 105 chapter 4: peripheral circuits and operation (sound generator) 4.13.5 one-shot output the sound generator has a one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. either 125 msec or 31.25 msec can be selected by shtpw register for one-shot buzzer signal output time. the output of the one-shot buzzer is controlled by writing "1" into the one-shot buzzer trigger bzsht. when this trigger has been assigned, a buzzer signal in synchronization with the internal 256 hz signal is output from the buzzer output terminal. thereafter, when the set time has elapsed, a buzzer signal in synchronization with the 256 hz signal goes off in the same manner as for the start of output. the bzsht also permits reading. when bzsht is "1", the one-shot output circuit is in operation (during one-shot output) and when it is "0", it shows that the circuit is in the ready (outputtable) status. in addition, it can also terminate one-shot output prior to the elapsing of the set time. this is done by writing a "1" into the one-shot buzzer stop bzstp. in this case as well, the buzzer signal goes off in synchronization with the 256 hz signal. when "1" is written to bzsht again during a one-shot output, a new one-shot output for 125 msec or 31.25 msec starts from that point (in synchronization with the 256 hz signal). the one-shot output cannot add an envelope for short durations. however, the sound level can be set by selecting the duty ratio, and the frequency can also be set. one-shot output is invalid during normal buzzer output (during bze = "1"). figure 4.13.5.1 shows timing chart for one-shot output. 256 hz shtpw bzsht (w) bzsht (r) bzstp bz output fi g. 4.13.5.1 timing chart for one-shot output
106 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (sound generator) 4.13.6 i/o memory of sound generator t able 4.13.6.1 shows the i/o addresses and the control bits for the sound generator. t able 4.13.6.1 control bits of sound generator address comment d3 d2 register d1 d0 name init ? 1 10 0 4096.0 1 3276.8 2 2730.7 3 2340.6 [bzfq2, 1, 0] frequency (hz) 4 2048.0 5 1638.4 6 1365.3 7 1170.3 [bzfq2, 1, 0] frequency (hz) ff6eh 0 bzfq2 bzfq1 bzfq0 rr/w 0 ? 3 bzfq2 bzfq1 bzfq0 ? ? 2 0 0 0 unused buzzer frequency selection ff6fh 0 bdty2 bdty1 bdty0 rr/w 0 ? 3 bdty2 bdty1 bdty0 ? ? 2 0 0 0 unused buzzer signal duty ratio selection (refer to main manual) ff6ch enrtm enrst enon bze r/w w r/w enrtm enrst ? 3 enon bze 0 reset 0 0 1 sec reset on enable 0.5 sec invalid off disable envelope releasing time envelope reset (writing) envelope on/off buzzer output enable ff6dh 0 bzstp bzsht shtpw rw r/w 0 ? 3 bzstp ? 3 bzsht shtpw ? ? 2 0 0 0 stop trigger busy 125 msec invalid invalid ready 31.25 msec unused 1-shot buzzer stop (writing) 1-shot buzzer trigger (writing) 1-shot buzzer status (reading) 1-shot buzzer pulse width setting *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read bze: buzzer output control register (ff6ch?0) controls the buzzer signal output. when "1" is written: buzzer output on when "0" is written: buzzer output off reading: valid when "1" is written to bze, the bz signal is output from the bz terminal. when "0" is written, the bz terminal goes to low (v ss ). at initial reset, this register is set to "0". bzfq0?zfq2: buzzer frequency selection register (ff6eh?0?2) selects the buzzer signal frequency. t able 4.13.6.2 buzzer signal frequency setting buzzer frequency (hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 bzfq0 0 1 0 1 0 1 0 1 bzfq1 0 0 1 1 0 0 1 1 bzfq2 0 0 0 0 1 1 1 1 select the buzzer frequency from among the above 8 types that have divided the oscillation clock. at initial reset, this register is set to "0".
s1c63654 technical manual epson 107 chapter 4: peripheral circuits and operation (sound generator) bdty0?dty2: duty level selection register (ff6fh?0?2) selects the duty ratio of the buzzer signal as shown in table 4.13.6.3. t able 4.13.6.3 duty ratio setting bdty0 0 1 0 1 0 1 0 1 bdty1 0 0 1 1 0 0 1 1 bdty2 0 0 0 0 1 1 1 1 level level 1 (max.) level 2 level 3 level 4 level 5 level 6 level 7 level 8 (min.) 4096.0 2048.0 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 3276.8 1638.4 8/20 7/20 6/20 5/20 4/20 3/20 2/20 1/20 2730.7 1365.3 12/24 11/24 10/24 9/24 8/24 7/24 6/24 5/24 2340.6 1170.3 12/28 11/28 10/28 9/28 8/28 7/28 6/28 5/28 duty ratio by buzzer frequency (hz) the sound level of this buzzer can be set by selecting this duty ratio. however, when the envelope has been set to on (enon = "1"), this setting becomes invalid. at initial reset, this register is set to "0". enrst: envelope reset (ff6ch?2) resets the envelope. when "1" is written: reset when "0" is written: no operation reading: always "0" w riting "1" into enrst resets envelope and the duty ratio becomes maximum. if an envelope has not been added (enon = "0") and if no buzzer signal is being output, the reset becomes invalid. writing "0" is also invalid. this bit is dedicated for writing, and is always "0" for reading. enon: envelope on/off control register (ff6ch?1) controls the addition of an envelope onto the buzzer signal. when "1" is written: on when "0" is written: off reading: valid wr iting "1" into the enon causes an envelope to be added during buzzer signal output. when a "0" has been written, an envelope is not added. at initial reset, this register is set to "0". enrtm: envelope releasing time selection register (ff6ch?3) selects the envelope releasing time that is added to the buzzer signal. when "1" is written: 1.0 sec (125 msec 7 = 875 msec) when "0" is written: 0.5 sec (62.5 msec 7 = 437.5 msec) reading: valid the releasing time of the digital envelope is determined by the time for converting the duty ratio. when "1" has been written in enrtm, it becomes 125 msec (8 hz) units and when "0" has been written, it becomes 62.5 msec (16 hz) units. at initial reset, this register is set to "0".
108 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (sound generator) shtpw: one-shot buzzer pulse width setting register (ff6dh?0) selects the output time of the one-shot buzzer. when "1" is written: 125 msec when "0" is written: 31.25 msec reading: valid wr iting "1" into shtpw causes the one-short output time to be set at 125 msec, and writing "0" causes it to be set to 31.25 msec. it does not affect normal buzzer output. at initial reset, this register is set to "0". bzsht: one-shot buzzer trigger/status (ff6dh?1) controls the one-shot buzzer output. ?when writing when "1" is written: trigger when "0" is written: no operation w riting "1" into bzsht causes the one-short output circuit to operate and a buzzer signal to be output. this output is automatically turned off after the time set by shtpw has elapsed. the one-shot output is only valid when the normal buzzer output is off (bze = "0") and will be invalid when the normal buzzer output is on (bze = "1"). when a re-trigger is assigned during a one-shot output, the one-shot output time set with shtpw is measured again from that point (time extension). ?when reading when "1" is read: busy when "0" is read: ready during reading bzsht shows the operation status of the one-shot output circuit. during one-shot output, bzsht becomes "1" and the output goes off, it shifts to "0". at initial reset, this bit is set to "0". bzstp: one-shot buzzer stop (ff6dh?2) stops the one-shot buzzer output. when "1" is written: stop when "0" is written: no operation reading: always "0" w riting "1" into bzstp permits the one-shot buzzer output to be turned off prior to the elapsing of the time set by shtpw. writing "0" is invalid and writing "1" is also invalid except during one-shot output. this bit is dedicated for writing, and is always "0" for reading. 4.13.7 programming notes (1) since it generates a buzzer signal that is out of synchronization with the bze register, hazards may at times be produced when the signal goes on/off due to the setting of the bze register. (2) the one-shot output is only valid when the normal buzzer output is off (bze = "0") and will be invalid when the normal buzzer output is on (bze = "1").
s1c63654 technical manual epson 109 chapter 4: peripheral circuits and operation (r/f converter) 4.14 r/f converter 4.14.1 configuration of r/f converter the s1c63654 has a cr oscillation type r/f converter. tw o systems (channel 0 and channel 1) of cr oscillation circuit are built into this r/f converter, so it is possible to compose two types of r/f conversion circuits by connecting different sensors to each cr oscillation circuit. channel 0 can be used as an r/f conversion circuit using a resistive sensor such as a thermistor, and channel 1 can be used as an r/f conversion circuit same as channel 0, or an r/f conversion circuit for humidity conversion using a resistive humidity sensor. the channel to be used and sensor type for channel 1 are selected using software. resistance value (relative value to external reference resistance) of the resistive sensor that has been connected to the sensor input terminal is converted into frequency by the cr oscillation circuit and the number of clocks is counted in the built-in measurement counter. by reading the value of the measure- ment counter, it can obtain the data after digitally-converting the value detected by the sensor. v arious sensor circuits such as temperature/humidity measurement circuits can be easily realized using this r/f converter. the configuration of the r/f converter is shown in figure 4.14.1.1. v dd v ss osc1 osc3 ref0 sen0 rfin0 interrupt request ch. 0 oscillation control circuit ref1 v dd v ss sen1 hud rfin1 ch. 1 oscillation control circuit measurement counter time base counter data bus interrupt control ovtbc ovmc mc00 ~mc03 mc04 ~mc07 mc08 ~mc11 clock selector input control channel control ac, dc control mc12 ~mc15 time base counter control tc00 ~tc03 tc04 ~tc07 tc08 ~tc11 tc12 ~tc15 mc16 ~mc19 tc16 ~tc19 rfout fi g. 4.14.1.1 configuration of r/f converter
110 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (r/f converter) 4.14.2 connection terminals and cr oscillation circuit t wo systems of cr oscillation circuit, channel 0 and channel 1, are built into the r/f converter and perform cr oscillation with external resistor and capacitor. the counter that is used to obtain an r/f converted value is shared with channel 0 and channel 1. there- fore, operation for two systems is realized by switching the cr oscillation circuit that performs r/f conversion. the channel selection is done using the register sensel. when sensel is set to "0", channel 0 is selected and when "1" is set, channel 1 is selected. the sensor type to be r/f converted in the channel 1 can also be selected by the software, and it should be previously set using the register rfsel. channel selection sensel = "0": channel 0 sensel = "1": channel 1 sensor selection for channel 1 rfsel = "0": r/f conversion using a resistive sensor such as thermistor rfsel = "1": r/f conversion using a resistive humidity sensor * * the operation of the oscillation circuit differs from the normal resistive sensor. (refer to the following.) (1) r/f conversion using a resistive sensor such as thermistor channel 0 is set only for this conversion method, and channel 1 is selected into this method by setting rfsel to "0". this method should be selected for r/f conversion using a normal resistive sensor (dc bias), such as temperature measurement using thermistor. at initial reset, channel 1 is set into this conversion method. figure 4.14.2.1 shows the connection diagram of external elements. r1 r2 v ss c sen0 ref0 rfin0 channel 0 r1 r2 v ss c sen1 hud ref1 rfin1 channel 1 r1: r2: c: thermistor reference resistor capacitor fi g. 4.14.2.1 connection diagram in case of r/f conversion connect a resistive sensor (such as a thermistor) between the sen0 (sen1) and rfin0 (rfin1) terminals. next, set the reference value of the item to be measured (e.g. reference temperature in the case of temperature measurement) and connect the reference resistance equivalent to the sensor resistance value at the above reference value between the ref0 (ref1) and rfin0 (rfin1) terminals. an element that does not change due to temperature or other environmental conditions must be used as the reference resistance. connect an oscillating capacitor that is used for cr oscillation of both the reference resistance and the sensor between the rfin0 (rfin1) and v ss terminals. the hud terminal should be opened because it is not used in this method. the r/f converter performs cr oscillation using each of the two resistances (sensor and reference r esistance) in the same period, and counts the cr oscillation clock. difference in counted oscillation frequency can be evaluated in terms of the difference between the respective resistance values. measurement results can be obtained from the changes in resistance values after correcting the difference according to the program.
s1c63654 technical manual epson 111 chapter 4: peripheral circuits and operation (r/f converter) the cr oscillation circuit is designed so that either the reference resistance side or the sensor side can be operated independently by the oscillation control circuit. each circuit performs the same oscillating operation as follows: v ss tr2 tr1 tr3 v ss sen0(1) ref0(1) rfin0(1) v dd oscillation control circuit rfout count clock ? ? fi g. 4.14.2.2 cr oscillation circuit (dc bias) the tr1 (tr2) turns on first, and the capacitor connected between the ref (sen) and v ss terminals is charged through the reference resistance (sensor). if the voltage level of the rfin terminal decreases, the tr1 (tr2) turns off and the tr3 turns on. as a result, the capacitor becomes discharged, and oscilla- tion is performed according to cr time constant. the time constant changes as the sensor resistance value fluctuates, producing a difference from the oscillation frequency of the reference resistance. oscillation waveforms are shaped by the schmitt trigger and transmitted to the measurement counter. the clock transmitted to the measurement counter is also output from the rfout terminal while the sensor is oscillating. as a result, oscillation frequency can be identified by the oscilloscope. since this monitor has no effect on oscillation frequency, it can be used to adjust r/f conversion accuracy. oscillation waveforms and waveforms output from the rfout terminal are shown in figure 4.14.2.3. the "l" pulse width of the rfout output must be 10 sec or more (when v dd = 3.0 v, r sen0/1 = 50 k ? , c rf = 1000 pf). rfin0/1 terminal rfout output v dd v ss v dd v ss 10 sec or more fi g. 4.14.2.3 oscillation waveform
112 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (r/f converter) (2) r/f conversion using a resistive humidity sensor this conversion is possible only in channel 1, and this method is selected by setting the rfsel register to "1". this is basically the same as the r/f conversion described above (1), but the ac bias circuit works for the humidity sensor. figure 4.14.2.4 shows the connection diagram of external devices. r2 v ss c sen1 hud ref1 rfin1 channel 1 r1: r2: c: resistive humidity sensor reference resistor capacitor r1 fi g. 4.14.2.4 connection diagram of resistive humidity sensor connect a humidity sensor between the hud and sen1 terminals, and connect a reference resistance between the ref1 and rfin1 terminals. connect an oscillating capacitor that is used for cr oscillation of both the reference resistance and the sensor between the rfin1 and v ss terminals. the oscillating operation by reference resistance is the same as the r/f conversion described above (1). the humidity sensor cannot be dc biased for a long time, therefore this method powers the hud and sen1 terminals alternately. v ss tr1 tr2 v ss ref1 sen1 rfin1 v dd oscillation control circuit rfout count clock ? hud s1 s2 ? ? ? tr1 = on, s1 = on tr2 = on, s2 = on fi g. 4.14.2.5 cr oscillation circuit for resistive humidity sensor the oscillation waveform is the same as figure 4.14.2.3.
s1c63654 technical manual epson 113 chapter 4: peripheral circuits and operation (r/f converter) 4.14.3 operation of r/f conversion counter the r/f converter incorporates two types of counters: measurement counter mcxx and time base counter tcxx. the measurement counter is a 20-bit up counter that counts the cr oscillation clock with the reference resistance or sensor selected by software. the time base counter is a 20-bit up/ down counter to equal both oscillation times for the reference resistance and the sensor. the time base counter uses the count clock selected by the rfclk register (osc1 or osc3). each counter permits r eading and writing on a 4-bit basis. first start an r/f conversion for the reference resistance. the measurement counter starts counting up and the time base counter starts counting down. the counters stop counting when the measurement counter overflows (counter = 00000h). by resetting the time base counter to 00000h before starting an r/f conversion for the reference resistance, the reference oscillation time will be obtained from the time base counter. then start an r/f conversion for the sensor, the measurement counter starts counting up from 00000h and the time base counter starts counting up from the counted value. the counters stop counting when the time base counter overflows (counter = 00000h). the oscillation time in this phase is the same as that of the reference resistance. therefore, by converting a proper initial value for counting of the oscillation of the reference resis- tance into a complement (value subtracted from 00000h) and setting it into the measurement counter before starting to count, the number of counts for the sensor oscillation is obtained by reading the measurement counter after the r/f conversion. in other words, the difference between the reference r esistance and sensor oscillation frequencies can be found easily. for instance, if resistance values of the reference resistance and the sensor are equivalent, the same value as the initial value before converting into a complement will be obtained as the result. the time base counter allows reading of the counter value and presetting of data. by saving the counter value after the reference oscillation has completed into the ram, the subsequent reference oscillation phase can be omitted. the sensor oscillation can be started after setting the saved value to the time base counter and 00000h to the measurement counter. note: when setting the measurement counter, always write 5 words of data continuously in order from the lower address (ff92h ff93h ff94h ff95h ff96h). furthermore, an ld instruc- tion should be used for writing data to the measurement counter and a read-modify-write instruc- tion (and, or, add, sub, etc.) cannot be used. r/f conversion sequence an r/f conversion for the reference resistance starts by writing "1" to the register rfrunr. however, an initial value must be set to the measurement counter and the time base counter must be cleared to 00000h before starting the r/f conversion. when r/f conversion is initiated by the rfrunr register, oscillation by the reference resistance begins, and the measurement counter starts counting up from the initial value by the oscillation clock. the time base counter also starts counting down by the osc1 clock. if the measurement counter becomes 00000h due to overflow, the oscillation is terminated. at the same time an interrupt occurs and the rfrunr register is set to "0", and the r/f converter circuit stops operation completely. the time base counter value should be saved into the ram for r/f conversion of the sensor. figure 4.14.3.1 shows a timing chart for the reference oscillation.
114 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (r/f converter) interrupt is generated input clock rfrunr register rfin0/1 time base counter clock time base counter measurement counter clock rfout output measurement counter n * n+1 n+2 fffffh 00000h * : initial setting value (complement) for counting of reference resistance 00000h fffffh ffffeh ffffdh ffffch ffffbh x+3 x+2 x+1 x time base counter starts counting (count-down) starts measurement of reference resistance measurement counter starts counting fi g. 4.14.3.1 reference oscillation timing chart cr oscillation starts in synchronization with the falling edge of the input clock immediately after writing "1" to the rfrunr register. the measurement counter starts counting up at the falling edge of the first clock after cr oscillation is initiated. the time base counter is enabled at the falling edge of the first input clock. then, it counts down by the rising edge of the input clock. the rfrunr register is set to "0" at the falling edge of the input clock immediately after the measurement counter stops. interrupt conditions are sampled with the osc1 clock, so an interrupt occurs in synchronization with the rising edge of the osc1 clock immediately after the rfrunr register is set to "0". an r/f conversion for the sensor starts by writing "1" to the register rfruns. when performing this sensor oscillation after an reference oscillation has completed, it is not necessary to set initial values to the counters. if converting the sensor resistance independently, the measurement counter must be set to 00000h and the time base counter must be set to the value measured at the time of a reference oscillation. when r/f conversion is initiated by the rfruns register, oscillation by the sensor begins, and the measurement counter starts counting up from 00000h by the oscillation clock. the time base counter also starts counting up by the input clock. if the time base counter becomes 00000h, the oscillation is terminated. at the same time an interrupt occurs and the rfruns register is set to "0", and the r/f converter circuit stops operation completely. figure 4.14.3.2 shows a timing chart for the sensor oscillation. 00000h 00001h 00002h n-1 n * x x+1 x+2 x+3 x+4 x+5 ffffeh fffffh 00000h interrupt is generated time up input clock rfruns register rfin0/1 time base counter clock time base counter measurement counter clock rfout output measurement counter starts measurement of sensor time base counter starts counting (count-up) * : number of counts during sensor oscillation measurement counter starts counting fi g. 4.14.3.2 sensor oscillation timing chart the sensor oscillation starts in synchronization with the falling edge of the input clock immediately after writing "1" to the rfruns register. the measurement counter starts counting up at the falling edge of the first clock after cr oscillation is initiated. the time base counter is enabled at the falling edge of the first input clock. then, it counts up by the rising edge of the input clock. depending on the timing, the measurement counter may not count the cr oscillation clock at the time rfruns is set to "0".
s1c63654 technical manual epson 115 chapter 4: peripheral circuits and operation (r/f converter) the rfruns register is set to "0" at the falling edge of the input clock immediately after the time base counter reaches 00000h. interrupt conditions are sampled with the osc1 clock, so an interrupt occurs in synchronization with the rising edge of the osc1 clock immediately after the rfruns register is set to "0". by the above operation, the sensor is oscillated for the same period of time as the reference resistance is oscillated. therefore, the difference in oscillation frequency can be measured from the values counted by the measurement counter. since the reference resistance is oscillated until the measurement counter overflows, an appropriate initial value needs to be set before r/f conversion is started. if a smaller initial value is set, a longer counting period is possible, thereby ensuring more accurate detection. however, the time base counter may overflow while counting the oscillation frequency of the reference resistance. if an overflow occurs, cr oscillation and r/f conversion is terminated immediately. also in such cases, an interrupt occurs. moreover, the measurement counter may overflow while counting the sensor oscillation depending on initial value setting. if the measurement counter overflows, cr oscillation and r/f conversion is terminated at that point and an interrupt occurs. when these overflows occur, the correct value cannot be read. therefore, the overflow flags are provided to judge whether the read data is correct or an overflow occurs. there are two overflow flags; ovmc that indicates an measurement counter overflow and ovtbc that indicates an time base counter overflow. these flags are set to "1" if respective counter overflows. these flags are reset to "0" when r/f conversion is started or when "1" is written to the flag. when the interrupt occurs, be sure to r ead the overflow flags and check overflow. the initial value to be set depends on the measurable range by the sensor or where to set the reference r esistance value within that range. the initial value must be set taking the above into consideration. convert the initial value into a complement (value subtracted from 00000h) before setting it on the measurement counter. since the data output from the measurement counter after r/f conversion matches data detected by the sensor, process the difference between that value and the initial value before it is converted into a complement according to the program and calculate the target value. the above operations are shown in figure 4.14.3.3. measurement counter (mc) (00000h-n) (1) set the initial value 00000h-n 00000h count up ffffh 0 0 count up : m time base counter (tc) 00000h count down : x x ffffh 00000h (2) start reference oscillation (set rfrunr to "1") (3) read the measurement counter and process the m - n value by the program setting by software set the complement of the initial value n on the measurement counter. set 00000h on the time base counter. (set 00000h on the measurement counter. set x on the time base counter.) oscillation by reference resistance the cr oscillation stops when the measurement counter overflows and an interrupt occurs. save the tc value into the memory. when the value of the time base counter reaches 00000h, oscillation and counting stop, and an interrupt occurs. oscillation by sensor count up reference oscillation (1) set the initial value (00000h) (x) (2) start sensor oscillation (set rfruns to "1") sensor oscillation fi g. 4.14.3.3 sequence of r/f conversion note: set the initial value of the measurement counter taking into account the measurable range and the ov erflow of counters.
116 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (r/f converter) 4.14.4 interrupt function the r/f converter has a function which allows interrupt to occur after r/f conversion. when the measurement counter is counted up to 00000h, both counters stop counting. the interrupt factor flag irfb is set to "1" at the rising edge of the osc1 clock immediately after rfrunr is set to "0" and an interrupt occurs. when the time base counter is counted down to 00000h, both counters stop counting. the interrupt factor flag irfm is set to "1" at the rising edge of the osc1 clock immediately after the rfruns register is set to "0" and an interrupt occurs. if the measurement counter overflows during counting of the sensor oscillation, or the time base counter overflows during counting of the reference resistance oscillation, the interrupt factor flag irfm or irfb is also set to "1". these interrupt factors allow masking by the interrupt mask registers eirfm and eirfb. when the eirfm/eirfb has been set at "1", an interrupt occurs in the cpu. when the eirfm/eirfb is set at "0", no interrupt will occur in the cpu even if the interrupt factor flag is set to "1". the interrupt factor flag is reset to "0" by writing "1". ti ming of interrupt by the r/f converter is shown in figures 4.14.4.1 to 4.14.4.4. n 0 ffffch ffffbh n+1 n+2 n+3 ffffd ffffeh fffffh 0 x+3 x+2 x+1 x fffffh ffffeh oscillation by reference resistance input clock rfrunr register time base counter measurement counter clock measurement counter irfb interrupt request count-down ffffdh fi g. 4.14.4.1 reference oscillate completion interrupt 0 xx+4x+5 1 23 m-3m -2 m-1 m ffffeh fffffh 0 x+1 x+2 oscillation by sensor resistance input clock rfruns register time base counter measurement counter clock measurement counter irfm interrupt request count-up x+3 fi g. 4.14.4.2 sensor oscillate completion interrupt 0 xx+4x+5 1 23 ffffdh ffffeh fffffh 0 y-2 y-1 y x+1 x+2 x+3 oscillation by sensor resistance input clock rfruns register time base counter measurement counter clock measurement counter ovmc, irfm interrupt request count-up fi g. 4.14.4.3 measurement counter overflow interrupt
s1c63654 technical manual epson 117 chapter 4: peripheral circuits and operation (r/f converter) n 0 ffffch ffffbh n+1 n+2 n+3 m-2 m-1 m( 0) undefined 3210 fffffh ffffeh ffffdh overflow oscillation by reference resistance input clock rfrunr register time base counter measurement counter clock measurement counter ovtbc, irfb interrupt request count-down fi g. 4.14.4.4 time base counter overflow interrupt note: when the r/f converter interrupt is generated, be sure to check whether or not the r/f conversion has completed normally by reading the overflow flags. ? hen an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag (ovmc or ovtbc) is not reset. be sure to check and reset to "0" (writing "1") the overflow flag when the r/f converter interrupt occurs.
118 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (r/f converter) 4.14.5 i/o memory of r/f converter t able 4.14.5.1 shows the i/o addresses and the control bits for the r/f converter. t able 4.14.5.1 control bits of r/f converter address comment d3 d2 register d1 d0 name init ? 1 10 mc3 mc2 mc1 mc0 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc0?c3 lsb r/w r/w ff92h mc3 mc2 mc1 mc0 mc7 mc6 mc5 mc4 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc4?c7 ff93h mc7 mc6 mc5 mc4 mc19 mc18 mc17 mc16 ? ? 2 ? ? 2 ? ? 2 ? ? 2 msb measurement counter mc16?c19 r/w ff96h mc19 mc18 mc17 mc16 tc11 tc10 tc9 tc8 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc8?c11 r/w ff99h tc11 tc10 tc9 tc8 tc15 tc14 tc13 tc12 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc12?c15 r/w ff9ah tc15 tc14 tc13 tc12 tc19 tc18 tc17 tc16 ? ? 2 ? ? 2 ? ? 2 ? ? 2 msb time base counter tc16?c19 r/w ff9bh tc19 tc18 tc17 tc16 tc3 tc2 tc1 tc0 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc0?c3 lsb r/w ff97h tc3 tc2 tc1 tc0 tc7 tc6 tc5 tc4 ? ? 2 ? ? 2 ? ? 2 ? ? 2 time base counter tc4?c7 r/w ff98h tc7 tc6 tc5 tc4 r/w mc11 mc10 mc9 mc8 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc8?c11 ff94h mc11 mc10 mc9 mc8 r/w mc15 mc14 mc13 mc12 ? ? 2 ? ? 2 ? ? 2 ? ? 2 measurement counter mc12?c15 ff95h mc15 mc14 mc13 mc12 ffe7h 00ei rfb eirfm rr/w 0 ? 3 0 ? 3 eirfb eirfm ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (r/f converter reference oscillate completion) interrupt mask register (r/f converter sensor oscillate completion) fff7h 00i rfb irfm rr/w 0 ? 3 0 ? 3 irfb irfm ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (r/f converter reference oscillate completion) interrupt factor flag (r/f converter sensor oscillate completion) ff90h 0 rfclk rfsel sensel rr/w 0 ? 3 rfclk rfsel sensel ? ? 2 0 0 0 osc3 ac ch. 1 osc1 dc ch. 0 unused r/f conversion clock selection ch. 1 sensor type selection conversion channel selection ff91h ovtbc ovmc rfrunr rfruns r/w ovtbc ovmc rfrunr rfruns 0 0 0 0 overflow overflow run run non-ov non-ov stop stop time base counter overflow flag measurement counter overflow flag reference oscillation run control/status (writing "0" is ineffective) sensor oscillation run control/status (writing "0" is ineffective) *1 initial value at initial reset *3 constantly "0" when being read *2 not set in the circuit
s1c63654 technical manual epson 119 chapter 4: peripheral circuits and operation (r/f converter) mc0?c19: measurement counter (ff92h?f96h) the measurement counter counts up according to the cr oscillation clock. it permits writing and reading on a 4-bit basis. the complement of the number of clocks to be counted by the oscillation of the reference resistance must be entered in this counter prior to reference oscillation. when the counter reaches 00000h due to over- flow, the oscillation of the reference resistance stops. when converting a sensor oscillation, 00000h must be set in this register (it is unnecessary when it is done immediately after a reference oscillation has completed). the sensor oscillation and measurement counter stop when the time base counter overflows. number of clocks counted by the sensor oscillation can be evaluated from the value indicated by the counter when it stops. calculate the target value by processing the above counted number according to the program. measurable range and the overflow of the counter must be taken into account when setting an initial value to be entered prior to r/f conversion. at initial reset, this counter is undefined. tc0?c19: time base counter (ff97h?f9bh) w riting and reading is possible on a 4-bit basis by the time base counter that is used to adjust the cr oscillation time between the reference resistance and the sensor. the time base counter counts down during oscillation of the reference resistance and counts up to 00000h during oscillation of the sensor. 00000h needs to be entered in the counter prior to a reference oscillation in order to adjust the cr oscillating time (number of clocks) of both counts. the counter value after a reference oscillation has completed should be read from this register and save it in the memory. the saved value should be set in this counter before starting a sensor oscillation. at initial reset, this counter is undefined. rfclk: input clock selection (ff90h?2) selects the clock input to the time base counter. when "1" is written: osc3 when "0" is written: osc1 reading: valid select the count clock for the time base counter. when "1" is written to rfclk, the osc3 clock is selected. when "0" is written, the osc1 clock (typ. 32 khz) is selected. to select the osc3 clock, the osc3 oscilla- tion frequency must be 2 mhz or less. at initial reset, this register is set to "0". rfsel: sensor selection for channel 1 (ff90h?1) selects a sensor type to be used for channel 1. when "1" is written: resistive humidity sensor when "0" is written: resistive sensor reading: valid when "1" is written to rfsel, a resistive humidity sensor is selected as the sensor for channel 1. when "0" is written, a normal resistive sensor is selected. at initial reset, this register is set to "0". sensel: channel selection register (ff90h?0) selects the channel to be converted. when "1" is written: channel 1 when "0" is written: channel 0 reading: valid when "1" is written to sensel, channel 1 is selected for r/f conversion and when "0" is written, channel 0 is selected. at initial reset, this register is set to "0".
120 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (r/f converter) rfrunr: reference oscillation run control/status (ff91h?1) starts r/f conversion for the reference resistance and indicates the operating (run/stop) status. when "1" is written: r/f conversion starts when "0" is written: no operation when "1" is read: run status when "0" is read: stop status when "1" is written to rfrunr, r/f conversion for the reference resistance starts. the register remains at "1" during r/f conversion and is set to "0" when r/f conversion is terminated. w riting "0" to rfrunr is invalid. at initial reset, this register is set to "0". rfruns: sensor oscillation run control/status (ff91h?0) starts r/f conversion for the sensor and indicates the operating (run/stop) status. when "1" is written: r/f conversion starts when "0" is written: no operation when "1" is read: run status when "0" is read: stop status when "1" is written to rfruns, r/f conversion for the sensor starts. the register remains at "1" during r/f conversion and is set to "0" when r/f conversion is terminated. w riting "0" to rfruns is invalid. at initial reset, this register is set to "0". ov mc: measurement counter overflow flag (ff91h?2) indicates whether the measurement counter has overflown. when "1" is read: overflow has occurred when "0" is read: overflow has not occurred when "1" is written: flag reset when "0" is written: no operation if an overflow occurs while counting the oscillation of the sensor, ovmc is set to "1" and the interrupt occurs at the same time. this flag is reset by writing "1" or starting r/f conversion. at initial reset, this flag is set to "0". o vtbc: time base counter overflow flag (ff91h?3) indicates whether the time base counter has overflown. when "1" is read: overflow has occurred when "0" is read: overflow has not occurred when "1" is written: flag reset when "0" is written: no operation if an overflow occurs while counting the oscillation of the reference resistance, ovtbc is set to "1" and the interrupt occurs at the same time. this flag is reset by writing "1" or starting r/f conversion. at initial reset, this flag is set to "0".
s1c63654 technical manual epson 121 chapter 4: peripheral circuits and operation (r/f converter) eirfm, eirfb: interrupt mask registers (ffe7h?0, d1) select whether to mask interrupt with the r/f converter. when "1" is written: enable when "0" is written: mask reading: valid eirfm and eirfb are the interrupt mask registers for the sensor oscillate completion interrupt and the r eference oscillate completion interrupt. the r/f converter interrupt is permitted when "1" is written to eirfm and eirfb. when "0" is written, interrupt is masked. at initial reset, these registers are set to "0". irfm, irfb: interrupt factor flags (fff7h?0, d1) these flags indicate the status of the r/f converter interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred when "1" is written: flag is reset when "0" is written: invalid irfb is set to "1" when an r/f conversion for the reference resistor is terminated or when the time base counter overflows while counting the oscillation of the reference resistance. irfm is set to "1" when an r/f conversion for the sensor is terminated or when the measurement counter overflows while counting the oscillation of the sensor. from the status of these flags, the software can decide whether an r/f converter interrupt has occurred. further this flag is set in the above timing regardless of the interrupt mask register setting (except for debug mode). these flags are reset to "0" by writing "1". after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. after an initial reset, these flags are set to "0". 4.14.6 programming notes (1) depending on the initial value of the measurement counter (mc), the measurement counter or the time base counter may overflow while the cr oscillation clock is being counted. when setting the initial value, pay attention to cr oscillation frequency, its fluctuation range and the input clock frequency of the time base counter. if an overflow occurs, r/f conversion is terminated immediately. when the r/f conversion result (measurement counter value) is read, check the overflow flags (ovmc and ovtbc). the upper limit of the cr oscillation frequency is 500 khz. there is no lower- limit but make sure that the time base counter does not overflow. (2) when an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag (ovmc or ovtbc) is not reset. be sure to check and reset to "0" (writing "1") the overflow flag when the r/f converter interrupt occurs. (3) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. (4) when selecting osc3 for the time base counter clock, the maximum frequency of the osc3 clock is limited to 2 mhz. (5) when setting the measurement counter, always write 5 words of data continuously in order from the lower address (ff92h ff93h ff94h ff95h ff96h). furthermore, an ld instruction should be used for writing data to the measurement counter and a read-modify-write instruction (and, or, add, sub, etc.) cannot be used.
122 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (svd circuit) 4.15 svd (supply voltage detection) circuit 4.15.1 configuration of svd circuit the s1c63654 has a built-in svd (supply voltage detection) circuit, so that the software can find when the source voltage lowers. turning the svd circuit on/off and the svd criteria voltage setting can be done with software. figure 4.15.1.1 shows the configuration of the svd circuit. v detection output data bus dd v ss svdon svds2 | svds0 criteria voltage setting circuit svd circuit svddt fi g. 4.15.1.1 configuration of svd circuit 4.15.2 svd operation the svd circuit compares the criteria voltage set by software and the supply voltage (v dd terminal? ss terminal) and sets its results into the svddt latch. by reading the data of this svddt latch, it can be determined by means of software whether the supply voltage is normal or has dropped. the criteria voltage can be selected as shown in table 4.15.2.1 by the svds2?vds0 register. t able 4.15.2.1 criteria voltage svds2 1 1 1 1 0 0 0 0 svds1 1 1 0 0 1 1 0 0 svds0 1 0 1 0 1 0 1 0 criteria voltage ( v ) 2.90 2.75 2.60 2.45 2.30 2.15 2.00 1.85 when the svdon register is set to "1", source voltage detection by the svd circuit is executed. as soon as the svdon register is reset to "0", the result is loaded to the svddt latch and the svd circuit goes off. to obtain a stable detection result, the svd circuit must be on for at least 500 ?ec. so, to obtain the svd detection result, follow the programming sequence below. 1. set svdon to "1" 2. maintain for 500 ?ec minimum 3. set svdon to "0" 4. read svddt when the svd circuit is on, the ic draws a large current, so keep the svd circuit off unless it is.
s1c63654 technical manual epson 123 chapter 4: peripheral circuits and operation (svd circuit) 4.15.3 i/o memory of svd circuit t able 4.15.3.1 shows the i/o addresses and the control bits for the svd circuit. t able 4.15.3.1 control bits of svd circuit address comment d3 d2 register d1 d0 name init ? 1 10 ff05h 00 svddt svdon rr/w 0 ? 3 0 ? 3 svddt svdon ? ? 2 ? ? 2 0 0 low on normal off unused unused svd evaluation data svd circuit on/off ff04h 0 svds2 svds1 svds0 rr/w 0 ? 3 svds2 svds1 svds0 ? ? 2 0 0 0 unused svd criteria voltage setting 1 2.00 2 2.15 3 2.30 4 2.45 5 2.60 6 2.75 7 2.90 [svds2?] voltage(v) 0 1.85 *1 initial value at initial reset *2 not set in the circuit *3 constantly "0" when being read svds2?vds0: svd criteria voltage setting register (ff04h?2?0) criteria voltage for svd is set as shown in table 4.15.2.1. at initial reset, this register is set to "0". svdon: svd control (on/off) register (ff05h?0) t urns the svd circuit on and off. when "1" is written: svd circuit on when "0" is written: svd circuit off reading: valid when svdon is set to "1", a source voltage detection is executed by the svd circuit. as soon as svdon is reset to "0", the result is loaded to the svddt latch. to obtain a stable detection result, the svd circuit must be on for at least 500 ?ec. at initial reset, this register is set to "0". svddt: svd data (ff05h?1) this is the result of supply voltage detection. when "0" is read: supply voltage (v dd ? ss ) criteria voltage when "1" is read: supply voltage (v dd ? ss ) < criteria voltage w riting: invalid the result of supply voltage detection at time of svdon is set to "0" can be read from this latch. at initial reset, svddt is set to "0". 4.15.4 programming notes (1) to obtain a stable detection result, the svd circuit must be on for at least 500 ?ec. so, to obtain the svd detection result, follow the programming sequence below. 1. set svdon to "1" 2. maintain for 500 ?ec minimum 3. set svdon to "0" 4. read svddt (2) the svd circuit should normally be turned off because svd operation increase current consumption.
124 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (interrupt and halt) 4.16 interrupt and halt the s1c63654 provides the following interrupt functions. external interrupt: input interrupt (2 systems) internal interrupt: watchdog timer interrupt (nmi, 1 system) ?programmable timer interrupt (4 systems) ?serial interface interrupt (1 system) ?clock timer interrupt (4 systems) ?stopwatch timer interrupt (4 systems) ?r/f converter interrupt (2 systems) to authorize interrupt, the interrupt flag must be set to "1" (ei) and the necessary related interrupt mask r egisters must be set to "1" (enable). when an interrupt occurs the interrupt flag is automatically reset to "0" (di), and interrupts after that are inhibited. the watchdog timer interrupt is an nmi (non-maskable interrupt), therefore, the interrupt is generated r egardless of the interrupt flag setting. also the interrupt mask register is not provided. however, it is possible to not generate nmi since software can stop the watchdog timer operation. figure 4.16.1 shows the configuration of the interrupt circuit. note: after an initial reset, all the interrupts including nmi are masked until both the stack pointers sp1 and sp2 are set with the software. be sure to set the sp1 and sp2 in the initialize routine. further, when re-setting the stack pointer, the sp1 and sp2 must be set as a pair. when one of them is set, all the interrupts including nmi are masked and interrupts cannot be accepted until the other one is set. the s1c63654 has halt functions that considerably reduce the current consumption when it is not necessary. the cpu enters halt status when the halt instruction is executed. in halt status, the operation of the cpu is stopped. however, timers continue counting since the oscillation circuit operates. reactivating the cpu from halt status is done by generating a hardware interrupt request including nmi.
s1c63654 technical manual epson 125 chapter 4: peripheral circuits and operation (interrupt and halt) fi g. 4.16.1 configuration of the interrupt circuit k10 kcp10 sik10 k11 kcp11 sik11 k12 kcp12 sik12 k13 kcp13 sik13 ik1 eik1 it3 eit3 it2 eit2 it1 eit1 it0 eit0 irun eirun ilap eilap isw1 eisw1 isw10 eisw10 irfm eirfm irfb eirfb k00 kcp00 sik00 k01 kcp01 sik01 k02 kcp02 sik02 k03 kcp03 sik03 ik0 eik0 interrupt vector generation circuit program counter (low-order 4 bits) int interrupt request interrupt factor flag interrupt mask register input comparison register interrupt selection register interrupt flag nmi request watchdog timer isif eisif ipt1 eipt1 ipt0 eipt0 ictc1 ectc1 ictc0 ectc0
126 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (interrupt and halt) 4.16.1 interrupt factor t able 4.16.1.1 shows the factors for generating interrupt requests. the interrupt flags are set to "1" depending on the corresponding interrupt factors. the cpu operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are established. ?the corresponding mask register is "1" (enabled) ?the interrupt flag is "1" (ei) the interrupt factor flag is reset to "0" when "1" is written. at initial reset, the interrupt factor flags are reset to "0". ? since the watchdog timer's interrupt is nmi, the interrupt is generated regardless of the setting above, and no interrupt factor flag is provided. t able 4.16.1.1 interrupt factors interrupt factor programmable timer 1 (compare match) programmable timer 0 (compare match) programmable timer 1 (underflow) programmable timer 0 (underflow) serial interface (8-bit data input/output completion) k00?03 input (falling edge or rising edge) k10?13 input (falling edge or rising edge) clock timer 1 hz (falling edge) clock timer 2 hz (falling edge) clock timer 8 hz (falling edge) clock timer 32 hz (falling edge) stopwatch timer (direct run) stopwatch timer (direct lap) stopwatch timer (1 hz) stopwatch timer (10 hz) r/f converter (end of reference conversion) r/f converter (end of sensor conversion) ictc1 ictc0 ipt1 ipt0 isif ik0 ik1 it3 it2 it1 it0 irun ilap isw1 isw10 irfb irfm ( fff0h?1 ) ( fff0h?0 ) ( fff1h?1 ) ( fff1h?0 ) ( fff2h?0 ) ( fff3h?0 ) ( fff4h?0 ) ( fff5h?3 ) ( fff5h?2 ) ( fff5h?1 ) ( fff5h?0 ) ( fff6h?3 ) ( fff6h?2 ) ( fff6h?1 ) ( fff6h?0 ) ( fff7h?1 ) ( fff7h?0 ) interrupt factor flag note: after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.
s1c63654 technical manual epson 127 chapter 4: peripheral circuits and operation (interrupt and halt) 4.16.2 interrupt mask the interrupt factor flags can be masked by the corresponding interrupt mask registers. the interrupt mask registers are read/write registers. they are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. at initial reset, the interrupt mask register is reset to "0". t able 4.16.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags. t able 4.16.2.1 interrupt mask registers and interrupt factor flags ictc1 ictc0 ipt1 ipt0 isif ik0 ik1 it3 it2 it1 it0 irun ilap isw1 isw10 irfb irfm ( fff0h?1 ) ( fff0h?0 ) ( fff1h?1 ) ( fff1h?0 ) ( fff2h?0 ) ( fff3h?0 ) ( fff4h?0 ) ( fff5h?3 ) ( fff5h?2 ) ( fff5h?1 ) ( fff5h?0 ) ( fff6h?3 ) ( fff6h?2 ) ( fff6h?1 ) ( fff6h?0 ) ( fff7h?1 ) ( fff7h?0 ) interrupt factor flag ectc1 ectc0 eipt1 eipt0 eisif eik0 eik1 eit3 eit2 eit1 eit0 eirun eilap eisw1 eisw10 eirfb eirfm ( ffe0h?1 ) ( ffe0h?0 ) ( ffe1h?1 ) ( ffe1h?0 ) ( ffe2h?0 ) ( ffe3h?0 ) ( ffe4h?0 ) ( ffe5h?3 ) ( ffe5h?2 ) ( ffe5h?1 ) ( ffe5h?0 ) ( ffe6h?3 ) ( ffe6h?2 ) ( ffe6h?1 ) ( ffe6h?0 ) ( ffe7h?1 ) ( ffe7h?0 ) interrupt mask register 4.16.3 interrupt vector when an interrupt request is input to the cpu, the cpu begins interrupt processing. after the program being executed is terminated, the interrupt processing is executed in the following order. 1 the content of the flag register is evacuated, then the i flag is reset. 2 the address data (value of program counter) of the program to be executed next is saved in the stack area (ram). 3 the interrupt request causes the value of the interrupt vector (0100h?10eh) to be set in the program counter. 4 the program at the specified address is executed (execution of interrupt processing routine by software). t able 4.16.3.1 shows the correspondence of interrupt requests and interrupt vectors. t able 4.16.3.1 interrupt request and interrupt vectors interrupt vector 0100h 0102h 0104h 0106h 0108h 010ah 010ch 010eh interrupt factor watchdog timer r/f converter programmable timer serial interface k00?03 input k10?13 input clock timer stopwatch timer priority high low the four low-order bits of the program counter are indirectly addressed through the interrupt request.
128 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (interrupt and halt) 4.16.4 i/o memory of interrupt t ables 4.16.4.1 shows the i/o addresses and the control bits for controlling interrupts. t able 4.16.4.1(a) control bits of interrupt address comment d3 d2 register d1 d0 name init ? 1 10 ff20h sik03 sik02 sik01 sik00 r/w sik03 sik02 sik01 sik00 0 0 0 0 enable enable enable enable disable disable disable disable k00?03 interrupt selection register ff22h kcp03 kcp02 kcp01 kcp00 r/w kcp03 kcp02 kcp01 kcp00 1 1 1 1 k00?03 input comparison register ff24h sik13 sik12 sik11 sik10 r/w sik13 sik12 sik11 sik10 0 0 0 0 enable enable enable enable disable disable disable disable k10?13 interrupt selection register ff26h kcp13 kcp12 kcp11 kcp10 r/w kcp13 kcp12 kcp11 kcp10 1 1 1 1 k10?13 input comparison register ffe3h 000ei k0 rr/w 0 ? 3 0 ? 3 0 ? 3 eik0 ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (k00?03) ffe5h eit3 eit2 eit1 eit0 r/w eit3 eit2 eit1 eit0 0 0 0 0 enable enable enable enable mask mask mask mask interrupt mask register (clock timer 1 hz) interrupt mask register (clock timer 2 hz) interrupt mask register (clock timer 8 hz) interrupt mask register (clock timer 32 hz) ffe4h 000ei k1 rr/w 0 ? 3 0 ? 3 0 ? 3 eik1 ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (k10?13) ffe6h eirun eilap eisw1 eisw10 r/w eirun eilap eisw1 eisw10 0 0 0 0 enable enable enable enable mask mask mask mask interrupt mask register (stopwatch direct run) interrupt mask register (stopwatch direct lap) interrupt mask register (stopwatch timer 1 hz) interrupt mask register (stopwatch timer 10 hz) ffe7h 00ei rfb eirfm rr/w 0 ? 3 0 ? 3 eirfb eirfm ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (r/f converter reference oscillate completion) interrupt mask register (r/f converter sensor oscillate completion) ffe0h 00 ectc1 ectc0 rr/w 0 ? 3 0 ? 3 ectc1 ectc0 ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (programmable timer 1 compare match) interrupt mask register (programmable timer 0 compare match) fff0h 00 ictc1 ictc0 rr/w 0 ? 3 0 ? 3 ictc1 ictc0 ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (programmable timer 1 compare match) interrupt factor flag (programmable timer 0 compare match) ffe2h 000ei sif rr/w 0 ? 3 0 ? 3 0 ? 3 eisif ? ? 2 ? ? 2 ? ? 2 0 enable mask unused unused unused interrupt mask register (serial i/f) fff1h 00i pt1 ipt0 rr/w 0 ? 3 0 ? 3 ipt1 ipt0 ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (programmable timer 1 underflow) interrupt factor flag (programmable timer 0 underflow) ffe1h 00ei pt1 eipt0 rr/w 0 ? 3 0 ? 3 eipt1 eipt0 ? ? 2 ? ? 2 0 0 enable enable mask mask unused unused interrupt mask register (programmable timer 1 underflow) interrupt mask register (programmable timer 0 underflow) *1 initial value at initial reset *3 constantly "0" when being read *2 not set in the circuit
s1c63654 technical manual epson 129 chapter 4: peripheral circuits and operation (interrupt and halt) t able 4.16.4.1(b) control bits of interrupt address comment d3 d2 register d1 d0 name init ? 1 10 fff5h fff6h irun ilap isw1 isw10 r/w irun ilap isw1 isw10 0 0 0 0 (r) yes (w) reset (r) no (w) invalid interrupt factor flag (stopwatch direct run) interrupt factor flag (stopwatch direct lap) interrupt factor flag (stopwatch timer 1 hz) interrupt factor flag (stopwatch timer 10 hz) fff7h 00i rfb irfm rr/w 0 ? 3 0 ? 3 irfb irfm ? ? 2 ? ? 2 0 0 (r) yes (w) reset (r) no (w) invalid unused unused interrupt factor flag (r/f converter reference oscillate completion) interrupt factor flag (r/f converter sensor oscillate completion) it3 it2 it1 it0 r/w it3 it2 it1 it0 0 0 0 0 (r) yes (w) reset (r) no (w) invalid interrupt factor flag (clock timer 1 hz) interrupt factor flag (clock timer 2 hz) interrupt factor flag (clock timer 8 hz) interrupt factor flag (clock timer 32 hz) fff3h 000ik0 rr/w 0 ? 3 0 ? 3 0 ? 3 ik0 ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (k00?03) fff4h 000ik1 rr/w 0 ? 3 0 ? 3 0 ? 3 ik1 ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (k10?13) fff2h 000is if rr/w 0 ? 3 0 ? 3 0 ? 3 isif ? ? 2 ? ? 2 ? ? 2 0 (r) yes (w) reset (r) no (w) invalid unused unused unused interrupt factor flag (serial i/f) *1 initial value at initial reset *3 constantly "0" when being read *2 not set in the circuit ectc1, ectc0: interrupt mask registers (ffe0h?1, d0) eipt1, eipt0: interrupt mask registers (ffe1h?1, d0) ictc1, ictc0: interrupt factor flags (fff0h?1, d0) ipt1, ipt0: interrupt factor flags (fff1h?1, d0) refer to section 4.11, "programmable timer". eisif: interrupt mask register (ffe2h?0) isif: interrupt factor flag (fff2h?0) refer to section 4.12, "serial interface". kcp03?cp00, kcp13?cp10: input comparison registers (ff22h, ff26h) sik03?ik00, sik13?ik10: interrupt selection registers (ff20h, ff24h) eik0, eik1: interrupt mask registers (ffe3h?0, ffe4h?0) ik0, ik1: interrupt factor flags (fff3h?0, fff4h?0) refer to section 4.5, "input ports". eit3?it0: interrupt mask registers (ffe5h) it3?t0: interrupt factor flags (fff5h) refer to section 4.9, "clock timer". eirun, eilap, eisw1, eisw10: interrupt mask registers (ffe6h) irun, ilap, isw1, isw10: interrupt factor flags (fff6h) refer to section 4.10, "stopwatch timer". eirfb, eirfm: interrupt mask registers (ffe7h?1, d0) irfb, irfm: interrupt factor flags (fff7h?1, d0) refer to section 4.14, "r/f converter".
130 epson s1c63654 technical manual chapter 4: peripheral circuits and operation (interrupt and halt) 4.16.5 programming notes (1) the interrupt factor flags are set when the interrupt condition is established, even if the interrupt mask registers are set to "0". (2) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. (3) after an initial reset, all the interrupts including nmi are masked until both the stack pointers sp1 and sp2 are set with the software. be sure to set the sp1 and sp2 in the initialize routine. further, when re-setting the stack pointer, the sp1 and sp2 must be set as a pair. when one of them is set, all the interrupts including nmi are masked and interrupts cannot be accepted until the other one is set.
s1c63654 technical manual epson 131 chapter 5: summary of notes chapter 5s ummary of n otes 5.1 notes for low current consumption the s1c63654 contains control registers for each of the circuits so that current consumption can be r educed. these control registers reduce the current consumption through programs that operate the circuits at the minimum levels. the following lists the circuits that can control operation and their control registers. refer to these when programming. t able 5.1.1 circuits and control registers circuit (and item) cpu cpu operating frequency high-speed operation voltage regulator lcd system voltage circuit voltage halver mode svd circuit control register halt instruction clkchg, oscc vdc0, vdc1 lpwr vdc2, vdc3 svdon refer to chapter 7, "electrical characteristics" for current consumption. below are the circuit statuses at initial reset. cpu : operating status cpu operating frequency : low speed side (clkchg = "0") osc3 oscillation circuit is in off status (oscc = "0") internal logic operating voltage :v d1l (vdc0 = "0") high-speed operation voltage regulator :o ff status (vdc1 = "0") lcd system voltage circuit :o ff status (lpwr = "0") v oltage halver mode :o ff status (vdc2 = vdc3 = "0") svd circuit :o ff status (svdon = "0") also, be careful about panel selection because the current consumption can differ by the order of several a on account of the lcd panel characteristics.
132 epson s1c63654 technical manual chapter 5: summary of notes 5.2 summary of notes by function here, the cautionary notes are summed up by function category. keep these notes well in mind when programming. memory and stack (1 )m emory is not implemented in unused areas within the memory map. further, some non-implemen- tation areas and unused (access prohibition) areas exist in the peripheral i/o area. if the program that accesses these areas is generated, its operation cannot be guaranteed. refer to the i/o memory maps shown in table 4.1.1 for the peripheral i/o area. (2) part of the ram area is used as a stack area for subroutine call and register evacuation, so pay attention not to overlap the data area and stack area. (3) the s1c63000 core cpu handles the stack using the stack pointer for 4-bit data (sp2) and the stack pointer for 16-bit data (sp1). 16-bit data are accessed in stack handling by sp1, therefore, this stack area should be allocated to the area where 4-bit/16-bit access is possible (0100h to 01ffh). the stack pointers sp1 and sp2 change cyclically within their respective range: the range of sp1 is 0000h to 03ffh and the range of sp2 is 0000h to 00ffh. therefore, pay attention to the sp1 value because it may be set to 0200h or more exceeding the 4-bit/16-bit accessible range in the s1c63654 or it may be set to 00ffh or less. memory accesses except for stack operations by sp1 are 4-bit data access. after initial reset, all the interrupts including nmi are masked until both the stack pointers sp1 and sp2 are set by software. further, if either sp1 or sp2 is re-set when both are set already, the interrupts including nmi are masked again until the other is re-set. therefore, the settings of sp1 and sp2 must be done as a pair. po wer control (1) when setting the low-speed operation voltage regulator into the halver mode, make sure that the supply voltage is 2.4 v or higher using the svd circuit before writing "1" to vdc2. furthermore, switch the cpu clock to osc1. (2) when setting the lcd system voltage circuit into the halver mode, make sure that the supply voltage is 2.4 v or higher using the svd circuit before writing "1" to vdc3. furthermore, set the v c1 voltage (contrast) to 1.13 v or lower (lc register = 6 or less). w atchdog timer (1) when the watchdog timer is being used, the software must reset it within 3-second cycles. (2) because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (nmi) if it is not used. oscillation circuit (1) when switching the cpu system clock from osc1 to osc3, first set the operating voltage for high- speed operation (v d3 ). after that maintain 2.5 msec or more, and then turn the osc3 oscillation on. when switching from osc3 to osc1, set the operating voltage for low-speed operation (v d1l ) after switching to osc1 and turning the osc3 oscillation off. (2) it takes at least 5 msec from the time the osc3 oscillation circuit goes on until the oscillation stabi- lizes. consequently, when switching the cpu operation clock from osc1 to osc3, do this after a minimum of 5 msec have elapsed since the osc3 oscillation went on. further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (3) when switching the clock form osc3 to osc1, use a separate instruction for switching the osc3 oscillation off. an error in the cpu operation can result if this processing is performed at the same time by the one instruction. (4) when the low-speed operation voltage regulator is in the halver mode (vdc2 = "1"), the system can be operated only in low-speed using the osc1 clock. do not switch the system clock to osc3.
s1c63654 technical manual epson 133 chapter 5: summary of notes (5) do not switch the operating voltage to v d1l while the cpu is operating with the osc3 clock. further- more, do not stop the high-speed operating voltage regulator. (6) when selecting osc3 for the time base counter clock of the r/f converter, the maximum frequency of the osc3 clock is limited to 2 mhz. input port when input ports are changed from high to low by pull-down resistors, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. hence, when fetching input ports, set an appropriate waiting time. particular care needs to be taken of the key scan during key matrix configuration. make this waiting time the amount of time or more calcu- lated by the following expression. 10 c r c: terminal capacitance 5 pf + parasitic capacitance ? pf r: pull-down resistance 375 k ? (max.) output port (1) when using the output port (r02, r03) as the special output port, fix the data register (r02, r03) at "1" and the high impedance control register (r02hiz, r03hiz) at "0" (data output). be aware that the output terminal is fixed at a low (v ss ) level the same as the dc output if "0" is written to the r02 and r03 registers when the special output has been selected. be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (r02hiz, r03hiz). (2) a hazard may occur when the fout signal and the tout signal are turned on and off. (3) when f osc3 is selected for the fout signal frequency, it is necessary to control the osc3 oscillation circuit before output. refer to section 4.4, "oscillation circuit", for the control and notes. i/o port when in the input mode, i/o ports are changed from high to low by pull-down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci- tance. hence, when fetching input ports, set an appropriate wait time. particular care needs to be taken of the key scan during key matrix configuration. make this waiting time the amount of time or more calculated by the following expression. 10 c r c: terminal capacitance 5 pf + parasitic capacitance ? pf r: pull-down resistance 375 k ? (max.) lcd driver because at initial reset, the contents of display memory are undefined and lc3 C lc0 (lcd contrast) is set to 0000b, there is need to initialize by the software. furthermore, take care of the registers lpwr and aloff because these are set so that the display goes off. clock timer be sure to read timer data in the order of low-order data (tm0 C tm3) then high-order data (tm4 C tm7). stopwatch timer (1) the interrupt factor flag should be reset after resetting the stopwatch timer. (2) be sure to data reading in the order of swd0 C 3 swd4 C 7 swd8 C 11. (3) when data that is held by a lap input is read, read the capture buffer renewal flag crnwf after r eading the swd8 C 11 and check whether the data has been renewed or not. (4) when performing a processing such as a lap input preceding with 1 hz interrupt processing, read the lap data carry-up request flag lcurf before processing and check whether carry-up is needed or not.
134 epson s1c63654 technical manual chapter 5: summary of notes programmable timer (1) when reading counter data, be sure to read the low-order 4 bits (ptdx0?tdx3) first. furthermore, the high-order 4 bits (ptdx4?tdx7) are not latched when the low-order 4 bits are read. therefore, the high-order 4 bits should be read within 0.73 msec (when f osc1 is 32.768 khz) from reading the low-order 4 bits. when the cpu is running with the osc1 clock and the programmable timer is running with the osc3 clock, stop the timer before reading the counter data. the counter running with osc3 counts down for the value listed in table 5.2.1 while the cpu running with osc1 reads the low-order 4 bits and high-order 4 bits of the counter data by two instructions. t able 5.2.1 counter change with osc3 between readings low-order and high-order data with osc1 count clock osc3/1 osc3/4 osc3/32 counter change between reading 0200h 001ah 0002h in 16-bit mode, the counter data must be read in the order below. ptd00?td03 ptd04?dt07 ptd10?td13 ptd14?td17 (2) the programmable timer actually enters run/stop status in synchronization with the falling edge of the input clock after writing to the ptrunx register. consequently, when "0" is written to the ptrunx register, the timer enters stop status at the point where the counter is decremented (-1). the ptrunx register maintains "1" for reading until the timer actually stops. figure 5.2.1 shows the timing chart for the run/stop control. ptrunx (wr) ptdx0?tdx7 42h 41h 40h 3fh 3eh 3dh ptrunx (rd) input clock "1" (run) writing "0" (stop) writing fi g. 5.2.1 timing chart for run/stop control it is the same even in the event counter mode. therefore, be aware that the counter does not enter run/stop status if a clock is not input after setting the run/stop control register (ptrun0). (3) since the tout signal is generated asynchronously from the ptout register, a hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register. (4) when the osc3 oscillation clock is selected for the clock source, it is necessary to turn the osc3 oscillation on, prior to using the programmable timer. however the osc3 oscillation circuit requires a time at least 5 msec from turning the circuit on until the oscillation stabilizes. therefore, allow an adequate interval from turning the osc3 oscillation circuit on to starting the programmable timer. refer to section 4.4, "oscillation circuit", for the control and notes of the osc3 oscillation circuit. at initial reset, the osc3 oscillation circuit is set in the off state. (5) for the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. the programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as ? in the figure). input clock counter data (continuous mode) (reload data = 25h) 03h 02h 01h 00h 25h 24h counter data is determined by reloading. underflow (interrupt is generated) ? fi g. 5.2.2 reload timing for programmable timer to avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ? . be especially careful when using the osc1 (low- speed clock) as the clock source of the programmable timer and the cpu is operating with the osc3 (high-speed clock).
s1c63654 technical manual epson 135 chapter 5: summary of notes serial interface (1) perform data writing/reading to the data registers sd0?d7 only while the serial interface is not r unning (i.e., the synchronous clock is neither being input or output). (2) as a trigger condition, it is required that data writing or reading on data registers sd0?d7 be performed prior to writing "1" to sctrg. (the internal circuit of the serial interface is initiated through data writing/reading on data registers sd0?d7.) in addition, be sure to enable the serial interface with the esif register before setting the trigger. supply trigger only once every time the serial interface is placed in the run state. refrain from performing trigger input multiple times, as leads to malfunctioning. moreover, when the synchronous clock sclk is external clock, start to input the external clock after the trigger. (3) setting of the input/output permutation (msb first/lsb first) with the sdp register should be done before setting data to sd0?d7. (4) be aware that the maximum clock frequency for the serial interface is limited to 1 mhz when osc3 is used as the clock source of the programmable timer or in the slave mode. sound generator (1) since it generates a buzzer signal that is out of synchronization with the bze register, hazards may at times be produced when the signal goes on/off due to the setting of the bze register. (2) the one-shot output is only valid when the normal buzzer output is off (bze = "0") and will be invalid when the normal buzzer output is on (bze = "1"). r/f converter (1) depending on the initial value of the measurement counter (mc), the measurement counter or the time base counter may overflow while the cr oscillation clock is being counted. when setting the initial value, pay attention to cr oscillation frequency, its fluctuation range and the input clock frequency of the time base counter. if an overflow occurs, r/f conversion is terminated immediately. when the r/f conversion result (measurement counter value) is read, check the overflow flags (ovmc and ovtbc). the upper limit of the cr oscillation frequency is 500 khz. there is no lower- limit but make sure that the time base counter does not overflow. (2) when an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag (ovmc or ovtbc) is not reset. be sure to check and reset to "0" (writing "1") the overflow flag when the r/f converter interrupt occurs. (3) when selecting osc3 for the time base counter clock, the maximum frequency of the osc3 clock is limited to 2 mhz. (4) when setting the measurement counter, always write 5 words of data continuously in order from the lower address (ff92h ff93h ff94h ff95h ff96h). furthermore, an ld instruction should be used for writing data to the measurement counter and a read-modify-write instruction (and, or, add, sub, etc.) cannot be used. svd circuit (1) to obtain a stable detection result, the svd circuit must be on for at least 500 ?ec. so, to obtain the svd detection result, follow the programming sequence below. 1. set svdon to "1" 2. maintain for 500 ?ec minimum 3. set svdon to "0" 4. read svddt (2) the svd circuit should normally be turned off because svd operation increase current consumption.
136 epson s1c63654 technical manual chapter 5: summary of notes interrupt (1) the interrupt factor flags are set when the interrupt condition is established, even if the interrupt mask registers are set to "0". (2) after an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (i flag = "1") is set or the reti instruction is executed unless the interrupt factor flag is reset. therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. (3) after an initial reset, all the interrupts including nmi are masked until both the stack pointers sp1 and sp2 are set with the software. be sure to set the sp1 and sp2 in the initialize routine. further, when re-setting the stack pointer, the sp1 and sp2 must be set as a pair. when one of them is set, all the interrupts including nmi are masked and interrupts cannot be accepted until the other one is set.
s1c63654 technical manual epson 137 chapter 5: summary of notes 5.3 precautions on mounting oscillation characteristics change depending on conditions (board pattern, components used, etc.). in particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's r ecommended values for constants such as capacitance and resistance. disturbances of the oscillation clock due to noise may cause a malfunction. consider the following points to prevent this: (1) components which are connected to the osc1, osc2, osc3 and osc4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) as shown in the right hand figure, make a v ss pattern as large as possible at circumscription of the osc1, osc2, osc3 and osc4 terminals and the components connected to these terminals. furthermore, do not use this v ss pattern for any purpose other than the oscillation system. osc4 osc3 v ss sample v ss pattern (osc3) in order to prevent unstable operation of the oscillation circuit due to current leak between osc1/ osc3 and v dd , please keep enough distance between osc1/osc3 and v dd or other signals on the board pattern. the power-on reset signal which is input to the reset terminal changes depending on conditions (power rise time, components used, board pattern, etc.). decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. when using the built-in pull-down resistor of the reset terminal, take into consideration dispersion of the resistance for setting the constant. in order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the reset terminal in the shortest line. sudden power supply variation due to noise may cause malfunction. consider the following points to prevent this: (1) the power supply should be connected to the v dd , v ss , v dda and v ssa terminals with patterns as short and large as possible. in particular, the power supply for v dda and v ssa affect r/f conversion accuracy. (2) when connecting between the v dd and v ss terminals with a bypass capacitor, the terminals should be connected as short as possible. v dd v ss bypass capacitor connection example v dd v ss (3) components which are connected to the v d1, v d2 , v osc and v c1 C v c3 terminals, such as capacitors, should be connected in the shortest line. in particular, the v c1 C v c3 voltages affect the display quality. do not connect anything to the v c1 C v c3 terminals when the lcd driver is not used.
138 epson s1c63654 technical manual chapter 5: summary of notes the power supply terminals for the analog system should be connected as shown below even if the r/f converter is not used. v dda v dd v ssa v ss in order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. when a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. osc4 osc3 v ss large current signal line high-speed signal line prohibited pattern example vi sible radiation causes semiconductor devices to change the electrical characteristics. it may cause this ic to malfunction. when developing products which use this ic, consider the following precau- tions to prevent malfunctions caused by visible radiations. (1) design the product and implement the ic on the board so that it is shielded from visible radiation in actual use. (2) the inspection process of the product needs an environment that shields the ic from visible radiation. (3) as well as the face of the ic, shield the back and side too.
s1c63654 technical manual epson 139 chapter 6: basic external wiring diagram chapter 6b asic e xternal w iring d iagram x'tal c gx cr c gc c dc r cr c 1 ? 8 c p c res crystal oscillator trimmer capacitor ceramic oscillator gate capacitor drain capacitor resistor for osc3 cr oscillation capacitor capacitor reset terminal capacitor 32.768 khz, c i (max.) = 34 k ? 5?5 pf 4 mhz (3.0 v) 30 pf 30 pf 30 k ? (2 mhz) 0.2 f 3.3 f 0.1 f note: the above table is simply an example, and is not guaranteed to work. ca cb cc cd reset v dda v dd v d1 v d2 v osc osc1 osc2 osc3 osc4 test v ssa v ss c 1 c 2 c 3 c 4 c 5 c gx c dc c res c p 2.4v | 3.6v + x'tal cr *1 *2 r cr k00?03 k10?13 p00?03 p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) r00 r01 r02 (tout) r03 (fout) seg0 | seg31 com0 | com5 c 6 c 7 c 8 lcd panel 32 6 ? 1: ceramic oscillation ? 2: cr oscillation (external r) c gc v c1 v c2 v c3 input i/o output s1c63654 [the potential of the substrate (back of the chip) is v ss .] rfout sen0 ref0 rfin0 hud sen1 ref1 rfin1 c ad1 c ad2 r ref1 r tmp r ref2 r hud bz piezo coil
140 epson s1c63654 technical manual chapter 7: electrical characteristics chapter 7e lectrical c haracteristics 7.1 absolute maximum rating item supply voltage input voltage (1) input voltage (2) permissible total output current ? 1 operating temperature storage temperature soldering temperature / time permissible dissipation ? 2 ? 1 ? 2 ( v ss =0v ) symbol v dd v i v iosc i vdd topr tstg tsol p d rated value -0.5 to 4.5 -0.5 to v dd + 0.3 -0.5 to v d1 + 0.3 10 -20 to 70 -65 to 150 260 c, 10sec ( lead section ) 250 unit v v v ma c c mw the permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). in case of plastic package (qfp15-100pin). 7.2 recommended operating conditions item supply voltage oscillation frequency ( ta=-20 to 70 c ) symbol v dd f osc1 f osc3 unit v v v khz khz khz khz khz max. 3.6 3.6 3.6 1,430 2,000 2,000 4,000 typ. 3.0 3.0 3.0 32.768 1,100 min. 1.8 2.4 2.4 770 200 condition v ss =0v normal mode, osc3 off normal mode, osc3=4mhz (max.) halver mode, osc3 off crystal oscillation cr oscillation (built-in r), v dd =2.4 to 3.6v cr oscillation (external r), v dd =2.4 to 3.6v ceramic oscillation, v dd =2.4 to 3.6v when the r/f converter uses the osc3 clock ceramic oscillation, v dd =2.4 to 3.6v when the r/f converter does not use the osc3 clock 7.3 dc characteristics item high level input voltage ( 1 ) high level input voltage ( 2 ) low level input voltage ( 1 ) low level input voltage ( 2 ) high level input current (1) high level input current (2) low level input current ( 1 ) low level input current ( 2 ) high level output current ( 1 ) high level output current ( 2 ) low level output current ( 1 ) low level output current ( 2 ) common output current segment output current (during lcd output) segment output current (during dc output) r/f converter transistor on resistance unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 ? d2 /v c1 ? c3 are internal voltage, c 1 ? 8 =0.2 f symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 r rfintr r reftr r sen0tr r sen1tr unit v v v v a a a a ma ma ma ma a a a a a a ? ? ? max. v dd v dd 0.2? dd 0.1? dd 0.5 20 0 0 -0.5 -0.5 -10 -10 -300 40 100 100 typ. 12 20 50 min. 0.8? dd 0.9? dd 0 0 0 8 -0.5 -0.5 0.5 0.5 10 10 300 condition k00?3, k10?3, p00?3, p10?3 reset, test k00?3, k10?3, p00?3, p10?3 reset, test v ih1 =3.0v k00?3, k10?3, no pull down p00?3, p10?3, reset, test v ih2 =3.0v k00?3, k10?3, with pull down p00?3, p10?3, reset, test v il1 =v ss k00?3, k10?3, no pull down p00?3, p10?3, reset, test v il2 =v ss k00?3, k10?3, with pull down p00?3, p10?3, reset, test v oh1 =0.9? dd r00?3, p00?3, p10?3 v oh2 =0.9? dd bz v ol1 =0.1? dd r00?3, p00?3, p10?3 v ol2 =0.1? dd bz v oh3 =v c3 -0.05v com0? v ol3 =v ss +0.05v v oh4 =v c3 -0.05v seg0?1 v ol4 =v ss +0.05v v oh5 =0.9? dd seg0?1 v ol5 =0.1? dd v ds =0.1v , v dd =1.8v v ds =0.1v , v dd =1.8v v ds =0.1v , v dd =1.8v
s1c63654 technical manual epson 141 chapter 7: electrical characteristics 7.4 analog circuit characteristics and power current consumption item lcd drive voltage symbol v c1 v c2 v c3 unit v v v max. typ. +100mv 2? c1 3? c1 typ. 0.95 0.98 1.01 1.04 1.07 1.10 1.13 1.16 1.19 1.22 1.25 1.28 1.31 1.34 1.37 1.40 min. typ. -100mv 2? c1 0.9 3? c1 0.9 condition connect 1 m ? load resistor lc0?="0" between v ss and v c1 lc0?="1" (without panel load) lc0?="2" lc0?="3" lc0?="4" lc0?="5" lc0?="6" lc0?="7" lc0?="8" lc0?="9" lc0?="10" lc0?="11" lc0?="12" lc0?="13" lc0?="14" lc0?="15" connect 1 m ? load resistor between v ss and v c2 (without panel load) connect 1 m ? load resistor between v ss and v c3 (without panel load) unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 ? d2 /v c1 ? c3 are internal voltage, c 1 ? 8 =0.2 f svd voltage svd circuit response time current consumption ? 1 ? 2 ? 3 ? 4 ? 5 v svd t svd i op v s a a a a a a a a a a a typ. +100mv 500 1.80 0.90 2.8 1.4 5.0 3.5 800 1000 600 10 150 1.85 2.00 2.15 2.30 2.45 2.60 2.75 2.90 0.90 0.45 1.4 0.65 4.0 2.5 400 800 350 5 100 typ. -100mv no panel load. when svd circuit and r/f converter are in off status. vdc0=vdc1="0", oscc="0" vdc2=vdc3="0" vdc2=vdc3="1" vdc0=vdc1="1", oscc="1", vdc2=vdc3="0" svds0?="0" svds0?="1" svds0?="2" svds0?="3" svds0?="4" svds0?="5" svds0?="6" svds0?="7" during halt (32khz crystal) during execution (32khz crystal) during execution (2mhz ceramic) during execution (4mhz ceramic) during execution (1.1mhz cr) svd circuit current (during voltage detection) v dd =1.8 to 3.6v r/f converter circuit current operating frequency=10khz, v dd =1.8 to 3.6v lcd off (normal) ? 1, ? 2, ? 3 lcd off (halver) ? 1, ? 2, ? 4 lcd on (normal) ? 1, ? 2, ? 3 lcd on (normal) ? 1, ? 2, ? 4 lcd on (normal) ? 1, ? 2, ? 3 lcd on (halver) ? 1, ? 2, ? 4 lcd on (normal) ? 1, ? 5 lcd on (normal) ? 1, ? 5 lcd on (normal) ? 1, ? 5
142 epson s1c63654 technical manual chapter 7: electrical characteristics 7.5 oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the following characteristics as reference values. osc1 crystal oscillation circuit item oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak unit v v pf ppm ppm ppm v m ? max. 5 10 typ. 14 20 min. 1.8 1.8 -10 10 3.6 200 condition t sta 3sec ( v dd ) t stp 10sec ( v dd ) including the parasitic capacitance inside the ic (in chip) v dd =1.8 to 3.6v c g =5 to 25pf c g =5pf ( v dd ) between osc1 and v ss unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, c d =built-in, ta=-20 to 70 c osc3 ceramic oscillation circuit item oscillation start voltage oscillation start time oscillation stop voltage symbol vsta t sta vstp unit v ms v max. 5 typ. min. 2.4 2.4 condition (v dd ) v dd =2.4 to 3.6v (v dd ) unless otherwise specified: v dd =3.0v, v ss =0v, ceramic oscillator: 4mhz, c gc =c dc =30pf, ta=-20 to 70 c osc3 cr oscillation circuit (built-in r type) item oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc3 vsta t sta vstp unit % v ms v max. 30 3 typ. 1,100khz min. -30 2.4 2.4 condition (v dd ) v dd =2.4 to 3.6v (v dd ) unless otherwise specified: v dd =3.0v, v ss =0v, r cr =built in, ta=-20 to 70 c osc3 cr oscillation circuit (external r type) item oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc3 vsta t sta vstp unit % v ms v max. 30 3 typ. min. -30 2.4 2.4 condition (v dd ) v dd =2.4 to 3.6v (v dd ) unless otherwise specified: v dd =3.0v, v ss =0v, r cr =30k ? (2mhz), ta=-20 to 70 c
s1c63654 technical manual epson 143 chapter 7: electrical characteristics osc3 cr oscillation frequency-resistance characteristic (external r type) the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the following characteristics as reference values and evaluate the characteristics on the actual product. resistor value for cr oscillation r cr [k ? ] cr oscillation frequency f osc3 [khz] 0 20 40 60 80 100 120 10000 1000 100 v dd = 2.4?.6 v ta = 25 c typ. value
144 epson s1c63654 technical manual chapter 7: electrical characteristics 7.6 serial interface ac characteristics clock synchronous master mode ?during 32 khz operation item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh unit s s s max. 5 typ. min. 10 5 condition: v dd =3.0v, v ss =0v, ta=-20 to 70 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ?during 4 mhz operation item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh unit ns ns ns max. 200 typ. min. 400 200 note that the maximum clock frequency is limited to 1 mhz. condition: v dd =3.0v, v ss =0v, ta=-20 to 70 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd clock synchronous slave mode ?during 32 khz operation item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh unit s s s max. 10 typ. min. 10 5 condition: v dd =3.0v, v ss =0v, ta=-20 to 70 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ?during 4 mhz operation item transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh unit ns ns ns max. 500 typ. min. 400 200 note that the maximum clock frequency is limited to 1 mhz. condition: v dd =3.0v, v ss =0v, ta=-20 to 70 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd sclk out sout sin v oh v ol t sms t smh t smd v oh v ih1 v il1 v ol sclk in sout sin v ih1 v oh v ol t sss t ssh t ssd v ih1 v il1 v il1
s1c63654 technical manual epson 145 chapter 7: electrical characteristics 7.7 timing chart system clock switching vdc1 vdc0 oscc clkchg ? ? ? 2.5 msec min. 5 msec min. ? ? 1 instruction execution time or longer
146 epson s1c63654 technical manual chapter 7: electrical characteristics 7.8 r/f converter characteristics r/f converter oscillation frequency - capacitance characteristic capacitance [pf] (external rfin) oscillation frequency [hz] 470 1,000 2,200 4,700 1,000,000 100,000 10,000 1,000 100 10 1 ta = -20 ~ 70 c, r = 50 k ? , v dd = 3.3 v typ. +20% -20% r/f converter oscillation frequency - resistance characteristic resistance [k ? ] (external sen0, sen1 or ref) oscillation frequency [hz] 110 100 1,000 1,000,000 100,000 10,000 1,000 100 10 1 ta = -20 ~ 70 c, c = 1000 pf, v dd = 3.3 v typ. +20% -20%
s1c63654 technical manual epson 147 chapter 8: package chapter 8p a ckage 8.1 plastic package qfp15-100pin (unit: mm) the dimensions are subject to change without notice. 14 0.1 16 0.4 51 75 14 0.1 16 0.4 26 50 index 0.18 25 1 100 76 1.4 0.1 0.1 1.7 max 1 0.5 0.2 0 10 0.125 0.5 +0.1 ?.05 +0.05 ?.025
148 epson s1c63654 technical manual chapter 8: package 8.2 ceramic package for test samples qfp15-100pin (unit: mm) 13.97 0.15 12.00typ. 17.00 0.30 0.50 0.20 1 25 26 50 75 51 100 76 glass ceramic 0.50typ. 0.82 0.30 2.54max. 0.76 0.13 0.95 0.08 0.38 0.08
s1c63654 technical manual epson 149 chapter 9: pad layout chapter 9p ad l ay out 9.1 diagram of pad layout chip thickness: 400 m pad opening: 90 90 m x y (0, 0) 4.00 mm 2.86 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 die no. 75 80 85 89
150 epson s1c63654 technical manual chapter 9: pad layout 9.2 pad coordinates no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 pad name com0 com1 com2 ca cb v c1 v c2 v c3 v ssa rfout rfin0 rfin1 ref0 sen0 ref1 sen1 hud v dda cc cd v d2 v dd v osc osc1 osc2 v d1 osc3 osc4 v ss test reset seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 x 1.662 1.552 1.442 1.332 1.222 1.112 1.002 0.891 0.781 0.668 0.556 0.442 0.332 0.222 0.112 -0.001 -0.150 -0.314 -0.424 -0.534 -0.644 -0.756 -0.868 -0.978 -1.088 -1.201 -1.311 -1.421 -1.531 -1.641 -1.751 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 -1.866 y 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 1.298 0.876 0.756 0.636 0.516 0.396 0.276 0.156 0.036 -0.084 -0.204 -0.324 -0.444 -0.569 -0.694 no. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 pad name seg30 seg31 com3 com4 com5 v dd k00 k01 k02 k03 k10 k11 k12 k13 p00 p01 p02 p03 p10 p11 p12 p13 r00 r01 r02 r03 bz v ss seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 x -1.866 -1.866 -1.517 -1.406 -1.296 -1.186 -1.076 -0.966 -0.856 -0.745 -0.635 -0.525 -0.415 -0.304 -0.194 -0.084 0.026 0.137 0.247 0.357 0.467 0.578 0.688 0.798 0.908 1.019 1.129 1.239 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 1.866 y -0.819 -0.944 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -1.298 -0.968 -0.848 -0.728 -0.608 -0.488 -0.368 -0.248 -0.128 -0.008 0.112 0.232 0.352 0.472 0.592 0.712 0.832 unit: mm
s1c63654 technical manual epson 151 appendix peripheral circuit boards for s1c63654 appendix p eripheral c ircuit b o ards for s1c63654 this section describes how to use the peripheral circuit boards for the s1c63654 (s5u1c63000p1 and s5u1c63658p2), which provide emulation functions when mounted on the debugging tool for the s1c63 family of 4-bit single-chip microcomputers, the ice (s5u1c63000h1/s5u1c63000h2). this description of the s1c63 family peripheral circuit board (s5u1c63000p1) provided in this docu- ment assumes that circuit data for the s1c63654 has already been downloaded to the board. for informa- tion on downloading a circuit data and the board specifications, please see sections a.3 and a.5, respec- tively. please refer to the user? manual provided with your ice for detailed information on its functions and method of use. a.1 names and functions of each part a.1.1 s5u1c63000p1 the following explains the names and functions of each part of the s5u1c63000p1 board. vsvd fpga prog prg norm 1 1 2 15 led vc5 vlcd p r c 6 3 0 0 0 ver. x.x vc5 clk cn0 gnd gnd fosc3(cr) fosc1(cr) adosca sn0 st1 st0 lclk 32k eprom config sel flash cpa1 e iosel2 osc1(cr)adj osc3(cr)adj d cn3 connector (not used) cn2 connector cn1 connector 16 16 reset (3) (4) (9) (1) (2) (11) (10) (9) (8) (7) (6) (5) (1) vlcd when external lcd power supply has been selected by mask option, you can turn this control to adjust the lcd drive power supply voltage. (2) vsvd this control allows you to vary the power supply voltage artificially in order to verify the operation of the power supply voltage detect function (svd). (3) register monitor leds these leds correspond one-to-one to the registers listed below. the led lights when the data is logic "1" and goes out when the data is logic "0". vdc0?dc3, oscc, clkchg, lpwr, svds0?vds2, svdon
152 epson s1c63654 technical manual appendix peripheral circuit boards for s1c63654 (4) register monitor pins these pins correspond one-to-one to the registers listed below. the pin outputs a high for logic "1" and a low for logic "0". pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 monitor ? done: the monitor pin outputs a high while the led lights when initialization of this board completes without problems. name done * vdc0 vdc1 vdc2 vdc3 oscc clkchg lpwr svds0 svds1 svds2 svdon led no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 led name done * vdc0 vdc1 vdc2 vdc3 oscc clkchg lpwr svds0 svds1 svds2 svdon monitor pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 led (5) cr oscillation frequency adjusting control this control allows you to adjust the osc3 oscillation frequency. this function is effective when ceramic oscillation is selected for the osc3 oscillation circuit by mask option as well as when cr oscillation is selected. the oscillation frequency can be adjusted in the range of approx. 100 khz to 8 mhz. note that the actual ic does not operate with all of these frequencies; refer to chapter 7, "electrical characteristics", to select the appropriate operating frequency. not used not used osc3 rough adjustment osc3 fine adjustment (6) cr oscillation frequency monitor pins these pins allow you to monitor the clock waveform from the cr oscillation circuit with an oscillo- scope. note that these pins always output a signal waveform whether or not the oscillation circuit is operating. osc3 monitor pin (red) not used gnd pin (black) reset
s1c63654 technical manual epson 153 appendix peripheral circuit boards for s1c63654 (7) reset switch this switch initializes the internal circuits of this board and feeds a reset signal to the ice. (8) external part connecting socket unused (9) clk and prg switch if power to the ice is shut down before circuit data downloading is complete, the circuit configura- tion in this board will remain incomplete, and the debugger may not be able to start when you power on the ice once again. in this case, temporarily power off the ice and set clk to the 32k position and the prg switch to the prog position, then switch on power for the ice once again. this should allow the debugger to start up, allowing you to download circuit data. after downloading the circuit data, temporarily power off the ice and reset clk and prg to the lclk and the norm position, respec- tively. then power on the ice once again. (10) iosel2 when downloading circuit data, set iosel2 to the "e" position. otherwise, set to the "d" position. (11) vc5 when the internal lcd power supply has been selected by mask option, you can turn this control to fine-adjust the lcd drive power supply voltage. note, however, that the lcd drive power supply voltage in the actual ic is set according to the contents of the lcd contrast adjustment register.
154 epson s1c63654 technical manual appendix peripheral circuit boards for s1c63654 a.1.2 s5u1c63658p2 the following explains the names and functions of each part of the s5u1c63658p2 board. s1c63658 sen1 hud ref1 rfin1 gnd channel 1 rfout sen0 ref0 rfin0 gnd channel 0 (1) (2) (1) r/f converter monitor pins and external part connecting socket (channel 0) these monitor pins are used to check the operation of r/f converter channel 0. the socket is used to connect external resistors and a capacitor for r/f conversion. mount resistors and a capacitor on the platform attached with the s5u1c63658p2 and then connect it to the onboard socket. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 connecting a dc-bias resistive sensor (e.g. thermistor) rfout sen0 ref0 rfin0 gnd channel 0 capacitor reference resistance sensor (resistor) (2) r/f converter monitor pins and external part connecting socket (channel 1) these monitor pins are used to check the operation of r/f converter channel 1. the socket is used to connect external resistors and a capacitor for r/f conversion. mount resistors and a capacitor on the platform attached with the s5u1c63658p2 and then connect it to the onboard socket. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 capacitor reference resistance sensor (resistor) connecting a ac-bias resistive humidity sensor the sensor connect position changes according to the sensor type to be used. do not mount an ac bias sensor and a dc bias sensor at the same time as it causes a malfunction. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 capacitor reference resistance sensor (resistor) connecting a dc-bias resistive sensor (e.g. thermistor) sen1 hud ref1 rfin1 gnd channel 1
s1c63654 technical manual epson 155 appendix peripheral circuit boards for s1c63654 a.2 connecting to the target system this section explains how to connect the s5u1c63000p1 to the target system. first insert the s5u1c63658p2 board into the top slot of the ice and the s5u1c63000p1 board into the second upper slot. s5u1c63658p2 s5u1c63000p1 fi g. a.2.1 installing the peripheral circuit boards to the ice installing the s5u1c63000p1/63658p2 board set the jig included with the ice into position as shown in figure a.2.2. using this jig as a lever, push it toward the inside of the board evenly on the left and right sides. after confirming that the board has been firmly fitted into the internal slot of the ice, remove the jig. fi g. a.2.2 installing the board dismounting the s5u1c63000p1/63658p2 board set the jig included with the ice into position as shown in figure a.2.3. using this jig as a lever, push it toward the outside of the board evenly on the left and right sides. after confirming that the board has been dismounted from the backboard connector, pull the board out of the ice. fi g. a.2.3 dismounting the board board board
156 epson s1c63654 technical manual appendix peripheral circuit boards for s1c63654 to connect this board (s5u1c63000p1) to the target system, use the i/o connecting cables supplied with the board (80-pin/40-pin 2, 100-pin/50-pin 2, flat type). take care when handling the connectors, since they conduct electrical power (v dd = +3.3 v). cn1-1 (40-pin) cn1-2 (40-pin) i/o connection cable to target board mark cn2-1 (50-pin) cn2-2 (50-pin) fi g. a.2.4 connecting the s5u1c63000p1 to the target system
s1c63654 technical manual epson 157 appendix peripheral circuit boards for s1c63654 t able a.2.1 i/o connector pin assignment no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40-pin cn1-1 connector pin name v dd (= 3.3 v) v dd (= 3.3 v) k00 k01 k02 k03 k10 k11 k12 k13 v ss v ss p00 p01 p02 p03 p10 p11 p12 p13 v dd (= 3.3 v) v dd (= 3.3 v) cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected vss vss cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected vss vss no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40-pin cn1-2 connector pin name v dd (= 3.3 v) v dd (= 3.3 v) r00 r01 r02 r03 cannot be connected cannot be connected cannot be connected cannot be connected v ss v ss bz cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected v dd (= 3.3 v) v dd (= 3.3 v) cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected v ss v ss cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected reset v ss v ss no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 50-pin cn2-1 connector pin name v dd (= 3.3 v) v dd (= 3.3 v) seg0 (dc) seg1 (dc) seg2 (dc) seg3 (dc) seg4 (dc) seg5 (dc) seg6 (dc) seg7 (dc) v ss v ss seg8 (dc) seg9 (dc) seg10 (dc) seg11 (dc) seg12 (dc) seg13 (dc) seg14 (dc) seg15 (dc) v dd (= 3.3 v) v dd (= 3.3 v) seg16 (dc) seg17 (dc) seg18 (dc) seg19 (dc) seg20 (dc) seg21 (dc) seg22 (dc) seg23 (dc) v ss v ss seg24 (dc) seg25 (dc) seg26 (dc) seg27 (dc) seg28 (dc) seg29 (dc) seg30 (dc) seg31 (dc) v dd (= 3.3 v) v dd (= 3.3 v) cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 50-pin cn2-2 connector pin name v dd (= 3.3 v) v dd (= 3.3 v) cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected v ss v ss cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected v dd (= 3.3 v) v dd (= 3.3 v) cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected v ss v ss cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected v dd (= 3.3 v) v dd (= 3.3 v) cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected cannot be connected ? connectors cn2-1 and cn2-2 are used when the seg pins are set for dc output by mask option.
158 epson s1c63654 technical manual appendix peripheral circuit boards for s1c63654 a.3 downloading to s5u1c63000p1 a.3.1 downloading circuit data 1 ?when new ice (s5u1c63000h2) is used the s5u1c63000p1 board comes with the fpga that contains factory inspection data, therefore the circuit data for the model to be used should be downloaded. the following explains the downloading proce- dure. 1) remove the ice top cover and then set the dip switch "iosel2" on this board to the "e" position. 2) connect the ice to the host pc. then turn the host pc and ice on. 3) invoke the debugger included in the assembler package (ver. 5 or later). for how to use the ice and debugger, refer to the manuals supplied with the ice and assembler package. 4) download the circuit data file (.mot) corresponding to the model by entering the following commands in the command window. >xfer (erase all) >xfwr (download the specified file) * >xfcp (compare the specified file and downloaded data) ? the downloading takes about 15 minutes. 5) terminate the debugger and then turn the ice off. 6) set the dip switch "iosel2" on this board to the "d" position. 7) turn the ice on and invoke the debugger again. debugging can be started here. a.3.2 downloading circuit data 2 ?when previous ice (s5u1c63000h1) is used the standard ice (s5u1c63000h1, previous model) did not support the circuit data download function for this board. to use the download function, update the ice firmware according to the following procedure. 1) set the baud rate of the ice to 9600 bps. refer to the manual supplied with the ice for setting the dip switch. 2) connect the ice to the host pc and then start up the host pc in dos. when windows is running, re start in dos mode. note: do not use the dos prompt of windows. 3) turn the ice on. 4) configure the rs232c parameters for the host pc as follows: c:\>mode com1:9600,n,8,1,p (9600 bps, 8-bit data, 1 stop bit, no parity) 5) copy the following files included in the assembler package (ver. 5 or later) to a directory on the hard disk. tm63.exe, ice63.com, i63com.o, i63par 6) move to the directory in step 5, run the tm63. tm63 enters command ready status after invocation, enter a command as follows: ________ c:\>tm63 xat tm63 start on ibm pc tm63 start v01.01 ________________________________ >dlf ice63.com i63com.o i63par 0b ... _ >q 7) enter "q" to terminate tm63 after the prompt mark is displayed. 8) the ice firmware is now updated. turn the ice off and then download the circuit data by the proce- dure described in section a.3.1.
s1c63654 technical manual epson 159 appendix peripheral circuit boards for s1c63654 a.4 usage precautions to ensure correct use of the peripheral circuit board, please observe the following precautions. a.4.1 operational precautions (1) before inserting or removing cables, turn off power to all pieces of connected equipment. (2) do not turn on power or load mask option data if all of the input ports (k00?03) are held low. doing so may activate the multiple key entry reset function. (3) before debugging, always be sure to load mask option data. a.4.2 differences with the actual ic (1) differences in i/o s5u1c63000p1 and target system interface voltage is set to +3.3 v. to obtain the same interface voltage as in the actual ic, attach a level shifter circuit, etc. on the target system side to accommodate the required interface voltage.