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33110hkim 20100312-s00006 no.a1659-1/38 ver.1.03 LC88F52H0A overview the sanyo LC88F52H0A is a 16-bit microcomputer that, centered around an xstromy16 cpu, integrates on a single chip a number of hardware features such as 512k-byte flash rom (onboard programmable), 24k-byte ram, eight 16- bit timers, a base timer serving as a time-of-day clock,, a re al time clock, two synchronous sio interfaces with automatic transmission capability, two single master i 2 c/synchronous sio interface, a slave i 2 c/synchronous sio interface, four asynchronous sio (uart) interfaces, a 16-channel 12-bit resolution ad converter, 8bit resolution da converter, four multifrequency 12-bit pwm modules, a watchdog timer, a system clock frequency divider, a 59-source (32 modules) 14-vector interrupt feature, and on-chip debugger feature. features ? xstromy16 cpu ? 4g-byte address space ? general-purpose registers: 16 bits 16registers ? flash rom ? capable of onboard programming with a wide range of voltage levels (3.0 to 5.5v). ? block-erasable in 512 or 1k byte units. ? data written in 2-byte units. ? 524288 8 bits ? ram ? 24576 8 bits ordering number : ena1659 cmos lsi from 512k byte, ram 24k byte on-chip 16-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC88F52H0A no.a1228-2/38 ? minimum instruction cycle time (tcyc) ? 83.3 ns (12mhz) v dd = 4.5 to 5.5v ? 107 ns (9.3mhz) v dd = 3.0 to 5.5v ? 500 ns (2mhz) v dd = 2.5 to 5.5v ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units : 86 (p0n p1n, p2n, p3n, p4n, p5n, p6n, p7n, pan pb0 to pb6, pc2, pd0 to pd5) ? oscillation/normal withstand voltage i/o ports : 4 (pc0, pc1, pc3, pc4) ? reset pins : 1 (resb) ? test pins : 1 (test) ? power pins : 8 (v ss 1 to 4, v dd 1 to 4) ? timers ? timer 0: 16-bit timer that supports pwm/toggle outputs 1) 5-bit prescaler 2) 8-bit pwm 2, 8-bit timer + 8-bit pwm mode selectable 3) clock source selectable from system clock, osc0, osc1, and internal rc oscillator ? timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) may be divided into 2 channels of 8-bit timer 3) clock source selectable from system clock, osc0, osc1, and internal rc oscillator ? timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) may be divided into 2 channels of 8-bit timer 3) clock source selectable from system clock, osc0, osc1, and external events ? timer 3: 16-bit timer that supports pwm/toggle outputs 1) 8-bit prescaler 2) 8-bit timer 2ch or 8-bit timer + 8-bit pwm mode selectable 3) clock source selectable from system clock, osc0, osc1, and external events ? timer 4: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 0 ? timer 5: 16-bit timer that supports toggle outputs 1) clock source selectable from system clock and prescaler 0 ? timer 6: 16-bit timer that supports toggle outputs 1) clock source selectable fr om system clock and prescaler 1 ? timer 7: 16-bit timer that supports toggle outputs 1) clock source selectable fr om system clock and prescaler 1 * prescaler 0 and 1 are consisted of 4 bits and ca n choose their clock source from osc0 or osc1. ? base timer 1) clock may be selected from osc0 (32.768khz crystal os cillator) and frequency-divided output of system clock. 2) interrupts can be generated in 7 timing schemes. ? real time clock 1) calender with jan. 1, 2000 to dec.31, 2799 including automatic leap year calculation function. 2) consisted of independent second- minute-hour-day-month-year-century counters. 3) programmable count-clock calibration function.
LC88F52H0A no.a1228-3/38 ? serial interfaces ? sio0: 8-bit synchronous sio 1) lsb first/msb first mode selectable 2) supports data communication with a data lengt h of 8 bits or less (1 to 8 bits specifiable) 3) built-in 8-bit baudrate generator (4 tcyc to 512 tcyc transfer clocks) 4) continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) interval function (intervals specifiable in 0 to 64 tsck units) 6) wakeup function ? sio1: 8-bit synchronous sio 1) lsb first/msb first mode selectable 2) supports data communication with a data lengt h of 8 bits or less (1 to 8 bits specifiable) 3) built-in 8-bit baudrate generator (4 tcyc to 512 tcyc transfer clocks) 4) continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) interval function (intervals specifiable in 0 to 64 tsck units) 6) wakeup function ? smiic0: single master i 2 c/8-bit synchronous sio mode 0: single-master mode communication mode 1: synchronous 8-bit serial i/o (msb first) ? smiic1: single master i 2 c/8-bit synchronous sio mode 0: single-master mode communication mode 1: synchronous 8-bit serial i/o (msb first) ? sliic0: slave i 2 c/8-bit synchronous sio mode 0: i 2 c slave mode communication mode 1: synchronous 8-bit serial i/o (msb first) note: usable only with the external clock source ? uart0 1) data length : 8 bits (lsb first) 2) start bits : 1 bit 3) stop bits : 1 bit 4) parity bits : none/even parity/odd parity 5) transfer rate : 4/8 cycle 6) baudrate source clock : p07 input signal used as a 1 cycle signal (t0pwmh can be used as a clock source) or timer 4 cycle. 7) full duplex communication note: the ?cycle? refers to one period of the baudrate clock source. ? uart2 1) data length : 8 bits (lsb first) 2) start bits : 1 bit 3) stop bits : 1/2 bit 4) parity bits : none/even parity/odd parity 5) transfer rate : 8 to 4096 cycle 6) baudrate source clock : system clock/osc0/osc1/p26 input signal 7) wakeup function 8) full duplex communication note: the ?cycle? refers to one period of the baudrate clock source. ? uart3 1) data length : 8 bits (lsb first) 2) start bits : 1 bit 3) stop bits : 1/2 bit 4) parity bits : none/even parity/odd parity 5) transfer rate : 8 to 4096 cycle 6) baudrate source clock: system clock/osc0/osc1/p36 input signal 7) wakeup function 8) full duplex communication note: the ?cycle? refers to one period of the baudrate clock source.
LC88F52H0A no.a1228-4/38 ? uart4 1) data length : 8 bits (lsb first) 2) start bits : 1 bit 3) stop bits : 1/2 bit 4) parity bits : none/even parity/odd parity 5) transfer rate : 8 to 4096 cycle 6) baudrate source clock: system clock/osc0/osc1/p37 input signal 7) wakeup function 8) full duplex communication note: the ?cycle? refers to one period of the baudrate clock source. ? ad converter 1) 12/8 bits resolution selectable 2) analog input: 16 channels 3) comparator mode 4) automatic reference voltage generation ? da converter 1) 8 bits resolution 2) 2 converters built-in 3) able to choose output pins ? pwm ? pwm0: multifrequency 12-bit pwm 2 channels (pwm00 and pwm01) 1) 2-channel pairs controlled independently of one another 2) clock source selectable from system clock or osc1 3) 8-bit prescaler: tpwmr0 =(prescaler value + 1) clock period 4) 8-bit fundamental wave pwm generator circuit + 4-bit additional pulse generator circuit 5) fundamental wave pwm mode fundamental wave period: 16 tpwmr0 to 256 tpwmr0 high pulse width : 0 to (fundamental wave period - tpwmr0) 6) fundamental wave + additional pulse mode fundamental wave period: 16 tpwmr0 to 256 tpwmr0 overall period : fundamental wave period 16 high pulse width : 0 to (fundamental wave period - tpwmr0) ? pwm1: multifrequency 12-bit pwm 2 channels (pwm10 and pwm11) 1) 2-channel pairs controlled independently of one another 2) clock source selectable from system clock or osc1 3) 8-bit prescaler: tpwmr1 =(prescaler value + 1) clock period 4) 8-bit fundamental wave pwm generator circuit + 4-bit additional pulse generator circuit 5) fundamental wave pwm mode fundamental wave period: 16 tpwmr1 to 256 tpwmr1 high pulse width : 0 to (fundamental wave period - tpwmr1) 6) fundamental wave + additional pulse mode fundamental wave period: 16 tpwmr1 to 256 tpwmr1 overall period : fundamental wave period 16 high pulse width : 0 to(fundamental wave period - tpwmr1) ? watchdog timer 1) driven by the base timer + internal watchdog timer dedicated counter 2) interrupt or reset mode selectable
LC88F52H0A no.a1228-5/38 ? interrupts (peripheral function) ? 59 sources (32 modules), 14 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt contro l. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address interrupt source 1 08000h watchdog timer (1) 2 08004h base timer (2) 3 08008h timer 0 (2) 4 0800ch int0 (1) 5 08014h int1 (1) 6 08018h int2 (1)/timer 1 (2)/uart2 (4) 7 0801ch int3 (1)/timer 2 (4)/smiic0 (1)/sliic1 (1) 8 08020h int4 (1)/timer 3 (2) 9 08024h int5 (1)/timer 4 (1)/sio1 (2) 10 0802ch pwm0 (1)/smiic1(1) 11 08030h adc (1)/timer 5 (1) 12 08034h int6 (1)/timer 6 (1)/uart 3 (4) 13 08038h int7 (1)/sio0 (2)/sio0(2)/usrt4 (4) 14 0803ch port 0 (3)/port 5 (8)/rtc (1) ? 3 priority levels selectable. ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? a number enclosed in parentheses denotes the number of sources. ? subroutine stack: 24 k-byte ram area ? subroutine calls that automatically save psw, interrupt vector calls: 6 bytes ? subroutine calls that do not automatically save psw: 4 bytes ? multiplication/division instructions ? 16 bits 16 bits (18 tcyc execution time) ? 16 bits 16 bits (18 to 19 tcyc execution time) ? 32 bits 16 bits (18 to 19 tcyc execution time) ? oscillator circuits ? rc oscillator circuit (internal): for system clock ? cf oscillator circuit (built-in rf circuit): for system clock (osc1) ? vco oscillator circuit: for system clock (osc1) ? crystal oscillator circuit (built-in rf ci rcuit): for low-speed system clock (osc0) ? slrc oscillator circuit (internal): for system clock (in the case of exception processing) ? system clock divider function ? can run on low current. ? 1/1 to 1/128 of the system clock frequency can be set.
LC88F52H0A no.a1228-6/38 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) released by a system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) osc1, rc and osc0 oscillators automatically stop. 2) there are the six ways of releasing the hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2, int4 , int5, int6, and int7 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established at port 5 (5) having an interrupt established at sio0 or sio1 (6) having an interrupt established at uart2, uart3 or uart4 ? holdx mode: suspends instruction execu tion and the operation of the peripheral circuits except those which run on osc0. 1) osc1 and rc oscillations automatically stop. 2) osc0 maintains the state that is established when the holdx mode is entered. 3) there are seven ways of releasing the holdx mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2, int4 , int5, int6, and int7 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established at port 5 (5) having an interrupt source established at the base timer circuit (6) having an interrupt established at sio0 or sio1 (7) having an interrupt established at uart2, uart3 or uatr4 . ? on-chip debugger function ? supports software debugging with the ic mounted on the target board. ? supports source line debugging and tracing functions, and breakpoint setting and real time display. ? single-wire communication ? package form ? tqfp100(14 14): lead-free and halogen-free type ? development tools ? on-chip debugger: eocuif1 + LC88F52H0A ? programming board package programming board tqfp100 (14 14) w88f52tq ? flash programming manufacturer model name supported version device flash support group (single) af9708/09/09b/09c revision: after rev.03.32d 88f512sn af9723/23b flash support group (gang) af9833 sanyo skk/skk type-b application version after 1.06 chip data version after 2.22 LC88F52H0A
LC88F52H0A no.a1228-7/38 package dimensions unit : mm (typ) 3274 sanyo : tqfp100(14x14) 100 125 26 50 51 75 76 14.0 (1.0) (1.0) 0.1 0.125 16.0 0.2 0.5 1.2max 0.5 14.0 16.0
LC88F52H0A no.a1228-8/38 pin assignment sanyo: tqfp100 (1414) (lead-free and halogen-free type) pb5/sm1da pb4/sm1ck pb3/u4tx pb2/u4rx pb1/pwm11 pb0/pwm10 p37/t7o p36/t6o p35/u3tx p34/u3rx p33/int3 p32/int2 p31/int1 p30/int0 p07/t0pwmh/u0brg p06/t0pwml p05/p05int p04/p04int p03/p0int p02/p0int p01/p0int p00/p0int v ss 3 v dd 3 p40/int6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p55/p5int5 p56/p5int6 p57/p5int7 test resb pc0/xt1 pc1/xt2 v ss 1 pc3/cf1 pc4/vcot/cf2 v dd 1 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/u0tx p14/t3ol/u0rx p15/t3oh 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p41/int7 p42 p43/so1 p44/si1/sb1 p45/sck1 p46/pwm00 p47/pwm01 p27 p26/t5o p25/t4o p24/sm0do p23/sm0da p22/sm0ck v dd 2 v ss 2 p21/int5 p20/int4 pd5/da22 pd4/da21 pd3/da20 pd2/da02 pd1/da01 pd0/da00 p17/u2tx p16/u2rx 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pb6/sm1do p70/an8 p71/an9 p72/an10 p73/an11 p74/an12 p75/an13 p76/an14 p77/an15 v ss 4 v dd 4 pa0 pa1 pa2 pa3 pa4/sl0ck pa5/sl0da pa6/sl0do pa7 pc2/filt p50/p5int0 p51/p5int1 p52/p5int2 p53/p5int3 p54/p5int4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 top view LC88F52H0A
LC88F52H0A no.a1228-9/38 system block diagram clock generator cf rc x?tal port 0 port 1 sio0 sio1 sliic0 timer 0 timer 1 timer 2 timer 3 port 2 port 3 port 4 port 5 uart0 port a timer 4 pwm0 on-chip debugger port 6 xstromy16 cpu ram flash rom base timer watchdog timer pwm1 int0 to int7 timer 5 port 7 low speed rc uart2 timer 6 timer 7 smiic0 smiic1 uart3 uart4 ad da rtc port b port c port d vco pll
LC88F52H0A no.a1228-10/38 pin description pin name i/o description v ss 1, v ss 2, v ss 3, v ss 4 - - power sources v dd 1, v dd 2, v dd 3, v dd 4 - + power sources port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? hold release input (p00 to p03, p04, p05) ? port 0 interrupt input (p00 to p03, p04, p05) ? pin functions p06: timer 0l output p07: timer 0l output/uart0 clock input port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p10: sio0 data output p11: sio0 data inpu t/pulse input/output p12: sio0 clock input/output p13: uart0 transmit p14: timer 3l output/uart0 receive p15: timer 3h output p16: uart2 receive p17: uart2 transmit port 2 p20 to p27 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p20: int4 input/hold release input/timer 3 event i nput/timer 2l capture input/timer 2h capture input p21: int5 input/hold release input/timer 3 event i nput/timer 2l capture input/timer 2h capture input p22: smiic0 clock input/output p23: smiic0 bus input/output/data input p24: smiic0 data output (used in 3-wire sio mode) p25: timer 4 output p26: timer 5 output interrupt acknowledge type int4, int5: h level, l leve l, h edge, l edge, both edges port 3 p30 to p37 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p30: int0 input/hold releas e/timer 2l capture input p31: int1 input/hold releas e/timer 2h capture input p32: int2 input/hold release/timer 2 event input/timer 2l capture input p33: int3 input/hold release/timer 2 event input/timer 2h capture input p34: uart3 receive p35: uart3 transmit p36: timer 6 output p37: timer 7 output interrupt acknowledge type int0 to int3: h level, l level, h edge, l edge, both edges continued on next page.
LC88F52H0A no.a1228-11/38 continued from preceding page . pin name i/o description port 4 p40 to p47 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p40: int6 input/hold release input p41: int7 input/hold release input p43: sio1 data output p44: sio1 data in put/bus input/output p45: sio1 clock input/output p46: pwm00 output p47: pwm01 output interrupt acknowledge type int6, int7: h level, l leve l, h edge, l edge, both edges port 6 p60 to p67 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions an0 (p60) to an7 (p67): ad converter input port port 7 p70 to p77 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions an8 (p70) to an15 (p77): ad converter input port port a pa0 to pa7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? multiplexed pin functions pa4: sliic0 clock input pa5: sliic0 bus input/output/data input pa6: sliic0 data output (used in 3-wire sio mode) port b pb0 to pb6 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? multiplexed pin functions pb0: pwm10 output pb1: pwm11 output pb2: uart4 receive pb3: uart4 transmit pb4: smiic1 clock input/output pb5: smiic1 bus input/output/data input pb6: smiic1 data output (used in 3-wire sio mode) port c pc0 to pc4 i/o ? 5-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units (pc2) ? pin functions pc0: 32.768 khz crystal oscillator input pc1: 32.768 khz crystal oscillator output pc2: filt pc3: ceramic oscillator input pc4: ceramic oscillat or output/vco output port d pd0 to pd5 i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? multiplexed pin functions pd0: da00 output pd1: da01 output pd2: da02 output pd3: da10 output pd4: da11 output pd5: da12 output test i/o ? test pin ? used to communicate with on-chip debugger. ? connects an external 100k pull-down resistor. resb i reset pin
LC88F52H0A no.a1228-12/38 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of output type pull-up resistor p00 to p07 cmos p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 pa0 to pa7 pb0 to pb6 able to program special functions? output type from cmos output or n-channel open drain p60 to p67 p70 to p77 pd0 to pd5 pc2 1 bit cmos programmable pc0 - n-channel open drain (32.768khz crystal oscillator input) none pc1 - n-channel open drain (32.768khz crystal oscillator output) none pc3 - cmos (ceramic oscillator input) none pc4 - cmos (ceramic oscillator output) none * make the following connection to minimize the noise input to the v dd 1 pin and prolong the backup time. be sure to electrically short the v ss 1, v ss 2, v ss 3 and vss4 pins. example 1: when data is being backed up in the hold mode, the h level signals to the output ports are fed by the backup capacitors. example 2: when data is being backed up in the hold mode, the h level output at any ports is not sustained and is unpredictable. lsi power supply v ss 1 for buckup v ss 2v ss 3 v dd 3 v dd 2 v dd 1 v dd 4 v ss 4 power supply for buckup v dd 3 v dd 2 v dd 1 lsi v ss 1v ss 2v ss 3 v dd 4 v ss 4
LC88F52H0A no.a1228-13/38 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3, v dd 4 v dd 1=v dd 2=v dd 3= v dd 4 -0.3 +6.5 input voltage v i (1) resb -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2 ports 3, 4, 5 ports 6, 7 ports a, b, c, d -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 p40 to p45 ports 7, a, d pb2 to pb6 cmos output selected per applicable pin -10 ioph(2) p46, p47 pb0, pb1 per applicable pin -20 peak output current ioph(3) port 5, 6 pc0 to pc4 per applicable pin -5 iomh(1) ports 0, 1, 2, 3 p40 to p45 ports 5, 6, 7, a pb2 to pb6 ports d cmos output selected per applicable pin -7.5 iomh(2) p46, p47 pb0, pb1 per applicable pin -10 average output current (note 1-1) iomh(3) port 5, 6 pc0 to pc4 per applicable pin -3 ioah(1) pprts 5 pc0 to pc4 total of currents at applicable pins -15 ioah(2) port 6 total of currents at applicable pins -15 ioah(3) port 5, 6 pc0 to pc4 total of currents at applicable pins -20 ioah(4) ports 1,d1 p20 to p21 total of currents at applicable pins -25 ioah(5) p22 to p27 total of currents at applicable pins -25 ioah(6) ports 1, 2, d total of currents at applicable pins -45 ioah(7) ports 4 total of currents at applicable pins -25 ioah(8) ports 0, 3 total of currents at applicable pins -25 ioah(9) ports 0, 3, 4 total of currents at applicable pins -45 ioah(10) ports b, 7 total of currents at applicable pins -25 ioah(11) ports a total of currents at applicable pins -25 high level output current total output current ioah(12) ports 7, a, b total of currents at applicable pins -45 ma note 1-1: average output current refers to the average of output currents measured for a period of 100ms. continued on next page. .
LC88F52H0A no.a1228-14/38 continued from preceding page. specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit iopl(1) ports 0, 1, 3, 4 ports 7, a, b p20, p21, p24 to p27 pa0 to pa4, pa6, pa7 pb0 to pb4, pb6, pb7 per applicable pin 20 iopl(2) p22, p23 pa4, pa5 pb4, pb5 per applicable pin 25 peak output current iopl(3) ports 5, 6 pc0 to pc4 per applicable pin 10 ioml(1) ports 0, 1, 3, 4 ports 7, a, b p20, p21, p24 to p27 pa0 to pa4, pa6, pa7 pb0 to pb4, pb6, pb7 per applicable pin 15 ioml(2) p22, p23 pa4, pa5 pb4, pb5 per applicable pin 20 average output current (note 1-1) ioml(3) ports 5, 6 pc0 to pc4 per applicable pin 7.5 ioal(1) ports 5 pc0 to pc2 total of currents at applicable pins 15 ioal(2) port 6 pc3 to pc4 total of currents at applicable pins 15 ioal(3) port 5, 6 pc0 to pc4 total of currents at applicable pins 20 ioal(4) ports 1, d p20, p21 total of currents at applicable pins 45 ioal(5) p22 to p27 total of currents at applicable pins 45 ioal(6) ports 1, 2, d total of currents at applicable pins 80 ioal(7) port 4 total of currents at applicable pins 45 ioal(8) port 0, 3 total of currents at applicable pins 45 ioal(9) port 0, 3, 4 total of currents at applicable pins 80 ioal(10) port 7, b total of currents at applicable pins 45 ioal(11) port a total of currents at applicable pins 45 low level output current total output current ioal(12) port 7, a, b total of currents at applicable pins 80 ma allowable power dissipation pd max tqfp100(14 14) ta=-40 to +85 c 250 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: average output current refers to the average of output currents measured for a period of 100ms.
LC88F52H0A no.a1228-15/38 allowable operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit 0.081 s tcyc 66 s 4.0 5.5 0.103 s tcyc 66 s 3.0 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.490 s tcyc 66 s 2.5 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode 2.0 5.5 v ih (1) ports 0, 1, 2, 3, 4 port 5, a, b 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 6, 7, pc2 2.5 to 5.5 0.3v dd +0.7 v dd v ih (3) resb pc0, pc1, pc3, pc4 2.5 to 5.5 0.75v dd v dd high level input voltage v ih (4) p22, p23, pa4, pa5, pb4, pb5 i 2 c side 2.5 to 5.5 0.7v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) when ports 1, 2, 3, 4, 5, a and port b, pnfsan=0 ports 0, 6, 7, pc2 2.5 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) when ports 1, 2, 3, 4, 5, a and port b, pnfsan=1 2.5 to 4.0 v ss 0.2v dd v il (5) cf1, resb pc0, pc1, pc3, pc4 2.5 to 5.5 v ss 0.25v dd low level input voltage v il (6) p22, p23, pa4, pa5, pb4, pb5 i 2 c side 2.5 to 5.5 v ss 0.3v dd v 4.5 to 5.5 0.081 66 2.8 to 5.5 0.122 66 instruction cycle time (note 2-2) tcyc 2.5 to 5.5 0.490 66 s 4.5 to 5.5 0.1 12 3.0 to 5.5 0.1 8.3 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty505% 2.5 to 5.5 0.1 2 4.5 to 5.5 0.2 24 3.0 to 5.5 0.2 18.6 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 2.5 to 5.5 0.2 4 mhz note 2-1: v dd 3.0v must be maintained when making onboard programming into flash rom. note 2-2: relationship between tcyc and oscillation frequency is 1/fmcf when frequency division ratio is 1/1 and 2/fmcf when the ratio is 1/2. continued on next page.
LC88F52H0A no.a1228-16/38 continued from preceding page specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit fmcf(1) pc3 (cf1), pc4 (cf2) 12mhz ceramic oscillator mode see fig. 1. 4.5 to 5.5 12 fmcf(2) pc3(cf1), pc4(cf2) 8mhz ceramic oscillator mode see fig. 1. 3.0 to 5.5 8 fmcf(3) pc3(cf1), pc4(cf2) 4mhz ceramic oscillator mode see fig. 1. 2.5 to 5.5 4 fmrc internal rc oscillation 2.5 to 5.5 0.5 1.0 2.0 mhz fmslrc internal low-speed rc oscillation 2.5 to 5.5 18 30 45 fsx'tal xt1, xt2 32.768khz crystal oscillator mode see fig. 2. 2.5 to 5.5 32.768 khz fmvco(1) vco oscillator when setting vc3=1 when seldiv=0 or 1 see fig. 9. 2.5 to 3.8 5.0 9.0 fmvco(2) vco oscillator when setting vc3=0 when seldiv=2 or 3 see fig. 9. 2.5 to 3.8 5.0 12 fmvco(3) vco oscillator when setting vc3=1 when seldiv=0 or 1 see fig. 9. 3.6 to 5.5 5.0 9.0 fmvco(4) vco oscillator when setting vc3=0 when seldiv=2 or 3 see fig. 9. 3.6 to 5.5 9.0 12 oscillation frequency range (note 2-3) fmvco(5) vco oscillator when osc0=32.768khz seldiv setting range=0 to 3 seldly setting range=0 to 3 2.5 to 5.5 note 2-4 mhz note 2-3: see tables 1 and 2 for oscillator constant values. note 2-4: vco oscillation frequency = 0.032768 (56 (seldiv+3)+seldly)
LC88F52H0A no.a1228-17/38 electrical characteristics at ta = -40 to +85 c , v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable/ remarks conditions v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2 ports 3, 4, 5 ports 6, 7 ports a, b, c, d resb output disabled pull-up resistor off v in =v dd (including output tr. off leakage current) 2.5 to 5.5 1 low level input current i il (1) ports 0, 1, 2 ports 3, 4, 5 ports 6, 7 ports a, b, c, d resb output disabled pull-up resistor off v in =v ss (including output tr. off leakage current) 2.5 to 5.5 -1 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 ports 4, a, d p40 to p45 pb2 to pb6 i oh =-0.2ma 2.5 to 5.5 v dd -0.4 v oh (4) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) port 5, 6 pc2 i oh =-0.2ma 2.5 to 5.5 v dd -0.4 v oh (6) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (7) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (8) p46, p47 pb0, pb1 i oh =-1.0ma 2.5 to 5.5 v dd -0.4 v oh (9) i oh =-1.0ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (10) pc0, pc1, pc3, pc4, i oh =-0.4ma 2.5 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1, 3, 4 ports 7, d p20 to p21, p24 to p27 pa0 to pa3 pa6 to pa7 pb0 to pb3, pb6 i ol =1.0ma 2.5 to 5.5 0.4 v ol (4) i ol =11ma 4.5 to 5.5 1.5 v ol (5) i ol =3.0ma 3.0 to 5.5 0.4 v ol (6) p22, p23, pa4, pa5, pb4, pb5 i ol =1.3ma 2.5 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) ports 5, 6 pc2 i ol =1.0ma 2.5 to 5.5 0.4 v ol (9) i ol =1.0ma 3.0 to 5.5 0.4 low level output voltage v ol (10) pc0, pc1, pc3, pc4 i ol =0.4ma 2.5 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistor rpu(2) ports 0, 1, 2, 3 ports 4, 5, 6, 7 ports a, b, d, pc2 v oh =0.9v dd 2.5 to 4.5 18 55 150 k hysteresis voltage vhys resb when ports 1, 2, 3, 4, a pnfsan=1 2.5 to 5.5 0.1v dd v pin capacitance cp all pins pi ns other than that under test v in =v ss f=1mhz ta=25 c 2.5 to 5.5 10 pf
LC88F52H0A no.a1228-18/38 serial i/o characteristics at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v serial i/o characteristics (wakeup function disabled) (note 4-1-1) specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(1) 4 low level pulse width tsckl(1) 2 tsckh(1) ? see fig. 6. 2 tsckha(1) ? automatic communication mode ? see fig. 6. 6 tsckhbsy(1a) ? automatic communication mode ? see fig. 6. 23 input clock high level pulse width tsckhbsy(1b) sck0(p12) ? mode other than automatic communication mode ? see fig. 6. 2.5 to 5.5 4 period tsck(2) 4 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck tsckha(2) ? automatic communication mode ? cmos output selected ? see fig. 6. 6 tsckhbsy(2a) ? automatic communication mode ? cmos output selected ? see fig. 6. 4 23 serial clock output clock high level pulse width tsckhbsy(2b) sck0(p12) ? mode other than automatic communication mode ? see fig. 6. 2.5 to 5.5 4 tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) si0(p11), sb0(p11) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 input clock tdd0(1) ? (note 4-1-2) 1tcyc +0.05 serial output output clock output delay time tddo(2) so0(p10), sb0(p11) ? (note 4-1-2) 2.5 to 5.5 1tcyc +0.05 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: specified with respect to the falling edge of si oclk. specified as the interval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88F52H0A no.a1228-19/38 sio0 serial input/output characteristi cs (wakeup function enabled) (note 4-2-1) specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(3) 2 low level pulse width tsckl(3) 1 tsckh(3) 1 serial clock input clock high level pulse width tsckhbsy(3) sck0 (p12) ? see fig. 6. 2.5 to 5.5 2 tcyc data setup time tsdi(2) 0.03 serial input data hold time thdi(2) si0 (p11), sb0 (p11) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 serial output input clock output delay time tdd0(3) so0 (p10), sb0 (p11) ? (note 4-2-2) 2.5 to 5.5 1tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. note 4-2-2: specified with respect to the falling edge of si oclk. specified as the interval up to the time an output change begins in the open drain output mode. see fig.6.
LC88F52H0A no.a1228-20/38 sio1 serial input/output characteristi cs (wakeup function disabled) (note 4-3-1) specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(4) 4 low level pulse width tsckl(4) 2 tsckh(4) ? see fig. 6. 2 tsckha(4) ? automatic communication mode ? see fig. 6. 6 tsckhbsy(4a) ? automatic communication mode ? see fig. 6. 23 input clock high level pulse width tsckhbsy(4b) sck1(p45) ? mode other than automatic communication mode ? see fig. 6. 2.5 to 5.5 4 period tsck(5) 4 tcyc low level pulse width tsckl(5) 1/2 tsckh(5) ? cmos output selected ? see fig. 6. 1/2 tsck tsckha(5) ? automatic communication mode ? cmos output selected ? see fig. 6. 6 tsckhbsy(5a) ? automatic communication mode ? cmos output selected ? see fig. 6. 4 23 serial clock output clock high level pulse width tsckhbsy(5b) sck1(p45) ? mode other than automatic communication mode ? see fig. 6. 2.5 to 5.5 4 tcyc data setup time tsdi(3) 0.03 serial input data hold time thdi(3) si1(p44), sb1(p44) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 s input clock tdd0(4) ? (note 4-3-2) 1tcyc +0.05 serial output output clock output delay time tddo(5) so1(p43), sb1(p44) ? (note 4-3-2) 2.5 to 5.5 1tcyc +0.05 s note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: specified with respect to the falling edge of si oclk. specified as the interval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88F52H0A no.a1228-21/38 sio1 serial input/output characteristi cs (wakeup function enabled) (note 4-4-1) specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(6) 2 low level pulse width tsckl(6) 1 tsckh(6) 1 serial clock input clock high level pulse width tsckhbsy(6) sck1(p45) ? see fig. 6. 2.5 to 5.5 2 tcyc data setup time tsdi(4) 0.03 serial input data hold time thdi(4) si1(p44), sb1(p44) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 serial output input clock output delay time tdd0(6) so1(p43), sb1(p44) ? (note 4-4-2) 2.5 to 5.5 1tcyc +0.05 s note 4-4-1: these specifications are theoretical values. add margin depending on its use. note 4-4-2: specified with respect to the falling edge of si oclk. specified as the interval up to the time an output change begins in the open drain output mode. see fig. 6. smiic0 simple sio mode input/output characteristics specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(7) 4 low level pulse width tsckl(7) 2 input clock high level pulse width tsckh(7) sm0ck(p22) see fig. 6. 2.5 to 5.5 2 period tsck(8) 4 tcyc low level pulse width tsckl(8) 1/2 serial clock output clock high level pulse width tsckh(8) sm0ck(p22) ? cmos output selected ? see fig. 6. 2.5 to 5.5 1/2 tsck data setup time tsdi(5) 0.03 serial input data hold time thdi(5) sm0da(p23) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 serial output output delay time tdd0(7) sm0do(p24), sm0da(p23) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 6. 2.5 to 5.5 1tcyc +0.05 s note 4-5-1: these specifications are theoretical values. add margin depending on its use.
LC88F52H0A no.a1228-22/38 smiic0 i 2 c mode input/output characteristics specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tscl 5 low level pulse width tscll 2.5 input clock high level pulse width tsclh sm0ck(p22) ? see fig. 8. 2.5 to 5.5 2 period tsclx 10 tfilt low level pulse width tscllx 1/2 clock output clock high level pulse width tsclhx sm0ck(p22) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1/2 tscl sm0ck and sm0da pins input spike suppression time tsp sm0ck(p22) sm0da(p23) ? see fig. 8. 2.5 to 5.5 1 tfilt input tbuf sm0ck(p22) sm0da(p23) ? see fig. 8. 2.5 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 bus release time between start and stop output tbufx sm0ck(p22) sm0da(p23) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.6 s ? when smiic register control bit, i 2 cshds=0 ? see fig. 8. 2.0 input thd;sta sm0ck(p22) sm0da(p23) ? when smiic register control bit, i 2 cshds=1 ? see fig. 8. 2.5 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 4.1 start/restart condition hold time output thd;stax sm0ck(p22) sm0da(p23) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.0 s input tsu;sta sm0ck(p22) sm0da(p23) ? see fig. 8. 1.0 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 restart condition setup time output tsu;stax sm0ck(p22) sm0da(p23) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.6 s continued on next page.
LC88F52H0A no.a1228-23/38 continued from preceding page specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit input tsu;sto sm0ck(p22) sm0da(p23) ? see fig. 8. 1.0 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 4.9 stop condition setup time output tsu;stox sm0ck(p22) sm0da(p23) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.1 s input thd;dat sm0ck(p22) sm0da(p23) ? see fig. 8. 0 data hold time output thd;datx sm0ck(p22) sm0da(p23) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1 1.5 tfilt input tsu;dat sm0ck(p22) sm0da(p23) ? see fig. 8. 1 data setup time output tsu;datx sm0ck(p22) sm0da(p23) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1tscl -1.5tfilt tfilt input tf sm0ck(p22) sm0da(p23) ? see fig. 8. 2.5 to 5.5 300 ? when smiic register control bits, pslw=1, p5v=1 5 20 +0.1cb 250 ? when smiic register control bits, pslw=1, p5v=0 3 20 +0.1cb 250 sm0ck and sm0da pins fall time output tf sm0ck (p22) sm0da (p23) ? sm0ck, sm0da port output fast mode ? cb 400pf 3 to 5.5 100 ns note 4-6-1: these specifications are theoretical values. add margin depending on its use. note 4-6-2: the value of tfilt is determined by the values of the register smic0brg, bits 7 and 6 (brp1, brp0) and the system clock frequency. brp1 brp0 tfilt 0 0 tcyc 1 0 1 tcyc 2 1 0 tcyc 3 1 1 tcyc 4 set bits (bpr1, bpr0) so that the value of tfilt falls between the following range: 250ns tfilt >140ns note 4-6-3: cb represents the total loads (in pf) connected to the bus pins. cb 400pf note 4-6-4: the standard clock mode refers to a mode that is entered by configuring smic0brg as follows: 250ns tfilt >140ns brdq (bit5) = 1 scl frequency setting 100khz the high-speed clock mode refers to a mode that is entered by configuring smic0brg as follows: 250ns tfilt >140ns brdq (bit5) = 0 scl frequency setting 400khz
LC88F52H0A no.a1228-24/38 smiic1 simple sio mode input/output characteristics specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(7) 4 low level pulse width tsckl(7) 2 input clock high level pulse width tsckh(7) sm1ck(pb4) see fig. 6. 2.5 to 5.5 2 period tsck(8) 4 tcyc low level pulse width tsckl(8) 1/2 serial clock output clock high level pulse width tsckh(8) sm1ck(pb4) ? cmos output selected ? see fig. 6. 2.5 to 5.5 1/2 tsck data setup time tsdi(5) 0.03 serial input data hold time thdi(5) sm1da(pb5) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 serial output output delay time tdd0(7) sm1do(pb6), sm1da(pb5) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 6. 2.5 to 5.5 1tcyc +0.05 s note 4-7-1: these specifications are theoretical values. add margin depending on its use.
LC88F52H0A no.a1228-25/38 smiic1 i 2 c mode input/output characteristics specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tscl 5 low level pulse width tscll 2.5 input clock high level pulse width tsclh sm1ck(pb4) ? see fig. 8. 2.5 to 5.5 2 period tsclx 10 tfilt low level pulse width tscllx 1/2 clock output clock high level pulse width tsclhx sm1ck(pb4) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1/2 tscl sm0ck and sm0da pins input spike suppression time tsp sm1ck(pb4) sm1da(pb5) ? see fig. 8. 2.5 to 5.5 1 tfilt input tbuf sm1ck(pb4) sm1da(pb5) ? see fig. 8. 2.5 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 bus release time between start and stop output tbufx sm1ck(pb4) sm1da(pb5) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.6 s ? when smiic register control bit, i 2 cshds=0 ? see fig. 8. 2.0 input thd;sta sm1ck(pb4) sm1da(pb5) ? when smiic register control bit, i 2 cshds=1 ? see fig. 8. 2.5 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 4.1 start/restart condition hold time output thd;stax sm1ck(pb4) sm1da(pb5) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.0 s input tsu;sta sm1ck(pb4) sm1da(pb5) ? see fig. 8. 1.0 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 restart condition setup time output tsu;stax sm1ck(pb4) sm1da(pb5) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.6 s continued on next page.
LC88F52H0A no.a1228-26/38 continued from preceding page specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit input tsu;sto sm1ck(pb4) sm1da(pb5) ? see fig. 8. 1.0 tfilt ? standard clock mode ? specified as interval up to time when output state starts changing. 4.9 stop condition setup time output tsu;stox sm1ck(pb4) sm1da(pb5) ? high-speed clock mode ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1.1 s input thd;dat sm1ck(pb4) sm1da(pb5) ? see fig. 8. 0 data hold time output thd;datx sm1ck(pb4) sm1da(pb5) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1 1.5 tfilt input tsu;dat sm1ck(pb4) sm1da(pb5) ? see fig. 8. 1 data setup time output tsu;datx sm1ck(pb4) sm1da(pb5) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1tscl -1.5tfilt tfilt input tf sm1ck(pb4) sm1da(pb5) ? see fig. 8. 2.5 to 5.5 300 ? when smiic register control bits pslw=1, p5v=1 5 20 +0.1cb 250 ? when smiic register control bits pslw=1, p5v=0 3 20 +0.1cb 250 sm0ck and sm0da pins fall time output tf sm1ck(pb4) sm1da(pb5) ? sm0ck, sm0da port output fast mode ? cb 400pf 3 to 5.5 100 ns note 4-8-1: these specifications are theoretical values. add margin depending on its use. note 4-8-2: the value of tfilt is determined by the values of the register smic1brg, bits 7 and 6 (brp1, brp0) and the system clock frequency. brp1 brp0 tfilt 0 0 tcyc 1 0 1 tcyc 2 1 0 tcyc 3 1 1 tcyc 4 set bits (bpr1, bpr0) so that the value of tfilt falls between the following range: 250ns tfilt > 140ns note 4-8-3: cb represents the total loads (in pf) connected to the bus pins. cb 400pf note 4-8-4: the standard clock mode refers to a mode that is entered by configuring smic1brg as follows: 250ns tfilt > 140ns brdq (bit5) = 1 scl frequency setting 100khz the high-speed clock mode refers to a mode that is entered by configuring smic1brg as follows: 250ns tfilt > 140ns brdq (bit5) = 0 scl frequency setting 400khz
LC88F52H0A no.a1228-27/38 sliic0 simple sio mode input/output characteristics specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tsck(9) 4 low level pulse width tsckl(9) 2 serial clock input clock high level pulse width tsckh(9) sl0ck(pa4) see fig. 6. 2.5 to 5.5 2 tcyc data setup time tsdi(7) 0.03 serial input data hold time thdi(7) sl0da(pa5) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.5 to 5.5 0.03 serial output output delay time tdd0(9) sl0do(pa6), sl0da(pa5) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 6. 2.5 to 5.5 1tcyc +0.05 s note 4-9-1: these specifications are theoretical values. add margin depending on its use.
LC88F52H0A no.a1228-28/38 sliic1 i 2 c mode input/output characteristics specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit period tscl 5 low level pulse width tscll 2.5 clock input clock high level pulse width tsclh sl0ck(pa4) ? see fig. 8. 2.5 to 5.5 2 tfilt sl0ck and sl0da pins input spike suppression time tsp sl0ck(pa4) sl0da(pa5) ? see fig. 8. 2.5 to 5.5 1 tfilt bus release time between start and stop input tbuf sl0ck(pa4) sl0da(pa5) ? see fig. 8. 2.5 to 5.5 2.5 tfilt ? when smiic register control bit, i 2 cshds=0 ? see fig. 8. 2.0 start/restart condition hold time input thd;sta sl0ck(pa4) sl0da(pa5) ? when smiic register control bit i 2 cshds=1 ? see fig. 8. 2.5 to 5.5 2.5 tfilt restart condition setup time input tsu;sta sl0ck(pa4) sl0da(pa5) ? see fig. 8. 2.5 to 5.5 1.0 tfilt stop condition setup time input tsu;sto sl0ck(pa4) sl0da(pa5) ? see fig. 8. 2.5 to 5.5 1.0 tfilt input thd;dat sl0ck(pa4) sl0da(pa5) ? see fig. 8. 0 data hold time output thd;datx sl0ck(pa4) sl0da(pa5) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1 1.5 tfilt input tsu;dat sl0ck(pa4) sl0da(pa5) ? see fig. 8. 1 data setup time output tsu;datx sl0ck(pa4) sl0da(pa5) ? specified as interval up to time when output state starts changing. 2.5 to 5.5 1tscl -1.5tfilt tfilt
LC88F52H0A no.a1228-29/38 uart0 operating conditions at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit transfer rate ubr0 u0rx(p13), u0tx(p14), u0brg(p07) 2.5 to 5.5 4 8 tbgcyc note 4-9: tbgcyc denotes one cy cle of the baudrate clock source. uart2 operating conditions at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit transfer rate ubr2 u2rx(p16), u2tx(p17) 2.5 to 5.5 8 4096 tbgcyc note 4-10: tbgcyc denotes one cy cle of the baudrate clock source. uart3 operating conditions at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit transfer rate ubr3 u3rx(p34), u3tx(p35) 2.5 to 5.5 8 4096 tbgcyc note 4-10: tbgcyc denotes one cy cle of the baudrate clock source. uart4 operating conditions at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit transfer rate ubr4 u4rx(pb2), u4tx(pb3) 2.5 to 5.5 8 4096 tbgcyc note 4-10: tbgcyc denotes one cy cle of the baudrate clock source. pulse input conditions at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p30), int1(p31), int2(p32), int3(p33), int4(p20), int5(p21), int6(p40), int7(p41) ? interrupt source flag can be set. ? event inputs for timers 2 and 3 are enabled. 2.5 to 5.5 2 tcyc high/low level pulse width tpil(2) resb resetting is enabled. 2.5 to 5.5 10 s
LC88F52H0A no.a1228-30/38 ad converter characteristics at ta = -40 to +85 c, v ss 1 = v ss 2 = v ss 3 = v ss 4 = 0v 12-bit ad conversion mode specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit resolution nad 3.0 to 5.5 12 bit absolute accuracy etad (note 6-1) 3.0 to 5.5 16 lsb 4.5 to 5.5 27 209 conversion time tcad12 conversion time calculated 3.0 to 5.5 67 209 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p60) to an7(p67), an8(p70) to an15(p77) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formula: tcad12= ((52/( ad division ratio))+2) tcyc 8-bit ad conversion mode specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit resolution nad 3.0 to 5.5 8 bit absolute accuracy etad (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 17 129 conversion time tcad8 conversion time calculated 3.0 to 5.5 42 129 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p60) to an7(p67), an8(p70) to an15(p77) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formula: tcad8= ((32/(ad division ratio))+2) tcyc note 6-1: the quantization error (1/2lsb ) is excluded from th e absolute accuracy. note 6-2: the conversion time refers to the interval from th e time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. the conversion time is twice the normal value when one of the following conditions occurs: ? the first ad conversion is executed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is executed after the ad conversi on mode is switched from 8-bit to 12-bit ad conversion mode. da converter characteristics at ta=-40 to+85 c, v ss 1=v ss 2=v ss 3=v ss 4=0v specification parameter symbol applicable pin /remarks conditions v dd [v] min typ max unit resolution nda 3.0 to 5.5 8 bit absolute accuracy etda 3.0 to 5.5 2.0 lsb output resistor daor 3.0 to 5.5 9.5 16.0 22.9 k analog port output current vdaout da00(pd0) to da02(pd2) da10(pd3) to da12(pd5) 3.0 to 5.5 v ss v dd v
LC88F52H0A no.a1228-31/38 consumption current characteristics at ta=-40 to +85 c, v ss 1=v ss 2=v ss 3=v ss 4=0v typ: 5.0v (v dd =4.5v to 5.5v), 3.3v (v dd =3.0v to 4.5v, 2.2v to 4.5v) specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit iddop(1) ? fmcf=12mhz ceramic oscillation mode ? fmx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz ? internal rc oscillation stopped ? 1/1 frequency division mode 4.5 to 5.5 10.4 19 iddop(2) 4.5 to 5.5 8.50 17 iddop(3) ? fmcf=8mhz ceramic oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to 8mhz ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 4.5 4.91 13 iddop(4) 4.5 to 5.5 4.02 6.1 iddop(5) ? fmcf=4mhz ceramic oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to 4mhz ? internal rc oscillation stopped ? 1/2 frequency division mode 2.5 to 4.5 2.62 4.3 iddop(6) 4.5 to 5.5 2.18 6.0 iddop(7) ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to internal rc oscillation ? 1/1 frequency division mode 2.2 to 4.5 1.28 4.2 ma iddop(8) 4.5 to 5.5 72.9 195 iddop(9) ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to 32.768khz ? internal rc oscillation stopped ? 1/1 frequency division mode 2.2 to 4.5 39.8 160 a iddop(10) ? fmcf=0hz (oscillation stopped) ? fmvco=11.1mhz oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to vco ? internal rc oscillation stopped ? 1/1 frequency division mode 4.5 to 5.5 10.5 19.2 iddop(11) 4.5 to 5.5 9.07 17.3 normal mode consumption current (note 7-1) iddop(12) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? fmcf=0hz (oscillation stopped) ? fmvco=7.34mhz oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to vco ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 4.5 5.23 13.8 ma note 7-1: the consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. continued on next page.
LC88F52H0A no.a1228-32/38 continued from preceding page. specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit iddhalt(1) ? halt mode ? fmcf=12mhz ceramic mode ? fmx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz ? internal rc oscillation stopped ? 1/1 frequency division mode 4.5 to 5.5 3.70 6.5 iddhalt(2) 4.5 to 5.5 2.60 5.0 iddhalt(3) ? halt mode ? fmcf=10mhz ceramic oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to 10mhz ? internal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 4.5 1.34 3.5 iddhalt(4) 4.5 to 5.5 1.08 3.1 iddhalt(5) ? halt mode ? fmcf=4mhz ceramic oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to 4mhz ? internal rc oscillation stopped ? 1/2 frequency division mode 2.2 to 4.5 0.50 2.2 iddhalt(6) 4.5 to 5.5 0.53 3.0 iddhalt(7) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to internal rc oscillation ? 1/1 frequency division mode 2.2 to 4.5 0.26 2.1 ma iddhalt(8) 4.5 to 5.5 27.3 145 iddhalt(9) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to 32.768khz ? internal rc oscillation stopped ? 1/1 frequency division mode 2.2 to 4.5 9.52 112 a iddhalt(10) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmvco=11.1mhz oscillator mode ? fmx'tal=32.768khz crystal oscillator mode ? system clock set to vco ? internal rc oscillation stopped ? 1/1 frequency division mode 4.5 to 5.5 4.19 6.8 iddhalt(11) 4.5 to 5.5 3.18 5.5 halt mode consumptio n current (note 7-1) iidhalt(12) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? halt mode ? fmcf=0hz (oscillation stopped) ? fmvco=7.34mhz oscillator mode fmx'tal=32.768khz crystal oscillator mode ? system clock set to vco vinternal rc oscillation stopped ? 1/1 frequency division mode 3.0 to 4.5 1.68 4.0 ma iddhold(1) 4.5 to 5.5 0.11 98 hold mode consumption current iddhold(2) hold mode ? cf1=v dd or open (external clock mode) 2.5 to 4.5 0.04 72 iddhold(3) 4.5 to 5.5 19.0 132 holdx mode consumption current iddhold(4) v dd 1 holdx mode ? cf1=v dd or open (external clock mode) ? fmx'tal=32.768khz crystal oscillator mode 2.5 to 4.5 4.91 90 a note 7-1: the consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors.
LC88F52H0A no.a1228-33/38 f-rom programming characteristics at ta = +10 c to +55 c, v ss 1=v ss 2=v ss 3=v ss 4=0v specification parameter symbol applicable pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? microcontroller erase current current is excluded. 3.0 to 5.5 15 ma tfw(1) ? 512-/1k-byte erase operation 3.0 to 5.5 30 ms onboard programming time tfw(2) ? 2-byte programming operation 3.0 to 5.5 60 s power pin treatment conditions 1 (v dd 1, v ss 1) connect capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ? connect among the v dd 1 and v ss 1 pins and the capacitors c1 and c2 w ith the shortest possible lead wires, of the same length (l1=l1', l2=l2') wherever possible. ? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should be approximately 0.1 f or larger. ? the v dd 1 and v ss 1 traces must be thicker than the other traces. power pin treatment conditions 2 (v dd (2, 3, 4), v ss (2, 3, 4)) connect capacitors that meet the following condition between the v dd (2, 3, 4) and v ss (2, 3, 4) pins: ? connect among the v dd (2, 3, 4) and v ss (2, 3, 4) pins and the capacitor c3 with the shortest possible lead wires, of the same length (l3=l3') wherever possible. ? the capacitance of c3 should be approximately 0.1 f or larger. ? the v dd (2, 3, 4) and v ss (2, 3, 4) traces must be thicker than the other traces. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2 v ss (2, 3, 4) v dd (2, 3, 4) l3? l3 c3
LC88F52H0A no.a1228-34/38 characteristics of a sample osc1 system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic resonator circuit constant oscillation stabilization time nominal frequency vendor name resonator c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz cstce12m0g52-r0 (10) ( 10) open 470 2.4 to 5.5 0.02 0.2 c1, c2 integrated type cstce8m00g52-r0 (10) (10) open 1k 2.3 to 5.5 0.02 0.2 c1, c2 integrated type 8mhz cstls8m00g53-b0 (15) (15) open 1k 2.5 to 5.5 0.02 0.2 c1, c2 integrated type cstcr4m00g53-r0 (15) (15) o pen 1.5k 2.2 to 5.5 0.02 0.2 c1, c2 integrated type 4mhz murata cstls4m00g53-b0 (15) (15) o pen 1.5k 2.3 to 5.5 0.02 0.2 c1, c2 integrated type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the lower limit level of the operating voltage range (see figure 4) characteristics of a sample syst em clock oscillator circuit given below are the characteristics of a sample subsystem cl ock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal resonator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 10 10 open 0 2.2 to 5.5 0.8 2 applicable cl value=7.0pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is execut ed plus the time interval that is required for the oscillatio n to get stabilized after the hold mode is released (see figure 4). note: the traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd c1 c2 cf cf2 cf1 rd1 rf1 c3 rd2 c4 x?tal xt2 xt1 rf2
LC88F52H0A no.a1228-35/38 reset time and oscillation stabilization time hold release and oscillation stabilization time figure 4 oscillation stabilization time timing charts tmsx'tal tmscf internal rc oscillation cf1, cf2 xt1, xt2 state hold halt instruction execution hold release no hold release signal hold release signal valid interrupt operation tmsx'tal tmscf v dd 0v reset time power resb internal rc oscillation cf1, cf2 xt1, xt2 operating mode unpredictable reset i n iti a li za ti on i ns t ruc ti on execution user instruction execution operating v dd l o w e r limi t
LC88F52H0A no.a1228-36/38 figure 5 reset circuit * : * remarks: dix and dox denote the last bits communicated; x = 0 to 32768 figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res res tpil tpih note: reset signal must be present when power supply rises. determine the value of c res and r res so that the reset signal is present for 10 s after the su pp l y volta g e g ets stabilized. dataout: dataout: dataout: data ram transfer period (sio0 and sio1 only ) data ram transfer period (sio0 and sio1 only) di0 di7 dix di8 do0 do7 dox do8 di1 do1 sioclk: datain: datain: sioclk: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo tsckhbsy run: di6 do6 tsckhbsy
LC88F52H0A no.a1228-37/38 tbuf thd;sta tlow tr thd;dat thigh tf tsu;dat tsu;sta thd;sta tsp tsu;sto p s sr p sda sck s: start condition p: stop condition sr: restart condition figure 8 i 2 c timing figure 9 filt recommended circuit * take at least 50ms to oscillation to stabilize after pll is started. 100 2.2
LC88F52H0A no.a1228-38/38 sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of march, 2010. specifications and information herein are subject to change without notice. ps

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