general description the ds1110 delay line is an improved replacement for the ds1010. it has ten equally spaced taps providing delays from 5ns to 500ns. the devices are offered in a standard 14-pin dip, 16-pin so, or 14-pin tssop. the ds1110 series delay lines provide a nominal accuracy of ?% or ?ns, whichever is greater, at 5v and +25?. the ds1110 reproduces the input logic state at the tap 10 output after a fixed delay as specified by the dash number extension of the part number. the ds1110 is designed to produce both leading- and trailing-edge delays with equal precision. each tap is capable of dri- ving up to ten 74ls type loads. dallas semiconductor can customize standard products to meet special needs. features ? all-silicon, 5v, 10-tap delay line ? improved, drop-in replacement for the ds1010 ? 10 taps equally spaced ? delays are stable and precise ? leading- and trailing-edge accuracy ? delay tolerance ?% or ?ns, whichever is greater, at 5v and +25? ? economical ? auto-insertable, low profile ? low-power cmos ? ttl/cmos compatible ? vapor phase, ir, and wave solderable ? fast-turn prototypes ? delays specified over commercial and industrial temperature ranges ? custom delays available ? standard 14-pin dip, 16-pin so or, 14-pin tssop ds1110 10-tap silicon delay line _____________________________________________ maxim integrated products 1 top view 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc tap1 tap3 tap5 tap4 tap2 n.c. in tap7 tap9 tap10 gnd tap8 tap6 tssop ds1110e pin configurations ordering information rev 0; 6/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package ds1110-xxx -40 c to +85 c 14 dip ds1110e-xxx -40 c to +85 c 14 tssop ds1110s-xxx -40 c to +85 c 16 so applications communications equipment medical devices automated test equipment pc peripheral devices selector guide appears at end of data sheet. pin configurations continued at end of data sheet.
ds1110 10-tap silicon delay line 2 ______________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = 5.0v ?%, t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on any pin relative to ground .................-0.5v to +6.0v operating temperature range ...........................-40 c to +85 c storage temperature range .............................-55 c to +125 c soldering temperature...................see ipc/jedec j-std-020a parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.75 5.0 5.25 v high-level input voltage v ih (note 1) 2.4 v cc + 0.3 v low-level input voltage v il (note 1) -0.3 +0.8 v input leakage current i i 0v v i v cc -1.0 +1.0 ? active current i cc v cc = max, period = min (note 2) 40 150 ma high-level output current i oh v cc = min, v oh = 2.3v -1.0 ma low-level output current i ol v cc = min, v ol = 0.5v 12 ma ac electrical characteristics (v cc = 5.0v ?%, t a = -40? to +85?.) parameter symbol conditions min typ max units input pulse width t wi (note 6) 10% of tap 10 ns +25?, 5.0v (notes 3, 5, 6, 7) -2 table 1 +2 0? to +70? (notes 4?) -3 table 1 +3 input-to-tap delay (delays 40ns) t plh t phl -40? to +85? (notes 4?) -4 table 1 +4 ns +25?, 5.0v (notes 3, 5, 6, 7) -5 table 1 +5 0? to +70? (notes 4?) -8 table 1 +8 input-to-tap delay (delays > 40ns) t plh t phl -40? to +85? (notes 4?) -13 table 1 +13 % power-up time t pu 200 ms input period period (note 8) 2 (t wi ) or 20, wh i chever is gr eater ns
ds1110 10-tap silicon delay line _____________________________________________________________________ 3 note 1: all voltages are referenced to ground. note 2: measured with outputs open. note 3: initial tolerances are with respect to the nominal value at +25? and v cc = 5.0v for both leading and trailing edges. note 4: temperature and voltage tolerances are with respect to the actual delay measured over stated temperature range and a 4.75v to 5.25v range. note 5: intermediate delay values are available on a custom basis. note 6: see test conditions section. note 7: all tap delays tend to vary unidirectionally with temperature or voltage changes. for example, if tap 1 slows down, all other taps also slow down; tap 3 can never be faster than tap 2. note 8: pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.). capacitance (t a = +25?.) t ypical operating characteristics (v cc = 5.0v, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units input capacitance c in 510pf 47 48 49 50 51 52 53 54 46 ds1110-50 tap 10 delay vs. temperature ds1110 toc04 temperature ( c) delay (ns) 60 35 10 -15 -40 85 ds1110-500 tap 10 delay vs. temperature ds1110 toc03 temperature ( c) delay (ns) 60 35 10 -15 450 475 500 525 550 575 425 -40 85 500khz input 10 1.0 20 40 60 80 100 120 140 160 180 200 0 0.1 100 ds1110-50 active current vs. input frequency ds1110 toc02 frequency (mhz) active current (ma) 15pf load/tap v cc = 5.25v ds1110-500 active current vs. input frequency ds1110 toc01 frequency (mhz) active current (ma) 1.0 5 10 15 20 25 30 35 40 0 0.1 10 15pf load/tap v cc = 5.25v
ds1110 10-tap silicon delay line 4 ______________________________________________________________________ t ypical operating characteristics (continued) (v cc = 5.0v, t a = +25?, unless otherwise noted.) 47 49 51 53 55 45 ds1110-50 tap 10 delay vs. voltage ds1110 toc08 voltage (v) delay (ns) 5.125 5.000 4.875 4.750 5.250 falling edge rising edge ds1110-500 tap 10 delay vs. voltage ds1110 toc07 voltage (v) delay (ns) 5.125 5.000 4.875 480 500 520 540 460 4.750 5.250 falling edge rising edge 500khz input ds1110-50 delay vs. tap ds1110 toc06 tap delay (ns) 9 8 6 7 3 4 5 2 5 10 15 20 25 30 35 40 45 50 0 110 falling edge rising edge ds1110-500 delay vs. tap ds1110 toc05 tap delay (ns) 9 8 6 7 3 4 5 2 50 100 150 200 250 300 350 400 450 500 0 110 falling edge rising edge 500khz input pin description pin dip/tssop so name function 11 in input 2 2, 3, 15 n.c. no connection 78 gnd ground 13, 3, 12, 4, 11, 5, 10, 6, 9, 8 14, 4, 13, 5, 12, 6, 11, 7, 10, 9 tap 1?ap 10 tap output number 14 16 v cc 5.0v
detailed description the ds1110 delay line is an improved replacement for the ds1010. it has ten equally spaced taps providing delays from 5ns to 500ns. the devices are offered in a standard 14-pin dip, 16-pin so, or 14-pin tssop. the ds1110 series delay lines provide a nominal accuracy of ?% or ?ns, whichever is greater, at 5v and +25?. the ds1110 reproduces the input logic state at the tap 10 output after a fixed delay as specified by the dash number extension of the part number. the ds1110 is designed to produce both leading- and trailing-edge delays with equal precision. each tap is capable of dri- ving up to ten 74ls type loads. dallas semiconductor can customize standard products to meet special needs. for special requests call 972-371-4348. ds1110 10-tap silicon delay line _____________________________________________________________________ 5 10% 10% in t ap1 tap2 tap9 tap10 10% 10% figure 1. logic diagram part total delay* (ns) delay/tap (ns) ds1110-50 50 5 ds1110-60 60 6 ds1110-75 75 7.5 ds1110-80 80 8 ds1110-100 100 10 ds1110-125 125 12.5 ds1110-150 150 15 ds1110-175 175 17.5 ds1110-200 200 20 ds1110-250 250 25 ds1110-300 300 30 ds1110-350 350 35 ds1110-400 400 40 ds1110-450 450 45 ds1110-500 500 50 table 1. part number by delay (t phl , t plh ) v il in out 0.8v v ih t rise 2.2v 1.5v 1.5v 1.5v 1.5v 1.5v 0.8v 2.2v period t wi t plh t plh t f all t wi figure 2. timing diagram: silicon delay line * custom delays are available.
ds1110 terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of any tap out- put pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of any tap out- put pulse. test setup description figure 3 illustrates the hardware configuration used for measuring the timing parameters on the ds1110. a precision pulse generator under software control pro- duces the input waveform. time delays are measured by a time interval counter (20ps resolution) connected 10-tap silicon delay line 6 ______________________________________________________________________ pulse generator time interval counter vhf switch control unit stop device under test z0 = 50 ? start figure 3. test circuit
ds1110 10-tap silicon delay line _____________________________________________________________________ 7 between the input and each tap. each tap is selected and connected to the counter by a vhf switch-control unit. all measurements are fully automated, with each instrument controlled by a central computer over an ieee-488 bus. output each output is loaded with the equivalent of one 74fo4 input gate. delay is measured at the 1.5v level on the rising and falling edge. input condition ambient temperature +25? ?? supply voltage (v cc ) 5.0v ?.1v high = 3.0v ?.1v input pulse low = 0.0v ?.1v source impedance 50 ? max rise and fall time 3ns max pulse width 500ns (1? for -500ns) period 1? (2? for -500ns) table 2. test conditions note: the above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. chip information transistor count: 6813 selector guide part temp range pin- package total delay ( ns)* ds1110-50 -40 c to +85 c 14 dip 50 ds1110-60 -40 c to +85 c 14 dip 60 ds1110-75 -40 c to +85 c 14 dip 75 ds1110-80 -40 c to +85 c 14 dip 80 ds1110-100 -40 c to +85 c 14 dip 100 ds1110-125 -40 c to +85 c 14 dip 125 ds1110-150 -40 c to +85 c 14 dip 150 ds1110-175 -40 c to +85 c 14 dip 175 ds1110-200 -40 c to +85 c 14 dip 200 ds1110-250 -40 c to +85 c 14 dip 250 ds1110-300 -40 c to +85 c 14 dip 300 ds1110-350 -40 c to +85 c 14 dip 350 ds1110-400 -40 c to +85 c 14 dip 400 ds1110-450 -40 c to +85 c 14 dip 450 ds1110-500 -40 c to +85 c 14 dip 500 ds1110e-50 -40 c to +85 c 14 tssop 50 ds1110e-60 -40 c to +85 c 14 tssop 60 ds1110e-75 -40 c to +85 c 14 tssop 75 ds1110e-80 -40 c to +85 c 14 tssop 80 ds1110e-100 -40 c to +85 c 14 tssop 100 ds1110e-125 -40 c to +85 c 14 tssop 125 ds1110e-150 -40 c to +85 c 14 tssop 150 ds1110e-175 -40 c to +85 c 14 tssop 175 ds1110e-200 -40 c to +85 c 14 tssop 200 part temp range pin- package total delay ( ns)* ds1110e-250 -40 c to +85 c 14 tssop 250 ds1110e-300 -40 c to +85 c 14 tssop 300 ds1110e-350 -40 c to +85 c 14 tssop 350 ds1110e-400 -40 c to +85 c 14 tssop 400 ds1110e-450 -40 c to +85 c 14 tssop 450 ds1110e-500 -40 c to +85 c 14 tssop 500 ds1110s-50 -40 c to +85 c 16 so 50 ds1110s-60 -40 c to +85 c 16 so 60 ds1110s-75 -40 c to +85 c 16 so 75 ds1110s-80 -40 c to +85 c 16 so 80 ds1110s-100 -40 c to +85 c 16 so 100 ds1110s-125 -40 c to +85 c 16 so 125 ds1110s-150 -40 c to +85 c 16 so 150 ds1110s-175 -40 c to +85 c 16 so 175 ds1110s-200 -40 c to +85 c 16 so 200 ds1110s-250 -40 c to +85 c 16 so 250 ds1110s-300 -40 c to +85 c 16 so 300 ds1110s-350 -40 c to +85 c 16 so 350 ds1110s-400 -40 c to +85 c 16 so 400 ds1110s-450 -40 c to +85 c 16 so 450 ds1110s-500 -40 c to +85 c 16 so 500 * custom delays are available.
ds1110 10-tap silicon delay line maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information for the latest package outline information, go to www.maxim-ic. com/packages . 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc tap1 tap3 tap5 tap4 tap2 n.c. in top view tap7 tap9 tap10 gnd tap8 tap6 dip (300mil) not for use in new designs ds1110 15 14 13 12 11 10 9 2 3 4 5 6 7 8 n.c. tap1 tap3 tap5 tap4 tap2 n.c. n.c. 16 1v cc in1 tap7 tap9 tap10 gnd tap8 tap6 so (300mil) ds1110s pin configurations (continued)
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