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kaa00b209m-tgxx revision 1.3 march 2003 - 1 - mcp memory document title multi-chip package memory 256m bit(16mx16) nand flash/32m bit(2mx16) u t ram/128m bit(2mx16x4banks) mobilesdram revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 0.3 1.0 1.1 remark advance advance preliminary preliminary final final history initial issue. revised errorta : dpd -> dpd inserted the description of dpd mode by external pin revised t rdl (min.) : 2 clocks -> 15ns - revised advance to preliminary - revised twp : twp=25ns -> if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns - changed vih from 0.9xvddq to 0.8xvddq and voh from 0.95xvddq to 0.9xvddq - changed sdram input pulse level from 0.95xvddq to 0.9xvddq. - changed tdal from 2clk+trp to trdl+trp. - changed tarfc from 14clk to 105ns - changed tsrfx from 16clk to 120ns - inserted functional block diagram - inserted standby current in deep power down mode (iccd=20ua) - changed vcc/vccq from 1.85v 0.15v to 1.8v 0.15v - revised flash operation table(during read) - inserted 105mhz condition - changed tch and tcl from 3ns to 3.5ns for 66mhz - erased of external tcsr and addition of internal tcsr. - changed of dc current specification. - changed voh from 0.9xvccq to vccq-0.2v. - inserted standby current(i sb 2u) comment - changed vcc/vccq from 1.8v 0.15v to 1.85v 0.15v draft date january 15, 2002 january 28, 2002 march 4, 2002 april 9, 2002 august 17, 2002 october 7, 2002 note : for more detailed features and specifications including faq, please refer to samsung?s web site. http://samsungelectronics.com/semiconductors/products/products_index.html
kaa00b209m-tgxx revision 1.3 march 2003 - 2 - mcp memory document title multi-chip package memory 256m bit(16mx16) nand flash/32m bit(2mx16) u t ram/128m bit(2mx16x4banks) mobilesdram revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 1.2 1.3 remark final final history - revised errate unit of t arfc / t srfx : clk --> ns - addition of timing diagram - addition of internal tcsr - removal of external tcsr changed mcp part number. kaa00b206m --> kaa00b209m draft date february 24, 2003 march 25, 2003 note : for more detailed features and specifications including faq, please refer to samsung?s web site. http://samsungelectronics.com/semiconductors/products/products_index.html
kaa00b209m-tgxx revision 1.3 march 2003 - 3 - mcp memory general description features power supply voltage - nand, sdram : 1.7~2.0v - u t ram : 2.7~3.1v data output power : 1.7~2.0v operating temperature : -25 c ~ 85 c package : 127-ball tbga type - 10.5x12mm, 0.8mm pitch organization - memory cell array : (16m + 512k)bit x 16bit - data register : (256 + 8)bit x16bit automatic program and erase - page program : (256 + 8)word - block erase : (8k + 256)word page read operation - page size : (256 + 8)word - random access : 10 m s(max.) - serial page access : 50ns(min.) fast write cycle time - program time : 200 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years command register operation intelligent copy-back process technology : cmos organization : 2m x 16 bit read access time : 90ns, 100ns three state outputs compatible with low power sram deep power down : memory cell data holds invalid ? 1.8v power supply. ? lvcmos compatible with multiplexed address. ? four banks operation. ? frequency : 105mhz, 66mhz ? mrs cycle with address key programs. -. cas latency (1, 2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? special option for mobile application. -. pasr(partial array self refresh) with emrs cycle. -. internal tcsr(temperature compensated self refresh) -. ds(driver strength control) ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation. ? special function support. -. dpd mode by external pin ? dqm for masking. ? auto refresh. ? 64ms refresh period (4k cycle). multi-chip package memory 256m bit (16mx16) nand flash/32m bit (2mx16) utram/128m bit (2mx16x4banks) mobile sdram the kaa00b209m is a multi chip package memory which combines 256mbit nand flash memory, 32mbit unit transistor cmos ram and 128mbit synchronous high data rate dynamic ram. 256mbit nand flash memory is organized as 16m x16 bits and 32mbit u t ram is organized as 2m x16 bits and 128mbit sdram is organized as 2m x16 bits x4 banks. in 256mbit nand flash, a 264-word page program can be typically achieved within 200us and an 8k-word block erase can be typi- cally achieved within 2ms. in serial read operation, a byte can be read by 50ns. dq pins serve as the ports for address and data input/output as well as command inputs. even the write-intensive systems can take advantage of flash s extended reliability of 100k program/erase cycles with real time mapping-out algorithm. these algorithms have been implemented in many mass storage applications. in 128mbit sdram, synchronous design allows precise cycle control with the use of system clock, and i/o transactions are possibl e on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. the kaa00b209m is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. this device is available in 127-ball tbga type.
kaa00b209m-tgxx revision 1.3 march 2003 - 4 - mcp memory pin configuration tbga: top view (ball down) dnu 1 2 3 4 5 6 a b c d e f g h a14 a11 a8 vccn vccu vss a18 a6 a3 dnu a15 r/ b n ce n nc nc a7 a17 a5 re vccq a12 a10 a20 we zz u lb u cle ale dq9d a13 a9 a19 nc ub u a4 a2 dq14d dq10d dq8d dq11d a4d a3d a5d vss dq15d dq13d nc a7d a8d a9d vcc udqm ldqm dq12d ras cke cas vccq dq0d dq1d nc nc dpd clk dq2d dq3d dq4d dq5d a11d ba0 we d v ss dq6d dq7d nc a2d nc a1d a0d a10d a1 dnu wp n dnu vss vcc a6d cs d vss vcc vss ba1 7 8 10 9 j k l m vccq a16 dq14 dq5 dq10 dq2 dq1 dq0 a0 dnu vcc dq15 dq6 dq12 dq4 dq11 dq3 dq8 cs u dnu v ss dq7 dq13 vccu vccqu vccn vccqn dq9 oe u vcc vss dnu vss dnu 12 11 n
kaa00b209m-tgxx revision 1.3 march 2003 - 5 - mcp memory pin description pin name pin function pin name pin function a0~a20 address input(u t ram) cs d chip enable(sdram) a0d~a11d address input(sdram) cke clock enable(sdram) ba0~ba1 bank address input(sdram) ras row address strobe(sdram) dq0~dq15 data input/out put(u t ram, nand) cas column address strobe(sdram) dq0d~dq15d data input/out put(sdram) we d write enable(sdram) ce n chip enable(nand) ldqm low data out put mask(sdram) re read enable(nand) udqm upper data out put mask(sdram) wp n write protection(nand) dpd deep power down(sdram) ale address latch enable(nand) vccn power supply(nand) cle command latch enable(nand) vccu power supply(u t ram) r/ b n read/busy output(nand) vcc power supply(sdram) we write enable(nand, u t ram) vccqn data out power(nand) cs u chip enable(u t ram) vccqu data out power(u t ram) zz u deep power down(u t ram) vccq data out power(sdram) ub u upper byte (u t ram) v ss ground lb u low byte(u t ram) nc no connection oe u output enable(u t ram) dnu do not use clk system clock(sdram) ordering information samsung mcp memory(3chips) device type nand + u t ram + sdram nor flash density, voltage, organization, bank size, boot block 00 = none nand flash speed g= 50ns dram interface, density, voltage, organization 9 = sdr, 128m, 1.85v/1.85v, x16,t *t : internal tcsr(icc6:300ua(@85?c) u t ram speed q = 90ns s = 100ns u t ram density, voltage, organization 2 = 32m, 2.9v/1.85v, x16 package t = tbga nand flash density, voltage, organization b = 256m, 1.85v/1.85v, x16 sram density, voltage, organization 0 = none sdram speed v = 15ns x = 10ns ka a 00 b 2 0 9 m - t g x x version m = 1st generation
kaa00b209m-tgxx revision 1.3 march 2003 - 6 - mcp memory functional block diagram cle ce f vss wp ale vcc f x-buffers 256m+8m bit command nand flash array (256 + 8)word x 65536 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver bottom boot block precharge circuit. i/o circuit column select clk gen. row select data control control logic u t ram (2mb x16) main cell array ub vcc u vss cs u lb zz vccq u r/ b f re bank select data input register 2m x 16 2m x 16 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r 2m x 16 2m x 16 t i m i n g r e g i s t e r a 0 ~ a 20 we oe u clk cs vss cke ba0~ba1 vcc q /vcc ras a 0 ~ a 11 cas ldqm we udqm dpd dq 0 to dq15 dq 0 to dq15 dq 0 to dq15 dq 0 to dq15
kaa00b209m-tgxx revision 1.3 march 2003 - 7 - mcp memory 256mb(16m x 16) nand flash
kaa00b209m-tgxx revision 1.3 march 2003 - 8 - mcp memory figure 1. nand flash(x16) array organization note : column address : starting address of the register. * l must be set to "low". i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o8 to 15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 l* 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 l* 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 l* column address row address (page address) 256word 8 word page register (=256 words) 64k pages (=2,048 blocks) 256 word 16 bit 8 word 1 block =32 pages = (8k + 256) word i/o 0 ~ i/o 15 1 page = 264 word 1 block = 264 word x 32 pages = (8k + 256) word 1 device = 264words x 32pages x 2048 blocks = 264 mbits page register
kaa00b209m-tgxx revision 1.3 march 2003 - 9 - mcp memory product introduction this device is a 264mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 264 columns. spare eight columns are located from column address of 256~263. a 264-word data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of the 32 p ages formed by two nand structures, totaling 8448 nand structures of 16 cells. the array organization is shown in figure1. the progra m and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array con- sists of 2048 separately erasable 8k-word blocks. it indicates that the bit by bit erase operation is prohibited on this device. this device has addresses multiplexed into lower 8 i/o?s. this device allows sixteen bit wide data transport into and out of pag e reg- isters. this scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densi - ties by maintaining consistency in system board design. command, address and data are all written through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. some commands require one bus cycle. for example, reset command, read command, status read command, etc require just one cycle bus. some other commands like page program and copy-back program and block erase, require two cycles: one cycle for setup and the other cycle for execution. the 16m-word phys- ical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing sp e- cific commands into the command register. table 1 defines the specific commands of this device. the device includes one block sized otp(one time programmable), which can be used to increase system security or to provide identification capabilities. detailed information can be obtained by contact with samsung. table 1. command sets caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h - read 2 50h - read id 90h - reset ffh - o page program 80h 10h copy-back program 00h 8ah block erase 60h d0h read status 70h - o
kaa00b209m-tgxx revision 1.3 march 2003 - 10 - mcp memory dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions min typ max unit operating current sequential read i cc 1 trc=50ns, ce =v il i out =0ma - 8 15 ma program i cc 2 - - 8 15 erase i cc 3 - - 8 15 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 m a input leakage current i li v in =0 to vcc(max) - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 input high voltage v ih i/o pins v ccq -0.4 - v ccq +0.3 v except i/o pins v cc -0.4 - v cc +0.3 input low voltage, all inputs v il - -0.3 - 0.4 output high voltage level v oh i oh =-100 m a v cc q-0.1 - - output low voltage level v ol i ol =100ua - - 0.1 output low current(r/ b ) i ol (r/ b ) v ol =0.1v 3 4 - ma recommended operating conditions (voltage reference to gnd, t a =-25 to 85 c ) parameter symbo min typ. max unit supply voltage v cc 1.65 1.8 1.95 v supply voltage v ccq 1.65 1.8 1.95 v supply voltage v ss 0 0 0 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in/out -0.6 to + 2.45 v v cc -0.2 to + 2.45 v ccq -0.2 to + 2.45 temperature under bias t bias -40 to +125 c storage temperature t stg -65 to +150 c short circuit current ios 5 ma
kaa00b209m-tgxx revision 1.3 march 2003 - 11 - mcp memory capacitance ( t a =25 c, v cc =1.8v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. this device may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is pre- sented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks . refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correct ion. 3. the 2nd and 3rd blocks are good upon shipping. parameter symbol min typ. max unit valid block number n vb 2013 - 2048 blocks program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms ac test condition ( vcc=1.65v~1.95v , t a =-25 to 85 c unless otherwise noted) parameter value input pulse levels 0v to vccq input rise and fall times 5ns input and output timing levels vccq/2 output load (vccq:1.8v +/-10%) 1 ttl gate and cl=30pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by
kaa00b209m-tgxx revision 1.3 march 2003 - 12 - mcp memory ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns ce access time t cea - 45 ns re access time t rea - 30 ns re high to output hi-z t rhz - 30 ns ce high to output hi-z t chz - 20 ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) m s ac timing characteristics for command / address / data input note : 1. if t cs is set less than 10ns, t wp must be minimum 35ns, otherwise, t wp may be minimum 25ns. parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 .- ns ce hold time t ch 10 - ns we pulse width t wp 25 (1) - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns
kaa00b209m-tgxx revision 1.3 march 2003 - 13 - mcp memory nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perf or- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guar- anteed to be a valid block, does not require error correction. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 1st word in the spare area. samsung makes sure that either the 1st or 2nd page of every invali d block has non-ffffh data at the column address of 256 and 261. since the invalid block information is also erasable in most cas es, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow cha rt(fig- ure 2). any intentional erasure of the original invalid block information is prohibited. * check "ffh" at the column address 256 figure 2. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table and 261 of the 1st and 2nd page in the block
kaa00b209m-tgxx revision 1.3 march 2003 - 14 - mcp memory nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. to improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any bl ock replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
kaa00b209m-tgxx revision 1.3 march 2003 - 15 - mcp memory erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
kaa00b209m-tgxx revision 1.3 march 2003 - 16 - mcp memory samsung nand flash has two address pointer commands as a substitute for the most significant column address. ?00h? command sets the pointer to ?a? area(0~255word), and ?50h? command sets the pointer to ?b? area(256~263word). with these commands, the starting column address can be set to any of a whole page(0~263word). ?00h? or ?50h? is sustained until another address pointer com- mand is inputted. to program data starting from ?a? or ?b? area, ?00h? or ?50h? command must be inputted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 50h (2) command input sequence for programming ?b? area address / data input 80h 10h 50h 80h 10h address / data input only ?b? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?b? area(256~263), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b? area can be programmed. pointer operation table 2. destination of the pointer command pointer position area 00h 50h 0 ~ 255 word 256 ~ 263 word main array(a) spare array(b) "a" area 256 word (00h plane) "b" area (50h plane) 8 word "a" "b" internal page register pointer select command (00h, 50h) pointer figure 3. block diagram of pointer operation
kaa00b209m-tgxx revision 1.3 march 2003 - 17 - mcp memory system interface using ce don?t-care. ce we t wp t ch t cs start add.(3cycle) 80h data input ce cle ale we data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. start add.(3cycle) 00h ce cle ale we data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea ce re i/o 0 ~ 15 figure 4. program operation with ce don?t-care. figure 5. read operation with ce don?t-care. i/ox i/ox
kaa00b209m-tgxx revision 1.3 march 2003 - 18 - mcp memory ce we cle ale i/ox ao~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wp t ds t dh t alh command latch cycle ce we cle ale i/ox command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh a17~a24 a9~a16
kaa00b209m-tgxx revision 1.3 march 2003 - 19 - mcp memory input data latch cycle ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp sequential out cycle after read (cle=l, we =h, ale=l) re ce r/ b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* ? ? ? ? ? ? ? i/ox i/ox t rhz* t chz* t rp note : 1. transition is measured 200mv from steady state voltage with load. 2. this parameter is sampled and not 100% tested.
kaa00b209m-tgxx revision 1.3 march 2003 - 20 - mcp memory status read cycle ce we cle re i/ox 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls read1 operation (read one page) t rhz t chz ce n cle r/ b n i/ox we ale re busy a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar t r t rc t rhz t chz dout 264 t wc t rr ? ? ? t oh t oh n address 00h
kaa00b209m-tgxx revision 1.3 march 2003 - 21 - mcp memory read1 operation (intercepted by ce ) ce cle r/ b we ale re busy dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar t chz t r t rr t rc read2 operation (read one page) ce cle r/ b we ale re 50h dout dout 264 m address 256+m dout 256+m+1 selected row start address m 256 8 t ar t r t wb t rr a 0 ~a 2 are valid address & a 3 ~a 7 are "l" ? ? n address 00h i/ox i/ox col. add row add1 row add2 col. add row add1 row add2 t oh
kaa00b209m-tgxx revision 1.3 march 2003 - 22 - mcp memory page program operation ce cle r/ b we ale re 80h 70h i/o 0 din n din din 10h 264 n+1 sequential data input command column address page(row) address 1 up to 264 data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? n address i/ox col. add row add1 row add2 copy-back program operation ce cle r/ b we ale re 00h 70h i/o 0 8ah column address page(row) address program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc ? a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r busy ? i/ox col. add row add1 row add2
kaa00b209m-tgxx revision 1.3 march 2003 - 23 - mcp memory block erase operation (erase one block) ce cle r/ b we ale re 60h auto block erase erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc ? setup command i/ox a9~a16 a17~a24 manufacture & device id read operation ce cle we ale re 90h read id command maker code device code 00h t rea address. 1cycle t ar i/ox ech xx45h
kaa00b209m-tgxx revision 1.3 march 2003 - 24 - mcp memory device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command reg- ister along with three address cycles. once the command is latched, it does not need to be written for the following page read o pera- tion. two types of operations are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 264 words of data within the selected page are trans- ferred to the data registers in less than 10 m s(t r ). the system controller can detect the completion of this data transfer(tr) by analyz- ing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data starting from the selected column address up to the last column address[column 255/ 263 depending on the state of gnd input pin]. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of 256 ~263 words may be selectively accessed by writing the read2 command with gnd input pin low. addresses a 0~ a 2 set the starting address of the spare area while addresses a 3 ~a 7 must be low. the read1 command is needed to move the pointer back to the main area. figures6,7 show typical sequence and timings for each read operation. figure 6. read1 operation start add.(3cycle) 00h a 0 ~ a 7 & a 9 ~ a 24 data output(sequential) (00h command) data field spare field ce cle ale r/ b we re t r main array i/ox
kaa00b209m-tgxx revision 1.3 march 2003 - 25 - mcp memory figure 7. read2 operation 50h data output(sequential) spare field ce cle ale r/ b we start add.(3cycle) re t r a 0 ~ a 2 & a 9 ~ a 24 main array data field spare field a 3 ~ a 7 are "l" i/ox
kaa00b209m-tgxx revision 1.3 march 2003 - 26 - mcp memory page program the device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive words up to 264, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 256 words of data m ay be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the approp ri- ate cell. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the words other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write controller automatically executes the algorithms and timings necessary for program and veri fy, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the system controller can detect the completion of a program cycle by mon- itoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register. figure 8. program operation 80h r/ b address & data input i/o 0 pass 10h 70h fail t prog copy-back program the copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory. since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back is a sequential exec ution of page-read without burst-reading cycle and copying-program with the address of destination page. a normal read operation with "00h" command with the address of the source page moves the whole 264words data into the internal buffer. as soon as the flash returns to ready state, copy-back programming command "8ah" may be given with three address cycles of target page followed. the data stored in the internal buffer is then programmed directly into the memory cells of the destination page. once the copy-back pro- gram is finished, any additional partial page programming into the copied pages is prohibited before erase. since the memory arr ay is internally partitioned into two different planes, copy-back program is allowed only within the same memory plane. thus, a14, the plane address, of source and destination page address must be the same. figure 9. copy-back program operation 00h r/ b add.(3cycles) i/o 0 pass 8ah 70h fail t prog add.(3cycles) t r source address destination address i/ox i/ox
kaa00b209m-tgxx revision 1.3 march 2003 - 27 - mcp memory figure 10. block erase operation block erase the erase operation is done on a block basis. block address loading is accomplished in two cycles initiated by an erase setup co m- mand(60h). only address a 14 to a 24 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures th at memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 10 details the sequence. 60h block add. : a 9 ~ a 24 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 3 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. table3. read status register definition i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected i/o 8~15 not use don?t care i/ox
kaa00b209m-tgxx revision 1.3 march 2003 - 28 - mcp memory figure 11. read id operation ce cle ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code respectively. the command register remains in read id mode until further commands are issued to it. figure 11 shows the operation sequence. t whr figure 12. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. refer to figure 12 below. table4. device status after power-up after reset operation mode read 1 waiting for next command ffh r/ b t rst ech i/ox i/ox xx45h
kaa00b209m-tgxx revision 1.3 march 2003 - 29 - mcp memory ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart. its value can be det er- mined by the following guidance. vccqn r/ b n open drain output device gnd where i l is the sum of the input currents of all devices tied to the r/ b pin. rp rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp(min, 1.8v part) = vccq(max.) - v ol (max.) i ol + s i l = 1.9v 3ma + s i l busy ready vccqn vccqn-0.4v tf tr 0.4v figure 13. rp vs tr ,tf & rp vs ibusy t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43
kaa00b209m-tgxx revision 1.3 march 2003 - 30 - mcp memory the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.3v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 10 m s is required before internal circuit gets ready for any command sequences as shown in figure 14. the two step command sequence for program/erase provides additional software protection. figure 14. ac waveforms for power transition v cc wp high ? ? ~ 1.5v we data protection & power up sequence ~ 1.5v 10 m s ? ?
kaa00b209m-tgxx revision 1.3 march 2003 - 31 - mcp memory 32mb(2m x 16) u t ram
kaa00b209m-tgxx revision 1.3 march 2003 - 32 - mcp memory absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v dd +0.3v v voltage on v dd supply relative to vss v dd -0.2 to 3.6v v voltage on v ddq supply relative to vss v ddq -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -25 to 85 c functional description 1. x means don t care.(must be low or high state) cs zz oe we lb ub i/o 1~8 i/o 9~16 mode power h h x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected deep power down l h x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active
kaa00b209m-tgxx revision 1.3 march 2003 - 33 - mcp memory zz =v il cs =v ih zz =v il cs =v il , ub or/and lb =v il zz =v ih cs =v ih , zz =v ih standby mode state machines power on initial state (wait 200 m s) active standby mode deep power down mode standby mode characteristic power mode memory cell data standby current( m m a) wait time( m m s) standby valid 100 0 deep power down invaild 10 200 zz =v ih cs =v ih and zz =v ih recommended dc operating conditions 1) 1. t a =-25 to 85 c, otherwise specified. 2. overshoot: v ddq +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit power supply voltage v dd 2.7 2.9 3.1 v i/o power supply voltage v ddq 1.7 1.85 2.0 v ground vss 0 0 0 v input high voltage v ih 1.5 - v ddq +0.2 2) v input low voltage v il -0.2 3) - 0.4 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics 1. typical values are tested at v dd =2.9v, t a =25 c and not guaranteed. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to v dd -1 - 1 m a output leakage current i lo cs =v ih, zz =v ih , oe =v ih or we =v il , v io =vss to v ddq -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, zz 3 v ddq -0.2v, v in 0.2v or v in 3 v ddq -0.2v - 4 7 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs =v il , zz =v ih, vin=v il or v ih - 30 35 ma output low voltage v ol i ol =2.1ma - - 0.2 v output high voltage v oh i oh =-1.0ma 1.5 - - v standby current(cmos) i sb1 cs 3 v ddq -0.2v, zz 3 v ddq -0.2v, other inputs=vss to v ddq - 80 100 m a deep power down i sbd zz 0.2v, other inputs=vss to v ddq - 5 10 m a
kaa00b209m-tgxx revision 1.3 march 2003 - 34 - mcp memory ac characteristics (v dd =2.7~3.1v, v ddq =1.7~2.0v, t a =-25 to 85 c) 1. t wp (min)=90ns for continuous write operation over 80 times.(only in case of we controlled write operation) parameter list symbol speed bins units 90ns 100ns min max min max read read cycle time t rc 90 - 100 - ns address access time t aa - 90 - 100 ns chip select to output t co - 90 - 100 ns output enable to valid output t oe - 45 - 50 ns ub , lb access time t ba - 90 - 100 ns chip select to low-z output t lz 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 25 0 25 ns ub , lb disable to high-z output t bhz 0 25 0 25 ns output disable to high-z output t ohz 0 25 0 25 ns output hold from address change t oh 5 - 5 - ns write write cycle time t wc 90 - 100 - ns chip select to end of write t cw 80 - 90 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 80 - 90 - ns ub , lb valid to end of write t bw 80 - 90 - ns write pulse width t wp 70 1) - 80 1) - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 30 0 35 ns data to write time overlap t dw 40 - 45 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to v ddq -0.2v input rising and falling time: 5ns input and output reference voltage: v ddq /2 output load: c l =50pf
kaa00b209m-tgxx revision 1.3 march 2003 - 35 - mcp memory address data out previous data valid data valid u t ram timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , zz = we= v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( zz = we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. the minimum read cycle( t rc ) is determined later one of the t rc1 and t rc2. 4. t oe (max) is met only when oe becomes enable after t aa (max). data valid high-z t rc1 t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t rc2 t co address cs ub , lb oe data out
kaa00b209m-tgxx revision 1.3 march 2003 - 36 - mcp memory t as(3) timing waveform of write cycle(1) ( we controlled , zz =v ih ) timing waveform of write cycle(2) ( cs controlled , zz =v ih ) address data undefined ub , lb we data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) cs t wr(4)
kaa00b209m-tgxx revision 1.3 march 2003 - 37 - mcp memory timing waveform of write cycle(3) ( ub , lb controlled , zz =v ih ) (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs timing waveform of deep power down mode (deep power down mode) 1. when you toggle zz pin low, the device gets into the deep power down mode after 0.5 m s suspend period. 2. to return to normal operation, the device needs wake up period. 3. wake up sequence is just the same as power up sequence shown in next page 37. zz mode deep power down mode normal operation 0.5 m s 200 m s normal operation read operation twice or stay high during 300 m s suspend wake up cs ? ?
kaa00b209m-tgxx revision 1.3 march 2003 - 38 - mcp memory 200 m s read operation twice vcc zz cs timing waveform of power up(1) 200 m s timing waveform of power up(2) (no dummy cycle) 300 m s ? ? ? (power up(1)) 1. after v dd reaches v dd (min.) following power application, wait 200 m s with cs high and then toggle cs low and commit read operation at least twice. then you get into the normal operation. 2. read operation should be executed by toggling cs pin low. 3. the read operation must satisfy the spec. described on page 34 (read cycle (1), (2)). 4. zz pin should be kept high during whole power up sequence. (power up(2)) 1. after v dd reaches v dd (min.) following power application, wait 200 m s and wait another 300 m s with cs high if you don?t want to commit dummy read cycle. after total 500 m s wait, toggle cs low, then you get into the normal mode. 2. zz pin should be kept high during whole power up sequence. vcc (min) ? ? vccq ? vccq (min) vcc zz cs vcc (min) vccq vccq (min)
kaa00b209m-tgxx revision 1.3 march 2003 - 39 - mcp memory technical note u t ram usage and timing introduction u t ram is based on single-transistor dram cells. as with any other dram, the data in these cells must be periodically refreshed to prevent data loss. what makes the u t ram unique is that it offers a true sram style interface that hides all refresh operations from the memory controller. start with a dram technology the key point of u t ram is its high speed and low power. this high speed comes from the use of many small blocks such as 32kbits each to create u t ram arrays. the small blocks have short word lines thus with little capacitance eliminating a major factor of operating current dissipation in conventional dram blocks. each independent macro-cell on a u t ram device consists of a number of these blocks. each chip has one or more macro. the address decoding logic is also fast. u t ram performs a complete read operation in every trc, but u t ram needs power up sequence like dram. power up sequence and diagram 1. apply power. 2. maintain stable power for a minium 200 m s with cs u=high. 3. issue read operation at least 2 times. design achieves sram specific operations the u t ram was designed to work just like an sram - without any waits or other overhead for precharging or refreshing its internal dram cells. samsung electronics(samsung) hides these operations inside with advanced design technology - those are not to be seen from outside. precharging takes place during every access, overlapped between the end of the cycle and the decoding portion of the next cycle. hiding refresh is more difficult. every row in every block must be refreshed at least once during the refresh interval to prevent data loss. samsung provides an internal refresh controller for devices. when all accesses within refresh interval are directed to one macro-cell, as can happen in signal processing applica- tions, a more sophisticated approach is required to hide refresh. the pseudo sram is sometimes used on these appli- cations, which requires a memory controller that can hold off accesses when a refresh operation is needed. samsung?s unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power con- sumption) is that the u t ram never need to hold off accesses, and indeed it has no hold off signal. the circuitry that gives samsung this advantage is fairly simple but has not previ- ously been disclosed. avoid timing following figures show you an abnormal timing which is not supported on u t ram and its solution. if your system has a timing which sustains invalid states over 4 m s at read mode like figure 18, there are some guide lines for proper operation of u t ram. when your system has multiple invalid address signals shorter than trc on the timing shown in figure 1, u t ram needs a nor- mal read timing(trc) during that cycle(figure 19) or needs to toggle cs once to ?high? for about ?trc?(figure 20). cs u=v il , ub u or/and lb u=v il zz u=v ih read operation(2 times) power on initial state (wait 200 m s) active cs u=v ih cs u we address less than trc over 4 m s cs u we address trc over 4 m s figure 19. put on read operation every 4 m s figure 18.
kaa00b209m-tgxx revision 1.3 march 2003 - 40 - mcp memory figure 20. cs u we address over 4 m s trc toggle cs u to high every 4 m s cs u we address twp over 4 m s twc write operation has similar restriction to read operation. if your system has a timing which sustains invalid states over 4 m s at write mode and has continuous write signals with length of min. twc over 4 m s like figure 21, you must toggle we once to high figure 5. figure 21. cs we address twp over 4 m s twc trc figure 22. cs u we address twp over 4 m s twc trc and make it stay high at least for trc every 4 m s or toggle cs once to high for about trc. toggle cs u to high every 4 m s toggle we to high and make it stay high at least for trc every 4 m s
kaa00b209m-tgxx revision 1.3 march 2003 - 41 - mcp memory 128mb(8m x 16) mobile sdram
kaa00b209m-tgxx revision 1.3 march 2003 - 42 - mcp memory dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 c ~ 85 c) notes : 1. vih (max) = 2.2v ac.the overshoot voltage duration is 3ns. 2. vil (min) = -1.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v vout vddq. parameter symbol min typ max unit note supply voltage v dd 1.65 1.8 1.95 v v ddq 1.65 1.8 1.95 v input logic high voltage v ih 0.8 x v ddq 1.8 v ddq + 0.3 v 1 input logic low voltage v il -0.3 0 0.3 v 2 output logic high voltage v oh v ddq - 0.2 - - v i oh = -2ma output logic low voltage v ol - - 0.2 v i ol = 2ma input leakage current i li -10 - 10 ua 3 capacitance (v dd = 1.8v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 2.0 4.0 pf ras , cas , we , cs , cke, dqm c in 2.0 4.0 pf address c add 2.0 4.0 pf dq 0 ~ dq 15 c out 3.5 6.0 pf absolute maximum ratings notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 2.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 2.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma
kaa00b209m-tgxx revision 1.3 march 2003 - 43 - mcp memory dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c) notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. internal tcsr support . 4. unless otherwise noted, input swing ievei is cmos(vih /vil=vddq/vssq). parameter symbol test condition version unit note -il -15 operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 35 30 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 0.3 ma i cc2 ps cke & clk v il (max), t cc = 0.3 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 5.5 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 1 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 1.5 ma i cc3 ps cke & clk v il (max), t cc = 1 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 12 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 6 ma operating current (burst mode) i cc 4 i o = 0 ma page burst 4banks activated t ccd = 2clks 50 40 ma 1 refresh current i cc 5 t rc 3 t rc (min) 85 75 ma 2 self refresh current i cc 6 cke 0.2v internal tcsr range max 40 c max 85 c c 3 4 banks 160 300 ua 2 banks 140 200 1 bank 130 150
kaa00b209m-tgxx revision 1.3 march 2003 - 44 - mcp memory vddq 13.9k w 10.6k w output 30pf v oh (dc) = v ddq -0.2v , ioh = -0.1ma v ol (dc) = 0.2v, iol = 0.1ma vtt=0.5 x vddq 50 w output 30pf z0=50 w figure 2. ac output load circuit figure 1. dc output load circuit ac operating test conditions (v dd = 1.8v + 0.15v, t a = -25 to 85 c) parameter value unit ac input levels (vih/vil) 0.9 x v ddq / 0.2 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see figure 2
kaa00b209m-tgxx revision 1.3 march 2003 - 45 - mcp memory operating ac parameter (ac operating conditions unless otherwise noted) notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. minimum trdl=2clk and tdal(= trdl + trp) is required to complete both of last data write command(trdl) and precharge command (trp). 4. all parts allow every cycle column address change. 5. in case of row precharge interrupt, auto precharge and read burst stop. parameter symbol version unit note -il -15 row active to row active delay t rrd (min) 19 30 ns 1 ras to cas delay t rcd (min) 28.5 30 ns 1 row precharge time t rp (min) 28.5 30 ns 1 row active time t ras (min) 60 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 88.5 90 ns 1 last data in to row precharge t rdl (min) 2 clk 2,3 last data in to active delay t dal (min) trdl + trp - 3 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 auto refresh cycle time t arfc (min) 105 ns exit self refresh to write command t srfx (min) 120 ns col. address to col. address delay t ccd (min) 1 clk 4 number of valid output data cas latency=3 2 ea 5 number of valid output data cas latency=2 1
kaa00b209m-tgxx revision 1.3 march 2003 - 46 - mcp memory ac characteristics (ac operating conditions unless otherwise noted) notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. parameter symbol -1l -15 unit note min max min max clk cycle time cas latency=3 t cc 9.5 1000 15 1000 ns 1 cas latency=2 15 15 clk to valid output delay cas latency=3 t sac 7 9 ns 1,2 cas latency=2 8 9 output data hold time cas latency=3 t oh 2.5 2.5 ns 2 cas latency=2 2.5 2.5 clk high pulse width t ch 3.5 3.5 ns 3 clk low pulse width t cl 3.5 3.5 ns 3 input setup time t ss 3.0 4.0 ns 3 input hold time t sh 1.5 2.0 ns 3 clk to output in low-z t slz 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 7 9 ns cas latency=2 8 9
kaa00b209m-tgxx revision 1.3 march 2003 - 47 - mcp memory simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a11 & ba0 ~ ba1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba1 : bank select addresses. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data-in at that same clk in write operation (write dqm latency is 0), but in read operation, it makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba 0,1 a10/ap a11, a9 ~ a0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a0~a8) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a0~a8) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h
kaa00b209m-tgxx revision 1.3 march 2003 - 48 - mcp memory normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 reserved 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 reserved mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for nor- mal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved full page length : 512(x16) register programmed with normal mrs address ba0 ~ ba1 *1 a11 ~ a10/ ap a9 *2 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu w.b.l test mode cas latency bt burst length a. mode register field table to program modes register programmed with extended mrs address ba1 ba0 a11 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function mode select rfu ds rfu pasr notes: 1.rfu(reserved for future use) should stay "0" during mrs cycle. 2.if a9 is high during mrs cycle, "burst read single bit write" function will be enabled. 3.mobile sdram supports pasr of all banks, 1/2 of all banks and 1/4 of all banks. mode select driver strength pasr *3 ba1 ba0 mode a6 a5 driver strength a2 a1 a0 # of banks 0 0 normal mrs 0 0 full 0 0 0 4 banks 0 1 reserved 0 1 1/2 0 0 1 2 banks 1 0 emrs for mobile sdram 1 0 reserved 0 1 0 1 bank 1 1 reserved 1 1 reserved 0 1 1 reserved reserved address 1 0 0 reserved a11~a10/ap a9 a8 a7 a4 a3 1 0 1 reserved 0 0 0 0 0 0 1 1 0 reserved 1 1 1 reserved emrs for pasr(partial array self ref.) & ds(driver strength)
kaa00b209m-tgxx revision 1.3 march 2003 - 49 - mcp memory the dpd pin controls dpd(power off) mode. when you toggle dpd pin low, the device gets into the deep power down mode. and the dpd pin should be kept high during normal operation. after dpd(power off) mode, all operation are in non-active and all data are volatilized. and all pins except for dpd pin are in hi-z during dpd mode. after dpd mode exit, power up sequence should be asserted again and 200us waiting time is required before pre- charging all banks command. after precharging all banks, cbr auto refresh command, mode register set command and extended mode register set command should be asserted. b. deep power down mode by external pin 1. in order to save power consumption, mobile sdram has pasr option. 2. mobile sdram supports 3 kinds of pasr in self refresh mode : 4 banks, 2 banks and 1 bank. ba1=0 - 4 banks - 2 banks - 1 bank partial self refresh area 1. in order to save power consumption, mobile dram has internal tcsr option. 2. mobile dram supports 2 kinds of tcsr range by internal temperature sensor. temperature range self refresh current (icc6) unit 4 banks 2 banks 1 bank max 40 c 160 140 130 ua max 85 c 300 200 150 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=1 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 partial array self refresh internal temperature compensated self refresh
kaa00b209m-tgxx revision 1.3 march 2003 - 50 - mcp memory 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to define ds or pasr operating type of the device after normal mrs. emrs cycle is not mandatory and the emrs command needs to be issued only when ds or tcsr is used . the default state without emrs command issued is the full driver strength, all 4 banks refreshed. the device is now ready for the operation selected by emrs. for operating with ds or pasr, set ds or pasr mode in emrs setting stage. in order to adjust another mode in the state of ds or pasr mode, additional emrs set is required but power up sequence is not needed again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. c. power up sequence for mobile sdram d. burst sequence 1. burst length = 4 initial address sequential interleave a1 a0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. burst length = 8 initial address sequential interleave a2 a1 a0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
kaa00b209m-tgxx revision 1.3 march 2003 - 51 - mcp memory bank addresses (ba0 ~ ba1) this sdram is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. the ba0 ~ ba1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba0 ~ ba1 are latched at bank active, read, write, mode register set and precharge operations. address inputs (a0 ~ a11) the 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (a0 ~ a11). the 12 bit row addresses are latched along with ras and ba0 ~ ba1 during bank activate command. the 9 bit column addresses are latched along with cas , we and ba0 ~ ba1 during read or write command. clock (clk) the clock input is used as the reference for all sdram opera- tions. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in a valid state (low or high) for the duration of set- up and hold time around positive edge of the clock in order to function well q perform and icc specifications. clock enable (cke) the clock enable(cke) gates the clock onto sdram. if cke goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro- zen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when all banks are in the idle state and cke goes low synchronously with clock, the sdram enters the power down mode from the next clock cycle. the sdram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is syn- chronous as the internal clock is suspended. when cke goes high at least "1clk + tss" before the high going edge of the clock, then the sdram becomes active from the same clock edge accepting all the input commands. e. device operations addresses of 128mb nop and device deselect when ras , cas and we are high, the sdram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , we and all the address inputs are ignored. dqm operation the dqm is used to mask input and output operations. it works similar to oe during read operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock. the dqm signal is important during burst interruptions of write with read or precharge in the sdram. due to asynchronous nature of the internal write, the dqm operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. please refer to dqm timing diagram also. mode register set (mrs) the mode register stores the data for controlling the various operating modes of sdram. it programs the cas latency, burst type, burst length, test mode and various vendor specific options to make sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sdram. the mode register is written by asserting low on cs , ras , cas and we (the sdram should be in active mode with cke already high prior to writing the mode register). the state of address pins a0 ~ an and ba0 ~ ba1 in the same cycle as cs , ras , cas and we going low is the data written in the mode reg- ister. two clock cycles is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on the fields of functions. the burst length field uses a0 ~ a2, burst type uses a3, cas latency (read latency from column address) use a4 ~ a6, vendor specific options or test mode use a7 ~ a8, a10/ap ~ an and ba0 ~ ba1. the write burst length is programmed using a9. a7 ~ a8, a10/ap ~ an and ba0 ~ ba1 must be set to low for normal sdram operation. refer to the table for specific codes for various burst length, burst type and cas latencies.
kaa00b209m-tgxx revision 1.3 march 2003 - 52 - mcp memory extended mode register set (emrs) the extended mode register stores the data for selecting driver strength, partial self refresh or temperature compensated self refresh. emrs cycle is not mandatory and the emrs command needs to be issued only when ds or pasr is used . the default state without emrs command issued is the full driver strength, and all 4 banks refreshed. the extended mode register is writ- ten by asserting low on cs , ras , cas , we and high on ba1 ,low on ba0(the sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a11 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register con- tents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 - a2 are used for partial self refresh , a5 - a6 are used for driver strength, "low" on ba1 and "high" on ba0 are used for emrs. all the other address pins except a0 ~ a2, a5 ~ a6, ba1, ba0 must be set to low for proper emrs operation. refer to the table for specific codes. bank activate. the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank address, a row access is initiated. the read or write opera- tion can occur after a time delay of t rcd (min) from the time of bank activation. t rcd is an internal timing parameter of sdram, therefore it is dependent on operating clock frequency. the mini- mum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding off the result to the next higher integer. the sdram has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. also the noise generated during sensing of each bank of sdram is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different bank. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min). every sdram bank activate command must satisfy t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on con- secutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read com- mand is issued. the first output appears in cas latency number of clock cycles after the issue of burst read command. the burst length, burst sequence and latency from the burst read command is determined by the mode register which is already pro- grammed. the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in the mode register. the output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data out- put gapless. the burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid at every page burst length. e. device operations (continued)
kaa00b209m-tgxx revision 1.3 march 2003 - 53 - mcp memory e. device operations (continued) burst write the burst write command is similar to burst read command and is used to write data into the sdram on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid column address, a write burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing can be com- pleted yet. the writing can be completed by issuing a burst read and dqm for blocking data inputs or burst write in the same or another active bank. the burst stop command is valid at every burst length. the write burst can also be terminated by using dqm for blocking data and procreating the bank t rdl after the last data input to be written into the active row. see dqm operation also. all banks precharge all banks can be precharged at the same time by using pre- charge all command. asserting low on cs , ras , and we with high on a10/ap after all banks have satisfied t ras (min) require- ment, performs precharge on all banks. at the end of t rp after performing precharge to all the banks, all banks are in idle state. precharge the precharge operation is performed on an active bank by asserting low on cs , ras , we and a10/ap with valid ba0 ~ ba1 of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank active command in the desired bank. t rp is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t rp with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set etc. is possible only when all banks are in idle state. auto precharge the precharge operation can also be performed by using auto precharge. the sdram internally generates the timing to satisfy t ras (min) and "t rp " for the programmed burst length and cas latency. the auto precharge command is issued at the same time as burst read or burst write by asserting high on a10/ap. if burst read or burst write by asserting high on a10/ap, the bank is left active until a new command is asserted. once auto pre- charge command is given, no new commands are possible to that particular bank until the bank achieves idle state. auto refresh the storage cells of 64mb, 128mb and 256mb sdram need to be refreshed every 64ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the inter- nal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to com- plete the auto refresh operation is specified by t rc (min). the min- imum number of clock cycles required can be calculated by driving t rc with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop's until the auto refresh operation is completed. all banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sdram is being used for normal data transactions. the 64mb and 128mb sdram?s auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. the 256mb and 512mb sdram?s auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms. self refresh the self refresh is another refresh mode available in the sdram. the self refresh is the preferred refresh mode for data retention and low power operation of sdram. in self refresh mode, the sdram disables the internal clock and all the input buffers except cke. the refresh addressing and timing are inter- nally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low mat- ters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop's for a minimum time of tsrfc before the sdram reaches idle state to begin normal operation. in case that the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycles for 256mb and 512mb, and burst 4096 auto refresh cycles for 128mb and 64mb immediately before entering self refresh mode and after exiting in self refresh mode. on the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle.
kaa00b209m-tgxx revision 1.3 march 2003 - 54 - mcp memory d hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z *note : 1. cke to clk disable/enable = 1clk. 2. dqm makes data out hi-z after 2clks which should masked by cke " l" 3. dqm masks both data-in and data-out. e. basic feature and function descriptions 1. clock suspend 2. dqm operation 1) clock suspended during write clk cmd cke internal clk dq(cl2) dq(cl3) wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 not written suspended dout 2) clock suspended during read (bl=4) clk cmd cke internal clk dq(cl2) dq(cl3) rd masked by cke q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 masked by cke 1) write mask (bl=4) 2) read mask (bl=4) clk cmd dqm dq(cl2) dq(cl3) clk cmd dqm dq(cl2) dq(cl3) wr masked by cke masked by cke d 0 d 1 d 3 d 0 d 1 d 3 rd q 0 q 2 q 3 q 1 q 2 q 3 dqm to data-in mask = 0 dqm to data-out mask = 2 3) dqm with clock suspended (full page read) *2 clk cmd cke dqm dq(cl2) dq(cl3) rd q 0 q 2 q 4 q 6 q 7 q 8 q 1 q 3 q 6 q 7 q 5
kaa00b209m-tgxx revision 1.3 march 2003 - 55 - mcp memory tccd *2 tccd *2 tcdl *3 tccd *2 tcdl *3 *note: 1. by " interrupt", it is meant to stop burst read/write by external command before the end of burst. by " cas interrupt", to stop burst read/write by cas access ; read and write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (=1clk) dq(cl2) dq(cl3) 3. cas interrupt (i) 1) read interrupted by read (bl=4) *1 2) write interrupted by write (bl=2) clk cmd add rd rd a b 3) write interrupted by read (bl=2) qa 0 qb 0 qb 1 qb 1 qb 3 qa 0 qb 0 qb 1 qb 1 qb 3 clk cmd add dq wr wr a b da 0 db 0 db 1 clk cmd add dq(cl2) dq(cl3) wr rd a b da 0 qb 0 qb 1 da 0 qb 0 qb 1
kaa00b209m-tgxx revision 1.3 march 2003 - 56 - mcp memory *note: 1. to prevent bus contention, there should be at least one gap between data in and data out. hi-z hi-z *1 hi-z hi-z *1 hi-z 4. cas interrupt (ii) : read interrupted by write & dqm ii) cmd dqm (a) cl=2, bl=4 i) cmd dq clk dqm dq iii) cmd dqm dq iv) cmd dqm dq (b) cl=3, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq v) cmd dq dqm rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr q 0 d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 rd wr d 0 d 1 d 2 d 3 q 0
kaa00b209m-tgxx revision 1.3 march 2003 - 57 - mcp memory trdl =2clk tdal =trdl + trp *4 *note: 1. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. 2. to inhibit invalid write, dqm should be issued. 3. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only a nother bank pre- charge of four banks operation. trdl *1 1 2 *note: 1. samsung can support trdl=1clk and trdl=2clk for all memory devices. samsung recommends trdl=2 clk. 2. number of valid output data after row precharge : 1, 2 for cas latency = 2, 3 respectively. 3. the row active command of the precharge bank can be issued after trp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same bank is illegal 4. tdal defined last data in to active delay. samsung can support tdal=trdl+ trp . auto precharge starts *3 *2 *3 *2 5. write interrupted by precharge & dqm 6. precharge 7. auto precharge 1) trdl = 2clk cmd dq clk dqm wr pre d 0 d 1 d 2 masked by dqm 1) normal write cmd dq clk bl=4 & trdl=2clk d 0 d 1 d 2 d 3 wr pre 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 1) normal write (bl=4) clk cmd dq wr auto precharge starts@trdl=2clk *3 d 0 d 1 d 2 d 3 act 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3
kaa00b209m-tgxx revision 1.3 march 2003 - 58 - mcp memory *note: 1. samsung can support trdl=1clk and trdl=2clk for all memory devices. samsung recommends trdl=2 clk. 2. tbdl : 1 clk ; last data in to burst stop delay. read or write burst stop command is valid at every burst length. 3. number of valid output data after row precharge or burst stop : 1, 2 for cas latency= 2, 3 respectively. 4. pre : all banks precharge is necessary. mrs can be issued only at all banks precharge state. 1 2 1 2 *4 trp 2clk trdl *1 tbdl *2 8. burst stop & interrupted by precharge 9. mrs 1) normal write d 0 d 1 d 2 2) write burst stop (bl=8) cmd dq clk dqm bl=4 & trdl=2clk wr pre clk cmd dqm dq wr stop d 0 d 1 d 2 d 3 3) read interrupted by precharge (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 0 q 1 4) read burst stop (bl=4) clk cmd dq(cl2) dq(cl3) rd stop q 0 q 1 q 0 q 1 1) mode register set clk cmd pre mrs act
kaa00b209m-tgxx revision 1.3 march 2003 - 59 - mcp memory tss *1 tss *2 10. clock suspend exit & power down exit 1) clock suspend (=active power down) exit 2) power down (=precharge power down) exit clk cke internal clk cmd rd clk cke internal clk cmd nop act auto refresh command pre t rp t arfc(min) = 105ns auto cke = high refresh cmd an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(clk). all banks must be precharged and idle for t rp (min) before the auto refresh command is applied. no control of the external address pins is required once this cycle has started because of the internal address counter. when the refresh cycle has comple ted, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t arfc (min). ~ ~ ~ ~ ~ ~ clk a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. after 1 clock cycle from th e self refresh command, all of the external control signals including system clock(clk) can be disabled except cke. the clock is inter nally disabled during self refresh operation to reduce power. to exit the self refresh mode, supply stable clock input before returnin g cke high, assert deselect or nop command and then assert cke high. in case that the system uses burst auto refresh during normal opreation, it is recommended to use burst 4096 auto refresh cycle immediately before entering self refresh mode and after exitin g in self refresh mode. on the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle. self refresh command cke stable clock t ss nop self refresh clk t srfx(min) = 120ns t ss ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ act 11. auto refresh & self refresh
kaa00b209m-tgxx revision 1.3 march 2003 - 60 - mcp memory 12. about burst type control basic mode sequential counting at mrs a 3 = "0". see the burst sequence table. (bl=4, 8) bl=1, 2, 4, 8 and full page. interleave counting at mrs a 3 = "1". see the burst sequence table. (bl=4, 8) bl=4, 8. at bl=1, 2 interleave counting = sequential counting. random mode random column access t ccd = 1 clk every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of conventional dram. 13. about burst length control basic mode 1 at mrs a 2,1,0 = "000". at auto precharge, t ras should not be violated. 2 at mrs a 2,1,0 = "001". at auto precharge, t ras should not be violated. 4 at mrs a 2,1,0 = "010". 8 at mrs a 2,1,0 = "011". full page at mrs a 2,1,0 = "111". wrap around mode(infinite burst length) should be stopped by burst stop. ras interrupt or cas interrupt. special mode brsw at mrs a 9 = "1". read burst =1, 2, 4, 8, full page write burst =1. at auto precharge of write, t ras should not be violated. random mode burst stop t bdl = 1, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively using burst stop command, any burst length control is possible. interrupt mode ras interrupt (interrupted by precharge) before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl = 2 with dqm, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively. during read/write burst with auto precharge, ras interrupt can not be issued. cas interrupt before the end of burst, new read/write stops read/write burst and starts new read/write burst. during read/write burst with auto precharge, cas interrupt can not be issued.
kaa00b209m-tgxx revision 1.3 march 2003 - 61 - mcp memory function truth table (table 1) current state cs ras cas we ba address action note idle h x x x x x nop l h h h x x nop l h h l x x illegal 2 l h l x ba ca, a 10 /ap illegal 2 l l h h ba ra row (& bank) active ; latch ra l l h l ba a 10 /ap nop 4 l l l h x x auto refresh or self refresh 5 l l l l op code op code mode register access 5 row active h x x x x x nop l h h h x x nop l h h l x x illegal 2 l h l h ba ca, a 10 /ap begin read ; latch ca ; determine ap l h l l ba ca, a 10 /ap begin read ; latch ca ; determine ap l l h h ba ra illegal 2 l l h l ba a 10 /ap precharge l l l x x x illegal read h x x x x x nop (continue burst to end --> row active) l h h h x x nop (continue burst to end --> row active) l h h l x x term burst --> row active l h l h ba ca, a 10 /ap term burst, new read, determine ap l h l l ba ca, a 10 /ap term burst, new write, determine ap 3 l l h h ba ra illegal 2 l l h l ba a 10 /ap term burst, precharge timing for reads l l l x x x illegal write h x x x x x nop (continue burst to end --> row active) l h h h x x nop (continue burst to end --> row active) l h h l x x term burst --> row active l h l h ba ca, a 10 /ap term burst, new read, determine ap 3 l h l l ba ca, a 10 /ap term burst, new write, determine ap 3 l l h h ba ra illegal 2 l l h l ba a 10 /ap term burst, precharge timing for writes 3 l l l x x x illegal read with auto precharge h x x x x x nop (continue burst to end --> precharge) l h h h x x nop (continue burst to end --> precharge) l h h l x x illegal l h l x ba ca, a 10 /ap illegal l l h x ba ra, ra 10 illegal 2 l l l x x x illegal write with auto precharge h x x x x x nop (continue burst to end --> precharge) l h h h x x nop (continue burst to end --> precharge) l h h l x x illegal l h l x ba ca, a 10 /ap illegal l l h x ba ra, ra 10 illegal 2 l l l x x x illegal
kaa00b209m-tgxx revision 1.3 march 2003 - 62 - mcp memory *note: 1. all entries assume the cke was active (high) during the precharge clock and the current clock cycle. 2. illegal to bank in specified state ; function may be iegal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba (and a 10 /ap). 5. illegal if any bank is not idle. abbreviations : ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge function truth table (table 1) current cs ras cas we ba address action note precharging h x x x x x nop --> idle after t rp l h h h x x nop --> idle after t rp l h h l x x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a 10 /ap nop --> idle after t rp 4 row activating l l l x x x illegal h x x x x x nop --> row active after t rcd l h h h x x nop --> row active after t rcd l h h l x x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a 10 /ap illegal 2 l l l x x x illegal refreshing h x x x x x nop --> idle after t rc l h h x x x nop --> idle after t rc l h l x x x illegal l l h x x x illegal l l l x x x illegal mode register accessing h x x x x x nop --> idle after 2 clocks l h h h x x nop --> idle after 2 clocks l h h l x x illegal l h l x x x illegal l l x x x x illegal
kaa00b209m-tgxx revision 1.3 march 2003 - 63 - mcp memory function truth table (table 2) current state cke (n-1) cke n cs ras cas we address action note self refresh h x x x x x x exit self refresh --> idle after ts rfx (abi) l h h x x x x exit self refresh --> idle after ts rfx (abi) 6 l h l h h h x exit self refresh --> idle after ts rfx (abi) 6 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self refresh) all banks precharge power down h x x x x x x invalid l h h x x x x exit power down --> abi l h l h h h x exit power down --> abi 7 l h l h h l x illegal 7 l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain low power mode) all banks idle h h x x x x x refer to table 1 h l h x x x x enter power down h l l h h h x enter power down 8 h l l h h l x illegal 8 h l l h l x x illegal h l l l h h ra row (& bank) active h l l l l h x enter self refresh 8 h l l l l l op code mode register access l l x x x x x nop any state other than listed above h h x x x x x refer to operations in table 1 h l x x x x x begin clock suspend next cycle 9 l h x x x x x exit clock suspend next cycle 9 l l x x x x x maintain clock suspend *note: 6. cke low to high transition is asynchronous. 7. cke low to high transition is asynchronous if restarts internal clock. a minimum setup time 1clk + t ss must be satisfied before any command other than exit. 8. power down and self refresh can be entered only from the all banks idle state. 9. must be a legal command. abbreviations : abi = all banks idle, ra = row address
kaa00b209m-tgxx revision 1.3 march 2003 - 64 - mcp memory power up sequence single bit read - write - read cycle(same page) @cas latency=3, burst length=1 read & write cycle at same bank @burst length=4, trdl=2clk page read & write cycle at same bank @burst length=4 , trdl=2clk page read cycle at different bank @burst length=4 page write cycle at different bank @burst length=4, trdl=2clk read & write cycle at different bank @burst length=4 read & write cycle with auto precharge l @burst length=4 read & write cycle with auto precharge ll @burst length=4 clock suspension & dqm operation cycle @cas letency=2, burst length=4 read interrupted by precharge command & read burst stop cycle @ full page burst write interrupted by precharge command & write burst stop cycle @ full page burst, trdl=2clk burst read single bit write cycle @burst length =2 active/precharge power dower down mode @cas latency=2 burst length=4 self refresh entry & exit cycle & exit cycle mode register set cycle and auto refresh cycle extended mode register set cycle
kaa00b209m-tgxx revision 1.3 march 2003 - 65 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 high level is necessary cke cs ras cas addr ba0 ba1 dq a10/ap we power up sequence for mobile sdram dqm precharge t rp 16 17 18 19 20 21 22 24 23 25 ? ? ? ? key raa hi-z hi-z t arfc t arfc (all bank) auto refresh auto refresh normal mrs extended mrs row active (a-bank) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? *note: 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply v dd before or at the same time as v ddq . 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to define ds or pasr operating type of the device after normal mrs. emrs cycle is not mandatory and the emrs command needs to be issued only when ds, pasr or tcsr is used . the default state without emrs command issued is the full driver strength, all 4 banks refreshed. the device is now ready for the operation selected by emrs. for operating with ds or pasr, set ds or pasr mode in emrs setting stage. in order to adjust another mode in the state of ds or pasr mode, additional emrs set is required but power up sequence is not ne eded again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. : don?t care key clock hi ? ? ? ? ? ? ? ? raa ? ? ? ? ? ? ? ? ?
kaa00b209m-tgxx revision 1.3 march 2003 - 66 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba0,ba1 a10/ap we addr dqm : don?t care clock single bit read-write-read cycle(same page) @cas latency=3, burst length=1 high ra ca bs bs ra dq row active read write read row active precharge t cc t ch t cl t ras t rc t sh t ss *note 1 t rcd t rp t sh t ss t sh t ss t sh t ss *note 2 *note 2,3 *note 2,3 *note 2,3 *note 4 *note 2 *note 3 *note 3 *note 3 *note 4 t ss t sh t oh t slz t sac t sh t ss t sh t ss *note: 1. all input except cke & dqm can be don't care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba0,ba1. cb cc rb bs bs bs bs qa db qc rb
kaa00b209m-tgxx revision 1.3 march 2003 - 67 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle at same bank @burst length=4, trdl=2clk high ra ca ra cl=2 row active read write precharge t rc *note 1 t shz t sac t oh *note: 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clcok. 3. ouput will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst) ba0 dqm dq t rdl *note 2 *note 4 t shz t sac t oh t rdl *note 4 (a-bank) (a-bank) (a-bank) (a-bank) row active (a-bank) precharge (a-bank) { t rcd qa1 db0 qa0 qa2 db1 db2 db3 qa3 qa1 db0 qa0 qa2 db1 db2 db3 qa3 rb rb cb
kaa00b209m-tgxx revision 1.3 march 2003 - 68 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock page read & write cycle at same bank @burst length=4, trdl=2clk high ra ca ra cl=2 row active read write precharge *note: 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. t dal ,last data in to active delay, is 2clk + t rp . ba0 dqm dq t rdl *note 3 (a-bank) (a-bank) (a-bank) (a-bank) { *note 2 cb t dal *note 4 *note 1 t cdl read (a-bank) write (a-bank) row active (a-bank) cc cd rb rb qa1 dd0 qa0 qb0 dd1 qb1 qb2 dc0 dc1 qa1 dd0 qa0 qb0 dd1 qb1 dc0 dc1 t rcd
kaa00b209m-tgxx revision 1.3 march 2003 - 69 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock page read cycle at different bank @burst length=4 high raa caa raa cl=2 row active read precharge *note: 1. cs can be don't cared when ras , cas and we are high at the clock high going dege. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. ba0 dqm dq (a-bank) (a-bank) (d-bank) { *note 2 rcc read (b-bank) cbb rdd ccc cdd rbb rcc rdd qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 row active (b-bank) row active (c-bank) row active (d-bank) precharge (a-bank) read (c-bank) precharge (b-bank) read (d-bank) precharge (c-bank) *note 1 qaa0 qaa0 rbb
kaa00b209m-tgxx revision 1.3 march 2003 - 70 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap addr we : don?t care clock page write cycle at different bank @burst length=4, trdl=2clk high raa row active write write precharge *note: 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same. ba0 dqm dq *note 1 (a-bank) (a-bank) (d-bank) (all banks) *note 2 rab caa cbb rcc rdd ccc raa rbb rcc rdd daa3 dbb0 dbb1 dbb2 dbb3 dcc0 dcc1 ddd0 ddd1 ddd2 t cdl t rdl row active (b-bank) write (b-bank) row active (c-bank) row active (d-bank) write (c-bank) daa2 daa1 daa0 cdd
kaa00b209m-tgxx revision 1.3 march 2003 - 71 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle at different bank @burst length=4 high raa raa cl=2 row active read write read *note: 1. t cdl should be met to complete write. ba0 dqm dq (a-bank) (a-bank) (d-bank) (b-bank) precharge (a-bank) { caa rdb rbc cbc rdb t cdl *note 1 row active (d-bank) row active (b-bank) qaa1 qaa0 qaa2 qaa3 qbc0 qb c1 qbc2 ddb0 ddb1 ddb2 ddb3 qaa1 qaa0 qaa2 qaa3 qbc0 qb c1 cdb rbc ddb0 ddb1 ddb2 ddb3
kaa00b209m-tgxx revision 1.3 march 2003 - 72 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle with auto precharge i @burst length=4 high raa raa cl=2 row active read with precharge row active *note: 1. when read(write) command with auto precharge is issued at a-bank after a and b bank activation. - if read(write) command without auto precharge is issued at b-bank before a-bank auto precharge starts, a-bank auto precharge will start at b-bank read command input point . - any command can not be issued at a-bank during t rp after a-bank auto precharge starts. ba0 dqm dq (a-bank) auto pre (b-bank) (a-bank) read without auto precharge(b-bank) rbb rac cac caa cbb rbb dac0 dac0 charge (a-bank) row active (b-bank) auto precharge start point (a-bank) *note1 write with auto precharge (a-bank) qaa1 qaa0 qbb0 qbb1 dbb3 qbb2 qaa1 qaa0 qbb0 qbb1 dbb3 qbb2 dac1 dac1 rac
kaa00b209m-tgxx revision 1.3 march 2003 - 73 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read & write cycle with auto precharge ii @burst length=4 high ra cl=2 row active read with *note: 1. any command to a-bank is not allowed in this period. t rp is determined from at auto precharge start point ba0 dqm dq (a-bank) auto precharge auto precharge start point ca rb (a-bank) (a-bank) row active (b-bank) *note1 cb read with auto precharge (b-bank) auto precharge start point (b-bank) rb qa1 qa0 q a2 qa3 qb1 qb0 q b2 qb3 qa1 qa0 q a2 qa3 qb1 qb0 q b2 qb3 ra
kaa00b209m-tgxx revision 1.3 march 2003 - 74 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap addr we : don?t care clock clock suspension & dqm operation cycle @cas latency=2, burst length=4 ra row active read write *note: 1. dqm is needed to prevent bus contention. ba0 dqm dq *note 1 dqm ca qb0 qb1 dc0 dc2 clock suspension write cb ra t shz t shz read clock suspension write dqm read dqm qa1 qa2 qa3 qa0 cc
kaa00b209m-tgxx revision 1.3 march 2003 - 75 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock read interrupted by precharge command & read burst stop cycle @full page burst high raa cl=2 row active *note: 1. at full page mode, burst is finished by burst stop or precharge. 2. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1, 2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of "full page write burst stop cycle". 3. burst stop is valid at every burst length. ba0 dqm qaa3 (a-bank) caa cab burst stop precharge (a-bank) dq { qaa4 1 1 q aa2 qaa3 qaa4 2 raa read (a-bank) read (a-bank) qaa1 qaa0 q aa2 qaa1 qaa0 qab1 qab0 q ab2 qab3 q ab4 qab5 qab1 qab0 q ab2 qab3 q ab4 qab5 2
kaa00b209m-tgxx revision 1.3 march 2003 - 76 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap addr we : don?t care clock write interrupted by precharge command & write burst stop cycle @ full page burst, raa row active write *note: 1. at full page mode, burst is finished by burst stop or precharge. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl . dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length. ba0 dqm dq caa cab burst stop high raa daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 t bdl *note 1 t rdl *note 1,2 (a-bank) (a-bank) write (a-bank) precharge (a-bank) trdl=2clk daa2 daa1 daa0
kaa00b209m-tgxx revision 1.3 march 2003 - 77 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas ba1 a10/ap cl=3 addr we : don?t care clock burst read single bit write cycle @burst length=2 high raa cl=2 row active *note: 1. brsw modes is enabled by setting a9 "high" at mrs (mode register set). at the brsw mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge. ba0 dqm (a-bank) caa rcc precharge (c-bank) dq { raa write (a-bank) *note 2 rbb cab cbc ccd rbb rcc row active (b-bank) read with auto precharge (a-bank) row active (c-bank) write with auto precharge (b-bank) read (c-bank) daa0 q ab0 qab1 dbc0 q cd0 qcd1 daa0 q ab0 qab1 dbc0 q cd0 qcd1
kaa00b209m-tgxx revision 1.3 march 2003 - 78 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas a10/ap addr we : don?t care clock active/precharge power down mode @cas latency=2, burst length=4 precharge row active precharge *note: 1. all banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk + t ss prior to row active command. 3. can not violate minimum refresh specification. (64ms) ba dqm dq *note 1 power-down *note 2 ra ca qa0 qa1 qa2 precharge power-down read ra t shz *note 2 entry exit active power-down entry active power-down exit t ss *note 3 t ss t ss ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
kaa00b209m-tgxx revision 1.3 march 2003 - 79 - mcp memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas a10/ap addr we : don?t care clock self refresh entry & exit cycle self refresh entry *note: to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clcok cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in self refresh mode as long as cke stays "low". cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t srfx is required after cke going high to complete self refresh exit. 7. 4k cycle(64mb ,128mb) or 8k cycle(256mb, 512mb) of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. ba0,ba1 dqm dq *note 1 *note 4 t ss *note 3 t srfx *note 2 *note 6 self refresh exit auto refresh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? hi-z hi-z ?
kaa00b209m-tgxx revision 1.3 march 2003 - 80 - mcp memory 0 1 2 3 4 5 6 0 10 cke cs ras cas ba1 addr we : don?t care clock mode register set cycle key mrs new command *note: mode register set cycle 1. cs , ras , cas , ba0, ba1 & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. ba0 dqm dq ra auto refresh auto refresh cycle 1 2 3 4 5 6 7 8 9 high high new command * all banks precharge should be completed before mode register set cycle and auto refresh cycle. ? *note 2 *note 1 *note 3 t arfc ? ? ? ? ? ? ? ? ? ? ? hi-z hi-z
kaa00b209m-tgxx revision 1.3 march 2003 - 81 - mcp memory 0 1 2 3 4 5 6 cke cs ras cas ba1 addr we : don?t care clock extended mode register set cycle key emrs new command *note: extended mode register set cycle 1. cs , ras , cas , ba0, ba1 & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. ba0 dqm dq ra high *note 2 *note 1 *note 3 hi-z
kaa00b209m-tgxx revision 1.3 march 2003 - 82 - mcp memory package dimension 127-ball tape ball grid array package (measured in millimeters) top view bottom view side view 12.00 0.10 0.45 0.05 0.08max 0 . 3 2 0 . 0 5 1 . 3 0 0 . 1 0 #a1 10.50 0.10 1 2 . 0 0 0 . 1 0 1 4 2 7 6 5 3 8 a b c e g d f h 0.80 0.80 x11=8.80 a 0 . 8 0 x 1 2 = 9 . 6 0 1 2 . 0 0 0 . 1 0 4.40 127- ? 0.45 0.05 9 10 j k 4 . 8 0 0 . 8 0 b 10.50 0.10 0.20 m a b ? (datum a) (datum b) l 12 11 m n

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