k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram revision 1.4 december 2002 4mx16 mobile sdram (vdd/vddq 2.5v/1.8v or 2.5v/2.5v, tcsr & pasr ) 52csp
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram the k4s64163lf is 67,108,864 bits synchronous high data rate dynamic ram organized as 4 x 1,048,576 words by 16 bits, fabri- cated with samsung?s high performance cmos technology. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ? 2.5v power supply. ? lvcmos compatible with multiplexed address. ? four banks operation. ? mrs cycle with address key programs. -. cas latency (1 & 2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? emrs cycle with address key programs. ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation. ? special function support. -. pasr (partial array self refresh). -. tcsr (temperature compenasted self refresh). ? dqm for masking. ? auto refresh. ? 64ms refresh period (4k cycle). ? extended temperature operation (-25 c ~ 85 c). ? 52balls csp (gxxx - pb, axxx - pb free) general description features 1m x 16bit x 4 banks mobile sdram in 52csp * samsung electronics reserves the right to change products or specification without notice. bank select data input register 1m x 16 1m x 16 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we l(u)dqm lwe ldqm dqi clk add lcas lwcbr 1m x 16 1m x 16 timing register ordering information -g(a)s ; super low power, operating temp : -25 c ~ 85 c. -g(a)g ; low power, operating temp : -25 c ~ 85 c. notes : 1. in case of 40mhz frequency, cl1 can be supported. 2. in case of 33mhz frequency, cl1 can be supported. part no. max freq. interface package k4s64163lf-g(a)g/s75 133mhz(cl=3) 105mhz(cl=2) lvcmos 52 csp pb (pb free) k4s64163lf-g(a)g/s1h 105mhz(cl=2) k4s64163lf-g(a)g/s1l 105mhz(cl=3) *1 k4s64163lf-g(a)g/s15 66mhz(cl=2/3) *2 functional block diagram
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram symbol min typ max a 0.90 0.95 1.00 a 1 - 0.35 - e - 6.60 - e 1 - 3.75 - d - 11.00 - d 1 - 9.0 - e - 0.75 - b 0.40 0.45 0.5 z - - 0.10 f e d c b n l j h g 52ball(4x13) csp 1 2 5 6 a vss dq15 dq0 v dd b dq14 v ssq v ddq dq1 c dq13 v ddq v ssq dq2 d dq12 dq11 dq4 dq3 e dq10 v ssq v ddq dq5 f dq9 v ddq v ssq dq6 g dq8 v dd vss dq7 h clk udqm ldqm we j cke cs ras cas k a11 a9 ba1 ba0 l a8 a7 a0 a10 m a6 a5 a2 a1 n vss a4 a3 v dd pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 11 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable l(u)dqm data input/output mask dq 0 ~ 15 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground a package dimension and pin configuration m k < bottom view *1 > e 1 5 2 1 6 3 4 e d 1 d d / 2 e e/2 #a1 ball origin indicator < top view *2 > < top view *2 > a a1 b z *1: bottom view *2: top view [unit:mm] max. 0.20 encapsulant k 4 s 6 4 1 6 3 l f s e c w e e k x x x x
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 c to 85 c) notes : 1. v ih (max) = 3.0v ac.the overshoot voltage duration is 3ns. 2. v il (min) = -1.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. parameter symbol min typ max unit note supply voltage v dd 2.3 2.5 2.7 v v ddq 1.65 - 2.7 v input logic high voltage v ih 0.8 x v ddq - v ddq + 0.3 v 1 input logic low voltage v il -0.3 0 0.3 v 2 output logic high voltage v oh v ddq - 0.2v - - v i oh = -0.1ma output logic low voltage v ol - - 0.2 v i ol = 0.1ma input leakage current i li -10 - 10 ua 3 absolute maximum ratings notes : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 3.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma capacitance (v dd = 2.5v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 2.0 4.0 pf ras , cas , we , cs , cke, dqm c in 2.0 4.0 pf address c add 2.0 4.0 pf dq 0 ~ dq 15 c out 3.5 6.0 pf
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c) notes : 1. measured with outputs open. 2. refresh period is 64ms. 3. k4s64163lf-g(a)g** 4. k4s64163lf-g(a)s** 5. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq) parameter symbol test condition version unit note -75 -1h -1l -15 operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 50 50 45 40 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 0.5 ma i cc2 ps cke & clk v il (max), t cc = 0.5 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 10 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 7 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 5 ma i cc3 ps cke & clk v il (max), t cc = 5 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 20 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 20 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 80 65 65 55 ma 1 refresh current i cc5 t rc 3 t rc (min) 115 110 100 80 ma 2 self refresh current i cc6 cke 0.2v tcsr range max 45 c max 85 c c -g(a)g 4 banks 235 350 ua 3 2 banks 210 290 1 bank 195 270 -g(a)s 4 banks 130 230 4 2 banks 105 170 1 bank 90 150
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram ac operating test conditions (v dd = 2.5v 0.2v , t a = -25 to 85 c) parameter value unit ac input levels (vih/vil) 0.9 x v ddq / 0.2 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see fig. 2 v ddq 500 w 500 w output 30pf vtt=0.5 x v ddq 50 w output 30pf z0=50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit v oh (dc) = v ddq -0.2v , i oh = -0.1ma v ol (dc) = 0.2v, i ol = 0.1ma operating ac parameter (ac operating conditions unless otherwise noted) notes : 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. minimum trdl=2clk and tdal(=trdl + trp) is required to complete both of last data wite command(trdl) and precharge command(trp). trdl=1clk can be supported only in the case under 100mhz with manual precharge mode. 4. all parts allow every cycle column address change. 5. in case of row precharge interrupt, auto precharge and read burst stop. parameter symbol version unit note - 75 -1h -1l -15 row active to row active delay t rrd (min) 15 19 19 30 ns 1 ras to cas delay t rcd (min) 19 19 24 30 ns 1 row precharge time t rp (min) 19 19 24 30 ns 1 row active time t ras (min) 45 50 60 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 65 70 84 90 ns 1 last data in to row precharge t rdl (min) 2 clk 2,3 last data in to active delay t dal (min) trdl + trp - 3 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 4 number of valid output data cas latency=3 2 ea 5 cas latency=2 1 cas latency=1 - 0
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram ac characteristics (ac operating conditions unless otherwise noted) notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. parameter symbol - 75 -1h -1l - 15 unit note min max min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 9.5 1000 9.5 1000 15 1000 ns 1 cas latency=2 9.5 9.5 12 15 cas latency=1 - - 25 30 clk to valid output delay cas latency=3 t sac 5.4 7 7 9 ns 1,2 cas latency=2 7 7 8 9 cas latency=1 - - 20 24 output data hold time cas latency=3 t oh 2.5 2.5 2.5 2.5 ns 2 cas latency=2 2.5 2.5 2.5 2.5 cas latency=1 - - 2.5 2.5 clk high pulse width t ch 2.5 3 3 3.5 ns 3 clk low pulse width t cl 2.5 3 3 3.5 ns 3 input setup time t ss 2.0 2.5 2.5 3.5 ns 3 input hold time t sh 1.0 1.5 1.5 2.0 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 7 7 9 ns cas latency=2 7 7 8 9 cas latency=1 - - 20 24 note : 1. samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. please contact to the memory marketing team in samsung electronics when considering the use of a product c on- tained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
k4s64163lf-g(a)g/s rev. 1.4 dec. 2002 cmos sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) note : 1. op code : operand code a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. partial self refresh can be issued only after setting partial self refresh mode. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data-in at that same clk in write operation (write dqm latency is 0), but in read operation makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 9 ~ a 0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h
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