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ir5001s & (pbf) 1 www.irf.com universal active oring controller data sheet no.pd60229 revb f 1 - typical application of the ir5001s in - 48v input, carrier class telecommunications equipment. typical application applications +48v input -48v input b -48v input a ir5001 vline vcc fetch inp inn gnd vout fetst ir5001 dc dc fet check pulse fet a status fet b status a b vline vcc fetch fetst vout gnd inn inp features description the ir5001s is a universal high-speed controller and n-channel power mosfet driver for active oring and reverse polarity protection applications. the output voltage of the ir5001s is determined based on the polarity of the voltage difference on its input terminals. in particular, if the current flow through an n-channel oring fet is from source to drain, the output of the ir5001s will be pulled high to vcc, thus turning the active oring fet on. if the current reverses direction and flows from drain to source (due to a short-circuit failure of the source, for example), the ic will quickly switch the active oring fet off. typical turn-off delay for the ir5001s is only 130ns, which helps to minimize voltage sags on the redundant dc voltage. both inputs to the ic (inn and inp) as well as vline input contain integrated high voltage resistors and internal clamps. this makes the ir5001s suitable for applications at voltages up to 100v, and with a minimum number o f external components. ? controller / driver ic in an so-8 package fo r implementation of active oring / reverse polarit y protection using n-channel power mosfets ? suitable for both input oring (for carrier class telecom equipment) as well as output oring fo r redundant dc-dc and ac-dc power supplies ? 130ns typical turn-off delay time ? 3a peak turn-off gate drive current ? asymmetrical offset voltage of the internal high-speed comparator prevents potential oscillations at light load ? ability to withstand continuous gate short conditions ? integrated voltage clamps on both comparator inputs allow continuous application of up to 100v ? option to be powered either directly from 36-75 v universal telecom bus (100v max), or from an external bias supply and bias resistor ? input/output pins to determine the state of the active oring circuit and power system redundancy ? -48v/-24v input active oring for carrier class communication equipment ? reverse input polarity protection for dc-dc power supplies ? 24v/48v output active oring for redundant ac-dc rectifiers ? low output voltage (12v, 5v, 3.3v...) active oring for redundant dc-dc and ac-dc power supplies ? active oring of multiple voltage regulators for redundant processor power ja =128 c/w inp vout gnd inn vline 4 3 2 1 5 6 7 8 fetst vcc fetch top view package / ordering information pkg part leadfree pin parts parts t & r desig. number part number count per tube per reel oriantation s ir5001s ir5001spbf 8 95 ------ s ir5001str IR5001STRPBF 8 ------- 2500 fig a
ir5001s & (pbf) 2 www.irf.com unless otherwise specified, these specifications apply over v line = 36v to 100v; vcc is decoupled with 0.1uf to gnd, c l =10nf at vout; inp is connected to gnd. typical values refer to t a =25c. minimum and maximum limits apply to t a = 0c to 85c temperature range and are 100% production-tested at both temperature extremes. low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. absolute maximum ratings caution: 1. stresses above those listed in "absolute maximum ratings" may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. 2. this device is esd sensitive. use of standard esd handling precautions is required. . electrical specifications vline voltage -5.0v to 100v (continuous) vcc voltage -0.5v to 15vdc icc current 5ma inn, inp voltage -5.0v to 100v (continuous) fetch, fetst -0.5v to 5.5v fetst sink current 10ma junction temperature -40c to 125c storage temperature range -65c to 150c parameters symbol test condition min typ max units vline=25v 0.14 0.3 0.5 vline=36v 0.2 0.5 0.75 vline=100v, note 1 1.2 1.7 2.2 vcc output voltage vcc(out) vline=25v 10.2 12.5 14.1 v uvlo section uvlo on threshold voltage vcc(on) vli ne=open, vinp = 0 ; vinn = - 0.3v vcc increased until vout switches from lo to hi , note 2 8.0 9.6 10.7 uvlo off threshold voltage vcc(off) vline=open, vinp=0, vinn=- 0.3v, vcc is decreased until vout switches from hi to lo 5.6 7.2 8.8 uvlo hysteresis 1.6 2.3 2.8 v input comparator section input offset voltage (vinp- vinn) vos vinp=0v and vinn ramping up, vout changes from hi to lo, fig.3 -7.9 -4.0 0 input hysteresis voltage vhyst vinp=0,vinn ramping down, figures 3 and 4 13 31 44 (inn) input bias current i(inn) vinp=0v, vinn=36v 0.2 0.5 0.9 (inp) input bias current i(inp) vinn=0v, vinp=36v 0.2 0.5 0.9 ma mv iline bias section vline bias current v ma
ir5001s & (pbf) 3 www.irf.com pin descriptions note 1: guaranteed by design but not tested in production. note 2: low vcc output voltage corresponds to low uvlo voltage pin# pin symbol pin description 1 vline ic power supply pin for 36v to 75v input communications systems. minimum 25v has to be applied at this pin to bias the ic. 2vcc output pin of the internal shunt regulator, or input pin for biasing the ic via external resistor. this pin is internally regulated at 12.5v typical. a minimum 0.1uf capacitor must be connected from this pin to gnd of ir5001. 3fetch fet check input pin. together with fet status output pin, the fetch pin can be used to determine the state of the active oring circuit and power system redu ndancy. 4fetst fet status output pin. together with fetch input pin, the fetst pin can be used to determine the state of the active oring circuit and power system redundancy. 5inp positive input of internal comparator. this pin should connect to the source of n-channel active oring mosfet. 6inn negative input pin of internal comparator. this pin should connect to the drain of n-channel active oring mosfet. 7 gnd ground pin of the ir5001. 8 vout output pin for the ir5001. this pin is used to directly drive the gate of the active oring n-channel mosfet. parameters symbol test condition min typ max units output section high level output voltage vout hi vline=25v, ioh=50ua, v(inn)=-0.3v 10.2 11.5 14.1 v low level output voltage vout lo iol=100ma, v(inn)=+0.3v 0.1 v turn-on delaytime td(on) 5 27 45 us rise time tr 0.09 0.7 1 ms turn-off delay time td(off) 110 130 170 fall time tf 10 26 39 fetch and fetst fetch sink current i(fetch) fetch=5v -0.5 -1.1 -2 ua fetch output delay time fetch_pd note 1 0.8 1.8 us fetch threshold vth(fetch) 0.9 1.2 1.5 v fetst threshold voltage vth(fetst) 5k resistor from fetst to 5v logic bias. v(inp) = gnd, v(inn) ramping down from 0 until fetst switches to low. -525 -300 -200 mv fetst low level output voltage vol isink=1ma, v(inn)=-0.5v 0 50 100 mv vout switching from lo to hi, fig.5 vout switching from hi to lo, fig.5 ns
ir5001s & (pbf) 4 www.irf.com figure 2 - simplified block diagram of the ir5001. block diagram 50k v line vcc v out 9v gnd inp inn 5v 0.3v 28mv 3.5mv 5v 70k 70k 1.25v fetst fetch 2ua level shifter 12v 1 2 8 7 5 6 4 3 uvlo 12v shunt regulator 5v, v ref generator 1.25v 5v clamp clamp
ir5001s & (pbf) 5 www.irf.com figure 3 - input comparator offset (vos ) and hysteresis voltage (vhyst) definition. figure 5 - dynamic parameters. figure 4 - input comparator hysteresis definition. parameter definition and timing diagram v inp - v inn v out (0,0) v os v hyst 90mv 0 v in (v inp - v inn ) v inp - v inn = 200mv t f t d(off) 90% 50% 10% v out v ol 50mv -50mv -90mv v oh 10ns t d(on) 10ns t r v inn (v inp =gnd) v out -vos v hyst gnd
ir5001s & (pbf) 6 www.irf.com typical operating characteristics 5.1 5.2 5.3 5.4 5.5 5.6 5.7 -40 -10 20 50 80 110 140 temperature (c) vos value (mv) 8.4 8.8 9.2 9.6 10 10.4 10.8 -40 0 40 80 120 temperature (c) uvlo_upper (v) 16 18 20 22 24 26 28 -40 0 40 80 120 temperature (c) fall time (ns) -380 -360 -340 -320 -300 -280 -40-20 0 20406080100 temperature (c) fetst threshold (mv ) 120 130 140 150 160 170 180 -40 -20 0 20 40 60 80 100 temperature (c) td(off) (ns) 15 17 19 21 23 25 27 29 31 -40 -10 20 50 80 110 140 temperature (c) hysteresis( mv) figure 6 - turn off delay vs. junction temperature figure 8 - vos vs. junction temperature figure 9 - fall time vs. junction temperature figure 10 - inp, inn input hysteresis vs. junction temp. figure 11 - fetst threshold voltage vs. junction temp. figure 7 - uvlo upper trip point vs. junction temperature
ir5001s & (pbf) 7 www.irf.com 117.0 117.5 118.0 118.5 119.0 119.5 120.0 120.5 121.0 20 40 60 80 100 vline (v) toff delay (ns ) typical operating characteristics 0 0.2 0.4 0.6 0.8 1 1.2 1.4 20 40 60 80 100 inn (v) i inn (ma ) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 20 40 60 80 100 vline (v) i vline (ma) figure 13 - i(vline) vs. vline and junction temperature figure 15 - turn off delay vs. vline at room temperature figure 14 - bias current i(inn) vs. v(inn) at vline=25v 11.6 11.8 12 12.2 12.4 12.6 12.8 13 20 40 60 80 100 vline (v) vcc (v) figure 12 - vcc vs. vline and junction temperature bottom: top: 25c 85c 125c -40c bottom: top: 125c 85c 25c -40c
ir5001s & (pbf) 8 www.irf.com detailed pin description v line and vcc vline and vcc are the input and output pins o f the internal shunt regulator. the internal shunt regulator regulates the vcc voltage at ~12v. the vcc pin should always be by-passed with a ceramic capacitor to the gnd pin. both vline and vcc pins can be used for biasing the ir5001s, as shown in fig. 16. the vline pin is designed to bias the ir5001s directly when the available bias voltage is above 25v and less than 100v (targeted at typical 36v ? 75v telecom applications). this connection is shown in fig 16.a. if the available vbias voltage is lower than 25v, then the ic must be biased using vcc pin and an external bias resistor as shown in fig. 16.b. if the available bias voltage is above 100v, both vline and vcc pins can be used with an external bias resistor. fo r calculation of the proper bias resistor value, see example below. when the vcc pin is used for biasing the ir5001s, the vbias must always be higher than the maximum value of the vcc uvlo threshold (10.7v). the rbias resistor should always be connected between the vbias voltage source and vcc pin. the rbias resistor is selected to provide adequate icc current for the ic. the minimum required icc to guarantee proper ic operation under all conditions is 0.5ma. the maximum icc is specified at 5ma. vbias ir5001 vcc fetch inp inn gnd out fetst vline + a) b) vbias ir5001 vcc fetch inp inn gnd out fetst vline rbias + figue 16 - biasing options for ir5001 an example of rbias calculation is given below. vbias voltages used in the example are referenced to ir5001s gnd: vbias min = 12v vbias max = 16v rbias = (vbias min ? vcc uvlomax) / icc min = = (12v ? 10.7v) / 0.5ma = 2.6kohm next, using a minimum vcc (10.2v), verify that icc with the selected rbias will be less than 5ma: icc max = (vbias max ? vcc min)/rbias = = (16v - 10.2v) / 2.6kohm = 2.23ma since 2.23ma is below 5ma max icc, the calculated rbias (2.6kohm) can be used in this design. inp and inn inputs inp and inn are the inputs of the internal high- speed comparator. both pins have integrated on- board voltage clamps and high-voltage 70kohm resistors. in a typical application, inp should be connected to the source of the n-fet and inn to the drain. to improve the noise immunity, the connections from inn and inp pins to the source and drain terminals of the n-fet should be as short as possible. the (inp ? inn) voltage difference determines the state of the vout pin of the ir5001s. when the body diode of the active oring n-fet is forward- biased and the current first starts flowing, the voltage difference inp ? inn will quickly rise toward ~700mv (typical body diode forward voltage drop). a s soon as this voltage exceeds vhyst ? ? ?
ir5001s & (pbf) 9 www.irf.com guarantees that once the oring n-fet is conducting and vout of the ir5001s is high (fet current flows from source to drain), the current must reverse the direction before the ir5001s will switch the fet off. the asymmetrical offset voltage prevents potential oscillations at light load that could otherwise occur if the offset voltage was centered around 0mv (as is the case in standard comparators). v out vout is the output pin of the ir5001s, and connects directly to the gate of the external active oring n- fet. the voltage level at the vout pin is typically a diode drop lower than the vcc voltage. fetst and fetch fetch and fetst pins are diagnostic pins that can be used to determine the status of the active oring circuit. fetst is an open-drain output pin. when the voltage difference between vinp - vinn is less than 0.3v, the fetst pin will be logic high. this is normally the case when active oring is operating properly (vinp - vinn is less than ~100mv). if the active oring fet is not turned on while the ir5001s is properly biased, the output of the fetst pin will be logic low (only the body diode of the n-fet is conducting, and vinp - vinn is ~700mv). fetch pin. in traditional systems with diode oring, it is not possible to determine if the diode is functioning properly unless external circuitry is used. for example, the diode could be failed short, and the system would not be aware of it until the source fails and the whole system gets powered down due to lost redundancy (shorted diode failed to isolate the source failure). with the fetch pin it is possible to perform a periodic check of the status of the active oring circuit to assure that system redundancy is maintained. in the ir5001s, the fetch pin is an input pin that can be used to turn off the output of the ir5001s: logic high signal on fetch will pull the vout pin low, and turn-off the channel of the active oring n-fet. this will force the current to flow through the body diode, resulting in vinp ? vinn voltage increase from less than ~100mv, to ~700mv. this voltage increase will be reported at fetst pin, which will switch from logic high to logic low, and indicate that the active oring circuit is working properly. failure of the fetst pin output to change from logic high to logic low would indicate that the active oring circuit may not be operating as designed, and the system may no longer have power redundancy. for details on how to use this feature consult ir5001s evaluation kit, p/n irdc5001-ls48v . if the fetch pin is not used, it should be tied to ground (for noise immunity purposes). fetst pin should be left open if unused. gnd in typical target applications, the ground pin (gnd) o f ir5001s is connected to the source of the active oring n-fet.
ir5001s & (pbf) 10 www.irf.com application information the ir5001s is designed for multiple active oring and reverse polarity protection applications with minimal number of external components. examples of typical circuit connections are shown below. negative rail oring/reverse polarity protection a typical connection of the ir5001s in negative rail active oring or reverse polarity protection is shown in fig. 17. in this example, ir5001s is biased directly from the positive rail. however, any of the biasing schemes shown in fig. 16 can be used. for input oring in carrier-class communications boards, one ir5001s is used per feed. this is shown in fig.1. an evaluation kit is available fo r typical system boards, with input voltages o f negative 36v to negative 75v, and for power levels from 30w to about 300w. the p/n for the evaluation kit is irdc5001-ls48v. this evaluation kit contains detailed design considerations and in-circuit performance data for the ir5001s. positive rail oring / ground oring in communications boards an example of a typical connection in positive rail oring is shown in fig. 18. typical applications are inside redundant ac-dc and dc-dc power supplies, or on-board oring. for positive rail oring, an additional vbias voltage above the positive rail is needed to bias the ir5001s. an evaluation kit for high-current 12v positive rail oring is available under p/n irac5001- hs100a, demonstrating performance of the ir5001s at 100a output current. considerations for the selection of the active oring n-channel mosfet active oring fet losses are all conduction losses, and depend on the source-drain current and r ds(on) of the fet. the conduction loss could be virtually eliminated if a fet with very low r ds(on) was used. however, using arbitrarily low r ds(on) is not desirable for three reasons: 1. turn off propagation delay. higher r ds(on) will provide more voltage information to the internal comparator, and will result in faster fet turn of f protection in case of short-circuit of the source (less voltage disturbance on the redundant bus). 2. undetected reverse (drain to source) current flow. with the asymmetrical offset voltage, some small current can flow from the drain to source of the oring fet and be undetected by the ir5001s. the amount of undetected drain- source current depends on the r ds(on) of the selected mosfet and its r ds(on) . to keep the reverse (drain-source) current below 5 ? 10% o f the nominal source-drain state, the r ds(on) o f the selected fet should produce 50mv to 100mv of the voltage drop during nominal operation. 3. cost. with properly selected r ds(on) , active oring using ir5001s can be very cost competitive with traditional oring while providing huge power loss reduction. for example, a fet with 20mohm r ds(on) results in 60mv voltage drop at 3a; associated power savings compared to the traditional diode oring (assuming typical 0.6v forward voltage drop) is ten fold(0.18w vs. 1.8w)! now assume that fet r ds(on) was 10mohm. the power loss would be reduced by additional 90mw, which is negligible compared to the power loss reduction already achieved with 20mohm fet. but to get this negligible saving, the cost of the active oring fet would increase significantly. vbias ir5001 vcc fetch inp inn gnd out fetst vline rbias + vin + vin - load redundant vin - vbias ir5001 vcc fetch inp inn gnd out fetst vline rbias + vout + vout - redundant vout + load figure. 18. connection of inn,inp, and gnd when the mosfet is placed in the path of positive rail. figure. 17 connection of inn, inp, and gnd for negative rail active oring or reverse polarity protection.
ir5001s & (pbf) 11 www.irf.com in a well - designed active oring circuit, the rds(on) of the active oring fet should generate between 50mv to 100mv of (inp ? inn) voltage during normal, steady state operation. (the normal operation refers to current flowing from the source to drain of the active oring fet, half of the full-load system current flowing through each or-ed source, at nominal input voltage). maximum powe r dissipation under worst-case conditions for the fet should be calculated and verified against the data sheet limits of the selected device. ir5001s thermal considerations maximum junction temperature of the ir5001s in an application should not exceed the maximum operating junction temperature, specified at 125c: tj = pdiss * rtheta j-a + tamb <= tj (max), where rtheta j-a is the thermal resistance from j unction to ambient thermal resistance (specified at 128 c/w), pdiss is ic power dissipation, and tamb is operating ambient temperature. the maximum power dissipation can be estimated as follows: pdiss < (tj max ? tamb max) / rtheta j-a since tj max= 125
ir5001s & (pbf) 12 www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the industrial market visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 12/15/2005 (s) soic package 8-pin surface mount, narrow body note: all measurements are in millimeters. pin no. 1 i k h detail-a detail-a 0.38 +/- 0.015 x 45 t g f d a b c e l j symbol a b c d e f g h i j k l t min 4.80 0.36 3.81 1.52 0.10 0.19 5.80 0 0.41 1.37 max 4.98 0.46 3.99 1.72 0.25 0.25 6.20 8 1.27 1.57 1.27 bsc 0.53 ref 7 bsc 8-pin feed direction figure a 1 1 1

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