1 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock july 2012 2012 integrated device technology, inc. dsc 5408/3 c commercial and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. features: ? ref input is 5v tolerant ? 3 pairs of programmable skew outputs ? low skew: 200ps same pair, 250ps all outputs ? selectable positive or negative edge synchronization: excellent for dsp applications ? synchronous output enable ? output frequency: 3.75mhz to 85mhz ? 2x, 4x, 1/2, and 1/4 outputs ? 3 skew grades: idt5v993a-2: t skew0 <250ps idt5v993a-5: t skew0 <500ps idt5v993a-7: t skew0 <750ps ? 3-level inputs for skew and pll range control ? pll bypass for dc testing ? external feedback, internal loop filter ? 12ma balanced drive outputs ? low jitter: <200ps peak-to-peak ? available in qsop package ? not recommended for new design functional block diagram gnd/soe 1q 0 skew select 1q 1 1f1:0 3 3 2q 0 skew select 2q 1 2f1:0 fs 3 ref pll fb 3 3q 0 skew select 3q 1 3f1:0 3 3 4q 0 4q 1 3 v ccq /pe idt5v993a nrnd 3.3v programmable skew pll clock driver turboclock? description: the idt5v993a is a high fanout 3.3v pll based clock driver intended for high performance computing and data-communications applications. a key feature of the programmable skew is the ability of outputs to lead or lag the ref input signal. the idt5v993a has six programmable skew outputs and two zero skew outputs. skew is controlled by 3-level input signals that may be hard-wired to appropri- ate high-mid-low levels. when the gnd/ soe pin is held low, all the outputs are synchro- nously enabled. however, if gnd/ soe is held high, all the outputs except 3q0 and 3q1 are synchronously disabled. furthermore, when the v ccq /pe is held high, all the outputs are synchronized with the positive edge of the ref clock input. when v ccq /pe is held low, all the outputs are synchronized with the negative edge of ref. both devices have lvttl outputs with 12ma balanced drive outputs.
2 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock pin configuration note: 1. stresses beyond those listed under absolute maximum ratings may cause per- manent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute-maximum-rated condi- tions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit supply voltage to ground ?0.5 to +7 v v i dc input voltage ?0.5 to v cc +0.5 v ref input voltage ?0.5 to +5.5 v maximum power dissipation (t a = 85c) 0.66 w t stg storage temperature ?65 to +150 c note: 1. capacitance applies to all inputs except test and fs. it is characterized but not produc- tion tested. capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance 4 6 pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ref fs 3f 0 3f 1 4q 1 4q 0 gnd 3q 1 3q 0 fb gnd test 2f 1 2f 0 gnd/soe 1f 1 1f 0 v ccn 1q 0 1q 1 gnd gnd 2q 0 2q 1 v ccn v ccn v ccq /pe v ccq qsop top view output skew with respect to the ref input is adjustable to com- pensate for pcb trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. skew is selectable as a multiple of a time unit t u which is of the order of a nanosecond (see pll programmable skew range and resolution table). there are nine skew configura- tions available for each output pair. these configurations are chosen by the nf 1:0 control pins. in order to minimize the number of control pins, 3-level inputs (high-mid-low) are used, they are intended for but not restricted to hard-wiring. undriven 3-level inputs default to the mid level. where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. the control summary table shows how to select specific skew taps by using the nf 1:0 control pins. programmable skew pin description pin name type description ref in reference clock input fb in feedback input test (1) in when mid or high, disables pll (except for conditions of note 1). ref goes to all outputs. skew selections (see control summary table) remain in effect. set low for normal operation. gnd/ soe (1) in synchronous output enable. when high, it stops clock outputs (except 3q 0 and 3q 1 ) in a low state - 3q 0 and 3q 1 may be used as the feedback signal to maintain phase lock. when test is held at mid level and gnd/ soe is high, the nf [1:0] pins act as output disable controls for individual banks when nf [1:0] = ll. set gnd/ soe low for normal operation. v ccq /pe in selectable positive or negative edge control. when low/high the outputs are synchronized with the negative/positive edge of the reference clock. nf [1:0] in 3-level inputs for selecting 1 of 9 skew taps or frequency functions fs in selects appropriate oscillator circuit based on anticipated frequency range. (see pll programmable skew range.) nq [1:0] out three output banks of two outputs with programmable skew (1q:3q), and 4q output has fixed zero skew outputs. v ccn pwr power supply for output buffers v ccq pwr power supply for phase locked loop and other internal circuitry gnd pwr ground note: 1. when test = mid and gnd/ soe = high, pll remains active.
3 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock external feedback by providing external feedback, the idt5v993a gives users flex- ibility with regard to skew adjustment. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. notes: 1. the device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. s electing the appropriate fs value based on input frequency range allows the pll to operate in its ?sweet spot? where jitter is lowest. 2. the level to be set on fs is determined by the nominal operating frequency of the vco and time unit generator. the vco freque ncy always appears at 1q 1:0 , 2q 1:0 , and the higher outputs when they are operated in their undivided modes. the frequency appearing at the ref and fb inputs will be the same as t he vco when the output connected to fb is undivided. the frequency of the ref and fb inputs will be 1/2 or 1/4 the vco frequency when the part is configured for a frequency multipl ication by using a divided output as the fb input. 3. skew adjustment range assumes that a zero skew output is used for feedback. if a skewed q output is used for feedback, then a djustment range will be greater. for example if a 4t u skewed output is used for feedback, all other outputs will be skewed ?4t u in addition to whatever skew value is programmed for those outputs. ?max adjustment? range applies to output pairs 3 and 4 where 6t u skew adjustment is possible and at the lowest f nom value. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing ac- curate responses to input frequency changes. fs = low fs = mid fs = high comments timing unit calculation (t u ) 1/(44 x f nom ) 1/(26 x f nom ) 1/(16 x f nom ) vco frequency range (f nom ) (1,2) 15 to 35mhz 25 to 60mhz 40 to 85 mhz skew adjustment range (3) max adjustment: 9.09ns 9.23ns 9.38ns ns 49 83 135 phase degrees 14% 23% 37% % of cycle time example 1, f nom = 15mhz t u = 1.52ns ? ? example 2, f nom = 25mhz t u = 0.91ns t u = 1.54ns ? example 3, f nom = 30mhz t u = 0.76ns t u = 1.28ns ? example 4, f nom = 40mhz ? t u = 0.96ns t u = 1.56ns example 5, f nom = 50mhz ? t u = 0.77ns t u = 1.25ns example 6, f nom = 80mhz ? ? t u = 0.78ns pll programmable skew range and resolution table control summary table for feedback signals nf1:0 skew (pair #1, #2) skew (pair #3) ll (1) ?4t u divide by 2 lm ?3t u ?6t u lh ?2t u ?4t u ml ?1t u ?2t u mm zero skew zero skew mh 1t u 2t u hl 2t u 4t u hm 3t u 6t u hh 4t u divide by 4 note: 1. ll disables outputs if test = mid and gnd/ soe = high.
4 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock recommended operating range idt5v993a-5, -7 idt5v993a-2 (industrial) (commercial) symbol description min. max. min. max. unit v cc power supply voltage 3 3.6 3 3.6 v t a ambient operating temperature -40 +85 0 +70 c power supply characteristics symbol parameter test conditions (1) typ. (2) max. unit i ccq quiescent power supply current v cc = max., test = mid, ref = low, 8 25 ma v cc/pe = low, gnd/ soe = low, all outputs unloaded i cc power supply current per input high v cc = max., v in = 3v 1 30 a i ccd dynamic power supply current per output v cc = max., c l = 0pf 55 90 a/mhz i tot total power supply current v cc = 3.3v, f ref = 20mhz, c l = 160pf (1) 29 ? v cc = 3.3v, f ref = 33mhz, c l = 160pf (1) 42 ? ma v cc = 3.3v, f ref = 66mhz, c l = 160pf (1) 76 ? note: 1. for eight outputs, each loaded with 20pf. dc electrical characteristics over operating range symbol parameter conditions min. max. unit v ih input high voltage guaranteed logic high (ref, fb inputs only) 2 ? v v il input low voltage guaranteed logic low (ref, fb inputs only) ? 0.8 v v ihh input high voltage (1) 3-level inputs only v cc ? 0.6 ? v v imm input mid voltage (1) 3-level inputs only v cc /2 ? 0.3 v cc /2+0.3 v v ill input low voltage (1) 3-level inputs only ? 0.6 v i in input leakage current v in = v cc or gnd ? 5 a (ref, fb inputs only) v cc = max. v in = v cc high level ? 200 i 3 3-level input dc current (test, fs) v in = v cc /2 mid level ? 50 a v in = gnd low level ? 200 i pu input pull-up current (v ccq /pe) v cc = max., v in = gnd ? 100 a i pd input pull-down current (gnd/ soe )v cc = max., v in = v cc ? 100 a v oh output high voltage v cc = min., i oh = ? 12ma 2.4 ? v v ol output low voltage v cc = min., i ol = 12ma ? 0.55 v note: 1. these inputs are normally wired to v cc , gnd, or unconnected. internal termination resistors bias unconnected inputs to v cc /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved.
5 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock switching characteristics over operating range idt5v993a-2 idt5v993a-5 idt5v993a-7 symbol parameter min. typ. max. min. typ. max. min. typ. max. unit f nom vco frequency range see pll programmable skew range and resolution table t rpwh ref pulse width high (11) 3?? 3??3??ns t rpwl ref pulse width low (11) 3?? 3??3??ns t u programmable skew time unit see control summary table t skewpr zero output matched-pair skew (xq 0 , xq 1 ) (1,2,3) ? 0.05 0.2 ? 0.1 0.25 ? 0.1 0.25 ns t skew0 zero output skew (all outputs) (1,4) ? 0.1 0.25 ? 0.25 0.5 ? 0.3 0.75 ns t skew1 output skew ? 0.25 0.5 ? 0.6 0.7 ? 0.6 1 ns (rise-rise, fall-fall, same class outputs) (1,6) t skew2 output skew ? 0.3 1.2 ? 0.5 1.2 ? 1 1.5 ns (rise-fall, divided-divided) (1,6) t skew3 output skew ? 0.25 0.5 ? 0.5 0.7 ? 0.7 1.2 ns (rise-rise, fall-fall, different class outputs) (1,6) t skew4 output skew ? 0.5 0.9 ? 0.5 1 ? 1.2 1.7 ns (rise-fall, nominal-divided) (1,2) t dev device-to-device skew (1,2,7) ? ? 0.75 ? ? 1.25 ? ? 1.65 ns t pd ref input to fb propagation delay (1,9) ? 0.25 0 0.25 ? 0.5 0 0.5 ? 0.7 0 0.7 ns t odcv output duty cycle variation from 50% (1) ? 1.2 0 1.2 ? 1.2 0 1.2 ? 1.2 0 1.2 ns t pwh output high time deviation from 50% (1,10) ? ? 2 ? ? 2.5 ? ? 3 ns t pwl output low time deviation from 50% (1,11) ? ? 1.5 ? ? 3 ? ? 3.5 ns t orise output rise time (1) 0.15 1 1.2 0.15 1 1.8 0.15 1.5 2.5 ns t ofall output fall time (1) 0.15 1 1.2 0.15 1 1.8 0.15 1.5 2.5 ns t lock pll lock time (1,8) ? ? 0.5 ? ? 0.5 ? ? 0.5 ms t jr cycle-to-cycle output jitter (1) rms ? ? 25 ? ? 25 ? ? 25 ps peak-to-peak ? ? 200 ? ? 200 ? ? 200 notes: 1. all timing and jitter tolerances apply for f nom > 25mhz. 2. skew is the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with the specified load. 3. t skewpr is the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . 4. t skew0 is the skew between outputs when they are selected for 0t u . 5. for idt5v993a-2 t skew0 is measured with c l = 0pf; for c l = 20pf, t skew0 = 0.35ns max. 6. there are 2 classes of outputs: nominal (multiple of t u delay), and divided (3qx only in divide-by-2 or divide-by-4 mode). 7. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) 8. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. 9. t pd is measured with ref input rise and fall times (from 0.8v to 2v) of 1ns. 10. measured at 2v. 11. measured at 0.8v. input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall times, 0.8v to 2v ? 10 ns/v t pwc input clock pulse, high or low 3 ? ns d h input duty cycle 10 90 % r ef reference clock input 3.75 85 mhz note: 1. where pulse width implied by d h is less than t pwc limit, t pwc limit applies.
6 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock 2.0v t pwl t pwh t orise t ofall 0.8v ? 1ns ? 1ns 2.0v 0.8v 3.0v 0v vth = 1.5v 150 ? v cc output 20pf 150 ? ac test loads and waveforms lvttl input test waveform lvttl output waveform
7 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock ref divided by 2 ref divided by 4 t skew1, 3, 4 t skew2 t skew3 t skew3 ref fb q other q t ref t pd t skewpr t skew0, 1 t skewpr t skew0, 1 t jr t odcv t odcv t rpwh t rpwl t skew3, 4 notes: v ccq /pe: the ac timing diagram applies to v ccq /pe=v cc . for v ccq /pe=gnd, the negative edge of fb aligns with the negative edge of ref, divided outputs change on the negative edge of ref, and the positive edges of the divide-by-2 and the divide-by-4 signals align. skew: the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 20pf and terminated with 75 to v cc /2. t skewpr : the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . t skew0 : the skew between outputs when they are selected for 0t u . t dev : the output-to-output skew between any two devices operating under the same conditions (v cc , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. t pwh is measured at 2v. t pwl is measured at 0.8v. t orise and t ofall are measured between 0.8v and 2v. t lock : the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. ac timing diagram
8 commercial and industrial temperature ranges idt5v993a 3.3v programmable skew pll clock driver turboclock ordering information idt xxxxx xx x package process device type blank i 5v993a-2 5v993a-5 5v993a-7 3.3v programmable skew pll clock driver turboclock quarter-size small outline package qsop - green q qg commercial (0c to +70c) industrial (-40c to +85c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
|
