View ADG1611_6528819.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 typical on resistance, 5 v, +12 v, +5 v, and +3.3 v quad spst switches data sheet ADG1611/adg1612/adg1613 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009-2012 analog devices, inc. all rights reserved. features 1 typical on resistance 0.2 on resistance flatness 3.3 v to 8 v dual-supply operation 3.3 v to 16 v single-supply operation no v l supply required 3 v logic-compatible inputs rail-to-rail operation continuous current per channel lfcsp package: 280 ma tssop package: 175 ma 16-lead tssop and 16-lead, 4 mm 4 mm lfcsp applications communication systems medical systems audio signal routing video signal routing automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems relay replacements general description the ADG1611 / adg1612 / adg1613 contain four independent single-pole/single-throw (spst) switches. the ADG1611 and adg1612 differ only in that the digital control logic is inverted. the ADG1611 switches are turned on with logic 0 on the appropriate control input, while logic 1 is required for the adg1612 switches. the adg1613 has two switches with digital control logic similar to that of the ADG1611 ; the logic is inverted on the other two switches. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. the adg1613 exhibits break-before-make switching action for use in multiplexer applications. inherent in the design is the low charge injection for minimum transients when switching the digital inputs. the ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distorti on is critical. the on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. the cmos construction ensures ultralow power dissipation, making them ideally suited for portable and battery-powered instruments. functional block diagrams in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 ADG1611 07981-001 notes 1. switches shown for a logic 1 input. figure 1. in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1612 07981-033 notes 1. switches shown for a logic 1 input. figure 2. notes 1. switches shown for a logic 1 input. in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1613 07981-034 figure 3. product highlights 1. 1.6 maximum on resistance over temperature. 2. minimum distortion: thd + n = 0.007%. 3. 3 v logic-compatible digital inputs: v inh = 2.0 v, v inl = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <16 nw. 6. 16-lead tssop and 16-lead, 4 mm 4 mm lfcsp.
ADG1611/adg1612/adg1613 data sheet rev. b | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams............................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? 5 v dual supply ......................................................................... 3 ? 12 v single supply........................................................................ 4 ? 5 v single supply.......................................................................... 5 ? 3.3 v single supply........................................................................6 ? continuous current per channel, s or d..................................7 ? absolute maximum ratings ............................................................8 ? esd caution...................................................................................8 ? pin configurations and function descriptions ............................9 ? typical performance characteristics ........................................... 10 ? test circuits..................................................................................... 13 ? terminology .................................................................................... 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 16 ? revision history 3/12rev. a to rev. b changes to figure 16...................................................................... 11 8/09rev. 0 to rev. a changes to on resistance (r on ) parameter, on resistance match between channels (r on ) parameter, and on resistance flatness (r flaton ) parameter, table 4 ............................................................ 6 changes to figure 7 caption......................................................... 10 1/09revision 0: initial version
data sheet ADG1611/adg1612/adg1613 rev. b | page 3 of 16 specifications 5 v dual supply v dd = +5 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 1 typ v s = 4.5 v, i s = ?10 ma; see figure 24 1.2 1.4 1.6 max v dd = 4.5 v, v ss = 4.5 v on resistance match between channels (?r on ) 0.04 typ v s = 4.5 v, i s = ?10 ma 0.08 0.09 0.1 max on resistance flatness (r flat(on) ) 0.2 typ v s = 4.5 v, i s = ?10 ma 0.25 0.29 0.34 max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off ) 0.1 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 25 0.3 1 6 na max drain off leakage, i d (off ) 0.1 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 25 0.3 1 6 na max channel on leakage, i d , i s (on) 0.2 na typ v s = v d = 4.5 v; see figure 26 0.4 1.5 10 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh +0.005 0.1 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 t on 165 ns typ r l = 300 , c l = 35 pf 212 253 285 ns max v s = 2.5 v; see figure 31 t off 105 ns typ r l = 300 , c l = 35 pf 137 150 159 ns max v s = 2.5 v; see figure 31 break-before-make time delay, t d ( adg1613 only) 25 ns typ r l = 300 , c l = 35 pf 20 ns min v s1 = v s2 = 2.5 v; see figure 32 charge injection 140 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 33 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 channel-to-channel crosstalk 110 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise (thd + n) 0.007 % typ r l = 110 , 5 v p-p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth 42 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s (off ) 63 pf typ v s = 0 v, f = 1 mhz c d (off ) 63 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 154 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max v dd /v ss 3.3/8 v min/max 1 guaranteed by design, not subject to production test.
ADG1611/adg1612/adg1613 data sheet rev. b | page 4 of 16 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 0.95 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 24 1.1 1.25 1.45 max v dd = 10.8 v, v ss = 0 v on resistance match between channels (?r on ) 0.03 typ v s = 0 v to 10 v, i s = ?10 ma 0.06 0.7 0.08 max on resistance flatness (r flat(on) ) 0.2 typ v s = 0 v to 10 v, i s = ?10 ma 0.23 0.27 0.32 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.1 na typ v s = 1 v/10 v, v s = 10 v/1 v, see figure 25 0.3 1 6 na max drain off leakage, i d (off ) 0.1 na typ v s = 1 v/10 v, v s = 10 v/1 v see figure 25 0.3 1 6 na max channel on leakage, i d , i s (on) 0.2 na typ v s = v d = 1 v or 10 v; see figure 26 0.4 1.5 10 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 t on 125 ns typ r l = 300 , c l = 35 pf 156 190 215 ns max v s = 8 v; see figure 31 t off 75 ns typ r l = 300 , c l = 35 pf 87 93 99 ns max v s = 8 v; see figure 31 break-before-make time delay, t d ( adg1613 only) 35 ns typ r l = 300 , c l = 35 pf 30 ns min v s1 = v s2 = 8 v; see figure 32 charge injection 170 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 33 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 channel-to-channel crosstalk 110 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion + noise 0.012 % typ r l = 110 , 5 v p-p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth 38 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s (off ) 60 pf typ v s = 6 v, f = 1 mhz c d (off ) 60 pf typ v s = 6 v, f = 1 mhz c d , c s (on) 154 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 12 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 320 a typ digital inputs = 5 v 480 a max v dd 3.3/16 v min/max 1 guaranteed by design, not subject to production test.
data sheet ADG1611/adg1612/adg1613 rev. b | page 5 of 16 5 v single supply v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to 125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 1.7 typ v s = 0 v to 4.5 v, i s = ?10 ma; see figure 24 2.15 2.4 2.7 max v dd = 4.5 v, v ss = 0 v on resistance match between channels (?r on ) 0.05 typ v s = 0 v to 4.5 v, i s = ?10 ma 0.09 0.12 0.15 max on resistance flatness (r flat(on) ) 0.4 typ v s = 0 v to 4.5 v, i s = ?10 ma 0.53 0.55 0.6 max leakage currents v dd = 5.5 v, v ss = 0 v source off leakage, i s (off ) 0.05 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 25 0.3 1 6 na max drain off leakage, i d (off ) 0.05 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 25 0.3 1 6 na max channel on leakage, i d , i s (on) 0.15 na typ v s = v d = 1 v or 4.5 v; see figure 26 0.4 1.5 10 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 t on 215 ns typ r l = 300 , c l = 35 pf 279 334 376 ns max v s = 2.5 v; see figure 31 t off 115 ns typ r l = 300 , c l = 35 pf 150 169 180 ns max v s = 2.5 v; see figure 31 break-before-make time delay, t d ( adg1613 only) 35 ns typ r l = 300 , c l = 35 pf 25 ns min v s1 = v s2 = 2.5 v; see figure 32 charge injection 80 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 33 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 channel-to-channel crosstalk 110 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 28 total harmonic distortion + noise 0.093 % typ r l = 110 , f = 20 hz to 20 khz, v s = 3.5 v p-p; see figure 30 ?3 db bandwidth 42 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s (off ) 72 pf typ v s = 2.5 v, f = 1 mhz c d (off ) 72 pf typ v s = 2.5 v, f = 1 mhz c d , c s (on) 160 pf typ v s = 2.5 v, f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd 3.3/16 v min/max 1 guaranteed by design, not subject to production test.
ADG1611/adg1612/adg1613 data sheet rev. b | page 6 of 16 3.3 v single supply v dd = 3.3 v, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 3.2 3.4 3.6 typ v s = 0 v to v dd , i s = ?10 ma, v dd = 3.3 v, v ss = 0 v; see figure 24 on resistance match between channels (?r on ) 0.06 0.07 0.08 typ v s = 0 v to v dd , i s = ?10 ma on resistance flatness (r flat(on) ) 1.2 1.3 1.4 typ v s = 0 v to v dd , i s = ?10 ma leakage currents v dd = 3.6 v, v ss = 0 v source off leakage, i s (off ) 0.02 na typ v s = 0.6 v/3 v, v d = 3 v/0.6 v; see figure 25 0.3 1 6 na max drain off leakage, i d (off ) 0.02 na typ v s = 0.6 v/3 v, v d = 3 v/0.6 v; see figure 25 0.3 1 6 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 0.6 v or 3 v; see figure 26 0.4 1.5 10 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 350 ns typ r l = 300 , c l = 35 pf 493 556 603 ns max v s = 1.5 v; see figure 31 t off 190 ns typ r l = 300 , c l = 35 pf 263 286 300 ns max v s = 1.5 v; see figure 31 break-before-make time delay, t d ( adg1613 only) 25 ns typ r l = 300 , c l = 35 pf 18 ns min v s1 = v s2 = 1.5 v; see figure 32 charge injection 50 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 33 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 channel-to-channel crosstalk 110 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 28 total harmonic distortion + noise 0.18 % typ r l = 110 , f = 20 hz to 20 khz, v s = 2 v p-p; see figure 30 ?3 db bandwidth 52 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s (off ) 76 pf typ v s = 1.5 v, f = 1 mhz c d (off ) 76 pf typ v s = 1.5 v, f = 1 mhz c d , c s (on) 160 pf typ v s = 1.5 v, f = 1 mhz power requirements v dd = 3.6 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 1.0 a max v dd 3.3/16 v min/max 1 guaranteed by design, not subject to production test.
data sheet ADG1611/adg1612/adg1613 rev. b | page 7 of 16 continuous current per channel, s or d table 5. parameter 25c 85c 125c unit continuous current, s or d v dd = +5 v, v ss = ?5 v tssop ( ja = 150.4c/w) 175 119 70 ma maximum lfcsp ( ja = 48.7c/w) 280 175 95 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 150.4c/w) 206 135 84 ma maximum lfcsp ( ja = 48.7c/w) 336 203 108 ma maximum v dd = 5 v, v ss = 0 v tssop ( ja = 150.4c/w) 140 91 63 ma maximum lfcsp ( ja = 48.7c/w) 220 140 84 ma maximum v dd = 3.3 v, v ss = 0 v tssop ( ja = 150.4c/w) 140 98 70 ma maximum lfcsp ( ja = 48.7c/w) 228 150 91 ma maximum
ADG1611/adg1612/adg1613 data sheet rev. b | page 8 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. parameter rating v dd to v ss 18 v v dd to gnd ?0.3 v to +18 v v ss to gnd +0.3 v to ?18 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 630 ma (pulsed at 1 ms, 10% duty-cycle maximum) continuous current, s or d 2 data + 15% operating temperature range industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance (2-layer board) 150.4c/w 16-lead lfcsp, ja thermal impedance (4-layer board) 48.7c/w reflow soldering peak temperature, pb free 260c esd caution 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. 2 see . table 5
data sheet ADG1611/adg1612/adg1613 rev. b | page 9 of 16 pin configurations and function descriptions 1 2 3 4 5 6 7 8 d1 s1 v ss d4 s4 gnd in1 in4 16 15 14 13 12 11 10 9 d2 s2 v dd d3 in3 s3 nc in2 07981-002 top view (not to scale) ADG1611/ adg1612/ adg1613 nc = no connect figure 4. 16-lead tssop pin configuration 07981-003 pin 1 indicator 1 s1 2v ss 3 gnd 4 s4 11 v dd 12 s2 10 nc 9s3 5 d 4 6 i n 4 7 i n 3 8 d 3 1 5 i n 1 1 6 d 1 1 4 i n 2 1 3 d 2 top view (not to scale) ADG1611/ adg1612/ adg1613 notes 1. nc = no connect. 2. exposed pad tied to substrate, v ss . figure 5. 16-lead lfcsp pin configuration table 7. pin function descriptions pin no. 16lead tssop 16lead lfcsp nemonic description 1 15 in1 logic control input. 2 16 d1 drain terminal. this pin can be an input or output. 3 1 s1 source terminal. this pin can be an input or output. 4 2 v ss most negative power supply potential. 5 3 gnd ground (0 v) reference. 6 4 s4 source terminal. this pin can be an input or output. 7 5 d4 drain terminal. this pin can be an input or output. 8 6 in4 logic control input. 9 7 in3 logic control input. 10 8 d3 drain terminal. this pin can be an input or output. 11 9 s3 source terminal. this pin can be an input or output. 12 10 nc no connection. 13 11 v dd most positive power supply potential. 14 12 s2 source terminal. this pin can be an input or output. 15 13 d2 drain terminal. this pin can be an input or output. 16 14 in2 logic control input. not applicable 17 (epad) ep (epad) exposed pad. tied to substrate, v ss . table 8. ADG1611 / adg1612 truth table ADG1611 in adg1612 in switch condition 0 1 on 1 0 off table 9. adg1613 truth table logic (in) switch 1, switch 4 switch 2, switch 3 0 off on 1 on off
ADG1611/adg1612/adg1613 data sheet rev. b | page 10 of 16 typical performance characteristics 0.4 0.6 0.8 1.0 1.2 1.4 ?8 ?6 ?4 ?2 0 2 4 6 8 on resistance ( ? ) v s or v d voltage (v) t a = 25c v dd = +3.3v v ss = ?3.3v v dd = +5v v ss = ?5v v dd = +8v v ss = ?8v 07981-013 figure 6. on resistance as a function of v d (v s ) for dual supply 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 on resistance ( ? ) v s or v d voltage (v) v dd = 3.3v v ss = 0v v dd = 12v v ss = 0v v dd = 5v v ss = 0v v dd = 16v v ss = 0v t a = 25c 07981-014 figure 7. on resistance as a function of v d (v s ) for single supply 0.4 0.6 0.8 1.0 1.2 1.4 ?6?4?20246 on resistance ( ? ) v s or v d voltage (v) t a = +125c t a = +85c t a = +25c t a = ?40c t a = +125c t a = +85c t a = +25c t a = ?40c v dd = +5v v ss = ?5v 07981-011 figure 8. on resistance as a function of v d (v s ) for different temperatures, 5 v dual supply 0.4 0.6 0.8 1.0 1.2 1.4 024681012 on resistance ( ? ) v s or v d voltage (v) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v 07981-010 figure 9. on resistance as a function of v d (v s ) for different temperatures, 12 v single supply 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 on resistance ( ? ) v s or v d voltage (v) t a = +125c t a = +85c t a = +25c t a = ?40c t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 5v v ss = 0v 07981-012 figure 10. on resistance as a function of v d (v s ) for different temperatures, 5 v single supply 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 on resistance ( ? ) v s or v d voltage (v) v dd = 3.3v v ss = 0v t a = ?40c t a = +25c t a = +85c t a = +125c 07981-006 figure 11. on resistance as a function of v d (v s ) for different temperatures, 3.3 v single supply
data sheet ADG1611/adg1612/adg1613 rev. b | page 11 of 16 07981-032 temperature (c) leakage current (na) 0 20406080100120 i d (off) +, ? i d , i s (on) +, + i d (off) ?, + i s (off) +, ? i s (off) ?, + i d , i s (on) ?, ? ?15 ?10 ?5 0 5 10 15 20 figure 12. leakage currents as a function of temperature, 5 v dual supply temperature (c) leakage current (na) 0 20406080100120 i d (off) +, ? i d , i s (on) +, + i d (off) ?, + i s (off) +, ? i s (off) ?, + i d , i s (on) ?, ? ?15 ?20 ?10 ?5 0 5 10 15 20 25 0 7981-031 figure 13. leakage currents as a function of temperature, 12 v single supply ?5 0 5 10 15 20 0 20406080100120 leakage current (na) temperature (c) i d , i s (off) +, + i d , i s (off) ?, ? i d (off) ?, + i s (off) +, ? i d (off) +, ? i s (off) ?, + 07981-019 figure 14. leakage currents as a function of temperature, 5 v single supply 0 20 40 60 80 100 120 temperature (c) i d , i s (off) +, + i d , i s (off) ?, ? i d (off) ?, + i s (off) +, ? i d (off) +, ? i s (off) ?, + ?4 ?2 0 2 4 6 8 10 12 14 16 18 leakage current (na) 07981-030 figure 15. leakage currents as a function of temperature, 3.3 v single supply ?100 0 100 200 300 400 500 600 i dd ( a) 024681012 logic (v) i dd per channel t a = 25c v dd = +12v v ss = 0v v dd = +5v v ss = ?5v v dd = +5v v ss = 0v v dd = +3.3v v ss = 0v 07981-005 figure 16. i dd vs. logic level 0 50 100 150 200 250 300 ?6 ?4 ?2 0 2 4 6 8 10 12 14 charge injection (pc) v s (v) v dd = +12v v ss = 0v v dd = +5v v ss = 0v v dd = +3.3v v ss = 0v v dd = +5v v ss = ?5v 07981-009 figure 17. charge injection vs. source voltage (v s )
ADG1611/adg1612/adg1613 data sheet rev. b | page 12 of 16 0 50 100 150 200 250 300 350 400 500 450 ?60 ?40 ?20 0 20 40 60 80 100 120 140 time (ns) temperature (c) 07981-018 t off (+3.3v) t on (+3.3v) t off (+5v) t off (5v) t on (+5v) t off (+12v) t off (5v) t on (+12v) figure 18. t on /t off times vs. temperature ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ? 5 off isol a tion (db) frequency (hz) 100k 1m 10m 100m 1g 10k 1k t a = 25c v dd = +5v v ss = ?5v 07981-007 figure 19. off isol ation vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 crosstalk (db) frequency (hz) 100k 1m 10m 100m 1g 10k 1k t a = 25c v dd = +5v v ss = ?5v 07981-017 figure 20. crosstalk vs. frequency insertion loss (db) frequency (hz) 100k 1m 10m 100m 1g 10k 1k ?6 ?5 ?3 ?1 ?4 ?2 0 t a = 25c v dd = +5v v ss = ?5v 07981-004 figure 21. on response vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (hz) 100k 1m 10m 10k 1k t a = 25c v dd = +5v v ss = ?5v acpsrr (db) 07981-008 no decoupling capacitors decoupling capacitors figure 22. acpsrr vs. frequency 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 thd + n (%) frequency (hz) 15k 20k 10k 5k 25k r l = 110 ? t a = 25c v dd = +3.3v v s = 2v v dd = +5v v s = 3.5v v dd = +5v v ss = ?5v v s = 5v p-p v dd = +12v v s = 5v p-p 07981-016 figure 23. thd + n vs. frequency
data sheet ADG1611/adg1612/adg1613 rev. b | page 13 of 16 test circuits sx dx v s i s v1 r on = v1/i s 07981-020 figure 24. on resistance sx dx v s a a v d i s (off) i d (off) 0 7981-021 figure 25. off leakage sx dx a v d i d (on) nc nc = no connect 07981-022 figure 26. on leakage v out 50 ? network analyzer r l 50? inx v in sx dx 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 07981-026 figure 27. off isolation channel-to-channel crosstalk = 20 log v out gnd s1 dx s2 v out network analyzer r l 50? r l 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss 07981-027 figure 28. channel-to-channel crosstalk v out 50 ? network analyzer r l 50? inx v in sx dx insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 0 7981-028 figure 29. bandwidth
ADG1611/adg1612/adg1613 data sheet rev. b | page 14 of 16 v out r s audio precision r l 110 ? inx v in sx dx v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 07981-029 figure 30. thd + noise v s inx sx dx gnd r l 300 ? c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss adg1612 ADG1611 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 07981-023 figure 31. switching times v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300? c l 35pf v out2 v out1 v dd v ss 0.1f v dd 0.1f v ss v in v out1 v out2 adg1613 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300? c l 35pf 07981-024 figure 32. break-before-make time delay inx v out adg1612 ADG1611 v in v in v out off ? v out on q inj = c l ? v out sx dx v dd v ss v dd v ss v s r s gnd c l 1nf 07981-025 figure 33. charge injection
data sheet ADG1611/adg1612/adg1613 rev. b | page 15 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t on the delay between applying the digital control input and the output switching on. see figure 31 . t off the delay between applying the digital control input and the output switching off. see figure 31 . charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. see figure 33 . off isolation a measure of unwanted signal coupling through an off switch. see figure 27 . crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. see figure 28 . bandwidth the frequency at which the output is attenuated by 3 db. see figure 29 . on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. see figure 30 . ac power supply rejection ratio (acpsrr) the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
ADG1611/adg1612/adg1613 data sheet rev. b | page 16 of 16 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 34. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pa d bottom view 031006-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 35. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADG1611bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG1611bruz-reel ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG1611bruz-reel7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG1611bcpz-reel ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 ADG1611bcpz-reel7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 adg1612bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1612bruz-reel ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1612bruz-reel7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1612bcpz- reel ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 adg1612bcpz-reel7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 adg1613bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1613bruz-reel ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1613bruz-reel7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1613bcpz-reel ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 adg1613bcpz-reel7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-13 1 z = rohs compliant part. ?2009-2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07981-0-3/12(b)

▲Up To Search▲

Price & Availability of ADG1611

	To Download ADG1611 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .