View MT29F8G08DAAWCA_6486635.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by micron without notice. 4gb, 8gb, and 16gb x8 nand flash memory features pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__1.fm - rev. b 2/07 en 1 ?2006 micron technology, inc. all rights reserved. nand flash memory mt29f4g08aaa, mt29f8g08baa, mt29f8g08daa, mt29f16g08faa features ? single-level cell (slc) technology ? organization ? page size x8: 2,112 bytes (2,048 + 64 bytes) ? block size: 64 pages (128k + 4k bytes) ? plane size: 2,048 blocks ? device size: 4gb: 4,096 bl ocks; 8gb: 8,192 blocks; 16gb: 16,384 blocks ?read performance ? random read: 25s (max) ? sequential read: 25ns (min) ?write performance ? program page: 220s (typ) ? block erase: 1.5ms (typ) ? data retention: 10 years ? endurance: 100,000 program/erase cycles ? first block (block address 00h) guaranteed to be valid up to 1,000 program/erase cycles 1 ? industry-standard basic nand flash command set ? advanced command set: ? program page cache mode ? page read cache mode ? one-time programmable (otp) commands ? two-plane commands ? interleaved die operations ? read unique id (contact factory) ? read id2 (contact factory) ? operation status byte prov ides a software method of detecting: ? operation completion ? pass/fail condition ? write-protect status ? ready/busy# (r/b#) signal provides a hardware method of detecting operation completion ? wp# signal: write protect entire device ? reset required after power-up ? internal data move operations supported within the plane from which data is read figure 1: 48-pin tsop type 1 notes: 1. for further details, see ?error management? on page 58. 2. for part numbering and markings, see figure 2 on page 2. 3. ocpl = off-center parting line. 4. for et devices, contact factory. options ?density 2 ? 4gb (single die) ? 8gb (dual-die stack 1 ce#) ? 8gb (dual-die stack 2 ce#) ? 16gb (quad-die stack) ? device width: x8 ? configuration # of die # of ce# # of r/b# i/o 1 1 1 common 2 1 1 common 2 2 2 common 4 2 2 common ?v cc : 2.7?3.6v ?package ? 48 tsop type i (lead-free plating) ? 48 tsop type i ocpl 3 (lead-free plating) ? operating temperature ? commercial (0c to +70c) ? extended (?40c to +85c) 4
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__1.fm - rev. b 2/07 en 2 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory part numbering information part numbering information micron ? nand flash devices are available in several different configurations and densities (see figure 2). figure 2: part number chart notes: 1. for et devices, contact factory. valid part number combinations after building the part number from the part numbering chart, verify that the part number is offered and valid by using the micron parametric part search web site at www.micron.com/products/parametric . if the device required is not on this list, contact the factory. mt 29f 4g 08 a a a wp es :a micron technology product family 29f = single-supply nand flash memory density 4g = 4gb 8g = 8gb 16g = 16gb device width 08 = 8 bits operating voltage range a = 3.3v (2.70?3.60v) design revision a = first revision production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample operating temperature range blank = commercial (0c to +70c) et = extended 1 (-40c to +85c) reserved for future use blank flash performance blank = standard package code wp = 48-pin tsop i (lead-free) wc = 48-pin tsop i ocpl (lead-free) feature set a = feature set a classification # of die # of ce# # of r/b# i/o a 1 1 1 common b 2 1 1 common d 2 2 2 common f 4 2 2 common
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40atoc.fm - rev. b 2/07 en 3 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 page read 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 random data read 05h-e0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 page read cache mode start 31h; page read cache mode start last 3fh. . . . . . . . . . . . . . . . . .22 read id 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 read status 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 program page 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 serial data input 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 program page cache mode 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 read for internal data move 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 program for internal data move 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 block erase 60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 one-time programmable (otp) area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 otp data program a0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 otp data protect a5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 otp data read afh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 two-plane operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 two-plane addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 two-plane page read 00h-00h-30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 two-plane random data read 06h-e 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 two-plane program page 80h-11h-80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 two-plane program page cache mode 80h-11h-80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 two-plane internal data move 00h-00h-35h /85h-11h-80h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 t wo-plane read for internal data move 00h -00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 two-plane program for internal data move 85h-11h-80h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 two-plane block erase 60h-60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 two-plane/multiple-die read status 78h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 interleaved die operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 interleaved program page operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 interleaved program page cache mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 interleaved two-plane program page operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 interleaved two-plane program page cache mode operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 interleaved block erase operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 interleaved two-plane block erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 reset ffh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40atoc.fm - rev. b 2/07 en 4 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory table of contents write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 v cc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40alof.fm - rev. b 2/07 en 5 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory list of figures list of figures figure 1: 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 3: 48-pin tsop type 1 pin assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: nand flash functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 6: array organization for mt29f4g08aaa and mt29f8g08daa (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: array organization for mt29f8g08baa and mt29f16g08faa (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: ready/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 9: tfall and trise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 10: iol vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 11: tc vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 12: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 13: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 14: page read cache mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 15: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 16: status register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 17: program and read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 18: random data input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 19: program page cache mode operat ion example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 20: internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 21: internal data move operation with random data in put . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 22: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 23: otp data program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 24: otp data protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 25: otp data read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 26: two-plane page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 27: two-plane page read operation with random data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: two-plane program page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 29: two-plane program page operation with random data input . . . . . . . . . . . . . . . . . . . . . . .40 figure 30: two-plane program page cache mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 31: two-plane internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 32: two-plane internal data move operation with random data input . . . . . . . . . . . . . . . .44 figure 33: two-plane block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 34: two-plane/multiple-die read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 35: interleaved program page operatio n with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 36: interleaved program page operat ion with status register monitoring . . . . . . . . . . . . . . . . . . . . . .48 figure 37: interleaved program page cache mode operation with r/b# monitoring . . . . . . . . . . . . . . . . .48 figure 38: interleaved program page cache mode operat ion with status register monitoring . . . . . . . .49 figure 39: interleaved two-plane progra m page operation with r/b# monitoring. . . . . . . . . . . . . . . . . . .50 figure 40: interleaved two-plane prog ram page operation with status regi ster monitoring. . . . . . . . . .51 figure 41: interleaved two-plane pr ogram page cache mode operation with r/b# monitoring . . . .52 figure 42: interleaved two-plan e program page cache mode oper ation with status register monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 43: interleaved block erase operatio n with r/b# monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 44: interleaved block erase operatio n with status register monitoring. . . . . . . . . . . . . . . . . . . . . . . . .54 figure 45: interleaved two-plan e block erase operation with r/b# monitoring . . . . . . . . . . . . . . . . . . . . .55 figure 46: interleaved two-plane block erase operation with status register monitoring . . . . . . . . . . . .55 figure 47: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 48: erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 49: erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 50: program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 51: program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 52: ac waveforms during power transi tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 53: command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 54: address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 55: input data latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40alof.fm - rev. b 2/07 en 6 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory list of figures figure 56: serial access cycle after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 57: serial access cycle after read (e do mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 58: read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 59: two-plane/multiple-die read stat us operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 60: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 61: read operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 62: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 63: page read cache mode operation, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 64: page read cache mode operation, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 65: page read cache mode operation without r/b#, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2 figure 66: page read cache mode operation without r/b#, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 figure 67: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 68: program page op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 69: program op eration with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 70: program page op eration with random data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5 figure 71: internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 72: program page cache mode operat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 73: program page cache mo de operation ending on 15h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 7 figure 74: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 75: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 76: 48-pin tsop type 1 (wp package code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 77: 48-pin tsop ocpl type 1 (wc pa ckage code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40alot.fm - rev. b 2/07 en 7 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory list of tables list of tables table 1: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 2: operational example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 3: array addressing: mt29f4g08aaa and mt29f8g08daa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 4: array addressing: mt28f8g08baa and mt 29f16g08faa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 6: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: two-plane command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 8: device id and configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 9: status register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 10: status register contents after re set operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 11: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 12: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 13: m29fxgxxxaa 3v device dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 14: valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 15: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 16: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 17: ac characteristics: command, data, and address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 18: ac characteristics: normal operat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 19: program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 8 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory general description general description nand flash technology provides a cost-effec tive solution for applications requiring high-density, solid-state storage. the mt 29f4g08aaa is a 4gb nand flash memory device. the mt29f8g08baa is a two-die stack th at operates as a single 8gb device. the mt29f8g08daa is a two-die stac k that operates as two independent 4gb devices. the mt29f16g08faa is a four-die stack that op erates as two independent 8gb devices, providing a total storage capacity of 16gb in a single, space-saving package. micron nand flash devices include standard nand flash features as we ll as new features designed to enhance system-level performance. micron nand flash devices use a highly multiplexed 8-bit bus (i/o[7:0]) to transfer data, addresses, and instructions. the five command pins (cle, ale, ce#, re#, we#) implement the nand flash command bus inte rface protocol. additi onal pins control hardware write protection (wp#) an d monitor device status (r/b#). this hardware interface creates a low-pin-coun t device with a standard pinout that is the same from one density to another, allo wing future upgrades to higher densities without board redesign. the mt29f4g, mt29f8g, and mt29f16g devi ces contain two planes per die. each plane consists of 2,048 blocks. each block is subdivided into 64 programmable pages. each page consists of 2,112 bytes. the pages are further divided into a 2,048-byte data storage region with a separate 64-byte area. the 64-byte area is typically used for error management functions. the contents of each page can be programmed in 220s (typ), and an entire block can be erased in 1.5ms (typ). on-chip contro l logic automates program and erase oper- ations to maximize cycle endurance. program/erase endurance is specified at 100,000 cycles with appropriate error corr ection code (ecc) and error management.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 9 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory general description figure 3: 48-pin tsop type 1 pin assignment (top view) notes: 1. ce2# and r/b2# are available on 8gb 2-ce # devices and 16gb devices only. these pins are nc for other configurations. x8 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc x8 dnu nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc dnu or vs s vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc dnu dnu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 10 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory general description table 1: signal descriptions symbol type description ale input address latch enable: duri ng the time ale is high, address information is transferred from i/o[7:0] into the on-chip address registe r on the rising edge of we# . when address information is not bein g loaded, ale should be driven low. ce#, ce2# input chip enable: gates transfers between th e host system and the nand flash device. after the device starts a program or er ase operation, ce# can be de-asserted. for the 8gb configuration, ce# controls the first 4gb of memory; ce2# controls the second 4gb of memory. for the 16gb co nfiguration, ce# controls the first 8gb of memory; ce2# controls the second 8gb. see ?bus operation? on page 15 for additional operational details. cle input command latch enable: when cle is hi gh, information is transferred from i/o[7:0] to the on-chip co mmand register on the rising edge of we#. when command information is not being loaded, cle should be driven low. re# input read enable: gates transfers from the nand flash device to the host system. we# input write enable: gates transfers from the host system to the nand flash device. wp# input write protect: protects against inadve rtent program and er ase operations. all program and erase operations are disabled when wp# is low. i/o[7:0] (x8) i/o data inputs/outputs: the bi directional i/os transfer address, data, and instruction information. data is output only during read operations; at other times the i/os are inputs. r/b#, r/b2# output ready/busy: an open-drain , active-low output, that uses an external pull-up resistor. r/b# is used to indicate wh en the chip is proc essing a program or erase operation. it is also used during read op erations to indicate when data is being transferred from the array into the seri al data register. when these operations have completed, r/b# returns to the high-z state. in the 8gb configuration, r/b# is for the 4gb of memory enabled by ce#; r/b2# is for the 4gb of memory enabled by ce2#. in the 16gb configuration, r/b# is for the 8gb of memory enabled by ce#; r/b2# is for the 8gb of memory enabled by ce2#. v cc supply v cc : power supply. v ss supply v ss : ground connection. nc ? no connect: ncs are not in ternally connected. they can be driven or left unconnected. dnu ? do not use: dnus must be left unconnected.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 11 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory architecture architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. this provides a memory device with a low pin count. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. the addresses are latched by an address register and sent to a row decoder or a column decoder to select a row address or a column address, respectively. the data are transferred to or from the nand flash memory array, byte by byte (x8), through a data register and a cache register. the cache register is closest to i/o control circuits and acts as a data buffer for the i/o data, whereas the data register is closest to the memory array and acts as a data buffer for the nand flash memory array operation. the nand flash memory array is programmed and read in page-based operations and is erased in block-based operations. during normal page operations, the data and cache registers are tied together and act as a single register. during cache operations the data and cache registers operate independen tly to increase data throughput. these devices also have a status register th at reports the status of device operation. figure 4: nand flash functional block diagram address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# i/ox control logic i/o control r/b# row decode column decode nand flash array (2 planes)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 12 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory addressing addressing nand flash devices do not contain dedicate d address pins. addresses are loaded using a 5-cycle sequence as shown in tables 3 and 4, on pages 13 and 14. see figure 5 for addi- tional memory mapping and addressing details. memory mapping figure 5: memory map notes: 1. as shown in table 3 on page 13, the hi gh nibble of address cycle 2 has no assigned address bits; however, these 4 bits must be held low during the addr ess cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not ha ve address bits assigned to them. 2. the 12-bit column address is capable of addres sing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. bytes 2,112 through 4,095 of each page are ?out of bounds,? do not exist in the device, and cannot be addressed. table 2: operational example block page min address in page max address in page out of bounds addresses in page 0 0 0x0000000000 0x000000083f 0x0000000840?0x0000000fff 0 1 0x0000010000 0x000001083f 0x0000010840?0x0000010fff 0 2 0x0000020000 0x000002083f 0x0000020840?0x0000020fff ?? ? ? 4,095 62 0x03fffe0000 0x03fffe083f 0x03fffe0840?0x03fffe0fff 4,095 63 0x03ffff0000 0x03ffff 083f 0x03ffff0840?0x03ffff0fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? blocks 4gb, 8gb 2 ce#: ba[17:6] 8gb 1 ce#, 16gb: ba[18:6] pages pa[5:0] bytes ca[11:0] 012 012 63 0 1 2 2,047 ? ? ? 2,111 4,095 spare area 8gb 2 ce#: 4,096 blocks per ce# 8gb 1 ce#: 8,192 blocks per ce# 16gb: 8,192 blocks per ce#
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 13 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory array organization array organization figure 6: array organization fo r mt29f4g08aaa and mt29f8g08daa (x8) notes: 1. for the 8gb mt29f8g08daa, the 4gb array or ganization shown applies to each chip enable (ce# and ce2#). notes: 1. block address concatenat ed with page address = actual page address. cax = column address; pax = page address; bax = block address. 2. if ca11 is ?1,? then ca[10:6] must be ?0.? table 3: array addressing: mt29f4g08aaa and mt29f8g08daa cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low ba17 ba16 cache register data register 2,048 blocks per plane 4,096 blocks per device 1 block 1 block i/o0 i/o7 1 page = (2k + 64 bytes) 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 plane = (128k + 4k) bytes x 2,048 blocks = 2,112mb 1 device = 2,112mb x 2 planes = 4,224mb plane of even-numbered blocks (0, 2, 4, 6, ..., 4,092, 4,094) plane of odd-numbered blocks (1, 3, 5, 7, ..., 4,093, 4,095) 64 2,048 64 2,112 bytes 2,112 bytes 64 64 2,048 2,048 2,048
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 14 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory array organization figure 7: array organization fo r mt29f8g08baa and mt29f16g08faa (x8) notes: 1. die 0, plane 0: ba18 = 0; ba6 = 0. die 0, plane 1: ba 18 = 0; ba6 = 1. die 1, plane 0: ba 18 = 1; ba6 = 0. die 1, plane 1: ba 18 = 1; ba6 = 1. 2. for the 16gb mt29f16g08faa, the 8gb array orga nization shown here applies to each chip enable (ce# and ce2#). notes: 1. cax = column address; pax = page address; bax = block address. 2. if ca11 is 1, then ca[10:6] must be ?0.? 3. die address boundary: 0 = 0?4gb; 1 = 4gb?8gb. table 4: array addressing: mt28f8g08baa and mt29f16g08faa cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7ca6ca5ca4ca3ca2ca1ca0 second low low low low ca11 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low ba18 3 ba17 ba16 cache register data register 2,048 blocks per plane 4,096 blocks per die 1 block 1 block plane 0: even- numbered blocks (0, 2, 4, 6, ..., 4,092, 4,094) 1 plane 1: odd- numbered blocks (1, 3, 5, 7, ..., 4,093, 4,095) plane 0: even- numbered blocks (4,096, 4,098, ..., 8,188, 8,190) plane 1: odd- numbered blocks (4,097,4,099, ..., 8,189, 8,191) 64 2,048 64 2,112 bytes 2,112 bytes 64 64 2,048 2,048 2,048 1 block 1 block 64 2,048 64 2,112 bytes 2,112 bytes 64 64 2,048 2,048 2,048 1 page = (2k + 64 bytes) 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 plane = (128k + 4k) bytes x 2,048 blocks = 2,112mb 1 die = 2,112mb x 2 planes = 4,224mb 1 device = 4,224mb x 2 die = 8,448mb i/o0 i/o7 die 0 die 1
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 15 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory bus operation bus operation the bus on mt29fxxx devices is multiplexed. data i/o, addresses, and commands all share the same pins, i/o[7:0]. the command sequence normally consists of a command latch cycle, address input cycles, and 1 or more data cycles?either read or write. control signals ce#, we#, re#, cle, ale, and wp# control nand flash device read and write opera- tions. on the 8gb mt29f8g08daa, ce# and ce2# each control independent 4gb arrays. on the 16gb mt29f16g08faa, ce# and ce2# each control independent 8gb arrays. ce2# functions the same as ce# for its own ar ray; all operations described for ce# also apply to ce2#. ce# is used to enable the device. when ce# is low and the device is not in the busy state, the nand flash memory will accept command, address, and data information. when the device is not performing an operat ion, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power consumption. see figure 61 on page 69 and figure 69 on page 75 for examples of ce# ?don?t care? operations. the ce# ?don?t care? operation enables the nand flash to reside on the same asyn- chronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flas h is busy with internal operations. this capability is important for designs that re quire multiple nand flash devices on the same bus. a high cle signal indicates th at a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. commands commands are written to the command register on the rising edge of we# when: ? ce# and ale are low, and ?cle is high, and ? the device is not busy as exceptions, the device accepts the read status, two-plane/multiple-die read status, and reset commands when busy. commands are transferred to the command register on the rising edge of we# (see figure 53 on page 65). commands are input on i/o[7:0]. address input addresses are written to the address register on the rising edge of we# when: ? ce# and cle are low, and ?ale is high addresses are input on i/o[7:0]. bits not part of the address space must be low. the number of address cycles required for each command varies. refer to the command descriptions to determine addressi ng requirements (see table 6 on page 19).
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 16 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory bus operation data input data is written to the data register on the rising edge of we# when: ? ce#, cle, and ale are low, and ? the device is not busy data is input on i/o[7:0]. see figure 55 on page 66 for additional data input details. reads after a read command is issued, data is tran sferred from the memory array to the data register on the rising edge of we#. r/b# goes low for t r and transitions high after the transfer is complete. when data is available in the data register, it is clocked out of the part by re# going low. see figure 60 on page 68 for detailed timing information. the read status (70h) command, two-plane/multiple-die read status (78h) command, or the r/b# signal can be used to determine when the device is ready. if a controller is using a timing of 30ns or longer for t rc, use figure 56 on page 66 for proper timing. if t rc is less than 30ns, use figure 57 on page 67 for extended data output (edo) timing. ready/busy# the r/b# output provides a hardware me thod of indicating the completion of program, erase, and read operations. the signal requires a pull-up resistor for proper operation. the signal is typically high, and transitions to low after the appro- priate command is written to the device. the signal pin?s open-drain driver enables multiple r/b# outputs to be or-tied. the read status command can be used in place of r/b#. typically, r/b# is connected to an interrupt pin on the system controller (see figure 8 on page 17). on the 8gb mt29f8g08daa, r/b# provides a status indication for the 4gb section enabled by ce#, and r/b2# does the same fo r the 4gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 4gb section. on the 16gb mt29f16g08faa, r/b# provides a status indication for the 8gb section enabled by ce#, and r/b2# does the same fo r the 8gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 8gb section. the combination of rp and capacitive loadin g of the r/b# circuit determines the rise time of the r/b# pin. the actual value used for rp depends on the system timing requirements. large values of rp cause r/b# to be delayed significantly. at the 10 to 90 percent points on the r/b# waveform, rise time is approximately two time constants (tc). the fall time of the r/b# signal is determ ined mainly by the output impedance of the r/b# pin and the total load capacitance. refer to figures 10 and 11 on page 18, which depict approximate rp values using a circuit load of 100pf. tc r c = where r = rp (resistance of pull-up resi stor), and c = total capacitive load.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 17 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory bus operation the minimum value for rp is determined by the output drive capability of the r/b# signal, the output voltage swing, and v cc . figure 8: ready/busy# open drain figure 9: t fall and t rise notes: 1. t fall and t rise calculated at 10 perc ent and 90 percent points. 2. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 3. t fall 10ns at 3.3v. 4. see tc values in figure 11 on page 18 for approximate rp value and tc. rp min 3.3v part , () v cc max () v ol max () ? i ol il + --------------------------------------------------------------- 3.2 v 8 ma il + -------------------------- == where il is the sum of the input currents of all devices tied to the r/b# pin. rp r/b# open drain output v cc gnd device i ol 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 ?1 0 2 4 0 2 4 6 t fall t rise tc v vcc 3.3
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 18 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory bus operation figure 10: i ol vs. rp figure 11: tc vs. rp notes: 1. wp# should be biased to cmos high or low for standby. 2. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . table 5: mode selection cle ale ce# we# re# wp# mode hll hx read mode command input lhl hx address input hll hh write mode command input lhl hh address input lll hh data input lllh x sequential read and data output xxxhhx during read (busy) xxxxxh during program (busy) xxxxxh during erase (busy) xxxxxl write protect x x h x x 0v/vcc 1 standby 3.50ma 3.00ma 2.50ma 2.00ma 1.50ma 1.00ma 0.50ma 0.00ma 0 2,000 4,000 6,000 8,000 10,000 12,000 rp i i ol at 3.60v (max) 1.20s 1.00s 800ns 600ns 400ns 200ns 0ns 0 2k 4k 6k 8k 10k 12k rp t i ol at 3.60v (max) rc = tc c = 100pf
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 19 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions command definitions notes: 1. indicates required data cycles be tween command cycle 1 and command cycle 2. 2. do not cross block address boundaries when using page read cache mode operations. 3. do not cross plane address boundaries when using read for internal data move and program for internal data move. see tabl es 3 and 4 on pages 13 and 14 for plane address boundary definitions. 4. the random data read command is li mited to use within a single page. 5. these commands are valid duri ng busy when performing an interleaved die operation. see ?interleaved die oper ations? on page 47 for additional details. 6. the random data input command is limited to use within a single page. table 6: command set command command cycle 1 number of address cycles data cycles required 1 command cycle 2 valid during busy notes page read 00h 5 no 30h no page read cache mode 31h ? no ? no 2 page read cache mode last 3fh ? no ? no 2 read for internal data move 00h 5 no 35h no 3 random data read 05h 2 no e0h no 4 read id 90h 1 no ? no read status 70h ? no ? yes program page 80h 5 yes 10h no 5 program page cache mode 80h 5 yes 15h no 5 program for internal data move 85h 5 optional 10h no 3 random data input 85h 2 yes ? no 6 block erase 60h 3 no d0h no 5 reset ffh ? no ? yes otp data program a0h 5 yes 10h no otp data protect a5h 5 no 10h no otp data read afh 5 no 30h no
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 20 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions notes: 1. do not cross plane addr ess boundaries when using two- plane read for internal data move and two-plane program for intern al data move. see tables 3 and 4 on pages 13 and 14 for plane addr ess boundary definitions. 2. the two-plane random data read command is limited to use with the two-plane page read command. 3. the two-plane/multiple-die read status command can be used to check status with two-plane and multiple-die operations, ex cluding the two-plane page read (00h-00h- 30h) command. 4. these commands are valid duri ng busy when performing in terleaved die op erations. see ?interleaved die oper ations? on page 47 for additional details. table 7: two-plane command set command command cycle 1 number of address cycles command cycle 2 number of address cycles command cycle 3 valid during busy notes two-plane page read 00h 5 00h 5 30h no two-plane read for internal data move 00h 5 00h 5 35h no 1 two-plane random data read 06h 5 e0h ? ? no 2 two-plane/multiple-die read status 78h 3 ? ? ? yes 3 two-plane program page 80h 5 11h-80h 5 10h no 4 two-plane program page cache mode 80h 5 11h-80h 5 15h no 4 two-plane program for internal data move 85h 5 11h-80h 5 10h no 1 two-plane block erase 60h 3 60h 3 d0h no 4
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 21 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions read operations page read 00h-30h at power-on, the device defaults to read mode. to enter read mode while in opera- tion, write the 00h command to the command register, then write 5 address cycles, and conclude with the 30h command. to determine the progress of the data transfer from the nand flash array to the data register ( t r), monitor the r/b# signal or, alternatively, issue a read status (70h) command. if the read status command is us ed to monitor the data transfer, the user must reissue the read (00h) command to receive data output from the data register. see figure 65 on page 72 and figure 66 on page 73 for examples. after the read command has been reissued, pulsing the re# line will re sult in outputting data, starting from the initial column address. a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data regist er, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address and going to the end of the page, read the data by repeatedly pulsing re# at the maximum t rc rate (see figure 12). figure 12: page read operation re# ce# ale cle i/ox 00h address (5 cycles) data output ( serial access) 30h r/b# we# t r don?t care
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 22 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions random data read 05h-e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h-30h) sequence. random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (2 cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing the re# pin outputs data sequentially (see figure 13). figure 13: random data read operation page read cache mode start 31h; page read cache mode start last 3fh micron nand flash devices have a cache register that can be used to increase the read operation speed when accessing se quential pages within a block. first, issue a normal page read (00h?30h) command sequence. see figure 14 on page 23 for operation details. the r/b# signal goes low for t r during the time it takes to transfer the first page of data from the memory to the data register. after r/b# returns to high, the page read cache mode star t (31h) command is latched into the command register. r/b# goes low for t dcbsyr1 while data is being transferred from the data register to the cache register. after the data register contents are transferred to the cache register, another page read is automatically started as part of the 31h command. data is transferred from the next sequential page of the memory array to the data register during the same time data is being read serially (pulsing re#) from the cache register. if the total time to output data exceeds t r, then the page read is hidden. the second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. r/b# will stay low up to t dcbsyr2. this time can vary, depending on whether the previous memory -to-data-register transfer was completed prior to issuing the next 31h command. see table 18 on page 63 for timing parameters. if the data transfer from memory to the da ta register is not completed before the 31h command is issued, r/b# stays low until the transfer is complete. it is not necessary to output a whole page of data before issuing another 31h command. r/b# will stay low until the previous page read is complete and the data has been transferred to the cache register. to read out the last page of data, the page read cache mode start last (3fh) command is issued. this command transfers da ta from the data register to the cache register without issuing another page read (see figure 14 on page 23). crossing block address boundaries when using the page read cache mode opera- tion is prohibited. re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r/b# t r
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 23 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 14: page read cache mode operation re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) data output (serial access) 31h 30h 31h 3fh r/b# we# t r data output (serial access) t dcbsyr1 t dcbsyr2 t dcbsyr2 don?t care
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 24 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions read id 90h the read id command is used to read the 5 bytes of identifier code programmed into the nand flash devices. the read id command reads a 5-byte table that includes manufacturer id, device configuration, and part-specific information (see table 8 on page 25). writing 90h to the command register puts the device into the read id mode. the command register stays in this mode unti l the next command cycle is issued (see figure 15). figure 15: read id operation notes: 1. see table 8 on page 25 for byte definitions. w e# ce# ale cle re# i/ox address, 1 cycle 90h 00h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 25 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions notes: 1. b = binary; h = hex. 2. the mt29f8g08daa device id code reflec ts the configuration of each 4gb section. 3. the mt29f16g08faa device id code reflec ts the configuration of each 8gb section. table 8: device id and configuration codes options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 notes byte 0 manufacturer id micron 001011002ch byte 1 device id mt29f4g08aaa 4gb, x8, 3v 11011100dch mt29f8g08baa 8gb, x8, 3v 11010011d3h mt29f8g08daa 8gb, x8, 3v 11011100dch2 mt29f16g08faa 16gb, x8, 3v 11010011d3h3 byte 2 number of die per ce 1 0 0 00b 2 0 1 01b cell type slc 0 0 00b number of simultaneously programmed pages 2 0 1 01b interleaved operations between multiple die on the same ce# not supported 00b supported 11b cache programming supported 11b byte value mt29f4g08aaa1001000090h mt29f8g08baa 1 1 0 1 0 0 0 1 d1h 3 mt29f8g08daa1001000090h 2 mt29f16g08faa 1 1 0 1 0 0 0 1 d1h 3 byte 3 page size 2kb 0 1 01b spare area size (bytes) 64b 11b block size (w/o spare) 128kb 0 1 01b organization x8 00b serial access (min) 25ns 1 0 1xxx0b byte value mt29fxg08xaa 1 0 0 1 0 1 0 1 95h byte 4 reserved 0 0 00b planes per ce# 2 0 1 01b 4 1 0 10b plane size 2gb 1 0 1 101b reserved 00b byte value mt29f4g08aaa0101010054h mt29f8g08baa 0 1 0 1 1 0 0 0 58h mt29f8g08daa0101010054h 2 mt29f16g08faa 0 1 0 1 1 0 0 0 58h 3
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 26 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions read status 70h these nand flash devices have an 8-bit status register the software can read during device operation. table 9 describes the status register. after a read status command, all read cycles will be from the status register until a new command is issued. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to start a new read status cycle to see these changes. in devices that have more than one die sharing a common ce# pin, the read status (70h) command reports the status of the die th at was last addressed. if interleaved oper- ations are started on both die, then the two-plane/multiple-die read status (78h) command must be used to select the di e that should report status. in this situa- tion, using the read status (70h) command wi ll result in bus contention, as both die will respond until the next operation is issued. while monitoring the status register to determine when the t r (transfer from nand flash array to data register) is complete, the user must reissue the read (00h) command to make the change from status to read mode. after the read command has been reis- sued, pulsing the re# line will result in outp utting data, starting from the initial column address. notes: 1. status register bit 0 reports a ?1? if a two-plane program page or two-plane block erase operation fails on one or both planes. status register bit 1 reports a ?1? if a two- plane program page cache mode operation fails on one or both planes. use two- plane/multiple-die read status (78h) to de termine the plane to which the operation failed. 2. status register bit 5 is ?0? during the actual programming operation. if cache mode is used, this bit will be ?1? when all in ternal operations are complete. 3. status register bit 6 is ?1? wh en the cache is ready to accept new data. r/b# follows bit 6. see figure 19 on page 29 and figure 73 on page 77. table 9: status register bit definition sr bit program page program page cache mode page read page read cache mode block erase definition 0 1 pass/fail pass/fail (n) ? ? pass/fail 0 = successful program/erase 1 = error in program/erase 1 ? pass/fail (n-1) ? ? ? 0 = successful program 1 = error in program 2? ? ? ? ? 0 3? ? ? ? ? 0 4? ? ? ? ? 0 5 ready/busy ready/busy 2 ready/busy ready/busy 2 ready/busy 0 = busy 1 = ready 6 ready/busy ready/busy cache 3 ready/busy ready/busy cache 3 ready/busy 0 = busy 1 = ready 7 write protect write protect write protect write protect write protect 0 = protected 1 = not protected
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 27 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 16: status register operation program operations program page 80h-10h micron nand flash devices are inherently page-programmed devices. pages must be programmed consecutively within a block, fr om the least significant page address to most significant page address (that is, 0, 1, 2, ?, 63). random page address program- ming is prohibited. micron nand flash devices also support partial-page programming operations. this means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of four programming opera- tions are supported before an erase is required. serial data input 80h program page operations require loading the serial data input (80h) command into the command register, followed by 5 addr ess cycles, then the data. serial data is loaded on consecutive we# cycles starting at the given address. the program (10h) command is written after the data input is complete. the control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. write verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of array programming time, t prog. the read status (70h) command and the reset (ffh) command are the only commands valid during the programming operation. bit 6 of the status re gister will reflect the state of r/b#. when the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see figure 17 on page 28). the command register stays in read status register mode until anot her valid command is written to it. random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h ) command. the random data input command can be used any number of times in the same page prior to issuing the page write (10h) command. see figure 18 on page 28 for the proper command sequence. 70h ce# cle we# re# i/ox status output t rea t clr
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 28 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 17: program and read status operation figure 18: random data input operation program page cache mode 80h-15h cache programming is actually a buffere d programming mode of the standard program page command. programming is started by loading the serial data input (80h) command to the command register, followed by 5 cycles of address and a full or partial page of data. the data is in itially copied into the cache register, and the cache program (15h) command is then latched to the command register. data is transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. th e time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and subsequent programming passes, transfer from the cache register to the data register is held off until current data register cont ent has been programmed into the array. the program page cache mode command can cross block address boundaries; it must not cross die address boundaries. random data input (85h) commands are permitted with program page cache mode operations. bit 6 (cache r/b#) of the status register can be read by issuing the read status (70h) command to determine when the cache register is ready to accept new data. the r/b# pin always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual program- ming of the array is complete for the current programming cycle. if just the r/b# pin is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache program (15h) command. if the cache program (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete (see figure 19 on page 29). i/ox 80h address (5 cycles) 10h 70h r/b# t prog status i/o 0 = 0 program successful i/o 0 = 1 program error d in i/ox 80h address (5 cycles) 85h address (2 cycles) 10h 70h r/b# t prog d in d in status
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 29 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions bit 0 of the status register returns the pass/f ail for the previous page when bit 6 of the status register is a ?1? (ready state). the pass/fail status of the current program opera- tion is returned with bit 0 of the status regist er when bit 5 of the status register is a ?1? (ready state) as shown in figure 19. figure 19: program page cache mode operation example notes: 1. see note 3, table 19 on page 64. 2. check i/o[6:5] for inte rnal ready/busy. check i/o[1:0] fo r pass/fail status. re# can stay low or pulse multiple times after a 70h command. internal data move an internal data move requires two comm and sequences. issue a read for internal data move (00h-35h) command first, then the program for internal data move (85h-10h) command. data moves are only supported within the plane from which data is read. moving data from odd to even blocks, from even to odd blocks, and across die boundaries is prohibited. read for internal data move 00h-35h the read for internal data move (00h-35h) command is used in conjunction with the program for internal data move (85h-10h) command. first, 00h is written to the command register, then the internal source address is written (5 cycles). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. the written column addresses are ignored even though all 5 address cycles are required. the memory device is now ready to accept the program for internal data move command. please refer to the description of this command in the following section. program for internal data move 85h-10h after the read for internal data move (00h-35h) command has been issued and r/b# goes high, the program for internal data move (85h-10h) command can be written to the command register. this command transfers the data from the cache register to the data register and programming of the new destination page begins. the sequence: 85h, destination address (5 cycles), then 10h, is written to the device. after 10h is written, r/b# goes low while the control logic automatically programs the new page. the read t cbsy r/b# i/ox r/b# i/ox address & data input 80h 15h address & data input 80h 15h address & data input 80h 15h address & data input 80h 10h t lprog 1 t cbsy address & data input 80h 15h address & data input 80h 10h status output 2 70h t lprog 1 status output 2 70h a: without status reads b: with status reads t cbsy t cbsy
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 30 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions status command can be used instead of the r/b# line to determine when the write is complete. when status register bit 6 = 1, bit 0 of the status register indicates if the opera- tion was successful. the random data input (85h) command can be used during the program for internal data move command sequence to modify one or more bytes of the orig- inal data. first, data is copied into th e cache register using the 00h-35h command sequence, then the random data input (8 5h) command is written along with the address of the data to be modified next. new da ta is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data are transferred to the data register, and programming of the new page is started. the random data input command can be issued as many times as necessary before starting the programming sequence with 10h (see figures 20 and 21). because internal data move operations do not use external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page contains a bit error due to charge loss or charge gain. in the case that multiple internal data mo ve operations are performed, these bit errors may accumulate without correction. for this reason, it is highly recommended that systems using internal data move operations also use a robust ecc scheme that can correct two or more bits per sector. figure 20: internal data move operation notes: 1. internal data move operations are only su pported within the plane from which data is read. figure 21: internal data move operation with random data input block erase operation block erase 60h-d0h erasing occurs at the block level. for ex ample, the mt29f4g08aaa device has 4,096 erase blocks, organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes). each block is 132k bytes (1 28k + 4k bytes). the block erase command operates on one block at a time (see figure 22 on page 31). three cycles of addresses ba[18:6] and pa[5:0] are required. although page addresses pa[5:0] are loaded, they are a ?don?t care? and are ignored for block erase opera- tions. see table 3 on page 13 for addressing details. i/ox 00h address (5 cycles) 35h 85h address (5 cycles) 10h 70h r/b# t prog t r status i/ox 00h address (5 cycles) 35h 85h address (5 cycles) data data 85h address (2 cycles) unlimited number of repetitions 10h 70h status r/b# t prog t r
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 31 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions the actual command sequence is a two-step process. the erase setup (60h) command is first written to the command register. then 3 cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command register. at the rising edge of we#, r/b# goes low and the control logic auto- matically controls the timing and erase-verify operations. r/b# stays low for the entire t bers erase time. the read status (70h) command can be used to check the status of the block erase operation. when bit 6 = 1, the erase operation is complete. bit 0 indicates a pass/fail condition where 0 = pass (see figure 22, and table 9 on page 26). figure 22: block erase operation one-time programmable (otp) area this micron nand flash device offers a protected, one-time programmable nand flash memory area. ten full pages (2,112 bytes per page) of otp data is available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. customers can use the otp area in any way they desire; typical uses include programming serial nu mbers or other data for permanent storage. in micron nand flash devices, the otp area leaves the factory in a non-written state (all bits are ?1s?). programming or part ial-page programming enables the user to program only ?0? bits in the otp area. the ot p area cannot be erased, even if it is not protected. protecting the otp area simply prevents further programming of the otp area. while the otp area is referred to as ?one-time programmable,? micron provides a unique way to program and verify data?before permanently protecting it and preventing future changes. re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h r/b# we# t bers don?t care i/o 0 = 0 erase successful i/o 0 = 1 erase error
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 32 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions otp programming and protection are accompli shed in two discrete operations. first, using the otp data program (a0h-10h) command, an otp page is programmed entirely in one operation or in up to four partial-page programming sequences. programming can occur on other pages within the otp area in a similar manner. second, the otp area is permanently protected from further programming using the otp data protect (a5h-10h) command. the pages within the otp area can always be read using the otp data read (afh-30h) command, whether or not it is protected. to determine whether or not the device is bu sy during an otp operation, either monitor r/b# or use the read status (70h) command. use of the two-plane/multiple- die read status (78h) command is prohibit ed during and following otp operations. otp data program a0h-10h the otp data program (a0h-10h) command is used to write data to the pages within the otp area. an entire page can be programmed at one time, or a page can be partially programmed up to four times. there is no erase operation for the otp pages. the otp data program enables programming into an offset of an otp page, using the two bytes of column address (ca[11:0]). the command is not compatible with the random data input (85h) command. the otp data program command will not execute if the otp area has been protected. to use the otp data program command, issue the a0h command. issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. next, write from 1 to 2,112 bytes of data. after data input is complete, issue the 10h command. the internal control logic automatically execut es the proper programming algorithm and controls the necessary timing for programm ing and verification. program verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low during the duration of the array programming time ( t prog). the read status (70h) command is the only comma nd valid during the otp data program operation. bit 5 of the status register will reflec t the state of r/b#. if bit 7 is ?0,? then the otp area has been protected; otherwise, it will be a ?1.? when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 9 on page 26). it is possible to program each otp page a maximum of four times.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 33 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 23: otp data program operation notes: 1. the otp page must be within the 02h?0bh range. we# ce# ale cle re# r/b# i/ox don?t care otp data written (following ?good? status confirmation) t wc t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 2,112 bytes a0h col add 1 col add 2 d in n d in m 00h 00h 10h 70h status otp page 1 t wb
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 34 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions otp data protect a5h-10h the otp data protect (a5h-10h) command is used to protect all the data in the otp area. after the data is protected it cannot be programmed further. when the otp area is protected, the pages within the area are no longer programmable and cannot be unpro- tected. to use the otp data protect command, issue the a5h command. next, issue the following 5 address cycles: 00h-00h-01h- 00h-00h. finally, issue the 10h command. r/b# goes low while the otp area is being protected. the protect command duration is similar to a normal page programming operation, t prog. the read status (70h) command is the only command valid during the otp data protect operation. bit 5 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 9 on page 26). figure 24: otp data protect operation notes: 1. otp data is protected foll owing ?good? status confirmation. otp data read afh-30h the otp data read (afh-30h) command is used to read data from a page within the otp area. an otp page within the otp area is available for reading data whether or not the area is protected. to use the otp data read command, issue the afh command. next, issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. finally, issue the 30h command. w e# ce# ale cle re# r/b# i/ox don?t care t wc t wb t prog otp data protect command otp data protected 1 program command read status command a5h col 00h col 00h 10h 70h status 01h 00h 00h
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 35 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command and the reset (ffh) command are the only commands valid during the otp data read operation. bi t 5 of the status register will reflect the state of r/b#. for details, refer to table 9 on page 26. normal read operation timings apply to otp read accesses (see figure 25). additional pages within the otp area can be selected by repeating the otp data read command. figure 25: otp data read operation notes: 1. the otp page must be within the 02h?0bh range. two-plane operations this nand flash device is divided into tw o physical planes. each plane contains a 2,112-byte data register, a 2,112-byte cache register, and a 2,048-block nand flash array. two-plane commands make better use of the flash arrays on these physical planes by performing program, read, or erase operations simultaneously, signifi- cantly improving system performance. two-plane addressing two-plane commands require two addresse s, one address per plane. these two addresses are subject to the following requirements: ? the least significant block address bit, ba 6, must be different for the two addresses. ? the most significant block address bit, ba18 for 16gb devices and for 8gb devices with 1 ce#, must be identical for each plane. ? the page address bits, pa[5:0], must be identical for both addresses. we# ce# ale cle re# r/b# i/ox busy t r d out n d out n + 1 d out m afh 00h 00h 30h don?t care otp page 1 col add 2 col add 1
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 36 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions two-plane page read 00h-00h-30h the two-plane page read (00h-00h-30h) operation is similar to the page read (00h-30h) operation. it transfers two pages of data from the nand flash array to the data registers. each page must be from a different plane on the same die. to enter the two-plane page read mode, write the 00h command to the command register, then write 5 address cycles fo r plane 0 (ba6 = 0). next, write the 00h command to the command register, then write 5 address cycles for plane 1 (ba6 = 1). finally, issue the 30h command. the first-pl ane and second-plane addresses must meet the two-plane addressing requirements and, in addition, they must have identical column addresses. after the 30h command is written, page data is transferred from both planes to their respective data registers in t r. during these transfers, r/b# goes low. when the trans- fers are complete, r/b# goes high. to read out the data from the plane 0 data register, pulse re# repeatedly. after the data cycle from the plane 0 address completes, issue a two-plane random data read (06h-e0h) command to select the plane 1 address, then repeatedly pulse re# to read out th e data from the plane 1 data register. alternatively, the read status (70h) command can monitor data transfers. when the transfers are complete, status register bit 6 is se t to ?1.? to read data from the first of the two planes, the user must first issue th e two-plane random data read (06h-e0h) command (see ?two-plane random data read 06h-e0h?) and pulse re# repeat- edly. when the data cycle is complete, issue a two-plane random data read (06h- e0h) command to select the other plane. to output the data beginning at the specified column address, pulse re# repeatedly. use of the two-plane/multiple-die read status (78h) command is prohibited during and following a two-plane page read operation. two-plane random data read 06h-e0h the two-plane random data read (06h-e0h) command is similar to the random data read (05h-e0h) command, except that it requires 5 address cycles rather than 2. the command selects a die and plane, and a column address from which to read data after a two-plane page read (00h-00h-30h) command. to issue a two-plane random data read command, issue the 06h command, then 5 address cycles, and follow with the e0h command. pulse re# repeatedly to read data from the new plane, beginning at the specified column address. the primary purpose of the two-plane rand om data read command is to select a new die and plane, and a column address within that die and plane. if a new die and plane do not need to be selected, then it is possible to use the random data read (05h-e0h) command instead (see ?rando m data read 05h-e0h? on page 22).
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 37 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 26: two-plane page read operation notes: 1. column and page addresses must be the same. 2. the least significant block address bit, ba6, must no t be the same for the first- and second-plane addresses. cle we# ale re# i/ox r/b# cle we# ale re# i/ox r/b# 00h col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 col add 1 col add 2 row add 1 row add 2 row add 3 00h 30h d out 0d out 1d out 06h e0h d out 0d out 1d out t r plane 0 address column address j plane 1 address plane 1 address plane 0 data plane 1 data page address m page address m 1 1 column address j
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 38 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 27: two-plane page read operation with random data read r/b# re# i/ox r/b# re# i/ox 00h 00h address (5 cycles) 05h e0h 30h t r plane 0 address plane 0 data plane 0 data address (5 cycles) address (2 cycles) data output data output plane 1 address 06h 05h e0h e0h plane 1 data plane 1 data address (5 cycles) address (2 cycles) data output data output plane 1 address 1 1
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 39 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions two-plane program page 80h-11h-80h-10h the two-plane program page (80h-11h-80h-10h) operation is similar to the program page (80h-10h) operation. it prog rams two pages of data from the data registers to the flash arrays. the pages must be programmed to different planes on the same die. within a block, the pages must be programmed consecutively from the least significant to most significant page address. random page programming within a block is prohibited. the first-plane address and the second-plane address must meet the two- plane addressing requirements (see ?two-plane addressing? on page 35). to begin the two-plane program page op eration, write the 80h command to the command register; write 5 address cycles for th e first plane; then write the data. serial data is loaded on consecutive we# cycles starting at the given address. next, write the 11h command. the 11h command is a ?dummy? command that informs the control logic that the first set of data for the firs t plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read status (70h) command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t dbsy are read status (70h) and reset (ffh). after t dbsy, write the 80h (or 81h) command to the command register; write 5 address cycles for the second plane; then write the data. the program (10h) command is written after the second -plane data input is complete. after the 10h command is written, the contro l logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operations to both planes. write verification only detect s ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of the array programming time ( t prog). when programming and verification are complete, r/b# returns high. the read status (70h) command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t prog are read status (70h), two-plane/ multiple-die read status (78h), and reset (ffh). when the device is ready, if the read status (70h) command indicates an error in the operation (status register bit 0 = 1), use the two-plane/multiple-die read status (78h) command twice?once for each plane?to determine which plane opera- tion failed. during serial data input for either plan e, the random data input (85h) command can be used any number of times to change the column address within that plane. for details on this command, see ?random data input 85h? on page 27. figure 28 shows two-plane program page operation. figure 28: two-plane program page operation r/b# i/ox 80h address (5 cycles) 70h 10h 11h 80h (or 81h) t dbsy t prog 1st plane address address (5 cycles) data input data input status 2nd plane address
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 40 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 29: two-plane program page operation with random data input two-plane program page cache mode 80h-11h-80h-15h the two-plane program page cache mode (80h-11h-80h-15h) operation is similar to the program page cache mode (80h-15h) operation. it programs two pages of data from the data registers to the nand flash arrays. the pages must be programmed to different planes on the same die. within a block, the pages must be programmed consecutively from the least significant to the most significant page address. random page programming within a block is prohibited. the first-plane and second-plane addresses must meet the two-plane addressing requirements (see ?two- plane addressing? on page 35). to enter the two-plane program page cache mode, write the 80h command to the command register, write 5 address cycles for the first plane, then write the data. serial data is loaded on consecutive we# cycles starting at the given address. next, write the 11h command. the 11h command is a ?dummy? command that informs the control logic that the first set of data for the firs t plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read status (70h) command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t dbsy are read status (70h) and reset (ffh). after t dbsy, write the 80h (or 81h) command to the command register, write 5 address cycles for the second plane, then write the data. the cache write (15h) command is written after the second-plane da ta input is complete. data is transferred from the cache registers to the data registers on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data registers and r/b# returns high, memory array programming to both planes begins. r/b# i/ox r/b# i/ox 80h address (5 cycles) 11h 80h (or 81h) 85h t dbsy t prog 1st plane address address (2 cycles) data input address (5 cycles) 2nd plane address data input data input 85h 10h address (2 cycles) 1 1 data input different column address than previous 5 address cycles, for 1st plane only different column address than previous 5 address cycles, for 2nd plane only repeat as many times as necessary repeat as many times as necessary
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 41 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions when r/b# returns high, new data can be written to the cache registers by issuing another two-plane program page cache mode (80h-11h-80h-15h) command sequence. the time that r/b# stays low ( t cbsy) is determined by the actual program- ming time of the previous operation. for the first cache operation, the duration of t cbsy is the time it takes for the data to be copied from the cache registers to the data registers. on the second and subsequent two-pl ane program page cache mode opera- tions, transfer from the cache registers to th e data registers is delayed until the current data register contents have been programmed into the arrays. if the r/b# pin is used to determine progra mming completion, the last operation of the program sequence must use the two-pl ane program page (80h-11h-80h-10h) command instead of the two-plane prog ram page cache mode (80h-11h-80h- 15h) command. if the two-plane program page cache mode (80h-11h-80h-15h) command is used for the last operation, then use read status (70h) to monitor opera- tion progress; status register bit 5 indicate s when programming is complete. see table 9 on page 26 for details of the status register. to determine when the current two-plane program page cache mode (80h- 11h-80h-10h) operation has completed, issue the read status (70h) command and check status register bits 5 and 6. when the device is ready, use status register bit 0 to determine if the current operation passed and status register bit 1 to determine if the previous operation passed. if either bit 0 or bi t 1 = 1, indicating a failed operation, then use the two-plane/multiple-die read status (78h) command twice?once for each plane?to determine which current or previous plane operation failed. for more information on status register bit definitions, see table 9 on page 26. during the serial data input for either plane, the random data input (85h) command can be used any number of times to change the column address within that plane. for details on this command, see ?random data input 85h? on page 27. see figure 29 on page 40 for an example.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 42 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 30: two-plane program page cache mode operation two-plane internal data move 00h-00h-35h/85h-11h-80h-10h a two-plane internal data move operation is similar to an internal data move operation, and requires two sequences. issue a two-plane read for internal data move (00h-00h-35h) command first, then the two-plane program for internal data move (85h-11h-80h-10h) command. data moves are only supported within the planes from whic h data is read. the first-plane and second- plane addresses must meet the two-plane ad dressing requirements for both the two- plane read for internal data move (00h-00h-35h) and two-plane program for internal data move (85h-11h-80h-10h) commands (see ?two-plane addressing? on page 35). t wo-plane read for internal data move 00h-00h-35h the two-plane read for internal data move (00h-00h-35h) command is used in conjunction with the two-plane program for internal data move (85h-11h- 80h-10h) command. first, write 00h to the command register, then write the first-plane internal source address (5 cycles). again, wr ite 00h to the command register, followed by the second-plane internal source address (5 cycles). finally, write 35h to the command register. after the 35h command, r/b# goes low for t r while two pages are read into their respective cache registers. r/b# i/ox 80h address/data input 11h 80h (or 81h) 15h t dbsy t cbsy 1st plane 2nd plane address/data input 1 1 2 r/b# i/ox 80h address/data input 11h 15h t dbsy t cbsy 1st plane 2nd plane address/data input 2 r/b# i/ox 80h address/data input 11h 10h t dbsy t lprog 1st plane 2nd plane address/data input 80h (or 81h) 80h (or 81h)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 43 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions the memory device is now ready to acce pt the two-plane program for internal data move (85h-11h-80h-10h) command. two-plane program for internal data move 85h-11h-80h-10h after the two-plane read for internal data move (00h-00h-35h) command has been issued and r/b# goes high (or the st atus register bit 6 is ?1?), the two-plane program for internal data move (85h -11h-80h-10h) command is used. pages must be read from and prog rammed to the same plane. first, write 85h to the command register, th en write the first-plane destination address (5 cycles), then write 11h to the command register. the 11h command is a ?dummy? command that informs the contro l logic that the first set of data for the first plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read status (70h) command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t dbsy are read status (70h) and reset (ffh). after t dbsy, write the 80h (or 81h) command to the command register, then write the second-plane destination address (5 cycles), then write 10h to the command register. data is transferred from the cache registers to the data registers on the rising edge of we#, and programming begins on both planes. r/b# goes low for the duration of array programming time, t prog. when program- ming and verification are complete, r/b# returns high. the read status (70h) command also indicates that the device is read y when status register bit 6 is set to ?1.? the only valid commands during t prog are read status (70h), two- plane/multiple-die read stat us (78h), and reset (ffh). if the read status (70h) command indicates an error in the operation (status register bit 0 = 1), use the two-plane/multiple-d ie read status (78h) command twice? once for each plane?to determine which plane operation failed. during the serial data input for either plane, the random data input (85h) command can be used any number of times to change the column address within that plane. for details on this command, see ?random data input 85h? on page 27. see figure 32 on page 44 for an example.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 44 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 31: two-plane internal data move operation figure 32: two-plane internal data move operation with random data input r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 85h 11h address (5 cycles) 1st-plane destination address (5 cycles) 2nd-plane source 1 r/b# i/ox 80h (or 81h) 10h address (5 cycles) t prog 2nd-plane destination 70h status 1 r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 1st-plane destination 2nd-plane destination 85h data data address (5 cycles) optional 85h 11h address (2 cycles) address (5 cycles) 2nd-plane source 1 r/b# i/ox t prog 80h (or 81h) data data address (5 cycles) optional 85h 10h 70h status address (2 cycles) 1 unlimited number of repetitions unlimited number of repetitions
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 45 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions two-plane block erase 60h-60h-d0h the two-plane block erase (60h-60h-d0h) operation is similar to the block erase (60h-d0h) operation. it erases two blocks instead of one. the blocks to be erased must be on different planes on the same die. the first-plane and second-plane addresses must meet the two-plane addressing requirements (see ?two-plane addressing? on page 35). additionally, the page addresses, pa[5:0], for both planes must be low. begin a two-plane block erase operation by writing 60h to the command register, followed by 3 address cycles of the first-pl ane block address. then write 60h again to the command register, followed by 3 address cycles of the second-plane block address. finally, issue the d0h command. r/b# goes low for the dura tion of block erase time, t bers. when block erasure is complete, r/b# returns high. the read status (70h) command also indicates that the device is ready when status register bi t 6 is set to ?1.? the only valid commands during t bers are read status (70h), two-plane/multiple-die read status (78h), and reset (ffh). if the read status (70h) command indicates an error in the operation (status register bit 0 = 1), then use the two-plane/multiple-die read status (78h) command twice?once for each plane?to determine which plane operation failed. figure 33: two-plane block erase operation re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h r/b# we# t bers don?t care 60h address input (3 cycles) i/o 0 = 0 erase successful i/o 0 = 1 erase error 1st plane 2nd plane
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 46 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions two-plane/multiple-die read status 78h in micron nand flash devices that have tw o planes, and possibly more than one die in a package that share the same ce# pin, it is possible to independently poll the status register of a particular plane and die using the two-plane/multiple-die read status (78h) command. this command can be used to check the status register during and after two-plane operations (with the exception of two-plane page read), and to check the status of interleaved die operations. after the 78h command is issued, the device requires 3 address cycles containing the block and page addresses, ba[18:6] and pa[ 5:0]. the most significant block address bit in the third address cycle, ba18, selects the proper die, and the least significant block address bit in the first address cycle, ba6, selects the proper plane within that die. after the 78h command and the 3 address cycl es, the status register is output on i/o[7:0] when re# is low. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necess ary to issue a new two-plane/multiple-die read status command to see these changes. the status register bit definitions are identical to those reported by the read status (70h) command (see table 9 on page 26). in devices that have more than one die sharing a common ce# pin, when one die is not busy (status register bit 5 is ?1?), it is possib le to initiate a new operation to that die even if the other die is busy (see ?interleaved die operations? on page 47). if both die are busy during or following an interleaved die operation, the read status (70h) command must not be used to check status, as both die will respond, causing bus contention on i/o[7:0]. the two-plan e/multiple-die read status (78h) command is required to check status duri ng and after interleaved die operations. use of the two-plane/multiple-die read status (78h) command is prohibited during and following power-on reset and otp commands. figure 34: two-plane/multiple-die read status cycle 78h address (3 cycles) status output t whr t ar t rea ce# cle we# ale re# i/ox
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 47 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions interleaved die operations in devices that have more than one die shar ing a common ce# pin, it is possible to significantly improve performance by interl eaving operations between the die. when both die are idle (r/b# is high or status register bit 5 is ?1?), issue a command to the first die (ba18 = 0). then, whil e the first die is busy (r/b# is low), issue a command to the other die (ba18 = 1). there are two ways to verify operation completi on in each die: using the r/b# signal, or monitoring the status register. r/b# remain s low while either die is busy. when r/b# goes high, then both die are idle and the operations are complete. alternatively, the two-plane/multiple-die read status (78h) command can report the status of each die individually. if a die is performing a cache operation, like program page cache mode (80h-15h) or two-plane program page cache mode (80h-11h- 80h-15h), then the die is able to accept the data for another cache operation when status register bit 6 is ?1.? all operations, includ ing cache operations, are complete on a die when status register bit 5 is ?1.? during and following interleaved die operations, the read status (70h) command is prohibited. instead, use the two-plane/multiple-die read status (78h) command. this command selects which die will report status. interleaved two-plane commands must also meet the requirements in ?two-plane addressing? on page 35. program page, program page cache mode, two-plane program page, two-plane program page cache mode, block erase, and two-plane block erase can be used as interleaved operations on separate die that share a common ce#. interleaved program page operations figures 35 and 36 show how to perform two types of interleaved program page oper- ations. in figure 35, the r/b# signal is monitored for operation completion. in figure 36 on page 48, the status register is monitored for operation completion with the two- plane/multiple-die read status (78h) command. random data input (85h) is permitte d during interleaved program page operations. figure 35: interleaved program pa ge operation with r/b# monitoring data address 80h 10h data address 80h 10h die 1 die 2 data address 80h 10h data address 80h 10h die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 48 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 36: interleaved program page op eration with status register monitoring interleaved program page cache mode operations figures 37 and 38 show how to perform two types of interleaved program page cache mode operations. in figure 37, the r/b# signal is monitored. in figure 38 on page 49, the status register is monitored with the two-plane/multiple-die read status (78h) command. random data input (85h) is permitted during interleaved program page cache mode operations. figure 37: interleaved program page ca che mode operation with r/b# monitoring data address 80h 10h data address 80h 10h die 1 die 2 status address data address 80h 10h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h data address 80h 15h data address 80h 15h die 1 die 2 data address 80h 15h data address 80h 15h die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 49 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 38: interleaved program page cache m ode operation with stat us register monitoring interleaved two-plane program page operations figure 39 on page 50 and figure 40 on page 51 show how to perform two types of inter- leaved two-plane program page operations. in figure 39, the r/b# signal is moni- tored for operation completion. in figure 40, the two-plane/multiple-die read status (78h) command is used to monitor th e status register for operation completion. the interleaved two-plane program pa ge operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 35 for details. random data input (85h) is permitted during interleaved two-plane program page operations. data address 80h 15h data address 80h 15h die 1 die 2 status address data address 80h 15h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 50 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 39: interleaved two-plane progra m page operation with r/b# monitoring notes: 1. two-plane addressing requirements apply. 1 data address 80h 11h data address 80h 10h die 1 die 1 data address 80h 11h data address 80h 10h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 1 data address 80h 11h data address 80h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 51 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 40: interleaved two-plane program page operation with status register monitoring notes: 1. two-plane addressing requirements apply. 1 data address 80h 11h data address 80h 10h die 1 die 1 data address 80h 11h data address 80h 10h die 2 die 2 address data address 80h 11h die 1 die 1 data address 80h 10h address die 1 data address 80h 11h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) status status 78h 78h 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 52 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions interleaved two-plane program page cache mode operations figures 41 and 42 show how to perform two types of interleaved two-plane program page cache mode operations. in fi gure 41, the r/b# signal is monitored. in figure 42 on page 53, the status register is monitored with the two- plane/multiple-die read status (78h) command. the interleaved two-plane program page cache mode operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 35 for details. random data input (85h) is permitted during interleaved two-plane program page cache mode operations. figure 41: interleaved two-plane program page cache mode operation with r/b# monitoring 1 data address 80h 11h data address 15h die 1 die 1 data address 80h 11h data address 80h (or 81h) 80h (or 81h) 15h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 1 data address 80h 11h data address 80h (or 81h) die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 15h
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 53 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 42: interleaved two-plane program page cach e mode operation with status register monitoring notes: 1. two-plane addressing requirements apply. 1 data address 80h 11h data address 80h (or 81h) 15h die 1 die 1 data address 80h 11h data address 15h die 2 die 2 address data address 80h 11h die 1 die 1 data address 15h address die 1 data address 80h 11h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) status status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h 78h 1 80h (or 81h) 80h (or 81h)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 54 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions interleaved block erase operations figures 43 and 44 show how to perform two types of interleaved block erase opera- tions. in figure 43, the r/b# signal is moni tored for operation completion. in figure 44, the two-plane/multiple-die read status (78h) command is used to monitor the status register for operation completion. figure 43: interleaved block erase operation with r/b# monitoring figure 44: interleaved block erase operation with status register monitoring interleaved two-plane block erase operations figures 45 and 46 on page 55 show how to perform two types of interleaved block erase operations. in figure 45, the r/b# sign al is monitored for operation completion. in figure 46, the two-plane/multiple-die read status (78h) command is used to monitor the status regist er for operation completion. the interleaved two-plane block erase oper ation must meet two-plane addressing requirements. see ?two-plane addressing? on page 35 for details. address 60h d0h die 1 address 60h d0h die 2 address 60h d0h die 1 address 60h d0h die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) address 60h d0h die 1 address 60h d0h die 2 address status die 1 address 60h d0h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 55 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions figure 45: interleaved two-plane block erase operation with r/b# monitoring notes: 1. two-plane addressing requirements apply. figure 46: interleaved two-plane block era se operation with status register monitoring notes: 1. two-plane addressing requirements apply. address 60h die 1 address 60h d0h die 1 address 60h die 2 address 60h d0h 60h die 2 address die 1 address 60h 60h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) d0h address 60h die 1 address 60h d0h die 1 address 60h die 2 address 60h d0h address 60h die 2 address die 1 die 1 address 60h 60h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h status d0h
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 56 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions reset operation reset ffh the reset command is used to put the memory device into a known condition and to abort the command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partiall y erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the data register and cache register contents are marked invalid. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register (see figure 47 and table 10). the reset command must be issued to all ce#s after power-on. the device will be busy for a maximum of 1ms. use of the two-plane/multiple-die read status (78h) command is prohibited during and following the initial reset command and otp oper- ations. figure 47: reset operation table 10: status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# high ready 11100000e0h wp# low ready and write protected 0110000060h cle ce# w e# r/b# i/ox t rst t wb ffh reset command
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 57 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory command definitions write protect operation it is possible to enable and disable pr ogram and erase commands using the wp# pin. figures 48 through 51 illu strate the setup time ( t ww) required from wp# toggling until a program or erase command is latched in to the command register. after command cycle 1 is latched, the wp# pin must not be toggled until the command is complete and the device is ready (status register bit 5 is ?1?). figure 48: erase enable figure 49: erase disable figure 50: program enable t ww 60h d0h we# i/ox wp# r/b# t ww 60h d0h we# i/ox wp# r/b# t ww 80h 10h we# i/ox wp# r/b#
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 58 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory error management figure 51: program disable error management this nand flash device is specified to have a minimum of 4,016 valid blocks (n vb ) out of every 4,096 total available blocks. this means the device s may have blocks that are invalid when shipped from the factory. an inva lid block is one that contains one or more bad bits. additional bad blocks may develop with use. however, the total number of available blocks will not fall below n vb during the endurance life of the product. although nand flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block management and error correction algo- rithms. this type of software en vironment ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc (up to 1,000 program/erase cycles) when shipped from the factory. this provides a reliable location for storing boot code and critical boot information. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by programming data other than ffh into the first spare location (column address 2,048) of the first or second page of each bad block. system software should check the first spar e address on the first and second page of each block prior to performing any progra m or erase operations on the nand flash device. a bad-block table can then be created, allowing system software to map around these areas. factory testing is performed under worst-case conditions. because blocks marked ?bad? may be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? check status after a program, erase, or internal data move operation. ? under typical use conditions, utilize a mi nimum of 1-bit ecc per 528 bytes of data. ? use bad-block management and a wear-leveling algorithm. t ww 80h 10h we# i/ox wp# r/b#
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 59 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory electrical characteristics electrical characteristics stresses greater than those listed in table 11 may cause permanent damage to the device. this is a stress rating only, and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating cond itions for extended periods may affect reliability. table 11: absolute maximum ratings voltage on any pin relative to v ss parameter/condition symbol min max unit voltage input mt29fxg08xaa v in ?0.6 +4.6 v v cc supply voltage mt29fxg08xaa v cc ?0.6 +4.6 v storage temperature t stg ?65 +150 c short circuit output current, i/os ?5ma table 12: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0 ? +70 o c extended ?40 ? +85 v cc supply voltage mt29fxg08xaa vcc 2.7 3.3 3.6 v ground supply voltage vss 0 0 0 v
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 60 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory electrical characteristics v cc power cycling micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. when v cc goes below approximately 2.0v, program and erase function s are disabled. wp# provides additional hardware protection. wp# should be kept at v il during power cycling. when v cc reaches 2.5v, 10s should be allowed for the nand flash to initialize before executing any commands (see figure 52). the reset command must be issued to all ce#s after power-on. the device will be busy for a maximum of 1ms. figure 52: ac waveforms during power transitions we# r/b# wp# v cc 10s high 3v device: 2.5v 3v device: 2.5v undefined don?t care i/ox ffh cle 1ms (max)
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 61 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory electrical characteristics notes: 1. invalid blocks are blocks that contain on e or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop below n vb during the endurance life of the device. do not erase or program blocks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid up to 1,000 program/erase cycles. 3. each 4gb section has a maximum of 80 invalid blocks. table 13: m29fxgxxxaa 3v device dc and operating characteristics parameter conditions symbol min typ max unit sequential read current t rc = 25ns; ce# = v il ; i out = 0ma i cc 1 ? 25 35 ma program current ?i cc 2 ? 25 35 ma erase current ?i cc 3 ? 25 35 ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb 1? ? 1 ma standby current (cmos) mt29f4g08aaa ce# = v cc - 0.2v; wp# = 0v/v cc i sb 2 ? 10 50 a mt29f8g08baa ?20100a mt29f8g08daa ?20100a mt29f16g08faa ?40200a input leakage current mt29f4g08aaa v in = 0v to v cc i li ? ? 10 a mt29f8g08baa ? ? 20 a mt29f8g08daa ? ? 20 a mt29f16g08faa ? ? 40 a output leakage current mt29f4g08aaa v out = 0v to v cc i lo ? ? 10 a mt29f8g08baa ? ? 20 a mt29f8g08daa ? ? 20 a mt29f16g08faa ? ? 40 a input high voltage i/o[7:0], ce#, cle, ale, we #, re#, wp#, r/b# v ih 0.8 x v cc ?v cc + 0.3 v input low voltage (all inputs) ?v il ?0.3 ? 0.2 x vcc v output high voltage i oh = ?400a v oh 2.4 ? ? v output low voltage i ol = 2.1ma v ol ??0.4v output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 ? ma table 14: valid blocks parameter symbol device min max unit notes valid block number n vb mt29f4g08aaa 4,016 4,096 blocks 1, 2 mt29f8g08baa 8,032 8,192 3 mt29f8g08daa 8,032 8,192 3 mt29f16g08faa 16,064 16,384 3
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 62 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory electrical characteristics notes: 1. these parameters are verified in device characterization and are not 100 percent tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device charac terization; not 100 percent tested. notes: 1. for page read cache mode and progra m page cache mode operations, cache mode timing applies. 2. timing for t adl begins in the address cy cle on the final ri sing edge of we # and ends with the first rising edge of we# for data input. table 15: capacitance description symbol device max unit notes input capacitance c in mt29f4g08aaa 10 pf 1, 2 mt29f8g08baa 20 mt29f8g08daa 20 mt29f16g08faa 40 input/output capacitance (i/o) c io mt29f4g08aaa 10 pf 1, 2 mt29f8g08baa 20 mt29f8g08daa 20 mt29f16g08faa 40 table 16: test conditions parameter value notes input pulse levels mt29fxg08xaa 0.0v to v cc input rise and fall times 5ns input and output timing levels v cc /2 output load 1 ttl gate and cl = 50pf 1 table 17: ac characteristics: command, data, and address input parameter symbol cache mode 1 standard mode unit notes min max min max ale to data start t adl 70 ? 70 ? ns 2 ale hold time t alh 10 ? 5 ? ns ale setup time t als 25 ? 10 ? ns ce# hold time t ch 10 ? 5 ? ns cle hold time t clh 10 ? 5 ? ns cle setup time t cls 25 ? 10 ? ns ce# setup time t cs 35 ? 15 ? ns data hold time t dh 10 ? 5 ? ns data setup time t ds 20 ? 10 ? ns write cycle time t wc 45 ? 25 ? ns we# pulse width high t wh 15 ? 10 ? ns we# pulse width t wp 25 ? 12 ? ns wp# setup time t ww 30 ? 30 ? ns
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 63 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory electrical characteristics notes: 1. for page read cache mode and progra m page cache mode operations, cache mode timing applies. 2. transition is measured 200mv from steady-st ate voltage with load. this parameter is sam- pled and not 100 percent tested. 3. the first time the reset (ffh) co mmand is issued while the device is id le, the device will go busy for a maximum of 1ms. thereafter, the device goes bu sy for maximum 5s. 4. do not issue a ne w command during t wb, even if r/b# is ready. table 18: ac characteristics: normal operation parameter symbol cache mode standard mode unit notes min max min max ale to re# delay t ar 10 ? 10 ? ns ce# access time t cea ?45?25ns1 ce# high to output high-z t chz ?45?30ns2 cle to re# delay t clr 10 ? 10 ? ns ce# high to output hold t coh 15 ? 15 ? ns cache busy in page read cache mode (first 31h) t dcbsyr1 ?3??s cache busy in page read cache mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 ? ? s output high-z to re# low t ir 0?0?ns1 data transfer from flash array to data register t r ?25?25s read cycle time t rc 50 ? 25 ? ns 1 re# access time t rea ?30?20ns1 re# high hold time t reh 15 ? 10 ? ns 1 re# high to output hold t rhoh 22 ? 22 ? ns re# high to we# low t rhw 100 ? 100 ? ns re# high to output high-z t rhz ?100?100ns2 re# low to output hold t rloh 5?5?ns re# pulse width t rp 25 ? 12 ? ns 1 ready to re# low t rr 20 ? 20 ? ns reset time (read/program/erase) t rst ? 5/10/500 ? 5/10/500 s 3 we# high to busy t wb ?100?100ns4 we# high to re# low t whr 60 ? 60 ? ns
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 64 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory electrical characteristics notes: 1. four total partial-page programs to the same page. 2. t cbsy max time depends on ti ming between internal prog ram completion and data-in. 3. t lprog = t prog (last page) + t prog (last - 1 page) - comman d load time (last page) - address load time (last page) - data load time (last page). 4. typical t prog time may increase for two-plane operations. table 19: program/erase characteristics symbol parameter typ max unit notes nop number of part ial page programs ? 4 cycles 1 t bers block erase operation time 1.5 2 ms t cbsy busy time for program cache operation 3600s2 t dbsy busy time for two-plane program page operation 0.5 1 s t lprog last page program operation time ???3 t obsy busy time for otp data progra m operation if otp is protected ?25s t prog page program operation time 220 600 s 4
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 65 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams timing diagrams figure 53: command latch cycle figure 54: address latch cycle we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls don?t care we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 don?t care undefined t wc
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 66 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 55: input data latch cycle notes: 1. d in final = 2,111 (x8). figure 56: serial access cycle after read note: use this timing diagram for t rc 30ns. w e# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 don?t care t wc d in 0 ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea don?t care t rhz t chz t rhz t rhoh r/b# t coh d out d out d out
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 67 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 57: serial access cycle after read (edo mode) note: use this timing diagram for t rc < 30ns. figure 58: read status operation d out d out ce# re# i/ox r/b# t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz don?t care d out re# ce# w e# cle i/ox t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output don?t care t cea t coh
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 68 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 59: two-plane/multiple-die read status operation figure 60: page read operation t whr t ar ce# cle w e# ale re# i/ox don?t care 78h row add 1 row add 2 row add 3 status output t ds t dh t wp t wp t wc t ch t als t alh t wh t cls t clh t alh t cs t cea t chz t rea t rhoh t rhz t coh d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 69 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 61: read operation with ce# ?don?t care? figure 62: random data read operation re# ce# t rea t chz t cea re# ce# ale cle i/ox i/ox out r/b# we# data output t r don?t care address (5 cycles) 00h 30h t coh we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 row add 1 row add 2 row add 3 00h t wb t ar t rr don?t care t rc t rhw d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n d out n + 1 30h t whr column address n column address m t r
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 70 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 63: page read cache mode operation, part 1 of 2 t wc we# ce# ale cle re# r/b# i/ox column address 0 1 d out page address m page address m column address 00h t cea t ds t clh t cls t cs t ch t dh don?t care t rr t wb t dcbsyr2 column address 0 continued to 1 of next page t rc t rea 30h d out 0 d out 0 d out 1 31h 31h col add 2 row add 1 row add 2 row add 3 00h t dcbsyr1 page address m + 1 col add 1 t rhw t r
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 71 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 64: page read cache mode operation, part 2 of 2 we# ce# ale cle re# r/b# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t clh t ch t rea t cea t rhw t ds t dh t rr t dcbsyr2 t dcbsyr2 t wb column address 0 31h d out 0 d out 3fh d out 1 d out 0 d out d out 1 t cls t cs t rc d out 31h t dcbsyr2 t rhw d out 1 d out d out 0
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 72 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 65: page read cache mode operation without r/b#, part 1 of 2 t wc we# ce# ale cle re# i/ox 30h 70h status d out 0 column address 0 1 d out 0 d out 1 d out column address 00h page address m page address m t cea t ds t clh t cls t cs t ch t dh don?t care 31h 31h column address 0 70h status i/o 6 = 0, cache busy = 1, cache ready i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 00h 00h 00h t rc t rea 70h status i/o 6 = 0, cache busy = 1, cache ready page address m + 1 t rhw
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 73 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 66: page read cache mode operation without r/b#, part 2 of 2 we# ce# ale cle re# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t rea t cea t ds t dh column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d out d out 1 d out 0 t rc d out 31h 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t ch t cls t cs t rhw
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 74 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 67: read id operation note: see table 8 on page 25 for actual values. figure 68: program page operation w e# ce# ale cle re# i/ox address, 1 cycle 90h 00h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr we# ce# ale cle re# r/b# i/ox t wc t adl serial data input command x8 device: m = 2,112 bytes program command read status command 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t whr t wb don?t care
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 75 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 69: program operation with ce# ?don?t care? figure 70: program page operation with random data input cle ce# we# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs don?t care data input 80h we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t adl random data input command column address program command read status command serial input 85h t prog t wb t whr don?t care col add 1 col add 2 d in n d in n+1 70h status 10h
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 76 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 71: internal data move operation note: internal data move operat ions are only supported within the plane from which data is read. figure 72: program page cache mode operation we# ce# ale cle re# r/b# i/ox t wb t prog t wb busy busy read status t wc internal data move don?t care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 col add 1 85h data 1 t r we# ce# ale cle re# r/b# i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial input t wc don?t care 80h t adl row add 3 serial data input program program
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 77 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 73: program page cache mode operation ending on 15h we# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page ? 1 serial data input serial input program program t wc don?t care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page ? 1 program successful t adl t whr t whr t adl
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 78 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory timing diagrams figure 74: block erase operation figure 75: reset operation we# ce# ale cle re# r/b# i/ox auto block erase setup command erase command read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr don?t care i/o0 = 0, pass i/o0 = 1, fail cle ce# w e# r/b# i/ox t rst t wb ffh reset command
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 79 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory package dimensions package dimensions figure 76: 48-pin tsop type 1 (wp package code) note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 4gb, 8gb, and 16gb x8 nand flash memory package dimensions pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 80 ?2006 micron technology, inc. all rights reserved. figure 77: 48-pin tsop ocpl type 1 (wc package code) note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 12.00 0.08 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 for reference only 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.
pdf: 09005aef81b80e13/source: 09005aef81b80eac micron technology, inc., reserves the right to change products or specifications without notice. 4gb_nand_m40a__2.fm - rev. b 2/07 en 81 ?2006 micron technology, inc. all rights reserved. 4gb, 8gb, and 16gb x8 nand flash memory revision history revision history rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/07 ? page 1: added mt29f8g08baa to title, 8g b (dual-die stack 1 ce#), 8gb (dual-die stack 2 ce#) to density options, 2 die, 1 ce#, 1 rb# to configuration options. added extended temperature to options. ? figure 2 on page 2: added classification b: 2 die, 1 ce#, 1 rb#. added extended temperature and note to contact factory. ? ?general description? on page 8: added mt29f8g08baa to first paragraph; revised fourth paragraph. ? figure 3 on page 9: modified note 1. ? figure 5 on page 12: revised block information. ? figure 7 on page 14: added new part number information to figure title and note 2. ? table 4 on page 14: changed part numbers in title. ? former figure 8 on page 17, ?time constant s? and figure 9 on page 17, ?minimum rp?: converted to equation format. ? table 8 on page 25: added mt29f8g08baa in bytes 1, 2, and 4, modified interleaved operations description, added note 3, changed part number in note 2. ??two-plane addressing? on page3 5: revised second bullet re ba18. ? ?error management? on page 58: modified second bullet. ? table 12 on page 59: added extended temperature. ? tables 13 and 14 on page 61, table 15 on page 62: added mt29f8g08daa. ? table 19 on page 64: changed t cbsy (max) and t prog (max) to 600s. rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/06 ?initial release.

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