HV9860 features ? switch mode controller for boost and fyback converters ? discontinuous conduction mode of operation ? high output current accuracy ? internal 2% voltage reference (0 o c HV9860 is a current mode control led driver ic designed to control a boost or fyback led driver in constant frequency mode. the controller uses a peak current-mode control scheme and includes an internal transconductance amplifer to accurately control the output current over all line and load conditions. the ic also provides a disconnect switch gate drive output, which can be used to achieve good pwm rise and fall times for the led current using an external disconnect fet. the HV9860 also has a duty pin which can be used to set the maximum duty cycle to either 90%(typ) or 75%(typ). the 75% duty cycle limit can be used for fyback applications. the HV9860 also provides a ttl compatible, low-frequency pwm dimming input that can accept an external control signal with a duty ratio of 0-100% and a frequency of up to a few kilohertz. the HV9860 includes a wiring fault detection function that sends a fag to the boost input power supply in case of an led to wiring fault. typical application circuit single channel boost led driver with led wiring fault detection HV9860 vcc vdd pwmi flag line gate cs ovp pwmo fbn comp ref fbp gnd vin 12v r cs r s l1 q1 q2 c in c o r l1 r l2 r o1 r o2 c c r r1 r r2 c dd c r duty 3.3v/5.0v r pull-up supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
2 HV9860 -g indicates package is rohs compliant (green) absolute maximum ratings parameter value vcc to gnd -0.5v to +45v vdd to gnd -0.5v to +13v gate, pwmo to gnd -0.3v to (v dd + 0.3v) ref to gnd -0.3v to +6.0v all other pins to gnd -0.3v to (ref + 0.3v) continuous power dissipation (t a = +25c) 16-lead soic 1000mw junction temperature +150c storage temperature range -65c to +150c ordering information device package option 16-lead soic 9.90x3.90mm body 1.75mm height (max) 1.27mm pitch HV9860 HV9860ng-g pin confguration product marking 16-lead soic (ng) 16-lead soic (ng) package may or may not include the following marks: si or stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. y = last digit of year sealed ww = week sealed l = lot number c = country of origin a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking HV9860ng y ww llllllll ccccccccc aaa vdd vcc gate cs line nc flag pwmi duty gnd ovp ref fbp fbn comp pwmo 1 16 8 9 thermal resistance package ja 16-lead soic (ng) 82 o c/w supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
3 HV9860 notes: * denotes specifcations guaranteed by design and characterization over the full operating ambient temperature range of 0 o c < t a < +125 o c. # denotes specifcations which are guaranteed by design. sym description min typ max unit conditions input v cc input dc supply voltage range * 10.0 - 40.0 v dc input voltage i insd shut-down mode supply current - - - 1.0 ma pwmd = gnd internal regulator v dd internally regulated voltage * 9.5 10.0 10.5 v v cc = 10.0 C 40.0v, pwmi = ref uvlo rise vdd under voltage lockout threshold * 8.0 - 9.0 v v dd rising uvlo hyst vdd under voltage lockout hysteresis - - 500 - mv v dd falling reference voltage ref internally regulated voltage * 4.9 5.0 5.1 v pwmi = ref; i ref_ext = 0 - 500a uvlo rise1 ref under voltage lockout threshold * 4.2 - 4.8 v ref rising uvlo hyst1 ref under voltage hysteresis - - 500 - mv ref falling pwm dimming v pwm(lo) pwmd input low voltage * - - 0.8 v --- v pwm(hi) pwmd input high voltage * 2.0 - - v --- r pwmi internal pull down resistance at pwmd - 50 100 150 k pwmi = 3.3v boost fet driver i source gate short circuit current, sourcing * 0.2 - - a v gate = 0v i sink gate sinking current * 0.4 - - a v gate = 10v t rise gate output rise time - - - 100 ns --- t fall gate output fall time - - - 70 ns --- d max maximum duty cycle at gate output * 87 - 93 % --- * 72 - 78 duty = ref disconnect fet driver i source,pwmo pwmo short circuit current, sourcing * 0.02 - - a v gate = 0v i sink,pwmo pwmo sinking current * 0.04 - - a v gate = 10v t rise,pwmo pwmo output rise time - - - 100 ns --- t fall,pwmo pwmo output fall time - - - 50 ns --- oscillator f osc oscillator frequency * 85 100 115 khz --- electrical characteristics (the * denotes the specifcations which apply over the full operating ambient temperature range of 0 o c < t a < +125 o c, otherwise the specifcations are at t a = 25 o c. v cc = 12v, c dd = 1.0f, c r = 0.1f, c gate = 1.0nf, c pwmo = 500pf, duty = gnd, pwmi = ref unless otherwise noted.) supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
4 HV9860 sym description min typ max unit conditions current sense t blank leading edge blanking * 100 - 250 ns --- t prop_delay1 delay to gate - - - 200 ns comp = ref ; 50mv overdrive at cs r div internal resistor divider ratio (comp to cs) # - 0.083 - - --- v offset comparator offset voltage # -10 - 10 mv --- over voltage protection v ovp,rising over voltage rising trip point * 1.95 2.05 2.15 v ovp rising v ovp,hyst over voltage hysteresis - - 0.15 - v ovp falling internal transconductance opamp gb gain-bandwidth product # - 1.0 - mhz 75pf capacitance at comp pin a v open loop dc gain - 60 - - db output open v cm input common-mode range # -0.3 - 1.5 v --- v o output voltage range # 0.7 - ref -0.7 v a v 60db g m transconductance - 1080 1200 1340 a/v --- v offset input offset voltage * -3.0 - 3.0 mv --- i bias input bias current # - 0.5 1.0 na --- i comp,dis discharging current - 1.0 - - ma v comp = 5.0v over current protection t blank,ocp blanking time for ocp * 500 - 900 ns --- g sc gain for short circuit comparator - 1.8 2.0 2.2 - --- v omin minimum output voltage of the gain stage * 0.14 0.20 0.26 v fbp = gnd t off propagation time to pwmo and gate for short circuit detection - - - 300 ns pwmi = ref; fbp = 400mv; fbn step from 0 to 900mv; pwmo goes from high to low; no capacitance at pwmo pin t hcp internal hiccup time # 2.22 2.56 2.91 ms --- short cathode detect (pwmd high) v ref1 comp over-voltage threshold * 4.60 - - v ref = 5.0v v ref2 fb under-voltage threshold * 0.10 - 0.15 v --- t prop_delay3 propagation delay to gate and pwmo - - 1.0 - s 50mv overdrive v line line under-voltage reset threshold * 1.95 2.05 2.15 v line voltage rising v line, hys line threshold hysteresis - - 0.15 - v --- electrical characteristics (cont.) notes: * denotes specifcations guaranteed by design and characterization over the full operating ambient temperature range of 0 o c < t a < +125 o c. # denotes specifcations which are guaranteed by design. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
5 HV9860 functional block diagram 100 khz oscillator sync t blank q r vdd vcc gate cs line pwmi duty gnd ref fbp fbn comp 8.5/8.0v 4.5/4.0v por dim min 2 2.0v/1.8v por clk flt dim 0.1v ref -0.3v pwmo dim 2. 0v /1 .8 v dim uvlo flag dim ovoc fc 500ns blnk blnk lop flag fault logic ref 10v regulator 10v regulator q s ovp for the ic to work as intended, the following power-on sequence is critical. 1. vcc to the ic 2. 3.3 or 5.0v to the pull-up resistor at flag 3. vin for the boost or fyback converter note that 1 and 2 can be interchanged but item 3 should always occur after items 1 and 2. power-on sequence supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
6 HV9860 power topology the HV9860 is a switch-mode led driver designed to control a boost or fyback converter in a constant frequency mode. the ic includes internal linear regulators which enables it to operate at input voltages from 10v to 40v. the ic includes features typically required in led drivers like open led pro - tection, output short circuit protection, linear and pwm dim - ming and accurate control of the led current. the ic also includes an open led current feedback loop detection which is used to detect a short cathode to ground fault. upon detection of the fault, the ic shuts down and signals the boost power supply to shutdown by pulling the flag pin low. the ic is restarted by cycling the boost power supply. power supply to the ic (vcc, vdd and ref) the HV9860 can be powered directly from its vcc pin that takes a voltage up to 40v. there are two linear regulators within the HV9860 - a 10v linear regulator (vdd) which is used for the two fet drivers and a 5v linear regulator (ref) which supplies power to the rest of the control logic. the ic also has a built-in under-voltage lockout which shuts off the ic if the voltage at either vdd or the ref pins fall below the corresponding uvlo threshold. both vdd and ref pins must by bypassed by a low esr capacitor (0.1f) for proper operation. the input current drawn from the external power supply (or vcc pin) is a sum of the 1.0ma(max) current drawn by the all the internal circuitry and the current drawn by the gate drivers (which in turn depends on the switching frequency, pwm dimming frequency and the gate charge of the exter - nal fets). i in = 1.0ma + q g1 ? f s + q g2 ? f pwmd in the above equation, f s is the switching frequency of the converter, f pwmd is the frequency of the applied pwm dim - ming signal, q g1 is the gate charge of the external boost fet and q g2 is the gate charge of the disconnect fet (both of which can be obtained from the fet datasheets). the ref pin can also be used as a reference voltage to set the led current using a resistor divider to the fbp pin. the ref pin can also be used to as the voltage for the pull-up resistor at the flag pin as long as the total external current draw from the ref pin does not exceed 0.5ma. current sense (cs) the current sense input is used to sense the source current of the switching fet. the cs input of the HV9860 includes a built in 100ns (minimum) blanking time to prevent spurious turn off due to the initial current spike when the fet turns on. the ic includes an internal resistor divider network, which steps down the voltage at the comp pins by a factor of 12 (11r:1r). this voltage is used as the reference for the cur - rent sense comparator. since the maximum voltage of the comp pin is ref -1.0v, this voltage determines the maxi - mum reference current for the current sense comparator and thus the maximum inductor current. the current sense resistor r cs should be chosen so that the input inductor current is limited to below the saturation cur- rent level of the input inductor. for discontinuous conduction mode of operation, no slope compensation is necessary. in this case, the current sense resistor is chosen as: r cs = v dd C 1.0v 12 ? i sat where i sat is the saturation current of the inductor. note: comp voltage lower than 1.0v will produce no gate pulses at gt pin. pwmo output the pwmo pin is used to drive a disconnect fet while driv - ing boost and fyback converters. this fet disconnects the output flter capacitors from the led load during pwm dim - ming and enables a high pwm dimming ratio. control of the led current (fbp, fbn and comp) the led current in the HV9860 is controlled in a closed- loop manner. the voltage reference at fbp which sets the led current is set by using a resistor divider from the ref pin (or can be set externally with a low voltage source). this reference voltage is compared to the voltage at the fbn pin, which senses the led current by using a current sense resistor. the hv9960 includes a 1.0mhz transconductance amplifer with tri-state output, which is used to close the feedback loops and provide accurate current control. the compensation network is connected at the comp pin. the output of the op-amp is buffered and connected to the current sense comparator using an 11r:1r resistor divider. the output of the op-amp is also controlled by the signal ap - plied to the pwmi pin. when pwmi is high, the output of the op-amp is connected to the comp pin. when pwmi is low, the output is left open. this enables the integrating capaci - tor to hold the charge when the pwmi signal has turned off the gate drive. when the ic is enabled, the voltage on the integrating capacitor will force the converter into steady state almost instantaneously. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
7 HV9860 linear dimming linear dimming can be accomplished in the HV9860 by vary - ing the voltage at the fbp pin. note that since the HV9860 is a peak current mode controller, it has a minimum on-time for the gate output. this minimum on-time will prevent the converter from turning off completely even when the iref pin is pulled to gnd. thus, linear dimming cannot accom - plish true zero led current. to get zero led current, pwm dimming has to be used. due to the offset voltage of the short circuit comparator as well as the non-linearity of the x2 gain stage, pulling the fbp pin very close to gnd might cause the internal short circuit comparator to trigger and shut down the ic. to overcome this, the output of the gain stage is limited to 140mv (mini - mum), allowing the iref pin to be pulled all the way to 0v without triggering the short circuit comparator. pwm dimming (pwmi) pwm dimming in the HV9860 can be accomplished using a ttl compatible square wave source at the pwmd pin. the clock of the HV9860 is synchronized to the rising edge of the pwmi. this removes any ficker that can occur at low pwm pulse widths which might occur due to the pwm pulse and clock being asynchronous. fault conditions the HV9860 is a robust controller which can protect the leds and the led driver in case of fault conditions. the HV9860 protects the system from three different fault condi - tions. ? open circuit fault ? short circuit fault (short across the led string) ? open loop fault (led string to ground fault) open circuit fault the HV9860 provides hysteretic over-voltage protection to protect the system from dangerous over-voltages in case of an open led condition. when the load is disconnected in a boost or fyback con - verter, the output voltage rises as the output capacitor starts charging. when the output voltage reaches the ovp ris - ing threshold, the HV9860 detects an over voltage condi - tion and turns off the converter (gate and pwmo outputs are disabled and comp is pulled to ground). the converter is turned back on only when the output voltage falls below the falling ovp threshold (which is 8% lower than the ris - ing threshold). this time is mostly dictated by the r-c time constant of the output capacitor c o and the resistor network used to sense over voltage (r o1 + r o2 ). in case of a persis- tent open circuit condition, this cycle keeps repeating main - taining the output voltage within an 8% band. note that the hiccup time between restart attempts in dependent entirely on the r-c time constant and the ovp resistor divider must be chosen accordingly. in most designs, the lower threshold voltage of the over voltage protection (v ovp C8%) at which point the HV9860 attempts to restart will be more than the steady state led string voltage. thus, when the led load is reconnected to the output of the converter, the voltage differential between the actual output voltage and the led string voltage will cause a spike in the output current. this causes a short cir - cuit to be detected and the HV9860 will trigger short circuit protection. this behavior continues till the output voltage be - comes lower than the led string voltage at which point, no fault will be detected and normal operation of the circuit will commence. short circuit fault when a short circuit condition is detected (output current be - comes higher than twice the steady state current), the gate and pwmo outputs are pulled low, and comp is pulled to ground. as soon as the disconnect fet is turned off, the output current goes to zero and the short circuit condition disappears. at this time, the internal 8-bit hiccup timer starts counting. once the counter reaches 256, the converter at- tempts to restart. if the fault condition still persists, the con - verter shuts down and goes through the cycle again. if the fault condition is cleared (due to a momentary output short) the converter will start regulating the output current normally. this allows the led driver to recover from accidental shorts without having to reset the ic. note that the power rating of the led sense resistor has to be chosen properly if it has to survive a persistent fault con - dition. the power rating can be determined using: p rs = i sat ? r s ? (t fault + t off ) t hiccup where i sat is the saturation current of the disconnect fet. in case of the HV9860, (t fault = t off ) is 350ns(max). the worst case hiccup time is 256*t s(min) = 2.23ms. during pwm dimming, the parasitic capacitance of the led string might cause a spike in the output current when the disconnect fet is turned on. if this spike is detected by the short circuit comparator, it will cause the ic to detect an over current condition falsely and shut down. in the HV9860, to prevent these false triggerings, there is a built-in 500ns(min) blanking network for the short circuit com - parator. this blanking network is activated when the pwmd input goes high. thus, the short circuit comparator will not see the spike in the led current during the pwm dimming 2 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
8 HV9860 turn-on transition. once the blanking timer is completed, the short circuit comparator will start monitoring the output cur - rent. thus, the total delay time for detecting a short circuit will depend on the condition of the pwmd input. if the output short circuit exists before the pwm dimming signal goes high, the total detection time will be: t detect1 = t blank + t delay 1150ns(max) if the short circuit occurs when the pwm dimming signal is already high, the time to detect will be: t detect1 = t delay 250ns(max) open loop fault open loop fault occurs when the any part of the led string is shorted to ground, bypassing the led current sense re - sistor. in this case, there is no direct feedback of the output current since the current sense resistor is bypassed. consider a case of three led light bars connected in series and driven from an led driver. assume that the input to the boost converter is 120v, and that each led light bar has a forward drop of about 80v (25 leds with 3.2v/per led). if one of connections between the led light bars is shorted to ground (see fig.1), then excessive current might fow through the leds. fig.1 : short cathode fault this situation needs to be detected and prevented. note that turning off the boost converter might not be suffcient in all cases. for example, if c1 was shorted in ground in fig.1, the led string voltage (one string: 80v) is lower than the input voltage (120v), and turning the boost converter off will not prevent the short circuit current. hence, in addition to turn - ing off the boost converter, the solution is to signal the input 120v power supply to turn off. this is achieved by means of the flag output (see typical application circuit). in the HV9860, a short cathode condition is detected by sensing the voltages at fbn and comp pins when pwmi = hi. if the short circuit to ground occurs at nodes a1 or c1, then the over-current condition will be detected by the convert - ers power supply, since its output is effectively shorted to ground. short cathode detection is needed only when the fault occurs at either c2 or c3 nodes. when a short to ground occurs at c2 or c3, then the led current is diverted away from the current sense resistor r cs and fows directly to ground. since the current through r cs = 0, the fbn voltage becomes zero. this causes the output of the transconductance amplifer to rail to its maximum output. the combination of fbn < 0.1v and comp > 4.7v is used to detect the short cathode fault. when the short cathode fault is detected, an internal 12-bit counter is started. when the counter reaches 4096, the ic is turned off and flag is pulled low. the counter is reset if the fault disappears during this time. short cathode detection there are two cases to consider when for short cathode pro - tection. (note that only a short circuit to ground at c2 or c3 is considered). case 1: short cathode condition exists prior to the boost converter being powered on. in this case, since the input voltage is lower than the led string voltage, when the boost power is applied, no current fows through the leds and nothing happens. when the ic is turned on by applying a pwmd signal, then the ic tries to regulate the led current. since the led current sense resistor is bypassed, fbn pin will be ground and comp will rail to ref. after the internal timer completes counting to 40ms, the ic will shut down and pull down the flag pin to indicate a fault condition to the boost converter. case 2: short cathode condition occurs during normal op - eration. in this case, when the short occurs, fbn will drop to zero and comp will ramp up to ref. at this point, the internal timer starts and after 40ms, the ic shuts down and the flag pin is pulled low. reset of the fault condition the line input is used to reset the ic in the case of an open loop fault condition. the ic is reset when the voltage at the line pin falls below 1.9v(typ). a resistor divider from the boost (or fyback) converters input voltage can be used to program the reset of the fault condition. q2 a1 c1 c2 c3 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
9 HV9860 pin description pin # pin name description 1 vdd this pin is the output of the high voltage linear regulator and the power supply to gate and pwmo. 2 vcc this is the input power supply pin. 3 gate this is the gate driver output for the switching fet. 4 cs this pin is used to sense the source current of the external power fet . 5 line this pin programs the input voltage reset threshold for the short-cathode led protection. 6 nc no connect pin. this pin should be left foating. 7 flag this is an open-drain, active-low output which indicates a short cathode fault. 8 pwmi a ttl compatible square wave signal can be applied to this pin to achieve pwm dimming of the led string. 9 pwmo this pin drives the external fet disconnecting the led string from the output ot the led driver. 10 comp led current error amplifer output. a compensation network is required at this pin for loop stability. 11 fbn led current feedback input. 12 fbp the voltage at this pin sets the output current level. the current reference can be set using a resistor divider from the ref pin. 13 ref this pin provides the power supply for the analog circuitry within the ic as well as providing a refer - ence which can be used to set the led current. 14 ovp this pin is used to detect an output over voltage condition 15 gnd ground return for all the low power analog internal circuitry as well as the gate drivers. this pin must be connected to the return path from the input. 16 duty this pin programs the maximum duty cycle. connecting the pin to gnd sets the maximum duty cycle at 90%. connecting it to ref sets the maximum duty cycle at 75%. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
10 HV9860 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-HV9860 a031511 16-lead soic (narrow body) package outline (ng) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 9.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ac, issue e, sept. 2005. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-16song, version g041309. d seating plane gauge plane l l1 l2 to p v iew side v iew vi ew a-a vi ew b vi ew b 1 e1 e a a2 a1 a a seating plane e b h h 16 1 note 1 note 1 (index area d/2 x e1/2) note: 1. this chamfer feature is optional. if it is not present, then a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator . supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?201 1 supertex inc. a ll rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com www.datasheet.co.kr datasheet pdf - http://www..net/
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