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pll frequency synthesizer data sheet adf4106 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2001C2012 analog devices, inc. all rights reserved. technical support www.analog.com features 6.0 ghz bandwidth 2.7 v to 3.3 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 programmable charge pump currents programmable antibacklash pulse width 3-wire serial interface analog and digital lock detect hardware and software power-down mode applications broadband wireless access satellite systems instrumentation wireless lans base stations for wireless radios general description the adf4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. it consists of a low noise, digital phase frequency detector (pfd), a precision charge pump, a programmable reference divider, programmable a counter and b counter, and a dual-modulus prescaler (p/p + 1). the a (6-bit) counter and b (13-bit) counter, in conjunction with the dual-modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter) allows selectable ref in frequencies at the pfd input. a complete phase-locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (vco). its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. functional block diagram 02720-001 clk data le ref in rf in a rf in b 24-bit input register sd out av dd dv dd ce agnd dgnd 14-bit r counter r counter latch 22 14 function latch a, b counter latch from function latch prescaler p/p + 1 n = bp + a load load 13-bit b counter 6-bit a counter 6 19 13 m3 m2 m1 mux sd out av dd high z muxout cpgnd r set v p cp phase frequency detector lock detect reference charge pump current setting 1 adf4106 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 2 figure 1.
adf4106 data sheet rev. e | page 2 of 24 table of contents specifications ..................................................................................... 3 timing characterisitics ............................................................... 4 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance char acteristics ............................................. 8 general description ....................................................................... 10 reference input section ............................................................. 10 rf input stage ............................................................................. 10 prescaler (p/p +1) ....................................................................... 10 a counter and b counter ......................................................... 10 r counter .................................................................................... 10 phase frequency detector (pfd) and charge pump ............ 11 muxout and lock detect ...................................................... 11 input shift register .................................................................... 11 the function latch .................................................................... 17 the initialization latch ............................................................. 18 applications ..................................................................................... 19 local oscillator for lmds base station transmitter ............ 19 interfacing ................................................................................... 20 pcb design guidelines for chip scale package .................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 r evision h istory 11/12 rev. d to rev. e changed eval - adf4106ebz1 to ev - adf4106sd1z ...... universal added rf in a to rf in b parameter, table 3 .................................... 6 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 22 9/11 re v . c to rev. d changes to normalized phase noise floor (pn synth ) parameter, table 1 ................................................................................................ 4 added normalized 1/f noise (pn 1_f ) parameter and endnote 12 , table 1 ................................................................................................ 4 changes to ordering guide .......................................................... 22 2/ 10 rev . b to rev. c changes to figure 4 and table 4 ..................................................... 6 changes to fig ure 12 ........................................................................ 8 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 6 /05 rev . a to rev. b updated format .................................................................. universal changes to figure 1 ........................................................................... 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 4 changes to table 3 ............................................................................. 5 changes to figure 3 and figure 4 .................................................... 6 changes to figure 6 ........................................................................... 7 changes to figure 10 ......................................................................... 7 deleted tpc 13 and tpc 14 ............................................................ 8 changes to figure 15 ......................................................................... 8 changes to figure 20 caption ...................................................... 10 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 2 1 5/03 rev . 0 to rev. a edits to specifications ....................................................................... 2 edits to tpc 11 .................................................................................. 7 updated outline dimensio ns ....................................................... 19 10/01 revision 0: initial revision
data sheet adf4106 rev. e | page 3 of 24 specifications av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. table 1. parameter b version 1 b chips 2 (typ) unit test conditions/comments rf characteristics see figure 18 for input circuit rf input frequency (rf in ) 0.5/6.0 0.5/6.0 ghz min/max for lower frequencies, ensure slew rate (sr) > 320 v/s rf input sensitivity C10/0 C10/0 dbm min/max maximum allowable prescaler output frequency 3 300 300 mhz max p = 8 325 325 mhz max p = 16 ref in characteristics ref in input frequency 20/300 20/300 mhz min/max for f < 20 mhz, ensure sr > 50 v/s ref in input sensitivity 4 0.8/v dd 0.8/v dd v p-p min/max biased at av dd /2 (see note 5 5 ) ref in input capacitance 10 10 pf max ref in input current 100 100 a max phase detector phase detector frequency 6 104 104 mhz max abp = 0, 0 (2.9 ns antibacklash pulse width) charge pump programmable, see table 9 i cp sink/source high value 5 5 ma typ with r set = 5.1 k low value 625 625 a typ absolute accuracy 2.5 2.5 % typ with r set = 5.1 k r set range 3.0/11 3.0/11 k typ see table 9 i cp three-state leakage 2 2 na max 1 na typical; t a = 25c sink and source current matching 2 2 % typ 0.5 v v cp v p ? 0.5 v i cp vs. v cp 1.5 1.5 % typ 0.5 v v cp v p ? 0.5 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v ih , input high voltage 1.4 1.4 v min v il , input low voltage 0.6 0.6 v max i inh , i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage 1.4 1.4 v min open-drain output chosen, 1 k pull-up resistor to 1.8 v v oh , output high voltage v dd ? 0.4 v dd ? 0.4 v min cmos output chosen i oh 100 100 a max v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies av dd 2.7/3.3 2.7/3.3 v min/v max dv dd av dd av dd v p av dd /5.5 av dd /5.5 v min/v max av dd v p 5.5v i dd 7 (ai dd + di dd ) 11 9.0 ma max 9.0 ma typ i dd 8 (ai dd + di dd ) 11.5 9.5 ma max 9.5 ma typ i dd 9 (ai dd + di dd ) 13 10.5 ma max 10.5 ma typ i p 0.4 0.4 ma max t a = 25c power-down mode 10 (ai dd + di dd ) 10 10 a typ
adf4106 data sheet rev. e | page 4 of 24 parameter b version 1 b chips 2 (typ) unit test conditions/comments noise characteristics normalized phase noise floor (pn synth ) 11 C223 C223 dbc/hz typ pll loop b/w = 500 khz, measured at 100 khz offset normalized 1/f noise (pn 1_f ) 12 ?122 ?122 dbc/hz typ 10 khz offset; normalized to 1 ghz phase noise performance 13 @ vco output 900 mhz 14 C92.5 ?92.5 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 5800 mhz 15 ?76.5 ?76.5 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 5800 mhz 16 ?83.5 ?83.5 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency spurious signals 900 mhz 14 C90/C92 C90/C92 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency 5800 mhz 15 C65/C70 C65/C70 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency 5800 mhz 16 C70/C75 C70/C75 dbc typ @ 1 mhz/2 mhz and 1 mhz pfd frequency 1 operating temperature range (b version) is C40c to +85c. 2 the b chip specifications are given as typical values. 3 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 4 av dd = dv dd = 3 v. 5 ac coupling ensures av dd /2 bias. 6 guaranteed by design. sample tested to ensure compliance. 7 t a = 25c; av dd = dv dd = 3 v; p = 16; rf in = 900 mhz. 8 t a = 25c; av dd = dv dd = 3 v; p = 16; rf in = 2.0 ghz. 9 t a = 25c; av dd = dv dd = 3 v; p = 32; rf in = 6.0 ghz. 10 t a = 25c; av dd = dv dd = 3.3 v; r = 16383; a = 63; b = 891; p = 32; rf in = 6.0 ghz. 11 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0 log n (where n is the n divider value) and 10 log f pfd . pn synth = pn tot ? 10 log f pfd ? 20 log n. 12 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. th e formula for calculating the 1/ f noise contribution at an rf frequency, f rf , and at a frequency offset, f, is given by pn = pn 1_f + 10 log(10 khz/f) + 20 log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll. 13 the phase noise is measured with the ev-adf 4106sd1z evaluation board and the agilent e4440a spectrum analyzer. the spectrum an alyzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 14 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz. 15 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 5800 mhz; n = 29000; loop b/w = 20 khz. 16 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 5800 mhz; n = 5800; loop b/w = 100 khz. timing characterisitics av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. table 2. parameter limit 1 (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulse width 1 operating temperature range (b version) is C40c to +85c.
data sheet adf4106 rev. e | page 5 of 2 02720-002 clock db22 db2 data le t 1 le db23 (msb) t 2 db1 (control bit c2) db0 (lsb) (control bit c1) t 3 t 4 t 6 t 5 figure 2. timing diagram
adf4106 data sheet rev. e | page 6 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 C 0.3 v to + 3.6 v av dd to dv dd C 0.3 v to + 0.3 v v p to gnd C 0.3 v to + 5.8 v v p to av dd C 0.3 v to + 5.8 v digital i/o voltage to gnd C 0.3 v to v dd + 0.3 v analog i/o voltage to gnd C 0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd C 0.3 v to v dd + 0.3 v rf in a to rf in b 320 mv operating temperature range industrial (b version) C 40c to +85c storage temperature range C 65c to +125c maximum junction temperature 150c tssop ja thermal impedance 112 c/w lf csp ja thermal impedance (paddle soldered) 30.4 c/w reflow soldering peak temperature 260c time at peak temperature 40 sec transistor count cmos 6425 bipolar 303 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only ; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
data sheet adf4106 rev. e | page 7 of 24 pin configurations a nd function descript ions 02720-003 r set cp cpgnd agnd 1 2 3 4 5 6 7 8 rf in b rf in a av dd ref in muxout le data clk ce dgnd 16 15 14 13 12 11 10 9 v p dv dd top view (not to scale) adf4106 note: transistor count 6425 (cmos), 303 (bipolar). figure 3 . 16 - lead tssop pin configuration 02720-004 15 muxout 14 le 13 d at a 12 clk cpgnd 1 agnd 2 agnd 3 20 c p 1 1 ce 6 7 8 dgnd 9 dgnd 10 19 18 17 16 rf in b 4 rf in a 5 r set v p dv dd dv dd pin 1 indic a t or t o p view adf4106 a v dd a v dd ref in notes 1. transis t or count 6425 (cmos), 303 (bipolar). 2. the exposed p ad must be connected t o agnd. figure 4 . 20 - lead lfcsp _vq pin configuration table 4 . pin function descri ptions pin no. tssp pin no. lfcsp mnemonic function 1 19 r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is set max cp r i 5 . 25 = so, with r set = 5.1 k?, i cp max = 5 ma. 2 20 cp charge pump output. when enabled , this provides i cp to the external loop filter, which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is the ground return pat h for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 18. 6 5 rf in a input to the rf prescaler. this small signal input is ac - coupled to the external vco. 7 6, 7 av dd analog power supply. this may range from 2.7 v to 3.3 v. decoupling capacitors to the analog ground plane shoul d be placed as close as possible to this pin. av dd must be the same value as dv dd . 8 8 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k?. see figure 18. th is input can be driven from a ttl or cmos crystal oscillator or it can be ac - coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three - state mode. taking the pi n high power s up the device, depending on the status of the power - down b it , f2. 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift register on the clk rising edg e. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches with the latch being selected using the control bits. 14 15 muxout this multiplexer output allows either the lock det ect, the scaled rf, or the scaled reference fre quency to be a ccessed externally. 15 16, 17 dv dd digital power supply. this may range from 2.7 v to 3.3 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 18 v p charge pump po wer supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5 v. ep exposed pad. the exposed pad must be connected to agnd.
adf4106 data sheet rev. e | page 8 of 24 typical performance char acteristics 02720-005 freq mags11 angs11 0.500 0.89148 ? 17.2820 0.600 0.88133 ? 20.6919 0.700 0.87152 ? 24.5386 0.800 0.85855 ? 27.3228 0.900 0.84911 ? 31.0698 1.000 0.83512 ? 34.8623 1.100 0.82374 ? 38.5574 1.200 0.80871 ? 41.9093 1.300 0.79176 ? 45.6990 1.400 0.77205 ? 49.4185 1.500 0.75696 ? 52.8898 1.600 0.74234 ? 56.2923 1.700 0.72239 ? 60.2584 1.800 0.69419 ? 63.1446 1.900 0.67288 ? 65.6464 2.000 0.66227 ? 68.0742 2.100 0.64758 ? 71.3530 2.200 0.62454 ? 75.5658 2.300 0.59466 ? 79.6404 2.400 0.55932 ? 82.8246 2.500 0.52256 ? 85.2795 2.600 0.48754 ? 85.6298 2.700 0.46411 ? 86.1854 2.800 0.45776 ? 86.4997 2.900 0.44859 ? 88.8080 3.000 0.44588 ? 91.9737 3.100 0.43810 ? 95.4087 3.200 0.43269 ? 99.1282 freq mags11 angs11 3.300 0.42777 ? 102.748 3.400 0.42859 ? 107.167 3.500 0.43365 ? 111.883 3.600 0.43849 ? 117.548 3.700 0.44475 ? 123.856 3.800 0.44800 ? 130.399 3.900 0.45223 ? 136.744 4.000 0.45555 ? 142.766 4.100 0.45313 ? 149.269 4.200 0.45622 ? 154.884 4.300 0.45555 ? 159.680 4.400 0.46108 ? 164.916 4.500 0.45325 ? 168.452 4.600 0.45054 ? 173.462 4.700 0.45200 ? 176.697 4.800 0.45043 178.824 4.900 0.45282 174.947 5.000 0.44287 170.237 5.100 0.44909 166.617 5.200 0.44294 162.786 5.300 0.44558 158.766 5.400 0.45417 153.195 5.500 0.46038 147.721 5.600 0.47128 139.760 5.700 0.47439 132.657 5.800 0.48604 125.782 5.900 0.50637 121.110 6.000 0.52172 115.400 freq unit ghz keyword r param type s impedance 50 ? data format ma figure 5 . s- parameter data for the rf input 0 ? 30 ? 5 ? 10 ? 25 ? 20 ? 15 02720-006 6 5 4 3 2 1 0 rf input frequency (ghz) rf input power (dbm) v dd = 3v v p = 3v t a = +85 c t a = ? 40 c t a = +25 c figure 6 . input sensitivity 0 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 02720-007 ? 2khz ? 1khz 900mhz 1khz 2khz frequency output power (db) v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 ? 93.0dbc/hz ref level = ? 14.3dbm figure 7 . phase noise (900 mhz, 200 khz, and 20 khz) ? 40 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 02720-008 100hz 1mhz frequency offset from 900mhz carrier output power (db) 10db/div r l = ? 40dbc/hz rms noise = 0.36 figure 8 . integrated phase noise (900 mhz, 200 khz, and 20 khz) 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 02720-009 ?400khz ?200khz 900mhz 200khz 400khz frequency output power (db) ref level = ?14.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 30 ?91.0dbc/hz figure 9 . reference spurs (900 mhz, 200 khz, and 20 khz) ?83.5dbc/hz 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 02720-010 ?2khz ?1khz 5800mhz 1khz 2khz frequency output power (db) ref level = ?10dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 figure 10 . phase noise (5.8 ghz,1 mhz, and 100 khz)
data sheet adf4106 rev. e | page 9 of 24 ? 40 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 02720-011 100hz 1mhz frequency offset from 5800mhz carrier phase noise (dbc/hz) 10db/div r l = ? 40dbc/hz rms noise = 1.8 figure 11 . integrated phase noise (5.8 ghz,1 mhz, and 100 khz) 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 02720-012 ?2m ?1m 5800 1m 2m frequenc y (hz) output power (db) ref leve l = ?10dbm ?65.0dbc ?66.0dbc v dd = 3 v , v p = 5v i cp = 5m a pfd frequenc y = 1mhz loo p bandwidth = 100khz res bandwidth = 1khz video bandwidth = 1khz swee p = 13 seconds a verages = 1 figure 12 . reference spurs (5.8 ghz,1 mhz, and 100 khz) ?60 ?100 ?90 ?80 ?70 02720-013 100 ?40 ?20 0 20 40 60 80 temperature (c) phase noise (dbc/hz) v dd = 3v v p = 3v figure 13 . phase noise (5.8 ghz,1 mhz, and 100 khz) vs. temperature ? 5 ? 105 ? 95 ? 85 ? 75 ? 65 ? 55 ? 45 ? 35 ? 25 ? 15 02720-014 5 0 1 2 3 4 tunning voltage (v) first reference spur (dbc) v dd = 3v v p = 5v fi gure 14 . reference spurs vs. v tune (5.8 ghz,1 mhz, and 100 khz) ?120 ?180 ?170 ?160 ?150 ?140 ?130 02720-015 100m 10k 100k 1m 10m phase etector frequency (hz) phase noise (dbc/hz) v dd = 3v v p = 5v figure 15 . phase noise (referred to cp output) vs. pfd frequency ?6 6 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 02720-016 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v cp (v) i cp (ma) v pp = 5v i cp settling = 5ma figure 16 . charge pump output characterist ics
adf4106 data sheet rev. e | page 10 of 24 general description reference input section the reference input stage is shown in figure 17. sw1 and sw2 are normally closed switches. sw3 is a normally open switch. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. 02720-017 100k ? nc ref in nc no sw1 sw2 buffer sw3 to r counter power-down control figure 17. reference input stage rf input stage the rf input stage is shown in figure 18. it is followed by a 2-stage limiting amplifier to generate the cml clock levels needed for the prescaler. 02720-018 500? 1.6v 500 ? agnd rf in a rf in b av dd bias generator figure 18. rf input stage prescaler (p/p +1) the dual-modulus prescaler (p/p + 1), along with the a counter and b counter, enables the large division ratio, n, to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the cmos a counter and b counter. the prescaler is programmable. it can be set in soft- ware to 8/9, 16/17, 32/33, or 64/65. it is based on a synchronous 4/5 core. there is a minimum divide ratio possible for fully contiguous output frequencies. this minimum is determined by p, the prescaler value, and is given by (p 2 ? p). a counter and b counter the a counter and b cmos counter combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 325 mhz or less. thus, with an rf input frequency of 4.0 ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. pulse swallow function the a counter and b counter, in conjunction with the dual- modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is ?? ?? r refin f abp vco f ???? where: f vco is the output frequency of the external voltage controlled oscillator (vco). p is the preset modulus of the dual-modulus prescaler (8/9, 16/17, etc.). b is the preset divide ratio of the binary 13-bit counter (3 to 8191). a is the preset divide ratio of the binary 6-bit swallow counter (0 to 63). f refin is the external reference frequency oscillator. load load from rf input stage prescaler p/p + 1 13-bit b counter to pfd 6-bit a counter n divider modulus control n = bp + a 02720-019 figure 19. a and b counters r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed.
data sheet adf4106 rev. e | page 11 of 24 phase frequency dete cto r (pfd) and charge pump the pfd takes inputs from the r counter and n counter (n = bp + a) and produces an output proportional to the phase and frequency difference between them. figure 20 is a simplified schematic. the pfd includ es a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the reference counter latch , abp2 and a bp1, control the width of the pulse. see table 7 . hi hi d1 d2 q1 q2 clr2 cp u1 u2 up down abp2 abp1 cpgnd u3 r divider programmable delay n divider v p charge pump 02720-020 clr1 figure 20 . pfd simplified schematic muxout and lock dete ct the output multiplexer on the adf4106 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function l atch. table 9 shows the full truth table. figure 21 shows the muxout section in block diagram form. lock detect muxout can be pro grammed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detec tor cycl es is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. it stay s set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n - channel , open - drain , analo g lock detect should be operated with an external pull - up resistor of 10 k? nominal. when lock is detected , this output is high with narrow, low - going pulses. 02720-021 dgnd dv dd control mux analog lock detect digital lock detect r counter output n counter output sdout muxout figure 21 . muxout circuit input shift register the adf4106 digital section includes a 24 - bit input shift register, a 14 - bit r counter, and a 19 - bit n counter, comprising a 6 - bit a counter and a 13 - bit b counter. data is clocked into the 24- bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing diagram of figure 2 . the truth table for these bits is shown in table 5 . table 6 shows a summary of how the latches are programmed. table 5 . c1, c2 truth table control bits c2 c1 d ata latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch (including prescaler) 1 1 initialization latch
adf4106 data sheet rev. e | page 12 of 24 table 6 . latch summary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp db21 db22 db23 0 0 x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 x x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 reference counter latch reserved lock detect precision test mode bits anti- backlash width 14-bit reference counter control bits reserved 13-bit b counter 6-bit a counter control bits n counter latch cp gain function latch prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits initialization latch 02720-022
data sheet adf4106 rev. e | page 13 of 24 table 7 . reference counter latch map ldp 0 1 abp2 abp1 0 0 2.9ns 0 1 1.3ns 1 0 6.0ns 1 1 2.9ns r14 r13 r12 .......... r3 r2 r1 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 x = don ? t care db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp db21 db22 db23 0 0 x reserved lock detect precision test mode bits anti- backlash width 14-bit reference counter control bits divide ratio antibacklash pulse width test mode bits should be set to 00 for normal operation. operation three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. both of these bits must be set to 0 for normal operation. 02720-023
adf4106 data sheet rev. e | page 14 of 24 table 8. n ( a , b ) counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 0 0 0 1 1 0 f4 (function latch) fastlock enable 1 1 a6 a5 .......... a2 a1 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 x x b13 b12 b11 b3 b2 b1 0 0 0 .......... 0 0 0 0 0 0 .......... 0 0 1 0 0 0 .......... 0 1 0 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 x = don?t care reserved 13-bit b counter 6-bit a counter control bits cp gain a counter divide ratio b counter divide ratio not allowed not allowed not allowed these bits are not used by the device and are don't care bits. operation cp gain charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fastlock mode is used. see function latch description. n = bp + a, p is prescaler value set in the function latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ? p). 02720-024
data sheet adf4106 rev. e | page 15 of 24 table 9 . function latch map p2 p1 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 x x 1 x 0 1 0 1 1 1 1 cpi6 cpi5 cpi4 cpi3 cpi2 cpi1 3k ? 5.1k ? 11k ? 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 tc4 tc3 tc2 tc1 0 0 0 0 3 0 0 0 1 7 0 0 1 0 11 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 1 0 0 1 39 1 0 1 0 43 1 0 1 1 47 1 1 0 0 51 1 1 0 1 55 1 1 1 0 59 1 1 1 1 63 f4 0 1 1 m3 m2 m1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 f5 x 0 1 negative positive prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state muxout control power- down 1 counter reset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal three-state fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin prescaler value pd polarity 02720-025
adf4106 data sheet rev. e | page 16 of 24 table 10 . initialization latch map p2 p1 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 x x 1 x 0 1 0 1 1 1 1 cpi6 cpi5 cpi4 cpi3 cpi2 cpi1 3k? 5.1k? 11k ? 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 tc4 tc3 tc2 tc1 0 0 0 0 3 0 0 0 1 7 0 0 1 0 11 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 1 0 0 1 39 1 0 1 0 43 1 0 1 1 47 1 1 0 0 51 1 1 0 1 55 1 1 1 0 59 1 1 1 1 63 f4 0 1 1 m3 m2 m1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 three-state f5 x 0 1 negative positive prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state muxout control power- down 1 counter reset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin prescaler value pd polarity 02720-026
data sheet adf4106 rev. e | page 17 of 24 the function latch with c2 and c1 set to 1 and 0, respectively, the on - chip function latch is p rogrammed. table 9 shows the input data format for programming the function l atch. counter reset db2 (f1) is the counter reset bit. when this is 1, the r counter and the n ( a , b ) counter are reset. for normal operation , this bit sh ould be 0. when powering up, disable the f1 bit (set to 0) . t he n counter will then resume counting in close alignment with the r counter. (the maximum error is one prescaler cycle). power - down db3 (pd1) and db21 (pd2) provide programmable power - down modes . they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2, pd1. in the programmed asynchronous power - down, the device powers down immediately after latching 1 into the pd1 bit , with the con dition that pd2 is loaded with 0. in the programmed synchrono us power - down, the device power - down is gated by the charge pump to prevent unwanted frequency jumps. once the power - down is enabled by writing 1 into the pd1 bit ( provided that 1 has also been l oaded to pd2), then the device g o es into power - down during the next charge pump event. when a power - down is activated (either synchronous or asynchronous mode, i ncluding ce pin activated power - down), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three - state mode. ? the digital clock detect circuitry is reset. ? the rf in input is debiased. ? the reference input buffer circuitry is disable d. ? the input register remains active and capable of loading and latching data. muxout control the on - chip multiplexer is controlled by m3, m2, and m1 on the adf4106 family. tabl e 9 shows the truth table. fastlock enable bit db9 of the function la tch is the fastlock enable b it. w hen this bit is 1 , f astlock is enabled. fastlock mode bit db10 of the function latch is the fastlock mode bit. when f astlock is enabled, this bit determines which fastlock m ode is used. if the fastlock mod e b it is 0, then fastlock mode 1 is selected ; and if the fastlock mo de bit is 1, then fastlock mode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters f astlock when 1 is written to the cp g ain bit in the n ( a , b ) counter latch. the device exits f astlock when 0 is written to the cp g ain bit in the n ( a , b ) counter latch. fastlock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters f astlock when 1 is written to the cp g ain bit in the n ( a , b ) counter latch. the device exits f astlock under the control of the timer c ounter. after the timeout period , which is determined by the value in tc4 to tc1, the cp g ain bit in the n ( a , b ) counter latch is aut omatically reset to 0 , and the device reverts to normal mode instead of f astlock. see table 9 for the timeout periods. timer counter control the user has the option of programming two charge pump currents. the intent is that curren t setting 1 is used when the rf output is stable and the system is in a static state. current setting 2 is used when the system is dynamic and in a state of change ( that is , when a new output frequency is programmed). the normal sequence of events follows . the user initially decides what the preferred charge pump currents are going to be. for example, the choice may be 2.5 ma as current setting 1 and 5 ma as the current setting 2. simultaneously, the decision must be made as to how long the secondary curre nt stay s active before reverting to the primary current. this is controlled by the timer counter control bit s , db14 to db11 (tc4 to tc1) , in the function la tch. the truth table is given in table 9 . t o program a new output frequency , simply program the n ( a , b ) counter latch with new values for a and b. simultaneously, the cp g ain bit can be set to 1, which sets the charge pump with the value in cpi6 to cpi4 for a period of time determined by tc4 to tc1. when this time is up, the cha rge pump current reverts to the value set by cpi3 to cpi1. at the same time , the cp g ain bit in the n ( a , b ) c ounter latch is reset to 0 and is now ready for the next time the user wishes to change the frequency. note that there is an enable feature on th e timer cou nter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mo de bit (db10) in the function lat ch to 1.
adf4106 data sheet rev. e | page 18 of 24 charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cpi4 program current setting 2 for the charge pump. the truth table is given in table 9 . prescaler value p2 and p1 in the function lat ch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always les s than or equal to 325 mhz. th erefore , with an rf frequency of 4 ghz, a prescaler value of 16/17 is valid , but a value of 8/9 is not valid. pd polarity this bit sets the phase detector polarity b it. see table 9 . cp three - state this bit controls the cp output pin. with the bit set high, the cp output is put into three - state. with the bit set low, the cp output is enabled. the initialization l atch when c2 and c1 = 1 and 1 , respectively, the initialization l atch is programmed. this is essentially the same as the function lat ch (programmed when c2 and c1 = 1 and 0 , respectively ). however, when the initialization l atch is programmed , there is an additional internal reset pulse applied to the r and n ( a , b ) counters. this pulse ensures tha t the n ( a , b ) counter is at the load point when the n ( a , b ) counter data is latched and the device begin s counting in close phase alignment. if the l atch is programmed for synchronous power - down (ce pin is high , pd1 bit is high , and pd2 bit is low), the internal pulse also triggers this power - down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse ; therefore, close phase alignment is maintained when counting resumes. when the first n ( a , b ) counter data is latched after initialization, the internal reset pulse is again activated. however, successive n ( a , b ) counter loads after this will not trigger the internal reset pulse. device programming a fter initial power - up after initial power up of the device, ther e are three methods f o r program ming the device : initialization latch, ce pin, and counter reset. initialization latch method ? apply v dd . ? program the initialization latc h (11 in two lsbs of input word). make sure that the f1 bit is programmed to 0. ? d o a fun ction latc h load (10 in two lsbs of the control word), making sure that the f1 bit is programmed to a 0. ? d o an r load (00 in two lsbs). ? d o an n ( a , b ) load (01 in two lsbs). when the initialization lat ch is loaded, the following occurs: ? the function latc h contents are loaded. ? an internal pulse resets the r, n ( a , b ) , and t imeout counters to load - state conditions and also three - states the charge pump. note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. ? latching the first n ( a , b ) counter data after the initialization word a ctivate s the same internal reset pulse. successive n ( a , b ) loads will not trigger the internal reset pulse , unless t here is another initialization. ce pin method ? apply v dd . ? bring ce low to put the device into power - down. this is an asychronous power - down in that it happens immediately. ? program the function l atch (10). ? program the r counter la tch (00). ? program the n ( a , b ) counter l atch (01). ? bring ce high to take the device out of power - down. the r and n ( a , b ) counters now resume counting in close alignment. note that after ce goes high, a 1 s duration may be required for the prescaler band gap voltage and oscillator i nput buffer bias to reach steady state. ce can be used to power the device up and down to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it is programmed at least once after v dd is initially applied. counter reset method ? apply v dd . ? do a function latch l oad (10 in two lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. ? do an r c ounter l oad (00 in two lsbs). ? do an n ( a , b ) c ounter l oad (01 in tw o lsbs). ? do a function latch l oad (10 in two lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initialization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three - states the charge pump but does not trigger synchronous power - down.
data sheet adf4106 rev. e | page 19 of 24 applications local oscillator for lmds base station transmitter figure 22 shows the adf4106 being used with a vco to produce the lo for an lmds base station. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ?. a typical base station system would have either a tcxo or an ocxo driving the reference in p ut without any 50 ? termination. to achieve a channel spacing of 1 mhz at the output, the 10 mhz reference input must be divided by 10, using the on - chip reference divider of the adf4106. the charge pump output of the adf4106 ( p in 2) drives the loop fil ter. in calculating the loop filter component values, a number of items need to be considered. in this example, the loop filter was designed so that the overall phase margin for the system would be 45. other pll system specifications include : k d = 2.5 m a k v = 80 mhz/v loop bandwidth = 50 khz f pfd = 1 mhz n = 5800 extra reference spur attenuation = 10 db t hese specifications are needed and used to derive the loop filter component values shown in figure 22. the circuit in figure 22 show s a typical phase noise performance of ?83 .5 dbc/hz at 1 khz offset from the carrier. spurs are better than ?62 dbc. the loop filter output drives the vco, which in turn is fed back to the rf input of the pll synt hesizer and also drives the rf o utput terminal. a t - circuit configuration provides 50 ? matching between the vco output, the rf output, and the rf in terminal of the synthesizer. in a pll system, it is important to know when the system is in lock. in figure 22 , this is accomplished by using the muxout signal from the synthesizer. the muxout pin can be programmed to monitor various internal signals in the synthesizer. one of these is the ld or lock - detect signal. adf4106 ce clk data le 1000pf 1000pf ref in 100pf cp muxout cpgnd agnd dgnd 100pf 1.5nf 20pf 100pf 51? 6.2k? 4.3k? 100pf 18? note decoupling capacitors (0.1 f/10pf) on av dd , dv dd , and v p of the adf4106 and on v cc of the v956me03 have been omitted from the diagram to aid clarity. spi ? -compatible serial bus r set rf in a rf in b av dd dv dd v p fref in v dd v p lock detect v cc v956me03 1, 3, 4, 5, 7, 8, 9, 11, 12, 13 18? 18? 100pf rf out 5.1k? 7 15 16 8 2 14 6 5 1 9 4 3 14 2 10 51? 02720-027 figure 22 . local oscillator for lmds base station
adf4106 data sheet rev. e | page 20 of 24 interfacing the adf4106 has a simple spi - compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 24 bits clock ed into the input registe r on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the l atch truth table. the maximum allowable serial clock rate is 20 mhz. this mea ns that the maximum update rate for the device is 833 khz , or one update every 1.2 s. this is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. aduc812 interface figure 23 shows the interface betwe en the adf4106 and the aduc812 m icro c onverter ? . since the aduc812 is based on an 8051 core, this inte rface can be used with any 8051 - based microcontroller. the microconverter is set up for spi master mod e with cpha = 0. to initiate the oper ation, the i/o port driving le is brought low. each latch of the adf4106 needs a 24- bit word. this is accomplished by writing three 8 - bit bytes from the microconverter to the device. when the third byte is written , the le input should be brought high to c omplete the transfer. on first applying power to the adf4106, it needs four writes (one each to the initialization latch, function la tch, r counter latch , and n counter latch) for the output to become active. i/o port lines on the aduc812 are also used to control power - down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. clk data le ce muxout (lock detect) mosi adf4106 sclock i/o ports aduc812 02720-028 figure 23 . aduc812 - to - adf4106 interface adsp2181 interface figure 24 shows the interface between the adf4106 and the adsp21 xx digital signal pr ocessor (dsp). the adf4 106 needs a 24 - bit serial word for each latch write. the easiest way to accomplish this using the adsp21 xx family is to use the autobuffered transmit mode of operation with alternate fra ming. this provides a means for transmitting an entire block of seria l data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24 - bit word. to program each 24 - bit latch, store the three 8 - bit bytes, enable the a utobuffered mode, and write to the transmit register of t he dsp. this last operation initiates the autobuffer transfer. clk data le ce muxout (lock detect) mosi adf4106 sclock i/o flags adsp-21xx tfs 02720-029 figure 24 . adsp - 21xx - to - adf4106 interface pcb design guideline s for chip scale package the lands on the lfcsp (cp - 20) are rectangular. the printed circuit board (pcb) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensure s that the solder joint size is maximized. the bottom of the lfcsp has a central thermal p ad. the thermal pad on the pcb should be at least as large as this exposed pad. on the pcb , there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensure s that shorting is avoided. thermal vias may be used on the pcb thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm , and the via barrel should be pla ted with 1 oz. copper to plug the via. the user should connect the pcb thermal pad to agnd.
data sheet adf4106 rev. e | page 21 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 25 . 16- lead thin shrink small outline package [tssop ] ( ru- 16) dimensions shown in millimeters 3.75 bcs sq compliant to jedec standards mo-220-vggd-1 1 0.50 bsc pin 1 indic a t or 0.75 0.60 0.50 t o p view 12 max 0.80 max 0.65 ty p sea ting plane pin 1 indic a t or coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 2.25 2.10 sq 1.95 20 6 1 6 10 11 1 5 5 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 04-09-2012-b bot t om view exposed pad 4.10 4.00 sq 3.90 figure 26 . 20- lead lead frame chip scale package [ lfcsp _vq ] 4 mm 4 mm body, very thin quad ( cp - 20 - 1 ) dimensions shown in millimeters
adf4106 data sheet rev. e | page 22 of 24 ordering guide model 1 temperature range package description package option adf4106bru C 40c to + 85c 16- lead thin shrink small outline package (tssop) ru -16 adf4106bru - ree l C 40c to + 85c 16 - lead thin shrink small outline package (tssop) ru - 16 adf4106bru- ree l7 C 40c to + 85c 16- lead thin shrink small outline package (tssop) ru -16 ADF4106BRUZ C 40c to + 85c 16- lead thin shrink small outline package (tssop) ru -16 ADF4106BRUZ-rl C 40c to + 85c 16- lead thin shrink small outline package (tssop) ru -16 ADF4106BRUZ-r7 C 40c to + 85c 16- lead thin shrink small outline package (tssop) ru -16 adf4106bcpz C4 0c to + 85c 20- lead lead frame chip scale package (lfcsp _vq) cp-20-1 adf4106bcpz-rl C 40c to + 85c 20- lead lead frame chip scale package (lfcsp _vq) cp-20-1 adf4106bcpz-r7 C 40c to + 85c 20- lead lead frame chip scale package (lfcsp _vq) cp-20-1 ev - adf 4106sd1z evaluation board ev -adf411xsd1z evaluation board 1 z = rohs complia nt.
data sheet adf4106 rev. e | page 23 of 24 notes
adf4106 data sheet rev. e | page 24 of 24 notes ? 2001 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respecti ve owners. d02720 - 0 - 11/12(e)

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