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16 - bit, 8 - channel simultaneous sampling data acquisition system data sh eet adas3023 features ease - of - use , 16- bit complete data acquisition system simultaneous sampling selection of 2, 4, 6, and 8 channels differential input voltage range: 20.48 v max imum high impedance 8 - channel input: >500 m high input common - mode rejection: 9 5 .0 db user - programmable input ranges on - chip 4.096 v reference and buffer no latency/pipeline delay (sar architecture) serial 4 - wire 1.8 v to 5 v spi - /sport - compatible interface 40 - lead lfcsp package (6 mm 6 mm) ? 40 c to +85c industrial temperature range applications mul ti channel data acquisition and system monitoring process control power line monitoring automated test equipment patient monitoring spectrum analysis instrumentation functional block dia gram figure 1. general description the adas3023 is a complete 16 - bit successive approximation - based analog - to - digital data acquisition s ystem. this device is capable of simultaneously sampling up to 500 ksps for two channels, 250 ksps for four channels, 167 ksps for six chan - nels , and 125 ksps for eight channels manufactured on the analog devices, inc., proprietary i cmos? high voltage industrial process technolog y. the adas3023 integrates eight channel s of low leakage track and hold, a programmable gain instru mentation amplifier (pgia) stage with a high common - mode rejection offering four differential input ranges, a precision low drift 4.096 v reference and buffer, and a 16 - bit charge redistribution successive approxi - mation register ( sar) analog - to - digital co nverter (adc). the adas3023 can resolve differential input ranges of up to 20.48 v when using 15 v supplies. the adas3023 simplifies design challenges by eliminating signal buffering, level shifting, amplification and attenuation, common - mode rejection, settling time, or any of the other analog signal conditioning challenges, yet allow s for smaller form factor, faster time to market, and lower costs. the adas3023 is factory calibrated and its operation is specified from ?40 c to +85c. table 1 . typical input range selection single - ended signals 1 input range, v in 0 v to 1 v 1.28 v 0 v to 2.5 v 2.56 v 0 v to 5 v 5.12 v 0 v to 10 v 10.24 v 1 see figure 39 and figure 40 in the analog inputs section for more information. buf ref logic/ interface track and hold pgia pulsar adc diff to com in0 cnv cs sck din sdo refin busy in1 in2 in3 in4 in5 in6 in7 com vddh avdd dvdd vio reset refx dgnd agnd vssh pd adas3023 10942-001 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
adas3023 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 6 absolute maximum ratings ....................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 terminology .................................................................................... 17 theory of operation ...................................................................... 19 overview ...................................................................................... 19 operation ..................................................................................... 19 transfer functions ...................................................................... 20 typical application connection diagram .............................. 21 analog inputs .............................................................................. 21 voltage reference input/output .............................................. 22 power supply ............................................................................... 24 power dissipation modes .......................................................... 24 conversion modes ..................................................................... 25 digital interface .............................................................................. 26 conversion control ................................................................... 26 reset and power - down (pd) inputs .................................... 26 serial data interface ................................................................... 27 general timing ........................................................................... 28 configuration register .............................................................. 29 packaging and ordering information ......................................... 30 outline dimensions ................................................................... 30 ordering guide .......................................................................... 30 revision history 5 / 1 3 revision 0: initial version rev. 0 | page 2 of 32
data sheet adas3023 specifications vddh = 15 v 5% , vssh = ?15 v 5% , avdd = dvdd = 5 v 5% ; vio = 1. 8 v to avdd , internal reference v ref = 4.096 v , f s = 500 k sps , a ll specifications t min to t max , unless otherwise noted. table 2 . parameter test conditions/comments min typ max unit 1 resolution 16 bits analog input ( in0 to in7 , com ) input impedance z in 500 m operating input voltage range 2 v in , o n any single pin vssh + 2 .5 vddh ? 2.5 v differential input voltage ranges , v in v in x ? com pgia gain = 0.2, v in = 40.96 v p -p ?5v ref +5v ref v pgia gain = 0.4, v in = 20.48 v p -p ?2.5v ref +2.5v ref v pgia gain = 0.8, v in = 10.24 v p -p ?1.25v ref +1.25v ref v pgia gain = 1.6, v in = 5.12 v p -p ?0.625v ref +0.625v ref v throughput conversion rate two channels 0 500 ksps four channels 0 250 ksps six channels 0 167 ksps eight channels 0 125 ksps transient response 3 full - scale step 8 20 ns dc accuracy no missing codes 16 bits integral linearity error pgia gain = 0.2 , 0.4, or 0.8, com = 0 v ?2 .5 1 +2 .5 lsb pgia gain = 1.6 , com = 0 v ?3 1 +3 differential linearity error all pgia gain s , com = 0 v ?0.95 0.5 +1. 25 lsb transition noise pgia gain = 0.2 or 0.4 6 lsb pgia gain = 0.8 7 lsb pgia gain = 1.6 10 lsb gain error 4 external reference, all pgia gains ? 0.075 + 0.075 %fs gain error match, delta mean external reference, all pgia gains ? 0.0 5 +0.0 5 %fs gain error temperature drift external reference, pgia gain = 0.2 , 0.4, or 0.8 1 ppm/c external reference, pgia gain = 1.6 2 ppm/c offset error 4 external reference, pgia gain = 0. 2 ? 65 ? 35 +12 lsb external reference, pgia gain = 0.4 ? 85 ? 45 +12 lsb external reference, pgia gain = 0. 8 ? 10 0 + 10 lsb external reference, pgia gain = 1.6 0 130 250 lsb offset error match , delta mean external reference, pgia gain = 0.2, 0.4, 0.8 , or 1.6 ?15 1 +1 5 lsb offset error temperature drift external reference, pgia gain = 0.2 or 0.4, in0 to in7 0 0.5 2 ppm/c external reference, pgia gain = 0.8, in0 to in7 0 1. 5 3 ppm/c external reference, pgia gain = 1.6, in0 to in7 0 2 .5 5 ppm/c ac accuracy 5 internal reference signal - to - noise ratio f in = 1 khz , com = 0 v pgia gain = 0.2 90.0 9 1.5 db pgia gain = 0.4 89.5 91.0 db pgia gain = 0.8 87.5 89.0 db pgia gain = 1.6 85.0 86.5 db signal - to - noise + distortion (sinad) f in = 1 khz, two , four , six , and eight c hannels pgia gain = 0.2 89.5 9 1.0 db pgia gain = 0.4 89.0 90.5 db pgia gain = 0.8 87.0 88.5 db pgia gain = 1.6 84.0 86.0 db rev. 0 | page 3 of 32
adas3023 data sheet parameter test conditions/comments min typ max unit 1 dynamic range f in = 1 khz, ?60 db input pgia gain = 0.2 91.0 92 db pgia gain = 0.4 90.5 91.5 db pgia gain = 0.8 88.0 89 .5 db pgia gain = 1.6 86.0 8 7.0 db total harmonic distortion f in = 1 khz, all pgia gains ?100 db spurious - free dynamic range f in = 1 khz, all pgia gains 1 05 db channel -to - channel crosstalk f in = 1 khz, all channels inactive 95 db dc common - mode rejection ratio (cmrr) all channels pgia gain = 0.2 95 .0 db pgia gain = 0.4 95.0 db pgia gain = 0.8 95.0 db pgia gain = 1.6 95.0 db ?3 db input bandwidth ?40 dbfs 8 mhz internal reference refx pins output voltage t a = 25c 4.088 4.096 4.104 v output current t a = 25c 250 a temperature drift refen bit = 1 5 ppm/c refen bit = 0 , refin pin = 2.5v 1 ppm/c line regulation internal reference avdd = 5 v 5% 20 v/v buffer only avdd = 5 v 5% 4 ppm refin output voltage 6 t a = 25c 2.495 2.5 2.505 v turn - on settling time c refin , c ref1 , c ref2 = 10 f||0.1 f 100 ms external reference refen bit = 0 voltage range refx input , refin = 0 v 4.000 4.096 4.104 v refin input (buffered) 2.5 2.505 v current drain f s = 500 ksps 100 a digital inputs logic levels v il vio > 3 v ?0.3 +0.3 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v v il vio 3 v ?0.3 +0.1 vio v v ih vio 3 v 0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs 7 data format twos complement v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vio 1.8 avdd + 0.3 v avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v vddh vddh > input voltage + 2.5 v 14.25 15 15.75 v vssh vssh < input voltage ? 2.5 v ?15.75 ?15 ?14.25 v rev. 0 | page 4 of 32
data sheet adas3023 parameter test conditions/comments min typ max unit 1 i vddh two channels 5.0 5.5 ma four channels 6.0 7.0 ma six channels 9.5 10.5 ma eight channels 9.5 10.5 ma pd = 1 10.0 a i vssh two channels ? 5.5 + 5.0 ma four channels ? 6.5 + 5.5 ma six channels ? 10.0 ? 8.5 ma eight channels ? 10.0 ? 8 .5 ma a ll pgia gains , pd = 1 10.0 a i avdd a ll pgia gains , pd = 0, reference buffer enabled 16.0 17.0 ma all pgia gains, pd = 0, r eference buffer disabled 15.5 ma a ll pgia gains , pd = 1 100 a i dvdd a ll pgia gains , pd = 0 2.5 3 ma a ll pgia gains , pd = 1 100 a i vio a ll pgia gains , pd = 0 , vio = 3.3 v 1.0 m a a ll pgia gains , pd = 1 10.0 a power supply sensitivity external r eference, t a = 25c pgia gain = 0.2 or 0.4, vddh/vssh = 15 v 5% 0. 1 lsb pgia gain = 0. 8, vddh/vssh = 15 v 5% 0.2 lsb pgia gain = 1.6, vddh/vssh = 15 v 5% 0.4 lsb pgia gain = 0.2 or 0.4, avdd, dvdd = 5 v 5% 1 .0 lsb pgia gain = 0. 8, avdd, dvdd = 5 v 5% 1 .5 lsb pgia gain = 1.6, avdd, dvdd = 5 v 5% 2.5 lsb temperature range specified performance t min to t max ?40 +85 c 1 the lsb unit means least significant bit. the weight of the lsb, referred to input, changes depending on the input voltage ra nge. see the programmable gain section f or the lsb size . 2 full - scale differential input ranges of 2.56 v, 5.12 v, 10.24 v, and 20.48 v are set by the configuration register. 3 if using the external multiplexer in front of the adas3023 , it must be switched at least 820 ns prior to the rising edge of cnv. 4 see the terminology section. these parameters are specified at ambient temperature wi th an external reference. all other influences of temperature and supply are measured and specified separately. 5 all ac specifications expressed in decibels are referenced to the full - scale input range (fsr) and are tested with an input signal at 0.5 db b elow full scale, unless otherwise specified. 6 this is the output from the internal band gap reference. 7 there is no pipeline delay. conversion results are available immediately after a conversion is completed. rev. 0 | page 5 of 32
adas3023 data sheet timing specification s vddh = 15 v 5%, v ssh = ?15 v 5% , a vdd = dvdd = 5 v 5% , v io = 1.8 v t o avdd, i nternal referenc e v ref = 4. 096 v, f s = 500 ks ps, all specifications t min t o t max , unless otherwise noted. 1 t able 3. parameter symbol min typ max unit time between conversions t cyc warp 2 mode, cms = 0 two channels 2. 0 100 0 s four channels 4. 0 100 0 s six channels 6. 0 100 0 s eight channels 8. 0 100 0 s normal mode (default), cms = 1 two channels 2. 1 100 0 s four channels 4. 1 100 0 s six channels 6. 1 100 0 s eight channels 8.1 1000 s conversion time : cnv rising edge to data available t conv warp mode, cms = 0 two channels 148 5 1630 ns four channels 285 0 3340 ns six channels 421 5 5000 ns eight channels 558 0 6700 ns normal mode (default) , cms = 1 two channels 157 5 1720 ns four channels 294 0 3430 ns six channels 430 5 5090 ns eight channels 567 0 6790 ns cnv pulse width t cnvh 10 ns cnv high to hold time (aperture delay) t ad 2 ns cnv high to busy/sdo2 d elay t cbd 520 ns sck period t sck t sdov + 3 ns low time t sckl 5 ns high time t sckh 5 ns sck falling edge to data remains valid t sdoh 4 ns sck falling edge to data valid delay t sdov vio > 4.5 v 12 ns vio > 3 v 18 ns vio > 2.7 v 24 ns vio > 2.3 v 25 ns vio > 1.8 v 37 ns cs / reset/pd cs / reset/pd low t o sdo d15 msb valid t en vio > 4.5 v 7 ns vio > 3 v 8 ns vio > 2.7 v 1 0 ns vio > 2.3 v 15 ns vio > 1.8 v 2 0 ns cs / reset/pd high to sdo high impedance t dis 25 ns cnv rising to cs t ccs 5 ns rev. 0 | page 6 of 32
data sheet adas3023 parameter symbol min typ max unit din din valid setup time from sck falling edge t dins 4 ns din valid hold time from sck falling edge t dinh 4 ns reset/pd high pulse t rh 5 ns 1 see figure 2 and figure 3 for load conditions. 2 exceeding the maximum time has an effect on the accuracy of the co nversion (see the conversion modes section). circuit and voltage diagrams f igure 2 . load circuit for digital interface timing f igure 3 . voltage levels for timing i ol 500a 500a i oh 1.4v to sdo c l 50 pf 10942-002 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 1 2v if vio > 2.5v; vio ? 0.5v if vio < 2.5v. 2 0.8v if vio > 2.5v; 0.5v if vio < 2.5v. 10942-003 rev. 0 | page 7 of 32
adas3023 data sheet timing diagrams figure 4 . general timing diagram with busy/sdo2 disabled figure 5 . general timing diagram with busy/sdo2 enabled 1 16 1 16 1 16 1 16 1 16 1 16 phase c nv sck din sdo busy/ sdo2 cs soc soc eoc note 2 note 1 note 4 note 3 note 2 note 1 eoc power up t conv t cyc t cnvh t cbd t ad conversion (n) conversion (n + 1) acquisition (n + 1) acquisition (n + 2) soc data (n) cfg (n + 2) cfg (n + 3) ch0 ch1 ch7 ch0 ch1 ch7 data (n + 1) 10942-004 notes 1. data access can only occur after conversion. both conversion result and the cfg register are updated at the end of the conversion (eoc). 2. a total of 16 sck falling edges are required for conversion result. an additional 16 edges after the last conversion result on busy reads back the cfg associated with conversion. 3. cs can be held low or connected to cnv. cs is shown with full independent control. 4. for optimal performance, data access should not occur during the sampling instant. a minimum time of at least the aperature delay, t ad , should lapse prior to data access. 1 16 phase cnv sck din sdo busy/ sdo2 cs soc soc eoc note 1 note 4 note 3 note 2 note 1 eoc power up t conv t cyc t cnvh t ad conversion (n) conversion (n + 1) acquisition (n + 1) acquisition (n + 2) soc data (n) cfg (n + 2) cfg (n + 3) data (n + 1) ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 1 16 1 16 1 16 1 16 1 16 1 16 1 16 10942-005 notes 1. data access can only occur after conversion. both conversion result and the cfg register are updated at the end of the conversion (eoc). 2. a total of 16 sck falling edges are required for conversion result. an additional 16 edges after the last conversion result on busy reads back the cfg associated with conversion. 3. cs can be held low or connected to cnv. cs is shown with full independent control. 4. for optimal performance, data access should not occur during the sampling instant. a minimum time of at least the aperature delay, t ad , should lapse prior to data access. rev. 0 | page 8 of 32
data sheet adas3023 absolute maximum rat ings table 4 . parameter rating analog inputs/outputs inx, com to agnd vssh ? 0.3 v to vddh + 0.3 v ref x to agnd agnd ? 0.3 v to avdd + 0.3 v refin to agnd agnd ? 0.3 v to +2.7 v refn to agnd 0.3 v ground voltage differences agnd, rgnd, dgnd 0.3 v supply voltages vddh to agnd C 0.3 v to +16.5 v vssh to agnd +0.3 v to ?16.5 v avdd, dvdd, vio to agnd ?0.3 v to +7 v acap, dcap, rcap to ag nd ?0.3 v to + 2.7 v digital inputs/outputs cnv, din, sck, reset, pd, cs to dgnd ?0.3 v to vio + 0.3 v sdo, busy/sdo2 to d gnd ?0.3 v to vio + 0.3 v internal power dissipation 2 w junction temperature 125c storage temperature range ?65c to +125c thermal impedance ja (lfcsp) 44.1 c/w jc (lfcsp) 0.28 c/w esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y . rev. 0 | page 9 of 32
adas3023 data sheet pin configuration and function descripti ons figure 6. pin configuration table 5 . pin function descriptions pin no. mnemonic type 1 description 1 to 4 in0 to in3 ai input channel 0 to input channel 3. 6 to 9 in4 to in7 ai input channel 4 to input channel 7. 5, 14, 23, 24, 29, 30, 40 agnd p analog ground. connect agnd to the system analog ground plane. 10 com ai in0 to in7 common channel input. input channel in0 to input channel in7 are referenced to a common point. the maximum voltage on this pin is 10.24 v for all pgia gains. 11 cs chip select. active low signal. enables the digital interface for writing and reading data. use the cs pin when shar ing the serial bus. for a dedicated and simplified adas3023 serial interface, tie cs to dgnd or cnv. 12 din di data input. din is the s erial data input for writing the 16 - bit configuration (cfg) word that is clocked in to the device on the sck rising edges. the cfg is an internal register that is updated on the rising edge of the next end of a conversion pulse , which coincides with the falling edge of busy /sdo2 . the cfg register is written into the device on the fir st 16 clocks after conversion. to avoid corrupting a conversion due to digital activity on the serial bus, do not write data during a conversion. 13 reset di asynchronous reset. a low -to - high transition resets the adas3023 . the current conversion, if active, is aborted and the cfg register is reset to t he default state. 15 pd di power - down. a low -to - high transition powers down the adas3023 , minimi z ing the device operating current . note that pd must be held high until the user is ready to power on the device. after powering on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of one dummy conversion before the device is ready to convert. n ote that the reset pin remains low for 10 0 ns after the release of pd. see the power - down mode secti on for more information. 16 sck di serial clock input. the din and sdo data sent to and from the adas3023 are synchronized wit h sck. 17 vio p digital interface supply. nominally, it is recommended that vio be at the same voltage as the supply of the host interface: 1.8 v, 2.5 v, 3.3 v, or 5 v. 18 sdo do serial data output. the conversion result is output on this pin and synchronized to the sck falling edges. the conversion results are presented on this pin in two s complement format . 19 busy/sdo2 do busy/ serial data output 2 . the converter busy signal is always output on the busy/sdo2 pin when cs is logi c high. if sdo2 is enabled when cs is brought low after the eoc, the sdo outputs the data . the conversion result is output on this pin and synchronized to the sck falling edges. the conversion results are presented on this pin in twos com plement format. 20 cnv di convert input. a conversion is in i tiated o n the rising edge of the cnv pin. 21, 22 dgnd p digital ground. connect dgnd to the system digital ground plane. 25 dcap p internal 2.5 v digital regulator output. decouple dcap, an internally regulated output , using a 10 f and a 0.1 f local capacitor . 26 acap p internal 2. 5 v analog regulator output. this regulator supplies power to the internal adc core and to all of the supporting analog circuits , except for the internal reference. decouple this internally regulated output ( acap ) using a 10 f capacitor and a 0.1 f local capacitor. 1 in0 2 in1 3 in2 4 in3 5 agnd 6 in4 7 in5 8 in6 9 in7 10 com 23 agnd 24 agnd 25 dcap 26 acap 27 dvdd 28 avdd 29 agnd 30 agnd 22 dgnd 21 dgnd 11 sc 21 nid 31 teser 51 dp 71 oiv 61 kcs 81 ods 91 2ods/ysub 02 vnc 41 dnga 33 1fer 43 2fer 53 dngr 63 nfer 73 nfer 83 hssv 93 hddv 04 dnga 23 nifer 13 pacr notes 1. connect the exposed pad to vssh. adas3023 top view (not to scale) 10942-006 pin 1 indicator rev. 0 | page 10 of 32
data sheet adas3023 pin no. mnemonic type 1 description 27 dvdd p digital 5 v supply. decouple th e dvdd supply to dgnd using a 10 f capacitor and 0.1 f local capacitor. 28 avdd p analog 5 v supply. decouple the avdd supply to agnd using a 10 f capacitor and 0.1 f local capacitor. 31 rcap p internal 2.5 v analog regulator output. rcap supplies power to the internal reference. decouple this internally regulated output (rcap) using a 10 f capacitor and a 0.1 f local capacitor. 32 refin internal 2.5 v band gap reference output, reference buffer input, or reference power - down input. ref1 and ref2 must be tied together externally. see the voltage refer ence input/output section for more information. 33, 34 ref1, ref2 ai/o reference input/output. regardless of the reference method, ref1 and ref2 need individual decoupling using external 10 f ceramic capacitors connected as close to ref1, ref2, and refn as possible. see the voltage reference input/output section for more information. 35 rgnd p reference supply ground. connect rgnd to the system a nalog ground plane. 36, 37 refn p reference input/output ground. connect t he 10 f capacitors that are on ref1 and ref2 to the refn pins , then connect the refn pins to the system analog ground plane. 38 vssh p high voltage analog negative supply. nominally , the supply of vssh is ? 15 v. decouple vssh using a 10 f capacitor and a 0.1 f local capacitor. connect the exposed pad to vssh. 39 vddh p high voltage analog positive supply. nominally, the supply of vddh is 15 v. decouple vddh using a 10 f capacitor and a 0.1 f local capacitor. ep n/a exposed pad . connect the exposed pad to vssh. 1 ai = a nalog i nput, ai/o = analog input/output, di = d igital i nput, do = d igital o utput, p = p ower , and n/a means not app licable. rev. 0 | page 11 of 32
adas3023 data sheet typical performance characteristics vddh = 15 v, vssh = ?15 v, avdd = dvdd = 5 v, vio = 1.8 v to avdd, unless otherwise noted. figure 7 . integral nonlinearity (inl) vs. code for all pgia gains figure 8 . differential nonlinearity (dnl) vs. code for all pgia gains figure 9 . histogram of a dc input at code center, pgia gain = 0.2 figure 10 . histogram of a dc input at code center, pgia gain = 0.4 figure 11 . histogram of a dc input at code center, pgia gain = 0.8 figure 12 . histogram of a dc input at code center, pgia gain = 1.6 0 8192 16384 24576 32768 code 40960 49152 57344 65536 inl (lsb) ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 for all pgia gains inl max = 0.875 inl min = ?1.216 10942-101 0 8192 16384 24576 32768 code 40960 49152 57344 65536 dnl (lsb) ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 for all pgia gains dnl max = 0.794 dnl min = ?0.661 10942-102 0 50000 100000 150000 200000 250000 300000 350000 400000 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 8007 count code in hex pgia gain = 0.2 f s = 500ksps internal reference 0 0 0 83 23813 278780 190408 6909 7 0 0 10942-103 0 50000 100000 150000 200000 250000 300000 350000 400000 7ff7 7ff8 7ff9 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 count code in hex pgia gain = 0.4 f s = 500ksps internal reference 0 0 0 962 74640 325285 97631 1481 1 0 0 10942-104 0 50000 100000 150000 200000 250000 300000 350000 400000 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 8007 count code in hex pgia gain = 0.8 f s = 500ksps internal reference 0 0 201 18671 188714 248346 43158 908 2 0 0 10942-105 0 50000 100000 150000 200000 250000 300000 350000 400000 8067 8068 8069 806a 806b 806c 806d 806e 806f 8070 8071 count code in hex pgia gain = 1.6 f s = 500ksps internal reference 0 6 450 9497 70413 185455 171423 56261 6254 238 3 10942-106 rev. 0 | page 12 of 32
data sheet adas3023 figure 13 . reference drift, internal reference figure 14 . reference buffer drift, internal reference figure 15 . 1 khz fft, pgia gain = 0.2 figure 16 . 1 khz fft, pgia gain = 0.4 figure 17 . 1 khz fft, pgia gain = 0.8 figure 18 . 1 khz fft, pgia gain = 1.6 0 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 40 50 60 count reference drift (ppm/c) 10942- 1 16 14 15 13 13 11 3 5 6 2 3 2 3 0 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 40 50 60 count reference buffer drift (ppm/c) 10942-117 46 13 2 1 28 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 amplitude (dbfs) frequency (khz) pgia gain = 0.2 f s = 500ksps f in = 1.12khz snr = 91.3db sinad = 91.3db thd = ?110.6db sfdr = 106.6db internal reference 10942-107 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 amplitude (dbfs) frequency (khz) pgia gain = 0.4 f s = 500ksps f in = 1.12khz snr = 91.2db sinad = 91.1db thd = ?107.0db sfdr = 106.0db internal reference 10942-108 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 amplitude (dbfs) frequency (khz) pgia gain = 0.8 f s = 500ksps f in = 1.12khz snr = 89.7db sinad = 89.6db thd = ?104.0db sfdr = 105.0db internal reference 10942-109 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 amplitude (dbfs) frequency (khz) pgia gain = 1.6 f s = 500ksps f in = 1.12khz snr = 87.3db sinad = 87.2db thd = ?103.0db sfdr = 106.0db internal reference 10942- 1 10 rev. 0 | page 13 of 32
adas3023 data sheet figure 19 . crosstalk vs. frequency figure 20 . cmrr vs. frequency figure 21 . vddh current vs. throughput figure 22 . vssh current vs. throughput figure 23 . avdd current vs. throughput figure 24 . dvdd current vs. throughput ?105 100 1k 10k 100k 1m ?80 ?85 ?90 ?95 ?100 crosstalk (db) frequency (hz) 10942-113 ch1, 2 active channels, 500ksps, pgia gain = 0.8 ch3, 4 active channels, 200ksps, pgia gain = 0.8 ch4, 6 active channels, 100ksps, pgia gain = 0.8 ch4, 8 active channels, 100ksps, pgia gain = 0.2 ch4, 8 active channels, 100ksps, pgia gain = 0.4 ch4, 8 active channels, 100ksps, pgia gain = 0.8 ch4, 8 active channels, 100ksps, pgia gain = 1.6 40 1 10 100 10k 1k 110 100 90 80 70 60 50 cmrr (db) frequency (hz) 10942-114 pgia gain = 0.2 pgia gain = 0.4 pgia gain = 0.8 pgia gain = 1.6 10 100 1000 vddh current (ma) throughput (ksps) 10942-115 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 vddh = 15v 2 active channels, pgia gain = 0.2 4 active channels, pgia gain = 0.2 6 active channels, pgia gain = 0.2 8 active channels, pgia gain = 0.2 2 active channels, pgia gain = 1.6 4 active channels, pgia gain = 1.6 6 active channels, pgia gain = 1.6 8 active channels, pgia gain = 1.6 10 100 1000 vssh current (ma) throughput (ksps) 10942-118 ?11.0 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 ?5.5 ?6.0 ?6.5 ?7.0 ?7.5 ?8.0 ?8.5 ?9.0 ?9.5 ?10.0 ?10.5 vssh = ?15v 2 active channels, pgia gain = 0.2 2 active channels, pgia gain = 1.6 4 active channels, pgia gain = 0.2 4 active channels, pgia gain = 1.6 6 active channels, pgia gain = 0.2 6 active channels, pgia gain = 1.6 8 active channels, pgia gain = 0.2 8 active channels, pgia gain = 1.6 10 100 1000 avdd current (ma) throughput (ksps) 10942-119 10 11 12 13 14 15 16 17 18 19 20 avdd = 5v internal reference external reference 10 100 1000 dvdd current (ma) throughput (ksps) 10942-120 0.5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 3.5 dvdd = 5v rev. 0 | page 14 of 32
data sheet adas3023 figure 25 . snr vs. temperature figure 26 . thd vs. temperature figure 27 . normalized offset error drift, pgia gain = 0.2 figure 28 . normalized offset error drift, pgia gain = 0.4 figure 29 . normalized offset error drift, pgia gain = 0.8 figure 30 . normalized offset error drift, pgia gain = 1.6 80 100 98 96 94 92 90 88 86 84 82 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 snr (db) temperature (c) 10942-111 ch1, pgia gain = 0.4, f s = 500ksps ch2, pgia gain = 0.8, f s = 250ksps ch5, pgia gain = 0.8, f s = 125ksps ch3, pgia gain = 1.6, f s = 167ksps ?120 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 thd (db) temperature (c) 10942-112 ch1, pgia gain = 0.4, f s = 500ksps ch2, pgia gain = 0.8, f s = 250ksps ch5, pgia gain = 0.8, f s = 125ksps ch3, pgia gain = 1.6, f s = 167ksps ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized offset error drift (lsb) temperature (c) 10942-121 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 pgia gain = 0.2 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized offset error drift (lsb) temperature (c) 10942-122 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 pgia gain = 0.4 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized offset error drift (lsb) temperature (c) 10942-123 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 pgia gain = 0.8 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized offset error drift (lsb) temperature (c) 10942-124 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 pgia gain = 1.6 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 rev. 0 | page 15 of 32
adas3023 data sheet figure 31 . normalized gain error drift error, pgia gain = 0.2 figure 32 . normalized gain error drift error , pgia gain = 0.4 figure 33 . normalized gain error drift error , pgia gain = 0.8 figure 34 . normalized gain error drift error , pgia gain = 1.6 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized gain error drift (lsb) temperature (c) 10942-125 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 pgia gain = 0.2 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized gain error drift (lsb) temperature (c) 10942-126 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 pgia gain = 0.4 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized gain error drift (lsb) temperature (c) 10942-127 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 pgia gain = 0.8 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 normalized gain error drift (lsb) temperature (c) 10942-128 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 pgia gain = 1.6 external reference f s = 125ksps t a = 25c ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 rev. 0 | page 16 of 32
data sheet adas3023 terminology operating input voltage range operating input voltage range is t he maximum input voltage range, including common - mode , which can be applied to the input channels , in 0 to in7 , and com. differential input voltage range differential input voltage range is t h e maximum differential full - scale input range. the value changes according to th e selected programmable gain setting. channel off leakage channel off leakage is t he leakage current with the channel turned off. channel on leakage channel on leakage is the leakage current with the channel turned on. common - mode rejection ratio (cmrr) cmrr is computed as the ratio of the signal magnitude of the converted result, referred to input , in the converted result to the amplitude of the common modulation signal applied to an input pair , expressed in decibels. cmrr is a measure of the abil ity of the adas3023 to reject signals, such as po wer line noise, that are common to the inputs. this specification is tested and specified for all input channel s , in 0 to in 7 , with respect to com. transient response transient response is a measure of the time required for the adas3023 to properly acquire the input after a full - scale step function is applied to the system . least significant bit (lsb) the lsb is the smallest increment that can be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is n ref v lsb 2 2 (v) = integral nonlinearity error (inl) inl refers to the deviation of each i ndividual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. th e deviation is measured from the middle of each code to the true straight line (see figure 37). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. dnl is often specified in terms of resolution for which no missing codes are guaranteed. offset error ideally, t he msb transition occur s at an input level that is ? lsb above analog ground. the offset error is the deviation of the actual transition from that point. gain error ideally, t he last transition (from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal ful l scale. the gain error is the deviation in lsb (or percentage of full - scale range) of the actual level of the last transition from the ideal level after the offset error is removed. closely related is the full - scale error (also in lsb or percentage of ful l - scale range), which includes the effects of the offset error. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and the point at which the input signal is held for a conv ersion. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with a ? 60 db fs input signal applied to the inputs. the value for dynamic range is expressed in decibels. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - (noise + distortion) ratio (sinad) sinad i s the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and th e peak spurious signal. rev. 0 | page 17 of 32
adas3023 data sheet channel -to - channel crosstalk channel - to - channel crosstalk is a measure of the level of crosstalk between any channel and all other channels . the crosstalk is measured by applying a dc input to the channel under te st and applying a full - scale, 1 0 khz sine wave signal to all other channels . the cro sstalk is the amount of signal that leaks into the test channel expressed in decibels. reference voltage temperature coefficient the r eference voltage temperature coefficient is derived from the typical shift of output voltage at 25c on a sample of device s at the maximum and minimum reference output voltage (v ref ) measured at t min , t a (25c), and t max expressed in ppm/c . 6 10 ) C ( ) ( ) ( C ) ( ) c ppm/ ( = min max ref ref ref ref t t c 25 v min v max v tcv here v ref ( max ) is the maximum v ref at t min , t a (25c), or t max . v ref ( min ) is the minimum v ref at t min , t a (25c), or t max . v ref (25 c ) = v ref at 25c. t max = +85c. t min = ? 40c. rev. 0 | page 18 of 32
data sheet adas3023 theory of operation overview the adas3023 is a 16 - bit, 8 - channel simultaneous system on a single chip that integrates the t ypical components used in a data acquisition system in one easy to use , programmable device . it is capable of converting two channels simultaneously up to 500,000 samples per second (500 k sps) throughput. the adas3023 features ? high impedance inputs ? high common - mode rejection ? an 8 - channel, low leakage track and hold ? a p rogrammable gain in strumentation amplifier (pgia) with four selectable differential input ranges from 2.56 v to 20.48 v ? a 16- bit pulsar ? adc with no missing codes ? an i nternal , precision, low drift 4.096 v reference and buffer the adas3023 uses the analog devices patented high voltage i cmos process allowing up to a 20.48 v differential input voltage range when using 15 v supplies , which makes the device suitable for industrial applications. the device is housed in a small 6 mm 6 mm, 40 - lead lfcsp package and can operate over the industrial temperature range of ? 40 c to +85 c . a typical discrete multichannel data acquisition system containing sim ilar circuitry require s more space on the circuit board than the adas3023 . therefore , advantages of the adas3023 solution include a reduced footprint and less complex design requirements , leading to faster time to market and lower cos ts . operation the analog circuitry of the adas3023 consists of a high impedance , low leakage , track - and - hold pgia with a high common - mode rejection that can accept the full - scale differ - ential voltages of 2.56 v, 5.12 v, 10.24 v , and 20.48 v (see figure 15 ) . t he adas3023 can be configured to sample two , four , six , or eight channels simultaneously. the adas3023 offers true high impedance inputs in a differential structure and rejects common - mode signals present on the inputs. this architecture does not require additional input buffers (op amps) th at are usually required for signal buffering, level shifting, amplification, attenuation , and kickback reduction when using switched capacitor - based sar adcs . digital control of the progra mmable gain setting of each channel input is set via the configuration (cfg) register . the conversion results are output in two s complement format on the serial data output (sdo) and through an optional secondary serial data output on the busy/ sdo2 pin . the digital interface uses a dedicated chip select ( cs ) to control data access to and from the adas3023 togeth er with a busy/sdo2 output, asyn - chronous reset (reset) , and power - down (pd) inputs. the internal reference of the adas3023 use s an internal temper - ature compensated 2.5 v output band gap reference , followed by a precision buffer amplifier to provide the 4.096 v high precision system reference. all of these components are configured through a serial (spi - compatible) , 16 - bit cfg register . configuration and conversion results are read after the conversions are completed . the adas3023 requires a minimum of three power supplies +15 v, ? 15 v , and +5 v. internal low drop out regul ators provide the necessary 2.5 v system voltages that must be decoupled externally via dedicated pins ( acap, dcap, and rcap ). the adas3023 can be interfaced to any 1.8 v to 5 v digital logic family using the dedicated vio logic level voltage supply (see table 9 ) . a rising edge on the cnv pin initiates a conversion and changes the adas3023 from track to hold. in this state, the adas3023 performs the analog signa l conditioning and conversion. when the signal conditioning is complete d , the adas3023 r eturns to the track state while , at the same time , quantiz es the sample . this two - tiered process satisfie s the necessary settling time requirement and achieves a fast throughput rate of up to 500 k sps with 16 - bit accuracy . figure 35 . simplified block diagram buf ref logic/ interface track and hold pgia pulsar adc diff to com in0 cnv cs sck din sdo refin busy in1 in2 in3 in4 in5 in6 in7 com vddh avdd dvdd vio reset refx dgnd agnd vssh pd adas3023 10942-007 rev. 0 | page 19 of 32
adas3023 data sheet figure 36 . system timing regardless of the type of signal, ( single - ended symmetric or a symmet r ic ), the adas3023 converts all signals present on the enabled input s and com pin in a differential fashion identical to an industry - standard difference or instrumentation amplifier. the conversion resul ts are available after the conversion is complete and can be read back at any time before t he end of the next con - versio n. avoid r eading back data during the quiet period, indicated by busy/sdo2 being active high. because the adas3023 has an on - board conversion clock, the serial clock (sck) is not required for the conversion process ; i t is only required to present results to the user. transfer functions the ideal transfer characteristic for the adas3023 is shown in figure 37 . the inputs are configured for differential input ranges and the data outputs are in twos complement format, as listed in table 6 . figure 37 . adc ideal transfer function table 6 . output codes and ideal input voltages description differential analog inputs, v ref = 4.096 v digital output code (twos complement hex) fsr ? 1 lsb (32,767 v ref )/(32,768 pgia gain) 0x7fff midscale + 1 lsb (v ref /(32,768 pgia gain)) 0x0001 midscale 0 0x0000 midscale ? 1 lsb ?(v ref /(32,768 pgia gain)) 0xffff ?fsr + 1 lsb ?(32,767 v ref )/(32,768 pgia gain) 0x8001 ?fsr ?v ref pgia gain 0x8000 cnv phase conversion acquisition t cyc t conv t acq 10942-008 100...000 100...001 100...010 011...101 011...110 011...111 twos complement straight binary 000...000 000...001 000...010 111...101 111...110 111...111 adc code analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 10942-009 rev. 0 | page 20 of 32
data sheet adas3023 figure 38 . complete 5 v, single - supply, 8 - channel data acquisition system with pgia typical application connection diagram as shown in figure 38 , the adp1613 is used in an inexpensive sepic - ?uk topology, which is an ideal candidate for providing the adas3023 with the necessary high voltage 15 v robust supplies (at 20 ma) and low output ripple (3 mv maximum) from an external 5 v supply. the adp1613 satisfies the specification requirements of the adas3023 using minimal external compo - nents yet achieves greater than 86% effic iency. see the cn - 0201 circuit note for complete information about this test setup. analog inputs input structure the adas3023 uses a differential input structure between each of the channel inputs, in 0 to in7 , and a common reference ( com ) , all of which sample simultaneously . figure 39 shows an equivalent circuit of the inputs. the diodes provide esd protection for the analog inputs ( in 0 to in7 ) and com from the high vo ltage supplies ( vddh and vssh ) . e nsure that the analog input signal does not exceed the supply rails by more than 0.3 v because this can cause the diodes to become forward - biased and to start conducting current. the voltages beyond the absolute maximum rat ings may cause permanent damage to the adas3023 (see table 4 ). figure 39 . equivalent analog input circuit programmable gain the adas3023 incorporates a programmable gain instru - mentation amplifier (pgia) with four selectable ranges. the pgia settings are specified in terms of the maximum absolute differential input voltage across an input pin and the com pin, for example inx to com. the power on and default condition s are preset to the 20.48 v ( pgia = 11) input range. note that because the adas3023 can use any input type, such as bipolar single - ended and pseudo bipolar, setting the pgia is important to make full use of the allowable input span. in0 in1 in2 in3 in4 in5 in6 in7 diff to com logic/ interface refin ref cnv reset sck din sdo vddh avdd dvdd vio cs com busy + + + enable adp1613 adas3023 comp fb freq en vin gnd ss sw + + v in = +5v + + + + vssh rf2 4.22k? rf1b 47.5k? r c 1 100k? c c 1 12nf c c 2 10pf c v 5 1f r en r b 0 1? r s 1 0? r s 2 dni c ss 1f z 1 c in 1f d1 d 2 c1 1f c2 1f l3 1f c out 3 4.7f c out 1 1f c out 2 2.2f +15v ?15v +5v adr434 refx pd agnd dgnd ad8031 4.096v + ? 1.78? r filt dni 50k? l1 47h l2 47h + +5v +5v buf 10942-200 pgia pulsar adc track and hold c pin inx or com vssh agnd vddh pgia 10942-010 track and hold rev. 0 | page 21 of 32
adas3023 data sheet table 7 d escribes each differential input range and the corre - sponding lsb size , pgia bit settings , and pg i a gain . table 7 . differential input ranges, lsb size, and pgia settings differential input ranges, inx ? com (v) lsb ( v) pgia cfg pgia gain (v/v) 20.48 625 11 0.2 10.24 312.5 00 0.4 5.12 156.3 01 0.8 2.56 78.13 10 1.6 common - mode operating range the differential input common - mode range changes according to the input range selected for a given channel and the high vol - tage power supplies. note that the operating input voltage of any input pin , as defined in the specifications section, requires a minimum of 2.5 v of headroom from the vddh/vssh supplies or ( vssh + 2.5 v) inx / com ( vddh C 2.5 v) th e following section s offer some examples of setting the pgia for various input signals. note that the adas3023 always takes the difference between the inx and com signals. single - ended signals with a n onzero dc offset (asymmetrical) when a 5.12 v p - p signal with a 2.56 v dc offset is connected to one of the input s (inx + ) and the dc ground sense of th e signal is connected to com, the pgia gain configuration is set to 01 for the 5.12 v range because the maximum differential voltage across the inputs is +5.12 v . this scenario uses only half the codes available for the transfer function. figure 40 . typical single - ended unipolar input using only half of the c odes single - ended signals with a 0 v dc offset (symmetrical) compared with the example in the single - ended signals with a nonzero dc offset (asymmetrical) section, a better s olution for single - ended signals , when possible, is to remove as much differential dc offset between inx and com such that the average voltage is 0 v (symmetr ical around the ground sense). the differential voltage across the inputs is never greater than 2.56 v , and the pgia gain configuration is set for a 2.56 v range (10 ). this scenario use s all of the codes available for the transfer function, making full use of the allowable differential input range. figure 41 . optimal single - ended configurat ion using all codes notice that the voltages in the examples are not integer values due to the 4.096 v reference and the scaling ratio s of the pgia . t he maximum allow ed dc offset voltage on the com input pin for various pgia g ains in this case is shown in table 8 . table 8 . dc offset voltage on com input and pgia settings 1 pgia gain (v/v) dc offs et voltage on com (v) 0.2 0 0.4 0 0.8 5.12 1.6 7.68 1 full - scale signal on inx . voltage reference in put/ out put the adas3023 allows the choice of an internal reference, an exter nal reference using an internal buffer , or an external reference . the internal reference of the adas3023 provides excellent performance and can be used in nearly any application . setting the reference selection mode uses the internal reference enable bit , ref en , and the refin pin as described in th e following section s ( internal reference , external reference and internal buffer , external reference , and reference decoupling ) . internal reference the precision internal reference is factory trimmed and is suitable for most applications. setting the refen bit in the cfg register to 1 (default) enables the internal reference and produces 4.096 v on the ref1 and ref2 pins ; this 4.096 v output serves as th e main system reference . the un buffered 2.5 v (typical) band gap reference voltage is output on the refin pin, which requires an external parallel combination of 10 f and 0.1 f capacitors to reduce the noise on the output. because the current output of refin is limited, it can be used as a source when followed by a suitable buffer, such as the ad8 031 . note that excessive loading of the refin output lower s the 4.096 v system reference because the internal amplifier uses a fixed gain. the internal reference output is trimmed to the targeted value of 4.096 v with an initial accuracy of 8 mv. the reference is also temperature compensate d to provide a t ypical drift of 5 ppm/c. when the internal reference is used , decouple the adas3023 , as shown in figure 42 . note that both the ref 1 and ref2 con - nections are shorted together and externally decoupled with adas3023 inx+ inx+ +5.12v 5.12v p-p com 0v com v off v off 10942-011 adas3023 inx+ inx+ +2.56v 5.12v p-p com ?2.56v com 0v 10942-012 rev. 0 | page 22 of 32
data sheet adas3023 suitable decoupling on the refin output and the rcap internally regulated supply. figure 42 . 4.096 v internal reference connection external reference and internal buffer the external reference and internal buffer are useful where a common system reference is used or when improved drift perfo rmance is required. setting bit ref en to 0 disables the internal band gap reference, allowing the user to provide an external voltage reference (2.5 v t yp ical) to the refin pin. the internal buffer remain s enabled, thus reducing the need for an external bu ffer amplifier to generate the main system refer ence. where refin = 2.5 v and ref1 and ref2 output 4.096 v , this serve s as the main system reference. for this configuration, connect the external source , as shown in figure 43 . any type of 2.5 v reference can be used in this config - uration ( low power, low drift, small package, and so forth ) because the internal buffer handles the dynamics of the adas3023 reference requirements. figure 43 . external reference using internal buffer external reference for applications that require a precise, low drift, 4.096 v reference , an external reference can be used. note that in this mode , disabling the inter nal buffer requires setting refen to 0, and driving or connecting refin to agnd; thus , both hardware and so ftware control are necessary. attempting to drive the ref1 and ref2 pins alone prior to disabling the internal buffer can cause source/sink contention in the ou tputs of the driving amplifiers. connect the precision 4.096 v reference directly to ref1 and ref2, which are the main system reference (see figure 44 ); two recommended references ar e the adr434 or adr444 . if an op amp is used as an external reference source, take note of the concerns regarding driving capacitive loads . capacitive loading for op amps usually refers to the ability of the amplifier to remain marginally stable in ac applications but can also play a role in dc applications, such as a reference source. keep in mind that the reference source see s the dynamics of the bit decision process on the reference pins and further analysis beyond the scope of this data sheet may be required. figure 44 . external reference reference decoupling with any of the reference topologies described in the voltage reference input/output section , th e ref1 and ref2 reference pins of the adas3023 have dynamic impedances and require sufficient decoupling , regardless of whether the pins are used as inputs or outputs. this decoupling usually consists of a low esr capacitor connected to each ref1 and ref2 pin and to the accom - panying refn return paths. c eramic chip capa citors ( x5r, 1206 size) are recommended for decoupling in all of the reference topologies described in the voltage reference input/output section. the placement of the reference decoupling capacitors plays an impo rtant role in system performance. using thick printed circuit board (pcb) traces, m ount t he decoupling capacitors on the same side as the adas3023 , close to the ref1 and ref2 pins. route the return paths to the refn inputs that , in turn , connect to the analog ground plane of the system . when it is necessary to connect to an internal pcb, m inimize the resistance of the return path to ground by using as many through vias as possible . using the shortest distance and several vias, connect t he refn and rgnd inputs to the analog ground plane of the system, preferably adjacent to the solder pads. one common mistake is to route these traces to an individual trace that connects to the ground of the system . this can introduce noise, which may adversely affect the lsb sensitivity. to prevent such noise, use pcbs with multi ple layers, including ground p lanes , rather than using single or double sided boards. smaller reference decoupling capacitor values (as low as 2.2 f) can be used with little impact , mainly on dnl and thd. further - more , there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) that is common in decoupling schemes for high frequency noise rejection. for applications that use multiple adas3023 device s or other pulsar adcs , using the internal reference buffer is mo st effective adas3023 refn ref2 10f 0.1f refn ref1 10f 0.1f refn refin 10f 0.1f band gap rcap 1f rgnd 10942-013 adas3023 refn ref2 10f 0.1f refn ref1 10f 0.1f refn refin 10f 0.1f band gap rcap 1f rgnd reference source = 2.5v 10942-014 adas3023 refn ref2 10f 0.1f refn ref1 10f 0.1f refin band gap rcap 1f rgnd reference source = 4.096v 10942-015 rev. 0 | page 23 of 32
adas3023 data sheet to buffer the external reference voltage and , th ereby , reduc e sar conversion crosstalk. the voltage reference temperature coefficient (tc) directly affects the full - scale accuracy of the system ; therefore, in applications where full - scale accuracy is crucial , care must be taken with the tc. for example , a 15 ppm/c tc of the reference changes the full - scale accuracy by 1 lsb/c . power supply the adas3023 use s five supplies: avdd, dvdd, vio, vddh , and vssh (see table 9 ) . note that the acap, dcap , and rcap pins are for informational purposes only because the y are the outputs of the internal supply regulators. table 9 . supplies mnemonic function required avdd analog 5 v core yes dvdd digital 5 v core yes , or can connect to avdd vio digital input/output yes , and can connect to dvdd (for the 5 v level) vddh positive h igh v oltage yes , +15 v typical vssh negative h igh v oltage yes , ?15 v typical acap analog 2.5 v core no, on chip dcap digital 2.5 v core no, on chip rcap analog 2.5 v core no, on chip core supplies the avdd and dvdd pins supply the adas3023 analog and digi ta l cores , respectively. sufficient decoupling of these supplies is required , consisting of at least a 10 f capacitor and 100 nf capaci - tor on each supply. place t he 100 nf capacitors as close as possible to the adas3023 . to reduce the number of supplies that are required , supply the dvdd f rom the analog supply by connecting a simple rc filter between avdd and dvdd , as shown in figure 45. figure 45 . supply connections vio is the variable digital input/output supply and allows direct interface with any l ogic between 1.8 v and 5 v (dvdd supply maximum). to reduce the supplies that are required , vio can , alternatively , be connected to dvdd when dvdd is supplied from the analog supply through an rc filter. the recommended low dropout regulators are adp3334 , adp1715 , adp7102 , and adp7104 for the avdd, dvdd, and vio supplies. no t e that the user must bring up the adas3023 power supplies in the following sequence: 1. vio 2. vddh 3. vssh 4. dvdd 5. av dd 6. ref x high voltage supplies the high voltage bipolar supplies, vddh and vssh , are required and must be at least 2.5 v larger than the maximum operating input voltage. specifically , any operating input voltage (as defined in table 2 ) of an input pin requires 2.5 v of headroom from the vddh/vssh supplies or ( vssh + 2.5 v) inx / com ( vddh ? 2.5 v) sufficient decoupling of these supplies is also required , consisting of at least a 10 f capacitor and 100 nf capacitor on each supply. power dissipation modes the adas3023 offers two power dissipation modes: fully operational mode and p ower - down mode. fully operational mode in f ully o perational mode, the adas3023 can perform the conversions normally . power - down mode to minimize the operating currents of the device when it is idle, place the device in full power - down mode by bringing the pd input high ; t h is places the adas3023 into a deep sleep mode in which cnv activity is ignored and the digital interface is inactive . refer to the reset and power - down (pd) inputs section for timing details. in deep sleep mode, the internal regulators (acap, rcap, and dcap) and the voltage reference are powered down. to reestablish operation, return pd to logic low . n ote that , before the device can operate at the specified performance, the reference voltage must charge up the external reservoir capacitor(s) and be allowed the specified settling time. r eset must be applied after r eturning pd to low to restore the adas3023 digital core, includ - ing the cfg register, to its default state. therefore, the desired cfg must be rewritten to the devi ce and one d ummy conversion must be completed before the device operation is restored to the config - uration programmed prior to pd assertion. note that when using the internal reference, sufficient time is required to settle it to the nominal value. for a typical connection , it requires 100 ms to settle to the nominal value (see figure 41) . + avdd agnd dvdd dgnd 10f + 10f 100nf 100nf 20? +5v digital supply +5v analog supply vio + 10f +1.8v to +5v digital i/o supply 100nf +15v ?15v + 10f 100nf + 10f 100nf vddh vssh adas3023 dgnd 10942-016 rev. 0 | page 24 of 32
data sheet adas3023 conversion modes the adas3023 offers two conversion modes to accommodate varying applications , and both modes are set with the conversion mode select bit, cms (bit 1) of the cfg register. warp mode ( cms = 0 ) setting cms to 0 is useful where the full 2 - channel throughput of 500 k sps is required. however, in this mode , the maximum time between conversions is restricted. if this maximum period is exceeded, the conversion result can be corrupted . therefore, t h e warp mode is best suited for continu ously sampled applications. normal mode ( cms = 1, default ) setting cms to 1 is useful for all applications where the full 500 k sps sample rate of the device is not required. in this m ode, there is no maximum time restriction between conversions . this mode is the default condition from the assertion of an asynchro - nous reset. the main difference between the normal mode and warp mode is that the busy/sdo2 time , t conv , is slightly longer in normal mode than in warp mode. rev. 0 | page 25 of 32
adas3023 data sheet digital interface the adas3023 digital interface consists of asynchronous inputs and a 4 - wire serial interface for conversion result readback and configuration register programming. this interface uses the three asynchronous signals ( c n v, r e s e t, and pd) and a 4 - wire serial interface comprised of cs , sdo, sck, and din. cs can also be tied to cnv for some applications . conversion results are presented to the serial data output pin (sdo) after the end of a conversion . the 16 - bit configuration word, cfg, is programmed on the serial data input pin, din during the first 16 scks of any data transfer . this c fg register controls the settings, such as selecting the number of channels to be converted, the programmable gain settings for each channel group , and the reference choice (see configuration register section for more information). conversion control the cnv input initiates conversion s for n enabled channels as defined in the cfg register. the adas3023 is fully asynchronous and can perform conversions at any frequency from dc up to 500 ksps , depending on the settings specified in the configuration register and the system serial clock rate . cnv rising start of conversion ( soc ) a rising edge on the cnv changes the state of the adas3023 from t rack mode to hold mode , as well as all that is necessar y to initiate a conversion . a ll conversion clocks are generated interna lly . after a conversion is initiated, the adas3023 ignores other activity on the cnv line (governed by the throughput rate ) until the end of the conversion . while the adas3023 is performing a conversion and the busy/ sdo2 output is driven high, the adas3023 uses a unique 2- phase conversion process , allowing for safe data access and quiet time. the cnv signal is decoupled from the cs pin, allowing multiple adas3023 devices to be controlled by the same processor. f or applica tions where snr is critical, the cnv source requires very low jitter , which is achieved by using a dedicated oscillator or by clocking cnv with a high frequency, low jitter clock. for appli - cations where jitter is more tolerable or a single device is in use, tie cnv to cs . for more information on sample clock jitter and aperture delay, see the mt - 007 mini tutorial , aperture time, aperture jitter, aperture delay time removing the confusion . although cnv is a digital signal, take care to ensure fast, clean edges with minimal overshoot, undershoot, and ringing. in addition, avoid digital activity close to the sampling instant because such activity can result in degraded snr performance. busy/sdo2 falling edge end of conversion ( eoc ) the eoc is indicated by busy/sdo2 returning low and can be used as a host interrupt. in addition, the eoc gates data access to and from the adas3023 . if the conversion result is not read prior to the next eoc event , the data is lost. furthermore , if the cfg update is not completed prior to the eoc, it is discarded and the current configuration is applied to future conversions . this pipeline ensures that the adas3023 has sufficient time to acquire the next sample to the specified 16 - bit accuracy. register pipeline the cfg register is written on the first 16 scks following the eoc event , and it is updated on the next eoc event. to ensure that all cfg updates are applied during a known safe instant to the var ious circuit elements, the asynchronous data transfer is synchroni z ed to the adas3023 timing engine using the eoc event. this synchronization introduces an inherent delay between updating the cfg register setting and the application of the configuration to a conversion. this pipeline , from the end of the current conversion (n) , consists of a one - deep delay be fore the cfg setting takes effect. this means that two soc and eoc events must elapse before the setting (that is, the new channel, gain, and so forth) takes effect. note that the nomenclature (n), (n + 1), and so forth is used in the remainder of the following digital section s ( serial data interface , general timing , an d configuration register ) for simplicity. note, however, that t here is no pipelin e after the end of a conversion before data can be read back. reset and power - down (pd) inputs the asynchronous reset and pd inputs can be used to reset and power down the adas3023 , respectively. timing details are shown in figure 46. f igure 46 . reset and pd timing a rising edge on reset or pd aborts the conversion p rocess and places sdo into high impedance, regardless of the cs level. note that reset has a minimum pulse width (active high) time for setting the adas3023 into the reset state. see the configuration register section for the default cfg setting when th e adas3023 returns from the reset state. if this default setting is used after reset is deasserted (logic 0), for the conversion result to be valid, a period equal to the acquisition time (t acq ) must elapse before cnv can be asserted ; otherwise, i f a conversion is initiated, the result is corrupted. in addition, the output data from the previous conversion is cleared upon a reset ; a ttempting 10942-017 cs sdo cnv n ? 1 undefined n see note see note n ? 2 x x x busy reset/ pd t dis t en t rh t acq t ccs cfg n + 1 x default notes 1. when the part is released from reset, t acq must be met for conversion n if using the default cfg setting for channel in0. when the part is released from power-down, t acq is not required, and the first two conversions, n and n + 1, are undefined. rev. 0 | page 26 of 32
data sheet adas3023 to access the data result prior to initiating a new conversion produces an invalid result. upon the device returning from power - down mode or from a reset when the default cfg is not used, there is no t acq requirement because the first two conver sions from power - up are undefined/ invalid because the one - deep delay pipeline requirement must be satisfied to reconfigure the device to the desired setting. serial data interfac e the adas3023 uses a simple 4 - wire interface and is compatible with f pg a s, dsps, and common serial interfaces such as a serial peripheral interface ( spi ) , qspi ? , and microwire ? . the interface uses the cs , sck, sdo , and din signals. timing signals for a serial interface are shown in figure 47. sdo is activated when cs is asserted. the conversion result is output on sdo and updated on the sck falling edges. simulta - neously, the 16 - bit cfg word is updated, if need ed, on the serial data input ( din ) . the state of busy/sdo2 (bit 0) determines the output format of the msb data when sdo is activated after the eoc. note that, in figure 47 , sck is shown as idling high. sck c an idle high or low , requiring the system developer to design an interface that suits setup and hold times for both sdo and din. figure 47 . serial timing din (mosi) sdo (miso) cs sck t dinh t dins t sdov t sdoh t sckl t sck t sckh t dis t en 10942-018 rev. 0 | page 27 of 32
adas3023 data sheet general timing figure 48 and figure 49 conversion timing diagrams sh ow the specific timing parameters , including the complete register to conversion and readback pipeline delay. th ese figures detail the timing from a power up or from returning from a full power down by use of the pd input. when the busy/sdo2 output is not enabled after the eoc, the data available on the sdo output (msb first) can be read after the16 sck rising edges in sequen - tial fashion (from c hannel 0 (ch0) to c hannel 7 (ch7) ) , as shown in figure 48. the converter busy signal is always output on the busy/sdo2 pin when cs is logic high. when the busy/sdo2 output is ena - bled when cs is brought low after the eoc, the sdo output s the data of channel 0 to channel 3 ( ch0, ch1, ch2 , and ch3 ) , and the sdo2 output s the data of channel 4 to channel 7 ( ch4, ch5, ch6 , and ch7 ) after 16 sck rising edges , as shown in figure 49 . the conversion result output on busy/sdo2 pin synchronizes to the sck falling edges. the conversion results are in twos comple - ment for mat. reading or writing data during the quiet convers ion phase (t conv ) may cause incorrect bit decisions. figure 48 . general timing diagram with busy/sdo2 disabled figure 49 . general timing diagram with busy/sdo2 e nabled 1 16 1 16 1 16 1 16 1 16 1 16 phase cnv sck din sdo busy/ sdo2 cs soc soc eoc note 2 note 1 note 4 note 3 note 2 note 1 eoc power up t conv t cyc t cnvh t ad conversion (n) conversion (n + 1) acquisition (n + 1) acquisition (n + 2) soc data (n) cfg (n + 2) cfg (n + 3) ch0 ch1 ch7 ch0 ch1 ch7 data (n + 1) 10942-019 t cbd notes 1. data access can only occur after conversion. both conversion result and the cfg register are updated at the end of the conversion (eoc). 2. a total of 16 sck falling edges are required for conversion result. an additional 16 edges after the last conversion result on busy reads back the cfg associated with conversion. 3. cs can be held low or connected to cnv. cs is shown with full independent control. 4. for optimal performance, data access should not occur during the sampling instant. a minimum time of at least the aperature delay, t ad , should lapse prior to data access. 1 16 phase cnv sck din sdo busy/ sdo2 cs soc soc eoc note 1 note 4 note 3 note 2 note 1 eoc power up t conv t cyc t cnvh t ad conversion (n) conversion (n + 1) acquisition (n + 1) acquisition (n + 2) soc data (n) cfg (n + 2) cfg (n + 3) data (n + 1) ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 ch0 ch4 ch1 ch5 ch2 ch6 ch3 ch7 1 16 1 16 1 16 1 16 1 16 1 16 1 16 10942-020 notes 1. data access can only occur after conversion. both conversion result and the cfg register are updated at the end of the conversion (eoc). 2. a total of 16 sck falling edges are required for conversion result. an additional 16 edges after the last conversion result on busy reads back the cfg associated with conversion. 3. cs can be held low or connected to cnv. cs is shown with full independent control. 4. for optimal performance, data access should not occur during the sampling instant. a minimum time of at least the aperature delay, t ad , should lapse prior to data access. rev. 0 | page 28 of 32
data sheet adas3023 configuration regist er the configuration register, cfg, is a 16 - bit programmable register for selecting all of the user - programmable options of the adas3023 (see table 11) . the register is loaded when data is read back for the first 16 sck rising edges , and it is updated at the next eoc. note that there is always a one - deep delay when writing to cfg , and when reading back from cfg , it is the setting associated with the current conversion. the default cfg setting is applied when the adas3023 returns from the reset state (reset = high) to the operational state (reset = low) . returning from the full power - down st ate (pd = high) to an enabled state (pd = low) , the default cfg setting is not applied and at least one dummy conversion is required for the user specified cfg to take effect. to ensure the digital core is in the default state, apply an external reset aft er the deassertion of pd. the default value is cfg[15:0] = 0xffff. to read back the contents of the configuration register, cfg, an additional 16 scks are provided after all of the channel data have been read, and cfg is made available on the sdo output. t he default cfg settings configure the adas3023 as follows: ? overwrites contents of the cfg register. ? selects the eight input channels mode. ? configures the pgia gain to 0.20 ( 20.48 v). ? enables the internal reference. ? selects normal conversion mode. ? disables the sdo2 read out mode. table 10. configuration register, cf g bit map ; default value = 0xffff (1111 1111 1111 1111) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg inx inx rsv pgia pgia pgia pgia pgia pgia pgia pgia rsv refen cms busy/sdo2 table 11 . configuration register description bit no. bit name description 15 cfg configuration update. 0 = keep s current configuration settings. 1 = overwrite s contents of register. [14:13] inx selection of the n umber of channels to be converted simultaneously . bit 14 bit 13 channels 0 0 2 0 1 4 1 0 6 1 1 8 12 rsv reserved. setting or clearing this bit has no effect. 11:4 pgia programmable gain selection (see the programmable gain section ). bit (odd) bit ( even ) pgia gain 0 0 10.24 v 0 1 5.12 v 1 0 2.56 v 1 1 20.48 v (d efault ) 11:10 pgia sets the gain of in0. 9:8 pgia sets the gain of in1. 7:6 pgia sets the gain of in3 to in2. 5:4 pgia sets the gain of in 4 to in7 . 3 rsv reserved. setting or clearing this bit has no effect. 2 ref en internal r eference (s ee the pin configuration and function descriptions and voltage reference input/output sections ) . 0 = disables the internal reference. disable the internal reference buffer by pulling refin to ground. 1 = enables the internal reference (d efault ) . 1 cms conversion m ode s elect ion (s ee the conversion modes section ) . 0 = uses the warp mode for conversions with a time between conversion restriction. 1 = uses the normal mode for conversions (d efault ) . 0 busy/sdo2 s econdary data output control using the busy/sdo2 pin . 0 = enables the device busy status when the cs pin is held high. on the cs falling edge , the msb of channel 1 is presented on the busy/sdo2 in put and subsequent data is presented on the sck falling edges. 1 = enables the device busy status only (default) . all data is transmitted via the sdo pin on the sck falling edge. rev. 0 | page 29 of 32
adas3023 data sheet packaging and ordering information outline dimensions figure 50 . 40 - lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp - 40 - 15 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad as3023bcpz ?40c to +85c 40 - lead lead frame chip scale package [ lfcsp_vq ] cp -40 -15 ADAS3023BCPZ -rl7 ?40c to +85c 40 - lead lead frame chip scale package [ lfcsp_vq ] cp -40 -15 eval - adas3023edz ?40c to +85c evaluation board 1 z = rohs compliant part. 07-19-2012-b 0.50 bsc bot t om view top view pin 1 indic at or exposed pa d pin 1 indic at or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 1.00 0.95 0.85 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min * 4.70 4.60 sq 4.50 * compliant to jedec standards mo-220- vjjd-5 with exception to exposed pad dimension. 40 1 11 10 20 21 30 31 rev. 0 | page 30 of 32
data sheet adas3023 notes rev. 0 | page 31 of 32
adas3023 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10942 -0- 5/13(0) rev. 0 | page 32 of 32

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