clock generator for powerquicc iii ? motorola, inc. 2004 motorola semiconductor technical data order number: XC9850 rev 0, 07/2004 clock generator for powerquicc iii the XC9850 is a pll based clock gen erator specifically designed for motorola microprocessor and microcontroller applications including the powerquicc iii. this device generates a microprocessor input clock plus the 500 mhz rapid i/o clock. th e microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. the rapid i/o outputs are lvds compatible. the device offers eight low skew clock outputs organized into two output banks, each configurable to support different clo ck frequencies. the extended temperature range of the XC9850 supports telecommunication and networking requirements. features ? 8 lvcmos outputs for processor and other circuitry ? 2 differential lvds outputs for rapid i/o interface ? crystal oscillator or external reference input ? 25 or 33 mhz input reference frequency ? selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33 or 16 mhz ? buffered reference clock output ? rapid i/o (lvds) output = 500, 250 or 125 mhz ? low cycle-to-cycle and period jitter ? 100-lead pbga package ? 100-lead pb-free package available ? 3.3v supply with 3.3v or 2.5v output lvcmos drive ? supports computing, networking, telecommunications applications ? ambient temperature range ?40c to +85c functional description the XC9850 uses either a 25 or 33 mhz reference frequency to generate 8 lvcmos output clocks, of which, the frequency is selectable from 16 mhz to 200 mhz. the reference is applied to the input of a pll and multiplied to 2 ghz. output dividers, div ide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output freq uencies of 200, 166, 133, 125, 111, 100, 83 66 50 33 or 16 mhz. the single-ended lvcmos outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. the 2 ghz pll output frequency is also divide d to produce a 125, 250 or 500 mhz clock output for rapid i/o appl ications such as found on the powerquicc iii communications processor. the input reference, either crystal or external input is also buffered to a separate output that my be used as the c lock source for a gigabit ethernet phy if desired. the reference clock may be provided by either an external clock i nput of 25 mhz or 33 mhz. an internal oscillator requiring a 2 5 mhz crystal for frequency control may also be used. the external clock source my be applied to either of two clock inputs and s elected via the clk_sel control input. both single ended lvcmos and diff erential lvpecl inputs are available. the crystal oscillator or external clock input is selected via the input pin of ref_sel . other than the crystal, no external components are required for crystal oscillator operation. the re f_33mhz configuration pins is used to se lect between a 33 and 25 mhz input frequency. the XC9850 is packaged in a 100 lead mapbga package to optimize both performance and board density. microprocessor clock generator scale 2:1 vf suffix vm suffix (pb-free) 100 mapbga package case 1462-01 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 1 data sheet XC9850
idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 2 XC9850 clock generator for powerquicc iii netcom XC9850 timing solutions 2 motorola figure 1. XC9850 logic diagram table 1. pin configurations pin i/o type function supply active/state clk input lvcmos pll reference clock input (pull-down) v dd pclk, pclk input lvpecl pll reference clock input (pclk - pull-down, pclk - pull-up and pull-down) v dd qa0, qa1, qa2, qa3 output lvcmos bank a outputs v ddoa qb0, qb1, qb2, qb3 output lvcmos bank b outputs v ddob qc0, qc1, qc0, qc1 output lvds bank c outputs v ddoc ref_out output lvcmos reference output (25 mhz or 33 mhz) v dd xtal_in input lvcmos crystal oscillator input pin v dd xtal_out output lvcmos crystal oscillator output pin v dd ref_clk_sel input lvcmos select between clk and pclk input (pull-down) v dd high ref_sel input lvcmos select between external input and crystal oscillator input (pull-down) v dd high ref_33mhz input lvcmos selects 33 mhz input (pull-down) v dd high mr input lvcmos master reset (pull-up) v dd low pll_bypass input lvcmos select pll or static test mode (pull-down) v dd high clk_a[0:5] 1 1. powerpc bit ordering (bit 0 = msb, bit 5 = lsb) input lvcmos configures bank a cl ock output frequency (pull-up) v dd high clk_b[0:5] 2 2. powerpc bit ordering (bit 0 = msb, bit 5 = lsb) powerpc bit ordering (bit 0 = msb, bit 1 = lsb) input lvcmos configures bank b cl ock output frequency (pull-up) v dd high rio_c [0:1] input lvcmos configures bank c clock output frequency (pull-down) v dd v dd 3.3 v supply v dda analog supply v ddoa supply for output bank a v ddob supply for output bank b gnd ground y n y 4, 8, 16, 40 qc0 pclk pclk clk ref_clk_sel xtal_in xtal_out ref_sel pll_bypass ref_33mhz clk_a[0:5] clk_b[0:5] rio_c[0:1] mr qc1 ref_out qc1 qc0 qb3 qb2 qb1 qb0 qa3 qa2 qa1 qa0 y n pll 2000 mhz ref osc 0 1 0 1 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 3 XC9850 clock generator for powerquicc iii netcom XC9850 motorola 3 timing solutions table 2. function table control default 0 1 ref_clk_sel 0 clk pclk ref_sel 0 clk or pclk xtal pll_bypass 0 normal bypass ref_33mhz 0 selects 25 mhz reference selects 33 mhz reference mr 1 reset normal clk_a, clk_b, and rio_c control output frequencies. see table 3 and table 4 for specific device configuration table 3. output configurations (banks a & b) clk_x[0:5] 1 1. powerpc bit ordering (bit 0 = msb, bit 5 = lsb) clk_x[0] (msb) clk_x[1] clk_x[2] clk_x[3] clk_x[4] clk_x[5] (lsb) n frequency (mhz) 111111 1 1 1 1 1 1 126 15.87 111100 1 1 1 1 0 0 120 16.67 101000 1 0 1 0 0 0 80 25.00 011110 0 1 1 1 1 0 60 33.33 010100 0 1 0 1 0 0 40 50.00 001111 0 0 1 1 1 1 30 66.67 001100 0 0 1 1 0 0 24 83.33 001010 0 0 1 0 1 0 20 100.00 001001 0 0 1 0 0 1 18 111.11 001000 0 0 1 0 0 0 16 125.00 000111 0 0 0 1 1 1 15 133.33 000110 0 0 0 1 1 0 12 166.67 000101 0 0 0 1 0 1 10 200.00 000100 0 0 0 1 0 0 8 2 2. minimum value for n 250 table 4. output configurations (bank c) rio_c[0:1] frequency (mhz) 00 50 (test output) 01 125 10 250 11 500 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 4 XC9850 clock generator for powerquicc iii netcom XC9850 timing solutions 4 motorola operation information output frequency configuration the XC9850 was designed to provide the commonly used frequencies in powerq uicc, powerpc and other microprocessor systems. table 3 lists the configuration values that will generate those common frequencies. the XC9850 can generate numerous other frequencie s that may be useful in specific applications. the output frequency (f out ) of either bank a or bank b may be calculated by the following equation. f out = 2000 / n where f out is in mhz and n = 2 * clk_x[0:5] this calculation is valid for all values of n from 8 to 126. note that n = 15 is a modified case of the configuration inputs clk_x[0:5]. to achieve n = 15 clk_x[0:5] is configured to 00111 or 7. crystal input operation tbd power-up and mr operation figure 2 defines the release time and the minimum pulse length for mr pin. the mr release time is based upon the power supply being stable and within v dd specifications. see table 11 for actual parameter values. the XC9850 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. figure 2. mr operation power supply bypassing the XC9850 is a mixed analog/digital product. the architecture of the XC9850 sup ports low noise signal operation at high frequencies. in order to maintain its superior signal quality, all v dd pins should be bypassed by high-frequency ceramic capacitors connecte d to gnd. if the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. figure 3. v cc power supply bypass mr v dd t reset_rel t reset_pulse v dd XC9850 0.1 p f 22 p f 0.1 p f 15 : v dd v dda f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
XC9850 motorola 5 timing solutions table 5. absolute maximum ratings 1 1. absolute maximum continuous ratings ar e those maximum values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adv ersely affect device reliabi lity. functional operation at absolute-maximum-rated co nditions is not implied. symbol characteristics min max unit condition v dd supply voltage (core) ?0.3 3.8 v v dda supply voltage (analog supply voltage) ?0.3 v dd v v ddox supply voltage (lvcmos output for bank a or b) ?0.3 v dd v v in dc input voltage ?0.3 v dd +0.3 v v out dc output voltage 2 2. v ddx references power supply pin asso ciated with specific output pin. ?0.3 v ddx +0.3 v i in dc input current r 20 ma i out dc output current r 50 ma t s storage temperature ?65 125 q c table 6. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v dd y 2 v mm esd protection (machine model) 125 v hbm esd protection (human body model) 2000 v cdm esd protection (charged device model) 500 v lu latch-up immunity 100 ma c in input capacitance 4 pf inputs c pd power dissipation capacitance 10 pf per output t ja thermal resistance (junction-to-ambient) 54.5 q c/w air flow = 0 t a ambient temperature ?40 85 q c table 7. dc characteristics (t a = ?40c to 85c) symbol characteristics min typ max unit condition supply current for v dd = 3.3 v r 5%, v ddoa = 3.3 v r 5 and v ddob = 3.3 v r 5% i dd + i dda maximum quiescent supply current (core) 200 ma v dd + v dda pins i dda maximum quiescent supply cu rrent (analog supply) 15 ma v ddin pins i ddoa , i ddob maximum bank a and b supply current 175 ma v ddoa and v ddob pins supply current for v dd = 3.3 v r 5%, v ddoa = 2.5 v r 5% and v ddob = 2.5 v r 5% i dd + i dda maximum quiescent supply current (core) 200 ma v dd + v dda pins i dda maximum quiescent supply cu rrent (analog supply) 15 ma v ddin pins i ddoa , i ddob maximum bank a and b supply current 100 ma v ddoa and v ddob pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 5 XC9850 clock generator for powerquicc iii netcom
idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 6 XC9850 clock generator for powerquicc iii netcom XC9850 timing solutions 6 motorola table 8. lvds dc characteristics (t a = ?40c to 85c) symbol characteristics min typ max unit condition differential lvds clock outputs (qc0, qc0 and qc1, qc1 ) for v dd = 3.3 v r 5% v pp output differential voltage 1 (peak-to-peak) (lvds) 1. v pp is the minimum differential input voltage swing requ ired to maintain ac characteristics including t pd and device-to-device skew. 100 400 mv v os output offset voltage (lvds) 1050 1600 mv table 9. lvpecl dc characteristics (t a = ?40c to 85c) 1 1. ac characteristics are design targets and pending characterization. symbol characteristics min typ max unit condition differential lvpecl clock inputs (clk1, clk1 ) for v dd = 3.3 v r 0.5% v pp differential voltage 2 (peak-to-peak) (lvpecl) 2. v pp is the minimum differential input voltage swing requ ired to maintain ac characteristics including t pd and device-to-device skew. 250 mv v cmr differential input crosspoint voltage 3 (lvpecl) 3. v cmr (ac) is the crosspoint of the differential input signal. norm al ac operation is obtained when t he crosspoint is within the v cmr (ac) range and the input swing lies within the v pp (ac) specification. violation of v cmr (ac) or v pp (ac) impacts the device propagation delay, device and part-to-part skew. 1.0 v dd ? 0.6 v table 10. lvcmos i/o dc characteristics (t a = ?40c to 85c) symbol characteristics min typ max unit condition lvcmos for v dd = 3.3 v r 5% v ih input high voltage 2.0 v dd + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos i in input current 1 1. inputs have pull-down resistors affecting the input current. 200 p av in = v ddl or gnd lvcmos for v dd = 3.3 v r 5%, v ddoa = 3.3 v r 5 and v ddob = 3.3 v r 5% v oh output high voltage 2.4 v i oh = ?24 ma v ol output low voltage 0.5 v i ol = 24 ma z out output impedance 14 ? 17 : lvcmos for v dd = 3.3 v r 5%, v ddoa = 2.5 v r 5% and v ddob = 2.5 v r 5% v oh output high voltage 1.9 v i oh = ?15 ma v ol output low voltage 0.4 v i ol = 15 ma z out output impedance 18 ? 22 : f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
XC9850 clock generator for powerquicc iii netcom XC9850 motorola 7 timing solutions figure 4. XC9850 ac test reference (lvds outputs) figure 5. XC9850 ac test reference (lvcmos outputs) table 11. ac characteristics (v dd = 3.3 v 5%, v ddoa = 3.3 v 5%,v ddob = 3.3 v 5%, t a = ?40c to +85c) 1 2 1. ac characteristics are design targets and pending characterization. 2. ac characteristics apply for parallel output termination of 50 : to v tt . symbol characteristics min typ max unit condition input and output timing specification f ref input reference frequency (25 mhz input) input reference frequency (33 mhz input) xtal input input reference frequency in pll bypass mode 3 3. in bypass mode, the XC9850 divides the input reference clock. 25 33 25 250 mhz mhz mhz mhz pll bypass f vco vco frequency range 4 4. the input reference frequency must match the vco lo ck range divided by the total feedback divider ratio: f ref = (f vco y m) ? n. 2000 mhz f mcx output frequency bank a output bank b output bank c output 15.87 15.87 50 200 200 500 mhz mhz mhz pll locked f refpw reference input pulse width 2 ns f refccc input frequency accuracy 100 ppm t r , t f output rise/fall time 150 500 ns 20% to 80% dc output duty cycle 43 47 50 50 57 53 % bank a and b bank c pll specifications t lock maximum pll lock time 10 ms t reset_ref mr hold time on power up 10 ns t reset_pulse mr hold time 10 ns skew and jitter specifications t sk(o) output-to-output skew (within a bank) 50 ps t sk(o) output-to-output skew (across banks a and b) 400 ps v ddoa = 3.3 v v ddob = 3.3 v t jit(cc) cycle-to-cycle jitter 200 150 ps ps bank a and b bank c t jit(per) period jitter 200 ps bank a and c t jit( ? ) i/o phase jitter rms (1 v ) 50 ps bank a and c pulse generator z = 50 : r t = 50 : z o = 50 : dut XC9850 v tt r t = 100 : z o = 50 : pulse generator z = 50 : r t = 50 : z o = 50 : dut XC9850 v tt z o = 50 : r t = 50 : v tt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 7
idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 8 XC9850 clock generator for powerquicc iii netcom XC9850 timing solutions 8 motorola table 12. XC9850 pin diagram (top view) 1 2 3 4 5 6 7 8 9 10 a v ddob v ddob clka[1] clka[3] clka[5] v dd qa1 qa2 v ddob v ddob b v ddob v ddob clka[0] clka[2] clka[4] qa0 v dd qa3 v ddob v ddob c rsvd rsvd v dd v dd v dd v dd v dd v dd v dd ref_out d v dda v dda v dd gnd gnd gnd gnd v dd qc0 qc0 e ref_sel clk v dd gnd gnd gnd gnd v dd v dd gnd f pclk pclk v dd gnd gnd gnd gnd v dd qc1 qc1 g ref_clk_sel ref_33mhz v dd gnd gnd gnd gnd v dd pll_bypass mr h xtal_in xtal_out v dd v dd v dd v dd v dd v dd rio_c[1] rio_c[0] j v ddob v ddob clkb[0] clkb[2] clkb[4] qb0 v ddob qb3 v ddob v ddob k v ddob v ddob clkb[1] clkb[3] clkb[5] v ddob qb1 qb2 v ddob v ddob table 13. XC9850 pin list signal 100 pin mapbga signal 100 pin mapbga signal 100 pin mapbga signal 100 pin mapbga signal 100 pin mapbga v ddob a1 rsvd c1 ref_sel e1 ref_clk_sel g1 v ddob j1 v ddob a2 rsvd c2 clk e2 ref_33mhz g2 v ddob j2 clka[1] a3 v dd c3 v dd e3 v dd g3 clkb[0] j3 clka[3] a4 v dd c4 gnd e4 gnd g4 clkb[2] j4 clka[5] a5 v dd c5 gnd e5 gnd g5 clkb[4] j5 v dd a6 v dd c6 gnd e6 gnd g6 qb0 j6 qa1 a7 v dd c7 gnd e7 gnd g7 v ddob j7 qa2 a8 v dd c8 v dd e8 v dd g8 qb3 j8 v ddob a9 v dd c9 v dd e9 pll_bypass g9 v ddob j9 v ddob a10 ref_out c10 gnd e10 mr g10 v ddob j10 v ddob b1 v dda d1 pclk f1 xtal_in h1 v ddob k1 v ddob b2 v dda d2 pclk f2 xtal_out h2 v ddob k2 clka[0] b3 v dd d3 v dd f3 v dd h3 clkb[1] k3 clka[2] b4 gnd d4 gnd f4 v dd h4 clkb[3] k4 clka[4] b5 gnd d5 gnd f5 v dd h5 clkb[5] k5 qa0 b6 gnd d6 gnd f6 v dd h6 v dd k6 v ddoa b7 gnd d7 gnd f7 v dd h7 qb1 k7 qa3 b8 v dd d8 v dd f8 v dd h8 qb2 k8 v ddob b9 qc0 d9 qc1 f9 rio_c[1] h9 v ddob k9 v ddob b10 qc0 d10 qc1 f10 rio_c[0] h10 v ddob k10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
idt? clock generator for powerquicc iii freescale timing solutions organization has been acquired by integrated device technology, inc XC9850 9 XC9850 clock generator for powerquicc iii netcom XC9850 timing solutions 9 motorola outline dimensions outline dimensions case 1462-01 issue o date 11/26/02 a1 index area b c 0.2 11 top view 11 4x a1 index area 9x 10 9 8 7 4 3 2 1 a b c d e f g h j k 3 bottom view b m 0.25 c a m 0.10 a 100x 0.55 0.45 6 5 1 0.5 0.5 9x 1 k side view a 0.35 a 0.12 a 100x 0.43 4 (1.18) 1.7 max rotated 90? clockwise detail k seating plane 0.29 5 notes: 1. 2. 3. 4. 5. all dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. maximum solder ball diameter measured parallel to datum a. datum a, seating plane, is defined by the spherical crowns of the solder balls. parallelism measurement shall exclude any effect of mark on top surface of packaging. vf suffix 100 map pbga package case 1462-01 issue o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom XC9850 clock generator for powerquicc iii netcom
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