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not recommended for new design this is information on a product still in production but not recommended for new designs. june 2011 doc id 5135 rev 6 1/20 1 m48z2m1y m48z2m1v 5 v or 3.3 v, 16 mbit (2 mb x 8) zeropower ? sram features integrated, ultra low power sram, power-fail control circuit, and batteries conventional sram operation; unlimited write cycles 10 years of data retention in the absence of power automatic power-fail chip deselect and write protection write protect voltages (v pfd = power-fail deselect voltage): ?m48z2m1y: v cc = 4.5 to 5.5 v; 4.2 v v pfd 4.5 v ?m48z2m1v: v cc = 3.0 to 3.6 v; 2.8 v v pfd 3.0 v batteries are internally isolated until power is applied pin and function compatible with jedec standard 2 mb x 8 srams rohs compliant ? lead-free second level interconnect 3 6 1 pldip36 module www.st.com
contents m48z2m1y, m48z2m1v 2/20 doc id 5135 rev 6 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m48z2m1y, m48z2m1v list of tables doc id 5135 rev 6 3/20 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. pldip36 ? 36-pin plastic dip long module, package mechanical data . . . . . . . . . . . . . . . 16 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
list of figures m48z2m1y, m48z2m1v 4/20 doc id 5135 rev 6 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. chip enable or output enable controlled, read mode ac waveforms. . . . . . . . . . . . . . . . . 8 figure 6. write enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. chip enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. pldip36 ? 36-pin plastic dip long module, package outline . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
m48z2m1y, m48z2m1v description doc id 5135 rev 6 5/20 1 description the m48z2m1y/v zeropower ? ram is a non-volatile 16 ,777,216-bit, static ram organized as 2,097,152 words by 8 bits. the device combines two internal lithium batteries, cmos srams and a control circuit in a plastic 36-pin dip, long module. the zeropower ram replaces industry standard srams. it provides the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. figure 1. logic diagram table 1. signal names a0-a20 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally ai02048 21 a0-a20 w dq0-dq7 v cc m48z2m1y m48z2m1v g v ss 8 e
description m48z2m1y, m48z2m1v 6/20 doc id 5135 rev 6 figure 2. dip connections figure 3. block diagram v ss v cc ai02049 m48z2m1y m48z2m1v 10 1 2 5 6 7 8 9 11 12 13 16 17 18 30 29 26 25 24 23 22 21 20 19 3 4 28 27 32 31 14 15 34 33 36 35 a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 a16 a18 a12 a14 w a17 a20 nc nc a19 ai02050 internal batterie s e v cc v ss voltage s en s e and s witching circuitry 204 8 k x 8 s ram array a0-a20 dq0-dq7 w g power e
m48z2m1y, m48z2m1v operation modes doc id 5135 rev 6 7/20 2 operation modes the m48z2m1y/v has its own power-fail detect circuit. the control circuitry constantly monitors the single 5 v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operations brought on by low v cc . as v cc falls below approximately 3 v, the control circuitry connects the batteries which sustain data until valid power returns. table 2. operating modes note: x = v ih or v il ; v so = battery backup switchover voltage. 2.1 read mode the m48z2m1y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 16,777,216 locations in the static storage array. thus, the unique address specified by the 21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e (chip enable) and g (output enable) access times are also satisfied. if the e and g access times are not met, valid data will be available after the later of chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e and g remain low, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 4. address controlled, read mode ac waveforms note: chip enable (e ) and output enable (g ) = low, write enable (w ) = high. mode v cc e g w dq0- dq7 power deselect 3.0 to 3.6 v or 4.5 to 5.5 v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) 1. see table 10 on page 15 for details. x x x high z cmos standby deselect v so (1) x x x high z battery backup mode ai02051 taxqx data valid a0-a20 dq0-dq7 tavav tavqv
operation modes m48z2m1y, m48z2m1v 8/20 doc id 5135 rev 6 figure 5. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high. table 3. read mode ac characteristics ai02052 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a20 e g dq0-dq7 valid symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5 v or 3.0 to 3.6 v (except where noted). m48z2m1y m48z2m1v unit ?70 ?85 min max min max t avav read cycle time 70 85 ns t avqv (2) 2. c l = 100 pf or 50 pf (see figure 9 on page 13 ). address valid to output valid 70 85 ns t axqx (2) address transition to output transition 5 5 ns t ehqz (3) 3. c l = 5 pf (see figure 9 on page 13 ). chip enable high to output hi-z 30 35 ns t elqv (2) chip enable low to output valid 70 85 ns t elqx (3) chip enable low to output transition 5 5 ns t ghqz (3) output enable high to output hi-z 25 35 ns t glqv (2) output enable low to output valid 35 45 ns t glqx (3) output enable low to output transition 5 5 ns
m48z2m1y, m48z2m1v operation modes doc id 5135 rev 6 9/20 2.2 write mode the m48z2m1y/v is in the write mode whenever w and e are active. the start of a write is referenced from the latter occu rring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for minimum of t ehax from e or t whax from w prior to the initiation of another read or write cycle. data-in must be valid t dveh or t dvwh prior to the end of write and remain valid for t ehdx or t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. figure 6. write enable controlled, write mode ac waveforms note: output enable (g ) = high. figure 7. chip enable controlled, write mode ac waveforms note: output enable (g ) = high. ai0205 3 tavav twhax tdvwh data input a0-a20 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai02054 tavav tehax tdveh a0-a20 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
operation modes m48z2m1y, m48z2m1v 10/20 doc id 5135 rev 6 table 4. write mode ac characteristics 2.3 data retention mode with valid v cc applied, the m48z2m1y/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ra m will automatically power-fail deselect, write protecting itself t wp after v cc falls below v pfd . all outputs become high impedance, and all inputs are treated as ?don't care.? if power fail detection occurs during a valid access, the memory cycle continues to completion. if the memory cycle fails to terminate within the time t wp , write protection takes place. when v cc drops below v so , the control circuit switches power to the internal energy source which preserves data. the internal coin cells will main tain data in the m48z2m1y/v af ter the initial application of v cc for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the batteries are disconnected, and the power supply is switched to external v cc . write protection continues for t er after v cc reaches v pfd to allow for processor stabilization. after t er , normal ram operation can resume. for more information on battery storage life refer to the application note an1012. symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5 v or 3.0 to 3.6v (except where noted). m48z2m1y m48z2m1v unit ?70 ?85 min max min max t avav write cycle time 70 85 ns t aveh address valid to chip enable high 65 75 ns t avel address valid to chip enable low 0 0 ns t avwh address valid to write enable high 65 75 ns t avwl address valid to write enable low 0 0 ns t dveh input valid to chip enable high 30 35 ns t dvwh input valid to write enable high 30 35 ns t ehax chip enable high to address transition 15 15 ns t ehdx chip enable high to input transition 10 15 ns t eleh chip enable low to chip enable high 55 75 ns t whax write enable high to address transition 5 5 ns t whdx write enable high to input transition 0 0 ns t whqx (2)(3) 2. c l = 5 pf (see figure 9 on page 13 ). 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. write enable high to output transition 5 5 ns t wlqz (2)(3) write enable low to output hi-z 25 30 ns t wlwh write enable pulse width 55 65 ns
m48z2m1y, m48z2m1v operation modes doc id 5135 rev 6 11/20 2.4 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low goin g spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1 f (as shown in figure 8 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to connect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 8. supply voltage protection ai02169 v cc 0.1 f device v cc v ss
maximum ratings m48z2m1y, m48z2m1v 12/20 doc id 5135 rev 6 3 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off) ?40 to 85 c t bias temperature under bias ?40 to 85 c t sld (1) 1. soldering temperature of the ic leads is to not exceed 260 c for 10 seconds. furthermore, the devices shall not be exposed to ir reflow nor preheat cycles (as performed as part of wave soldering). st recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. lead solder temperature for 10 seconds 260 c v io input or output voltages m48z2m1y ?0.3 to 7 v m48z2m1v ?0.3 to 4.6 v v cc supply voltage m48z2m1y ?0.3 to 7 v m48z2m1v ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
m48z2m1y, m48z2m1v dc and ac parameters doc id 5135 rev 6 13/20 4 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 6. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 9. ac testing load circuit parameter m48z2m1y m48z2m1v unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai07816 5v out c l = 100pf or 5pf (y) 50pf or 5pf (v) c l includes jig capacitance 1.9k device under test 1k
dc and ac parameters m48z2m1y, m48z2m1v 14/20 doc id 5135 rev 6 table 7. capacitance table 8. dc characteristics symbol parameter (1)(2) 1. effective capacitance measur ed with power supply at 5 v; sampled only, not 100% tested. 2. outputs deselected. min max unit c in input capacitance - 40 pf c io (3) 3. at 25 c. input / output capacitance - 40 pf sym parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5 v or 3.0 to 3.6 v (except where noted). m48z2m1y m48z2m1v unit min max min max i li (2) 2. outputs deselected. input leakage current 0 v v in v cc 4 4 a i lo (2) output leakage current 0 v v out v cc 4 4 a i cc supply current e = v il , outputs open 140 70 ma i cc1 supply current (standby) ttl e = v ih 10 2 ma i cc2 supply current (standby) cmos e v cc ? 0.2 v 8 1 ma v il input low voltage ?0.3 0.8 ?0.3 0.6 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 0.4 v v oh output high voltage i oh = ?1 ma 2.4 2.2 v
m48z2m1y, m48z2m1v dc and ac parameters doc id 5135 rev 6 15/20 figure 10. power down/up mode ac waveforms table 9. power down/up ac characteristics table 10. power down/up trip points dc characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5 v or 3.0 to 3.6 v (except where noted). min max unit t er e recovery time 40 120 ms t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v so v cc fall time m48z2m1y 10 s m48z2m1v 150 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t wp write protect time from v cc = v pfd m48z2m1y 40 150 s m48z2m1v 40 250 s symbol parameter (1)(2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 4.5 to 5.5 v or 3.0 to 3.6 v (except where noted). min typ max unit v pfd power-fail deselect voltage m48z2m1y 4.2 4.3 4.5 v m48z2m1v 2.8 2.9 3.0 v v so battery backup switchover voltage m48z2m1y 3.0 v m48z2m1v 2.45 v t dr (3) 3. at 25 c; v cc = 0 v. expected data rete ntion time 10 years ai01031 v cc e (per control input) outputs don't care high-z tf tfb tr trb twp tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so ter
package mechanical data m48z2m1y, m48z2m1v 16/20 doc id 5135 rev 6 5 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 11. pldip36 ? 36-pin plastic dip long module, package outline note: drawing is not to scale. table 11. pldip36 ? 36-pin plastic dip long module, package mechanical data pmdip a1 a l b e1 d e n 1 ea e 3 s c symb mm inches typ min max typ min max a 9.27 9.52 0.3650 0.3748 a1 0.38 0.0150 b 0.43 0.59 0.0169 0.0232 c 0.20 0.33 0.0079 0.0130 d 52.58 53.34 2.0701 2.1000 e 18.03 18.80 0.7098 0.7402 e1 2.30 2.81 0.0906 0.1106 e3 43.18 1.7 ea 14.99 16.00 0.5902 0.6299 l 3.05 3.81 0.1201 0.1500 s 4.45 5.33 0.1752 0.2098 n36 36
m48z2m1y, m48z2m1v part numbering doc id 5135 rev 6 17/20 6 part numbering table 12. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m48z 2m1y ?70 pl 1 device type m48z supply voltage and write protect voltage 2m1y (1) = v cc = 4.5 to 5.5 v; v pfd = 4.2 to 4.5 v 1. not recommended for new design. contac t st sales office for availability. 2m1v (1) = v cc = 3.0 to 3.6 v; v pfd = 2.8 to 3.0 v speed ?70 = 70 ns (y) ?85 = 85 ns (v) package pl = pldip36 temperature range 1 = 0 to 70c 9 = extended temperature shipping method blank = ecopack ? package, tubes
environmental information m48z2m1y, m48z2m1v 18/20 doc id 5135 rev 6 7 environmental information figure 12. recycling symbols this product contains a non-rechargeable lithi um (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
m48z2m1y, m48z2m1v revision history doc id 5135 rev 6 19/20 8 revision history table 13. document revision history date revision changes jul-1999 1 first issue 31-aug-2000 2 from preliminary data to datasheet 20-mar-2002 3 reformatted; temperature information added to tables ( ta bl e 7 , 8 , 3 , 4 , 9 , 10 ) 29-may-2002 3.1 modified ?v cc noise and negative going transients? text 28-mar-2003 3.2 remove 5 v/5%, add 3 v part ( figure 1 , 2 , 9 ; ta bl e 5 , 6 , 8 , 2 , 3 , 4 , 9 , 10 , 12 ) 02-jul-2003 3.3 changed characteristic ( ta bl e 8 ) 18-feb-2005 4 reformatted; ir reflow update ( ta b l e 5 ) 02-aug-2010 5 updated features , section 3 , ta b l e 1 2 ; added ecopack ? text to section 5 ; added section 7: environmental information . 24-jun-2011 6 devices are not recommended for new design (updated cover page, ta bl e 1 2 ); updated footnote of table 5: absolute maximum ratings ; updated section 7: environmental information .
m48z2m1y, m48z2m1v 20/20 doc id 5135 rev 6 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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