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asix electronics corporation released date: 6/21/2005 4f, no.8, hsin a nn rd., science-based industrial park, hsin-chu city , taiw an, r.o.c. tel: 886-3-579-9500 fa x: 886-3-579-9558 http://www.asix.com .tw/ AX88772 usb to 10/100 fast ethernet/homepna controller document no: ax 88772_07/ 6/ 21/ 05 features ? si ngl e chi p usb t o 10/ 100 fast et hernet and hom e pna and hom e pl ug net w ork c ont rol l e r ? int e grat es on-chi p 10/ 100m bps fast et hernet phy ? usb speci fi cat i on 1.0 and 1.1 and 2.0 com p l i a nt ? support s usb ful l and hi gh speed m odes wi t h b u s p o w er cap ab ility ? supports 4 endpoints on usb interface ? high perform ance packet transfer rate over usb bus usi ng propri e t a ry burst t r ansfer m echani s m (su b m itted fo r us p a ten t ap p licatio n ) ? ieee 802.3 10base-t and 100base-tx co m p atib le ? em bedded 20kb sr am for r x packet bufferi ng and 8kb sr am for tx packet bufferi ng ? support s bot h ful l - dupl ex and hal f-dupl ex operat i on i n fast et hernet ? provides optional mii inte rface for ethernet phy and hom e pna/ hom e plug phy interface ? support s suspend m ode and r e m o t e w a keup vi a li nk-up, m a gi c packet , or ext e rnal pi n ? opt i onal phy power down duri ng suspend m ode ? support s 256/ 512 by t e s (93c56/ 93c66) of seri al eepr o m (for st ori ng usb descri pt ors) ? support s aut o m a t i c l o adi ng of et hernet id, usb descri pt ors and adapt e r c onfi gurat i on from eeprom after p o w er-o n in itializatio n ? external phy loop-back diagnostic capability ? int e grat es on-chi p 3.3v t o 2.5v vol t a ge regul at or and requi res onl y si ngl e power suppl y : 3.3v ? sm al l form fact or wi t h 128-pi n lqfp package ? 12m hz and 25m hz cl ock i nput from ei t h er cry s t a l o r o s cillato r so u r ce ? operating tem p erature range: 0 c to 7 0 c. *ieee is a registered tradem ark of the institute of electrical and electronic engineers, inc. *all other tr adem ar ks and r e gister ed tradem ark are the property of their r e spective holder s . product description the AX88772 usb t o 10/ 100 fast et hernet / h om epna/ hom e pl ug cont rol l e r i s a hi gh perform ance and hi ghl y i n t e grat ed asic wi t h em bedded 28kb sr am for packet bufferi ng. it enabl e s l o w cost and affordabl e fast et hernet net w ork connect i on t o deskt op, not ebook pc , and em bedded sy st em usi ng popul ar usb port s . it has an usb interface to com m uni cat e wi t h usb host cont rol l e r and i s com p l i a nt wi t h usb speci fi cat i on v1.0, v1.1 and v2.0. it i m pl em ent s 10/100mbps ethernet lan f unction based on ieee802.3, and ieee802.3u standards or hom e pna standard. it i n t e grat es an on-chi p 10/ 100m bps et hernet phy t o si m p l i f y sy st em desi gn and provi des an opt i onal m e di a-i ndependent interface (mii) for im plem enting fast ethernet and hom e pna functions. system block diagram alway s contact asix for possible updates before starting a design. this data sheet contains new products inform ation. asix electr onics reserves the rights to m odify product speci fication without notice. no liability is assum e d as a result of the us e of this product. no rights under any pa tent accom p any the sale of the product. usb i/f AX88772 10/ 100 phy (fx) ma g n e tic rj4 5 r j 11 eeprom hom e lan phy ma g n e tic r j 45 m a gnet i c
AX88772 usb to 10/100 fast ethernet/homepna controller table of contents 1.0 introduction ................................................................................................................ 4 1.1 g ener al d e s cript ion ........................................................................................................... 4 1.2 AX88772 b loc k d iagram .................................................................................................... 4 1.3 AX88772 p inout d iagram ................................................................................................... 5 2.0 signal description .................................................................................................... 6 3.0 function description ............................................................................................ 10 3.1 usb c ore and i nter fac e .................................................................................................. 10 3.2 10/100 e ther net phy ......................................................................................................... 10 3.3 mac c ore ........................................................................................................................... 10 3.4 s tation m anagem ent (sta) ............................................................................................. 10 3.5 m emory a rbit e r ................................................................................................................ 11 3.6 usb to e ther net b ridge ................................................................................................... 11 3.7 s er ial eeprom l oader ................................................................................................... 11 3.8 g ener al p urpose i/o .......................................................................................................... 11 4.0 serial eeprom memory map ............................................................................... 12 4.1 d etailed d e s cript ion ........................................................................................................ 13 5.0 usb configuration structure ......................................................................... 16 5.1 usb c onfiguration ........................................................................................................... 16 5.2 usb i nter fac e .................................................................................................................... 16 5.3 usb e ndpoints ................................................................................................................... 16 6.0 usb commands ............................................................................................................. 17 6.1 usb s tandard c ommands ................................................................................................ 17 6.2 usb v endor c ommands .................................................................................................... 18 6.2.1 d etailed r egister d e s cript ion .................................................................................... 19 6.2.2 r em ote w akeup d e s cript ion ........................................................................................ 27 6.3 i nt e rrupt e ndpoint ........................................................................................................... 27 7.0 embedded ethernet phy register description .................................... 28 7.1 d etailed r egister d e s cript ion ........................................................................................ 28 7.1.1 b asic m ode c ontrol r egister (bmcr) ...................................................................... 28 7.1.2 b asic m ode s tatus r egister (bmsr) .......................................................................... 29 7.1.3 phy i dentifier r egister 1 ............................................................................................. 30 7.1.4 phy i dentifier r egister 2 ............................................................................................. 30 7.1.5 a uto n egotiation a dver tisem e nt r egister (anar) ............................................... 30 7.1.6 a uto n egotiation l ink p ar tner a b i lity r egister (anlpar) ................................ 31 7.1.7 a uto n egotiation e xpansion r egister (aner) ......................................................... 31 8.0 electrical specifications ................................................................................. 33 8.1 dc c haracteristics ........................................................................................................... 33 8.1.1 a bsolute m aximum r atings ......................................................................................... 33 8.1.2 r ecommended o perating c ondition ........................................................................... 33 asix electronics corporation 2
AX88772 usb to 10/100 fast ethernet/homepna controller 8.1.3 l eakage c urrent and c apacitance ............................................................................ 33 8.1.4 dc c har ac ter istic s of 2.5v i/o p ins ........................................................................... 34 8.1.5 dc c har ac ter istic s of 3.3v i/o p ins ........................................................................... 34 8.2 p ow er c onsumption ........................................................................................................... 34 8.3 p ow er - up s equence ............................................................................................................ 35 8.4 ac t im ing c har a c ter istic s .............................................................................................. 35 8.4.1 c loc k t im ing ................................................................................................................... 35 8.4.2 r eset t im ing .................................................................................................................... 36 8.4.3 mii t im ing (100m bps ) ..................................................................................................... 36 8.4.4 s tation m anagem ent t im ing ........................................................................................ 37 8.4.5 s er ial eeprom t im ing .................................................................................................. 38 9.0 package information ............................................................................................ 39 10.0 ordering information ...................................................................................... 40 appendix a: system applications ................................................................................. 41 a.1 usb to f ast e ther net c onver ter ..................................................................................... 41 a.2 usb to f ast e ther net and / or h ome lan c om b o solution ............................................ 41 revision history .................................................................................................................... 42 list of figures f igure 1: AX88772 b loc k d iagram ................................................................................................ 4 f igure 2: AX88772 p inout d iagram ................................................................................................ 5 f igure 3: i nternal d atapath d iagram of 10/100 e ther net phy and mii i nter fac e ........... 10 f igure 4: i nternal c ontrol m ux for s tation m anagement i nter fac e ................................. 11 f igure 5: m ultic a st f ilter e xample ............................................................................................ 23 list of tables t ab le 1: p inout d e s cript ion ............................................................................................................ 6 t ab le 2: s er ial eeprom m em or y m ap ....................................................................................... 12 t ab le 3: usb s tandard c ommand r egister m ap ....................................................................... 17 t ab le 4: usb v endor c ommand r egister m ap .......................................................................... 18 t ab le 5: r em ote w akeup t rut h t able ........................................................................................ 27 t ab le 6: e mbedded e ther net p hy r egister m ap ........................................................................ 28 asix electronics corporation 3
AX88772 usb to 10/100 fast ethernet/homepna controller 1.0 introduction 1.1 general description the AX88772 usb t o 10/ 100 fast et hernet / h om epna/ hom e pl ug cont rol l e r i s a hi gh perform ance and hi ghl y i n t e grat ed asic wi t h em bedded 28kb sr am for packet bufferi ng. it enabl e s l o w cost and affordabl e fast et hernet net w ork connection to desktop, not ebook pc, and em bedded system using popular usb ports. it has an usb interface to com m uni cat e wi t h usb host cont rol l e r and i s com p l i a nt wi t h usb speci fi cat i on v1.0, v1.1 and v2.0. it i m pl em ent s 10/100mbps ethernet lan f unction based on ieee802.3, and ieee802.3u standards or hom e pna standard. it i n t e grat es an on-chi p 10/ 100m bps et hernet phy t o si m p l i f y sy st em desi gn and provi des an opt i onal m e di a-i ndependent interface (mii) for im plem enting fast ethernet and hom e pna functions. the AX88772 needs 12m hz cl ock for usb operat i on and 25m hz cl oc k for fast et hernet operat i on. it i s i n 128-pi n lqfp l o w profi l e package wi t h c m os process and requi res onl y si ngl e 3.3v power suppl y t o operat e . 1.2 AX88772 block diagram rxip/rxin txop/txon m ii i/f gpio2~0 ma c co re mem o ry arb iter usb to ethernet b r i dge usb core and interface sta seeprom loader i/f general pur p ose i/ o 28kb sram eecs eeck eedi eedo 10/ 100 ethernet phy md c md i o dp/dm dprs/dm r s figure 1: AX88772 block diagram asix electronics corporation 4
AX88772 usb to 10/100 fast ethernet/homepna controller 1.3 AX88772 pinout diagram the AX88772 is housed in the 128-pin lqfp package. i n t _ r e gula t or _ e n hs _ t est _ m ode 1 2 34 56 78 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 33 34 35 36 37 38 39 40 41 42 43 asix AX88772 17 18 19 20 44 45 46 47 2 1 22 2 3 24 25 48 49 50 51 52 53 54 55 56 57 26 27 28 29 30 3 1 32 58 110 109 108 107 106 103 104 105 117 116 115 114 111 112 113 124 123 122 121 118 119 120 128 125 126 127 59 60 61 62 63 64 96 95 94 93 92 91 90 89 88 8 7 86 85 84 83 82 81 80 79 78 77 7 6 75 7 4 73 72 71 70 69 68 67 66 65 102 101 98 99 100 97 dm rs gnd vdd k vb us t e s t spee d up nc fo r c e fs _ n ex t w a k eup _ n gnd a h vdd3 sc a n _t e s t sc a n _e n a bl e cl k6 0 e xt cl ks e l vddk gnd ee ck ee cs ee di ee do vdd 3 v2 5 a gnd a vdd3 tx _ c l k tx _ e n nc nc tx _ e r t xd0 t xd1 t xd2 t xd3 nc nc nc nc gnd av d d k db 4 nc a gnd vd d3 gnd vd d2 a gnd a vddk rs t p b a vddk a gnd t xop t xon a gnd xi n2 5 m xout 2 5 m ibr e f nc vddk rxi p rxi n gnd vdd2 vdd2 rx _ c l k rx_dv rx_er r xd0 r xd1 r xd2 r xd3 db 3 db 2 db 1 db 0 crs co l gnd md i n t md c md i o gp i o 0 gp i o 1 gp i o 2 gn d vd d3 p hyr s t _n et _spe ed _l ed fdx_ l e d l i nk_ l e d c o l_ le d rx _ l ed us b_ s p e ed_ l ed le d gn d v ddk dp dm gn d gnd vd dk re set_ n vdd a h gnd gnd xi n 1 2 m xout 12 m av d d 3 ag n d rr ef a gnd rp u dp rs a vdd3 gnd vdd3 nc nc a vddk a gnd a gnd a vddk av d d k a gnd nc nc nc i n t _ r e gula t or _ e n hs _ t est _ m ode 1 2 34 56 78 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 33 34 35 36 37 38 39 40 41 42 43 asix AX88772 17 18 19 20 44 45 46 47 2 1 22 2 3 24 25 48 49 50 51 52 53 54 55 56 57 26 27 28 29 30 3 1 32 58 110 109 108 107 106 103 104 105 117 116 115 114 111 112 113 124 123 122 121 118 119 120 128 125 126 127 59 60 61 62 63 64 96 95 94 93 92 91 90 89 88 8 7 86 85 84 83 82 81 80 79 78 77 7 6 75 7 4 73 72 71 70 69 68 67 66 65 102 101 98 99 100 97 dm rs gnd vdd k vb us t e s t spee d up nc fo r c e fs _ n ex t w a k eup _ n gnd a h vdd3 sc a n _t e s t sc a n _e n a bl e cl k6 0 e xt cl ks e l vddk gnd ee ck ee cs ee di ee do vdd 3 v2 5 a gnd a vdd3 tx _ c l k tx _ e n nc nc tx _ e r t xd0 t xd1 t xd2 t xd3 nc nc nc nc gnd av d d k db 4 nc a gnd vd d3 gnd vd d2 a gnd a vddk rs t p b a vddk a gnd t xop t xon a gnd xi n2 5 m xout 2 5 m ibr e f nc vddk rxi p rxi n gnd vdd2 vdd2 rx _ c l k rx_dv rx_er r xd0 r xd1 r xd2 r xd3 db 3 db 2 db 1 db 0 crs co l gnd md i n t md c md i o gp i o 0 gp i o 1 gp i o 2 gn d vd d3 p hyr s t _n et _spe ed _l ed fdx_ l e d l i nk_ l e d c o l_ le d rx _ l ed us b_ s p e ed_ l ed le d gn d v ddk dp dm gn d gnd vd dk re set_ n vdd a h gnd gnd xi n 1 2 m xout 12 m av d d 3 ag n d rr ef a gnd rp u dp rs a vdd3 gnd vdd3 nc nc a vddk a gnd a gnd a vddk av d d k a gnd nc nc nc hs _ t est _ m ode 1 2 34 56 78 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 33 34 35 36 37 38 39 40 41 42 43 asix AX88772 17 18 19 20 44 45 46 47 2 1 22 2 3 24 25 48 49 50 51 52 53 54 55 56 57 26 27 28 29 30 3 1 32 58 110 109 108 107 106 103 104 105 117 116 115 114 111 112 113 124 123 122 121 118 119 120 128 125 126 127 59 60 61 62 63 64 96 95 94 93 92 91 90 89 88 8 7 86 85 84 83 82 81 80 79 78 77 7 6 75 7 4 73 72 71 70 69 68 67 66 65 102 101 98 99 100 97 dm rs gnd vdd k vb us t e s t spee d up nc fo r c e fs _ n ex t w a k eup _ n gnd a h vdd3 sc a n _t e s t sc a n _e n a bl e cl k6 0 e xt cl ks e l vddk gnd ee ck ee cs ee di ee do vdd 3 v2 5 a gnd a vdd3 tx _ c l k tx _ e n nc nc tx _ e r t xd0 t xd1 t xd2 t xd3 nc nc nc nc gnd av d d k db 4 nc a gnd vd d3 gnd vd d2 a gnd a vddk rs t p b a vddk a gnd t xop t xon a gnd xi n2 5 m xout 2 5 m ibr e f nc vddk rxi p rxi n gnd vdd2 vdd2 rx _ c l k rx_dv rx_er r xd0 r xd1 r xd2 r xd3 db 3 db 2 db 1 db 0 crs co l gnd md i n t md c md i o gp i o 0 gp i o 1 gp i o 2 gn d vd d3 p hyr s t _n et _spe ed _l ed fdx_ l e d l i nk_ l e d c o l_ le d rx _ l ed us b_ s p e ed_ l ed le d gn d v ddk dp dm gn d gnd vd dk re set_ n vdd a h gnd gnd xi n 1 2 m xout 12 m av d d 3 ag n d rr ef a gnd rp u dp rs a vdd3 gnd vdd3 nc nc a vddk a gnd a gnd a vddk av d d k a gnd nc nc nc figure 2: AX88772 pinout diagram asix electronics corporation 5
AX88772 usb to 10/100 fast ethernet/homepna controller 2.0 signal description the fol l o wi ng abbrevi a t i ons appl y t o t h e fol l o wi ng pi n descri pt i on t a bl e. i2 input, 2.5v with 3.3v tolerant b2 bi -directional i/o, 2.5v with 3.3v tolerant i 3 i n p u t , 3 . 3 v b 5 bi-directiona l i/o, 3.3v with 5v tolerant i5 input, 3.3v with 5v tolerant pu internal pull up (75k) o2 output, 2.5v w i th 3.3v tol erant pd internal pul l dow n (75k) o3 output, 3.3v p power pin o5 output, 3.3v with 5v tolerant s schmitt trigger b b i - d i r e c t i o n a l i / o table 1: pinout description pin name t y pe pin no pin description usb interface dp b 3 2 usb 2 . 0 d a ta p o s itiv e p i n . dm b 31 usb 2.0 dat a negat i v e pi n. dprs b 36 usb 1.1 data positive pin. please connect to dp through a 39ohm (+/-1%) serial resistor. dm r s b 35 usb 1.1 dat a negat i v e pi n. pl ease connect t o dm t h rough a 39ohm (+/-1%) serial resistor. vb us i5/ p d/ s 10 vb us pi n i nput . pl ease connect t o usb bus power. xin12m i3 26 12mhz crystal or oscillator cl ock input. this clock is needed for usb phy tran sceiv e r to o p e rate. x o u t 1 2 m o 3 2 7 12mhz crystal or oscillator clock output. rref i 30 for usb phy? s i n t e rnal bi asi ng. pl ease connect t o agnd t h rough a 12.1kohm (+/ - 1%) resi st or . rpu i 34 for usb phy? s internal biasi ng. please connect to a vdd3 (3.3v) t h rough a 1.5kohm (+/ - 5%) resi st or . station management interface m d c o2 121 st at i on m a nagem e nt dat a c l ock out put . t he t i m i ng reference for m d io. al l dat a t r ansfers on m d io are sy nchroni zed t o t h e ri si ng edge of t h i s cl ock. the frequency of m d c i s 1.5m hz. m d i o b 2 / p u 1 2 0 st at i on m a nagem e nt dat a input / o ut put . s eri a l dat a i nput / out put transfers from /to the phys. the tran sfer prot ocol conform s t o t h e ieee 802.3u mii spec. m d int i2/ p u 1 17 st at i on m a nagem e nt int e rrupt i nput . mii interface rx_clk i2 104 receive clock. rx _clk is received from phy to p rovi de t i m i ng reference for the transfer of rxd [7: 0 ] , r x _dv, and r x _er si gnal s on receive direction of mii interface. rxd [3:0] i 2 1 10, 1 0 9 , 108, 107 receive data. rxd [3:0] is driven synchronously with respect to r x _c lk by phy. rx_dv i2 105 receive data valid. r x_dv is driven synchronously with respect to r x _c lk by phy. it i s assert ed hi gh when val i d dat a i s present on rxd [3:0] . r x _ e r i 2 1 0 6 receive error. rx_er is driven synchronously with respect to r x _c lk by phy. it i s assert ed hi gh for one or m o re r x _c lk peri ods t o i ndi cat e t o t h e m a c that an error has detected. col i2 1 1 6 co llisio n detected . col is d r iv en h i g h b y phy wh en th e co llisio n is detected. asix electronics corporation 6
AX88772 usb to 10/100 fast ethernet/homepna controller c r s i2 1 15 c a rri er sense. c r s i s assert ed hi gh asy n chronousl y b y the phy when either transm it or receive m e dium is non-idle. tx_clk i2 102 transm it clock. tx_clk is received from phy to provide tim ing reference for t h e t r ansfer of txd [3: 0 ] , tx_en and tx_er si gnal s on transm it direction of mii interface. txd [3: 0 ] o2 82, 83, 84, 85 transm i t dat a . txd [3: 0 ] i s t r ansi t i oned sy nchronousl y wi t h respect t o t h e ri si ng edge of tx_c lk. tx_en o2 89 transm i t enabl e . tx_en i s t r ansi t i oned s y n chronousl y wi t h respect t o t h e ri si ng edge of tx_c lk. tx_en i s assert ed hi gh t o i ndi cat e a v a lid txd [3 :0 ]. tx_er o2 88 transm i t c odi ng error. tx_er i s t r ansi t i oned sy nchronousl y wi t h respect t o t h e ri si ng edge of tx_c lk. w hen assert ed hi gh for one or m o re tx_c lk, t h e phy shal l em i t one or m o re code-groups t h at are n o t p a rt o f th e v a lid d a ta o r d e lim iter set so m e wh ere in th e fram e b e in g tran sm itted . serial eeprom interface eec k o5 4 eepr o m c l ock. eec k i s an out put cl ock t o eepr o m t o provi de tim ing reference for the transfer of eecs, eedi, and eedo signals. eec s o5 5 eepr o m c h i p sel ect . eec s i s assert ed hi gh sy nchronousl y wi t h respect t o ri si ng edge of eec k as chip select signal. eedi o5 6 eeprom data in. eedi is the seri al out put dat a t o eepr o m ? s dat a i nput pi n and i s sy nchronous wi t h respect t o t h e ri si ng edge of eec k. eedo i5/ p d 9 eepr o m dat a out . eedo i s t h e seri al i nput dat a from eepr o m ? s dat a out put pi n. ethernet phy interface xin25m i3 59 25mhz crystal or oscillator cl ock input. this clock is needed for the em bedded 10/ 100 et hernet phy t o operat e . x o u t 2 5 m o 3 5 8 25mhz crystal or oscillator clock input. r s tpb i 65 r e set i nput of em bedded et hernet phy: r s tpb i s an act i v e l o w i nput used for resetting internal ethernet phy. w h en internal ethernet phy is used, user can connect this pin to an external rc circuit, which gets pulled-up to avddk (2.5v). the reset period from 50m s t o 150m s i s recom m e nded. rxip i 52 receive data input positive pin for both 10base-t and 100b ase-tx. rxin i 51 receive data input ne gative pin for both 10base-t and 100b ase-tx. txop o 62 t r ansm it data output pos itive pin for both 10base-t and 100 base-tx txon o 61 t r ansm i t dat a out put negat i v e pi n for bot h 10base-t and 100 base-tx ibref b 56 for et hernet phy? s i n t e rnal bi asi ng. pl ease connect t o gnd t h rough a 12.3kohm resi st or . rx_led o3 92 receive activity led indicator . this pin drives low and high in turn (blinking) when ethernet phy is receiving and drives high when not receiving. col_ led o3 9 3 co llisio n d e tected led in d i cato r . th is p i n d r iv es lo w wh en th e eth e rn et phy d e tects co llisio n an d d r iv es h i g h wh en n o co llisio n . link_led o3 94 li nk st at us led i ndi cat or. thi s pi n dri v es l o w cont i nuousl y when t h e et hernet l i nk i s up and dri v es l o w and hi gh i n t u rn (bl i nki ng) when ethernet phy is in recei ving or transm itting state. fdx_led o3 95 ful l - dupl ex led i ndi cat or. thi s pi n dri v es l o w when t h e et hernet phy i s i n ful l - dupl ex m ode and dri v es hi gh when i n hal f dupl ex m ode. et_speed_led o3 96 ethernet speed led indicator . th is p i n d r iv es lo w wh en th e eth e rn et phy i s i n 100b ase-tx m ode and dri v es hi gh when i n 10b ase-t m ode. misc. pins asix electronics corporation 7
AX88772 usb to 10/100 fast ethernet/homepna controller r e set_n i5/ p u/ s 12 c h i p r e set input . r e set_n pi n i s act i v e l o w. w h en assert ed, i t put s th e en tire ch ip in to reset state im m e d i ately. after co m p letin g reset, eeprom d a ta will b e lo ad ed au to m a tically. extw akeup_n i5/ p u/ s 1 1 r e m o t e -wakeup t r i gger from ext e rnal pi n. extw akeup_n shoul d be assert ed l o w for m o re t h an 2 cy cl es of 12m hz cl ock t o be effective. for gpio [2: 0 ] b 5 / p d 1, 2, 3 general purpose inpu t / out put pi ns. t hese pi ns are defaul t as i nput pi ns aft e r power -on reset . pl ease use gpio0 for cont rol l i ng t h e power down pi n of ext e rnal et hernet phy , i f appl i cabl e . phyrst_n o2 122 phyrst_n is a tri-state out put used for resetting external ethernet phy. th is p i n is d e fau lt in tri-state after p o w er-o n reset. if ex tern al eth e rn et phy?s reset lev e l is activ e lo w, co n n ect th is to phy?s reset pi n wi t h a pul l e d-down resi st or. if i t ? s act i v e hi gh, connect t h i s t o phy with a p u lled - u p resisto r . th is way can m a k e su re th e ex tern al et hernet phy st ay s i n reset st at e before soft ware bri ngs i t out of reset . for c e fs_n i3/ p u 15 force usb ful l speed (act i v e l o w). for norm a l operat i on, user shoul d keep t h i s pi n nc t o enabl e usb hi gh speed handshaki ng process t o deci de t h e speed of usb bus. set t i ng t h i s pi n l o w set s t h e devi ce t o operat e at ful l speed m ode onl y and di sabl es c h i r p k (hs handshaki ng process). led o3 125 led i ndi cat or: w h en usb bus i s i n ful l speed, t h i s pi n dri v es hi gh cont i nuousl y . w h en usb bus i s i n hi gh speed, t h i s pi n dri v es l o w cont i nuousl y . thi s pi n dri v es hi gh and l o w i n t u rn (bl i nki ng) t o i ndi cat e tx dat a t r ansfer goi ng on whenever t h e host cont rol l e r sends bul k out dat a t r ansfer. usb_speed_le d o3 126 usb bus speed led i ndi cat or. w h en usb bus i s i n ful l speed, t h i s pi n dri v es hi gh cont i nuousl y . w h en usb bus i s i n hi gh speed, t h i s pi n dri v es l o w cont i nuousl y . testspeedup i3/ p d 13 test pi n. for norm a l operat i on, user shoul d keep t h i s pi n nc . hs_test_m ode i3/ p d 42 t e st pi n. for norm a l operat i on, user shoul d keep t h i s pi n nc . sc an_test i3/ p d 43 t e st pi n. for norm a l operat i on, user shoul d keep t h i s pi n nc . sc an_enab le i3/ p d 44 t e st pi n. for norm a l operat i on, user shoul d keep t h i s pi n nc . c l k60ext i3/ p d 45 t e st pi n. for norm a l operat i on, user shoul d keep t h i s pi n nc . c l ksel i3/ p d 46 t e st pi n. for norm a l operat i on, user shoul d keep t h i s pi n nc . db [4: 0 ] i2 101, 1 1 1 , 1 12, 1 13, 1 14 debug pi ns. for norm a l operat i on, user shoul d set t h ese pi ns l o w . on-chip regulator pins int_regulato r_ en i 20 on-chi p 3.3v t o 2.5v vol t a ge regul at or enabl e . c onnect t h i s pi n t o vddah di rect l y t o enabl e on-chi p regul at or . connect t h i s pi n t o gndah to disable on-chip regulator . vddah p 22 3.3v power suppl y t o on-chi p 3.3v t o 2.5v vol t a ge regul at or . gndah p 23 ground pi n of on-chi p 3.3v t o 2.5v vol t a ge regul at or . v25 p 21 2.5v vol t a ge out put of on-chi p 3.3v t o 2.5v vol t a ge regul at or . power and ground pins vddk p 16, 24, 74, 99, 1 18 dig ital co re po wer . 2 . 5 v . vdd2 p 80, 86, 123 di gi t a l i/ o power . 2.5v . vdd3 p 8, 19, 41, 97, 128 digital i/o power . 3.3v . gnd p 7, 17, 18, 25, 40, 75, 81, 87, 98, 100, 1 19, 124, 127 di gi t a l ground. avddk p 49, 53, 57, 64, 66, 68 anal og c o re power . 2.5v . avdd3 p 28, 37, 39 analog i/o power . 3.3v . asix electronics corporation 8
AX88772 usb to 10/100 fast ethernet/homepna controller agnd p 29, 33, 38, 50, 54, 55, 60, 63, 67, 69 anal og ground. asix electronics corporation 9
AX88772 usb to 10/100 fast ethernet/homepna controller 3.0 function description 3.1 usb core and interface the usb core and interface contains an usb 2.0 transcei ver, serial interface engine (sie), usb bus protocol handshaki ng bl ock, usb st andard com m a nd, vendor com m a nd regi st ers, l ogi c for support i ng bul k t r ansfer, and i n t e rrupt transfer, etc. the usb interface is used to com m unicate with usb host c ontroller and is com p liant with usb specification v1.0, v1.1 and v2.0. 3.2 10/100 ethernet phy the 10/100 fast ethernet phy is com p lia nt with ieee 802.3 and ieee 802.3u standard s. it contains an on-chip crystal oscillator, pll-based clock m u ltiplier, digital phase-locke d loop for data/tim ing recovery . it provides over-sam pling m i xed-si gnal t r ansm i t dri v ers com p l y i ng wi t h 10/ 100b ase-tx t r ansm i t wave shapi ng / sl ew rat e cont rol requi rem e nt s. it has robust m i xed-signal loop adaptive equalizer for receiving signa l recovery. it contains baseline wander corrective bl ock t o com p ensat e dat a dependent offset due t o ac coupl i ng t r ansform e rs. it support s aut o -negot i a t i on and has m u l t i -funct i on led out put s. 3.3 mac core the mac core supports 802.3 and 802.3u mac sub-layer functi ons, such as basic mac fram e receive and transm it, crc checking and generation, filtering, forwarding, flow-control in full-duplex m ode, and collision-detection and handling in half-duplex m ode, etc. it provides a m e dia-inde pendent interface (mii) for im pl em enting fast ethernet and hom e pna funct i ons. the mac core interfaces to both extern al mii interface i/o pins and mii in terface of the em bedded 10/100 ethernet phy. the selection between the two mii interfaces is done via usb vendor com m a nd, soft ware phy select register. figure 3 shows the datapath diagram of 10/100 ethernet phy and mii interface to mac core. 10/ 100 ethernet phy mii interface i/o: rx_clk, rxd [3:0] , rx_dv, rx_ e r, col, crs tx_clk, txd [3:0], tx_en, t x _ e r rxip/rxin txop/txon tx rx ma c co re figure 3: internal datapath diagram of 10/100 ethernet phy and mii interface 3.4 station management (sta) the station m a nagem e nt interface provides a sim p le, two-wire, serial interface to connect to a m a naged phy device for the purposes of controlling the phy and gathering status from the phy. the station m a nagem e nt interface allows asix electronics corporation 10
AX88772 usb to 10/100 fast ethernet/homepna controller co m m u n i catin g with m u ltip le phy d e v i ces at th e sam e tim e b y id en tifyin g th e m a n a g e d phy with 5 - b it, u n i q u e ph y id. the phy id of t h e em bedded 10/ 100 et hernet phy i s bei ng pre-assi gned t o ?1_0000?. figure 4 shows the internal control m ux for the station m a nagem e nt interface. w h en doing read, the ?m din? signal will be driven from 10/100 ethernet phy only if phy id m a tches with ?1_0000?, otherwise, it will always be driven from ext e rnal m d io pi n of t h e asic . 10/ 100 et hernet phy ph y id = 1 _ 0000 m dout md i n sta md c md i o figure 4: internal control mux for station managem e nt interface 3.5 memory arbiter the m e m o ry arbiter block is responsible for storing received mac fram e s into on-chip sram (packet buffer) and then forwardi ng t o usb bus upon request from usb host vi a bul k i n t r ansfer. it al so m oni t o rs packet buffer usage i n ful l - dupl ex m ode for t r i ggeri ng pause fram e t r ansm i ssi on out on tx di rect i on. the m e m o ry arbi t e r bl ock i s al so responsible for storing mac fram e s received from usb host via bulk out transfer and wa iting to be transm itted out t o wards et hernet net w ork. 3.6 usb to ethernet bridge the usb t o et hernet bri dge bl ock i s responsi b l e for conve rt i ng et hernet m a c fram e i n t o usb packet s or vi ce-versa. this block supports proprietary burst transfer m echanism (s ubm itted for us patent applica tion) to offload software burden and t o offer very hi gh packet t r ansfer t h roughput over usb bus. 3.7 serial eeprom loader the seri al eepr o m l o ader i s responsi b l e for readi ng confi gurat i on dat a aut o m a t i cal l y from ext e rnal seri al eepr o m aft e r power-on reset . 3.8 general purpose i/o there are 3 general purpose i/ o pi ns provi ded by t h i s asic . asix electronics corporation 11
AX88772 usb to 10/100 fast ethernet/homepna controller 4.0 serial eeprom memory map eeprom offset high byte low byte 00h r e served w o rd c ount for prel oad 0 1 h f l a g 02h lengt h of hi gh-speed devi ce descri pt or (by t es) eepr o m offset of hi gh-speed devi ce descri pt or 03h lengt h of hi gh-speed c onfi gurat i on descri pt or (by t es) eepr o m offset of hi gh-speed c onfi gurat i on descri pt or 04h node id 1 node id 0 05h node id 3 node id 2 06h node id 5 node id 4 07h language id hi gh b y t e language id low b y t e 08h lengt h of m a nufact ure st ri ng (by t es) eepr o m offset of m a nufact ure st ri ng 09h lengt h of product st ri ng (by t es) eepr o m offset of product st ri ng 0ah lengt h of seri al num b er st ri ng (by t es) eepr o m offset of seri al num b er st ri ng 0b h lengt h of c onfi gurat i on st ri ng (by t es) eepr o m offset of c onfi gurat i on st ri ng 0ch length of interface 0 string (bytes ) eeprom offset of interface 0 string 0dh length of interface 1/0 string (bytes) eeprom offset of interface 1/0 string 0eh length of interface 1/1 string (bytes) eeprom offset of interface 1/1 string 0fh phy r e gi st er offset for int e rrupt endpoi nt phy r e gi st er offset for int e rrupt endpoi nt 10h max packet size high byte max packet size low byte 11h secondary phy _ ty pe [7: 5 ] and phy _ id [4: 0 ] pri m ary phy _ ty pe [7: 5 ] and phy _ id [4: 0 ] 12h pause fram e high w a ter mark pause fram e low w a ter mark 13h lengt h of ful l - speed devi ce descri pt or (by t es) eepr o m offset of ful l - speed devi ce descri pt or 14h lengt h of ful l - speed c onfi gurat i on descri pt or (by t es) eepr o m offset of ful l - speed c onfi gurat i on descri pt or 1 5 h - 1 f h r e s e r v e d r e s e r v e d table 2: serial eeprom mem o ry map asix electronics corporation 12
AX88772 usb to 10/100 fast ethernet/homepna controller 4.1 detailed description the fol l o wi ng sect i ons provi de det a i l e d descri pt i on for som e of the field in serial eeprom m e m o ry m a p, for other fields not covered here, pl ease refer t o AX88772l appl i cat i on not e for m o re det a i l s . 4.1.1 word count for preload (00h) the num ber of words t o be prel oaded by t h e eepr o m l o ader = 15h. 4.1.2 flag (01h) bit 1 5 bit 1 4 bit 1 3 bit 1 2 bit 1 1 bit 1 0 bit 9 bit 8 reserv ed t d p e c e m bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t a c e r d c e s c p r d c k 1 r w u reserv ed s p sp: self-power (for usb getstatus) 1: sel f power. 0: b u s power. r w u: r e m o t e w a keup support . 1: indi cat e t h at t h i s devi ce support s r e m o t e w a keup. 0: not support . dck: disable chirp k. 1: di sabl ed. 0: enable. scpr: software control phy reset. 1: the pr l and pr te bi t s of soft ware r e set r e gi st er cont rol t h e phyr st_n out put l e vel . 0: the usb reset on usb bus and pr te bi t of soft ware r e set r e gi st er cont rol t h e phyr st_n out put l e vel . rdce: rx dro p crc en ab le. 1: crc byte is dropped on receive d mac fram e forwarding to host. 0: crc byte is not dropped. t a ce: tx ap p e n d crc en ab le. 1 : crc b y te is g e n e rated an d ap p e n d e d b y th e asic fo r ev ery tran sm itted mac fram e . 0 : crc b y te is n o t ap p e n d e d . c e m : c a pt ure effect i v e m ode. 1: capture effective m ode enable. 0: di sabl ed. tdpe: test debug port enabl e . 1: enabl e t e st debug port for chi p debug purpose. 0: di sabl e t e st debug port and t h e chi p operat e i n norm a l funct i on m ode b i t 1, 10~ 15: r e served. 4.1.3 node id (04~06h) the node id 0 t o 5 by t e s represent t h e m a c address of t h e devi ce, for exam pl e, i f m a c address = 01-23-45-67-89-ab h, t h en node id 0 = 01, node id 1 = 23, node id 2 = 45, node id 3 = 67, node id 4 = 89, and node id 5 = ab . asix electronics corporation 13
AX88772 usb to 10/100 fast ethernet/homepna controller 4.1.4 phy register offset for interrupt endpoint (0fh) bit 1 5 bit 1 4 bit 1 3 bit 1 2 bit 1 1 bit 1 0 bit 9 bit 8 reserved phy register of fset 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved phy register of fset 2 phy register offset 1: fill in phy? s register offset of prim ary phy here . upon each interrupt endpoint issued, its register value will be reported in byte # 5 and 6 of interr upt endpoint packet. phy register offset 2: fill in phy?s register offset of prim ary phy here. upon each interrupt endpoint issued, its register value will be reported in byte # 7 and 8 of interr upt endpoint packet. 4.1.5 max packet siz e high/low byte (10h) fill in this field the m a xim u m rx/tx mac fram e size suppor ted by this asic. the num ber m u st be even num ber in t e rm s of by t e and shoul d be l e ss t h an or equal t o 2500 by t e s. 4.1.6 primary/secondary phy_type and phy_id (11h) the 3 bi t s phy _ ty pe fi el d for bot h pri m ary and secondary phy i s defi ned as fol l o ws, 3?b000: 10/ 100 et hernet phy or 1m hom e phy . 3?b111: non-support e d phy . for exam pl e, t h e hi gh b y t e val u e of ?e0h? m eans t h at secondary phy i s not support e d. not e t h at t h e phy _ id of t h e em bedded 10/ 100 et hernet phy i s bei ng assi gned t o 5?b1_0000. 4.1.7 pause frame high water and low water mark (12h) w h en operating in full-duplex m ode, correct setting of this field is very im porta nt and can affect the overall packet receive throughput perform ance in a great d eal. the high w a ter mark is the thres hold to trigger sending of pause fram e and the low w a ter mark is the threshold to stop sending of pause fram e . note that each free buffer count here represents 256 bytes of packet storage space in sram. tot a l free buffer count = 80 sto p sendi n g pause fram e when free buffer > low w a ter m a r k st art sendi n g pause fram e when free buffer < hi g h w a t e r m a r k 0 asix electronics corporation 14
AX88772 usb to 10/100 fast ethernet/homepna controller 4.1.8 pow er-up steps after p o w er-o n reset, th e asic will au to m a tically p e rfo rm fo llo win g step s to th e eth e rn et ph ys v i a mdc/mdio lin es, 1. w r i t e t o phy _ id of 00h wi t h phy regi st er offset 00h t o power down al l phy s at t ached t o st at i on m a nagem e nt interface. 2. w r i t e t o pri m ary phy _ id wi t h phy regi st er offset 00h t o power down pri m ary phy . 3. w r i t e t o secondary phy _ id wi t h phy regi st er offset 00h t o power down secondary phy . asix electronics corporation 15
AX88772 usb to 10/100 fast ethernet/homepna controller 5.0 usb configuration structure 5.1 usb configuration the AX88772 support s 1 c onfi gurat i on onl y . 5.2 usb interface the AX88772 supports 1 interface. 5.3 usb endpoints the AX88772 support s fol l o wi ng 4 endpoi nt s: endpoi nt 0: c ont rol endpoi nt . it i s used for confi guri ng t h e devi ce, e.g., st andard com m a nds and vendor com m a nds, etc. endpoi nt 1: int e rrupt endpoi nt . it i s used for report i ng st at us. endpoint 2: bulk in endpoi nt. it is used for r eceiving ethernet packet. endpoint 3: bulk out endpoi nt. it is used for tran sm itting ethernet packet. asix electronics corporation 16
AX88772 usb to 10/100 fast ethernet/homepna controller 6.0 usb commands there are t h ree com m a nd groups for endpoi nt 0 (c ont rol endpoi nt ) i n AX88772: the usb st andard com m a nds the usb vendor com m a nds the usb c o m m uni cat i on c l ass com m a nds 6.1 usb standard commands the language id i s 0x0904 for engl i s h ppll m eans buffer l e ngt h c c m eans confi gurat i on num ber i i m eans interface num ber aa m eans device address setup command data bytes access ty pe description 8006_00 01 00 00 llpp ppll by t e s i n dat a st age r ead get devi ce descri pt or 8006_0002 0000_llpp ppll by t e s i n dat a st age r ead get c onfi gurat i on descri pt or 8006_0003_0000_llpp ppll by t e s i n da t a st age r ead get support e d language id 8006_0103_0904_llpp ppll by t e s i n dat a st age r ead get m a nufact ure st ri ng 8006_0203_0904_llpp ppll by t e s i n dat a st age r ead get product st ri ng 8006_0303_0904_llpp ppll by t e s i n da t a st age r ead get seri al num b er st ri ng 8006_0403_0904_llpp ppll by t e s i n dat a st age r ead get c onfi gurat i on st ri ng 8 0 0 6 _ 0 5 0 3 _ 0 9 0 4 _ l l p p p p l l by tes in data stage read get interface 0 string 8 0 0 6 _ 0 6 0 3 _ 0 9 0 4 _ l l p p p p l l by tes in data stage read get interface 1/0 string 8 0 0 6 _ 0 7 0 3 _ 0 9 0 4 _ l l p p p p l l by tes in data stage read get interface 1/1 string 8008_0000_0000_0100 1 by t e s i n dat a st age r ead get c onfi gurat i on 0009_c c 00_0000_0000 no dat a i n dat a st age w r i t e set c onfi gurat i on 810a_0000 _i i00_0100 1 bytes in data stage read get interface 010b_as00_0000_0000 no data in data stage w r ite set interface 0005_aa00_0000_0000 no dat a i n dat a st age w r i t e set address table 3: usb standard com m a nd register map asix electronics corporation 17
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2 usb vendor commands no setup command data bytes access ty pe description 1 . c 002_aa0b _0c 00_0800 8 b y tes in data stag e r ead rx /tx sram read register 2. 4003_aa0b _0c 00_0800 8 by t e s i n dat a st age w ri t e r x / t x sr am w r i t e r e gi st er 3. 4006_0000_0000_0000 no dat a i n dat a st age w ri t e soft ware seri al m a nagem e nt c ont rol reg i ster 4. c 007_ aa00_c c 00_0200 2 by t e s i n dat a st age r ead phy r ead r e gi st er 5. 4008 _aa00_c c 00_0200 2 by t e s i n dat a st age w ri t e phy w r i t e r e gi st er 6. c 009_0000_0000_0100 1 by t e s i n dat a st age r ead se ri al m a nagem e nt st at us r e gi st er 7. 400a_0000_0000_0000 no dat a i n dat a st age w ri t e hardware seri al m a nagem e nt c ont rol reg i ster 8. c 00b _aa00_0000_0200 2 by t e s i n dat a st age r ead sr om r ead r e gi st er 9. 400c _aa00_c c dd_0000 no dat a i n dat a st age w ri t e sr om w r i t e r e gi st er 10. 400d_0000_0000_0000 no dat a i n dat a st age w ri t e sr om w r i t e enabl e r e gi st er 11. 400e_0000_0000_0000 no dat a i n dat a st age w ri t e sr om w r i t e di sabl e r e gi st er 12. c 00f_0000_0000_0200 2 by t e s i n dat a st age r ead r x c ont rol r e gi st er 13. 4010_aab b _0000_0000 no dat a i n dat a st age w ri t e r x c ont rol r e gi st er 14. c 011_0000_0000_0300 3 by t e s i n dat a st age r ead ipg/ ipg1/ i pg2 r e gi st er 15. 4012_aab b _ c c 00_0000 no dat a i n dat a st age w ri t e ipg/ ipg1/ i pg2 r e gi st er 16. c 013_0000_0000_0600 6 by t e s i n dat a st age r ead node id r e gi st er 17. 4014_0000_0000_0600 6 by t e s i n dat a st age w ri t e node id r e gi st er 18. c 015_0000_0000_0800 8 by t e s, ma0~ma7 , in data stage read mu lticast filter array reg i ster 19. 4016_0000_0000_0800 8 by t e s, ma0~ma7 , in data stage w r ite mu lticast filter array reg i ster 20. 4017_aa00_0000_0000 no dat a i n dat a st age w ri t e test r e gi st er 21. c 019_0000_0000_0200 2 by t e s i n dat a st age r ead et hernet / h om epna phy address reg i ster 22. c 01a_0000_0000_0200 2 by t e s i n dat a st age r ead m e di um st at us r e gi st er 23. 401b _aab b _0000 _0000 no dat a i n dat a st age w ri t e m e di um m ode r e gi st er 24. c 01c _0000_0000_0100 1by t e s i n dat a st age r ead m oni t o r m ode st at us r e gi st er 25. 401d_aa00_0000_0000 no dat a i n dat a st age w ri t e m oni t o r m ode r e gi st er 26. c 01e _0000_0000_0100 1 by t e s i n dat a st age r ead gpios st at us r e gi st er 27. 401f_aa00_0000_0000 no dat a i n dat a st age w ri t e gpios r e gi st er 28. 4020_aa00_0000_0000 no dat a i n dat a st age w ri t e soft ware r e set r e gi st er 29. c 021_aa00_0000_0100 1 by t e s i n dat a st age r ead soft ware phy sel ect st at us r e gi st er 30. 4022_aa00_0000_0000 no dat a i n dat a st age w ri t e soft ware phy sel ect r e gi st er table 4: usb vendor com m a nd register map asix electronics corporation 18
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.1 detailed register description 6.2.1.1 rx/tx sram read register (02h, read only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] reserv ed b [3 :0 ] 0 h c [3: 0 ] dd [7 :0 ] in data stag e ee [7 :0 ] in data stag e ff [7 :0 ] in data stag e gg [7 :0 ] in data stag e hh [7 :0 ] in data stag e ii [7 :0 ] in data stag e jj [7 :0 ] in data stag e kk [7 :0 ] in data stag e {b [3 :0 ], aa [7 :0 ]}: th e read address of r x or tx sr am . c [0 ]: ram selectio n . 0: indicates to read from rx sram. 1: indicates to read from tx sram. c [3 :1 ]: reserv ed . {dd [7 :0 ], ee [7 :0 ], ff [7 :0 ], gg [7 :0 ], hh [7 :0 ], ii [7 :0 ], jj [7 :0 ], kk [7 :0 ]}: th e 6 4 - b its o f d a ta p r esen ted in data stag e are th e d a ta to b e written to rx o r tx sram. 6.2.1.2 rx/tx sram w r ite register (03h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] reserv ed b [3 :0 ] reserv ed c [3 :0 ] dd [7 :0 ] in data stag e ee [7 :0 ] in data stag e ff [7 :0 ] in data stag e gg [7 :0 ] in data stag e hh [7 :0 ] in data stag e ii [7 :0 ] in data stag e jj [7 :0 ] in data stag e kk [7 :0 ] in data stag e {b [3 :0 ], aa [7 :0 ]}: th e write ad d r ess o f rx o r tx sram. c [0 ]: ram selectio n . 0 : in d i cates to write to rx sram. 1 : in d i cates to write to tx sram. c [3 :1 ]: reserv ed . {dd [7 :0 ], ee [7 :0 ], ff [7 :0 ], gg [7 :0 ], hh [7 :0 ], ii [7 :0 ], jj [7 :0 ], kk [7 :0 ]}: th e 6 4 - b its o f d a ta p r esen ted in data stag e are th e d a ta to b e written to rx o r tx sram. 6.2.1.3 software serial managem e nt c ontrol register (06h, write only) w h en software needs to access to ethernet phy?s internal registers, one has to first issue this com m a nd to request the ownership of serial manage m e nt interface. the ownership status of the interface can be retrieved from serial m a nagem e nt st at us r e gi st er. asix electronics corporation 19
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.1.4 phy read register (07h, read only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] 00h cc [7 :0 ] aa [4:0] : the phy id value. c c [4: 0 ] : the regi st er address of ethernet phy?s internal register. aa [7:5] : reserved cc [7 :5 ]: reserv ed 6.2.1.5 phy w r ite register (08h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] 00h cc [7 :0 ] aa [4:0] : the phy id value. c c [4: 0 ] : the regi st er address of ethernet phy?s internal register. aa [7:5] : reserved cc [7 :5 ]: reserv ed 6.2.1.6 serial managem e nt status register (09h, read only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 r e s e r v e d h o s t _ e n host_en: host access enable. software can read this register to determ ine the current ownership of serial managem e nt interface. 1: software is allowed to access ethern et phy?s internal registers via phy r ead register or phy w r ite registers. 0: asic?s hardware owns the serial managem e nt interface and so ftware?s access is ignored. 6.2.1.7 hardware serial managem e nt c ontrol register (0ah, write only) w h en software is done accessing serial managem e nt interface, one needs to issue this com m a nd to release the ownership of the interface back to asic?s hardware. afte r issuing this com m a nd, follo wing phy read register or phy w r ite register from software will be ignored. note : soft ware shoul d i ssue t h i s com m a nd every t i m e aft e r finished accessing serial manage m e nt interface to release the ownership back to hardware to allow periodic interrupt endpoint to be able to access the ethernet phy?s registers via the serial managem e nt interface. 6.2.1.8 srom read register (0bh, read only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] aa [7:0]: the read address of serial eerom. asix electronics corporation 20
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.1.9 srom w r ite register (0ch, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] 00h cc [7 :0 ] dd [7:0] aa [7:0] : the write address of serial eerom . { dd [7 :0 ], cc [7 :0 ] }: th e write d a ta v a lu e o f serial eerom 6.2.1.10 w r ite srom enable (0dh, write only) user issu es th is co m m a n d to en ab le write p e rm issio n to serial eeprom fro m srom w r ite reg i ster. 6.2.1.11 w r ite srom disable (0eh, write only) user issu es th is co m m a n d to d i sab l e write p e rm issio n to serial eeprom fro m srom w r ite reg i ster. 6.2.1.12 rx control register (0fh, read only and 10h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 s o r e s e r v e d a p am a b s e p am all p r o 0 h r e s e r v ed m f b [1 :0 ] aa [7:0] = { so, reserved, ap, am, ab, reserved, amall, pro } bb [7 :0 ] = { 0 h , reserv ed [3:2] , sb [1:0] } pro: packet_type_prom i scuous. 1: all fram e s received by the asic are forwarded up toward the host. 0: disabled (default). amall: packet_type_all_multicast. 1: all m u lticast fram e s received by the asic are forw arded up toward the host, not just the fram e s whose scram b lin g resu lt o f da m a tch i n g with m u lticast ad d r ess list p r o v i d e d in mu lticast filter array reg i ster. 0 : disab l ed . th is o n l y allo ws m u lticast fram e s wh o s e scram b lin g resu lt o f da field m a tch i n g with m u lticast ad d r ess list p r o v i d e d in mu lticast filter array reg i ster to b e fo rward e d u p to ward th e h o s t (d efau lt). sep: save error packet. 1: received packets with crc error ar e saved and forwarded to the host anyway. 0: received packets with crc error are discarded auto m a tically without forwardi ng to the host (default). ab: packet_type_broadcast. 1: all broadcast fram e s received by the asic are forwarded up toward the host (default). 0: di sabl ed. am: packet_type_multicast. 1 : all m u lticast fram e s wh o s e scram b lin g resu lt o f da m a tch i n g with m u lticast ad d r ess list are fo rward e d u p to th e h o s t (d efau lt). 0: di sabl ed. ap: accept physical address from multicast filter array. 1: al l o w uni cast packet s t o be forwarded up t o ward host i f t h e l ookup of scram b l i ng resul t of da i s found wi t h i n m u lticast ad d r ess list. 0: disabled, that is, unicast pack ets filtering are done without regard ing m u lticast address list (default). so: start op eratio n . 1: et hernet m a c st art operat i ng. 0: et hernet m a c st op operat i ng (defaul t ) . asix electronics corporation 21
AX88772 usb to 10/100 fast ethernet/homepna controller mfb [1:0]: maxim u m fram e burst transfer on usb bus. 00: 2048 b y t e s 01: 4096 b y t e s 10: 8192 b y t e s 1 1 : 16384 b y t e s (defaul t ) . 6.2.1.13 ipg/ipg1/ipg2 control register (11h, read only and 12h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] bb [7 :0 ] cc [7 :0 ] aa [6:0] = ipg [6:0] . bb [6:0] = ipg1 [6:0] . cc [6:0] = ipg2 [6:0] . ipg [6: 0 ] : int e r packet gap for back-t o-back t r ansfer on tx di rect i on i n m ii m ode (defaul t = 15h). ipg1 [6:0] : ipg part1 value (default = 0ch). ipg2 [6: 0 ] : ipg part 1 val u e + part 2 val u e (defaul t = 12h). aa [7] : reserved. bb [7 ]: reserv ed . cc [7 ]: reserv ed . 6.2.1.14 node id register (13h, read only and 14h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 aa [7:0] bb [7 :0 ] cc [7 :0 ] dd [7:0] ee [7:0] ff [7:0] aa [7:0] = noid 0. bb [7:0] = noid 1. cc [7:0] = noid 2. dd [7:0] = noid 3. ee [7:0] = noid 4. ff [7:0] = noid 5. {ff [7: 0 ] , ee [7: 0 ] , dd [7: 0 ] , c c [7: 0 ] , b b [7: 0 ] , aa [7: 0 ] } = et hernet m a c address [47: 0] of t h e node. asix electronics corporation 22
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.1.15 multicast filter array (15h, read only and 16h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 ma 0 [ 7 :0 ] ma 1 [ 7 :0 ] ma 2 [ 7 :0 ] ma 3 [ 7 :0 ] ma 4 [ 7 :0 ] ma 5 [ 7 :0 ] ma 6 [ 7 :0 ] ma 7 [ 7 :0 ] {m a7 [7:0] , m a 6 [7:0] , m a 5 [7:0] , m a 4 [7:0] , m a 3 [7 :0 ], ma2 [7 :0 ], ma1 [7 :0 ], ma0 [7 :0 ]} = th e m u lticast ad d r ess b it m a p fo r m u lticast fram e filterin g b l o c k . see fig u r e 5 : mu lticast filter ex am p l e, fo r ex am p l e. crc3 2 {crc31, 30, 29, 28, 27, 26} address[5: 0] = 1ah m a r [ 63: 0] = 400_0000h da 81 81 81 81 81 81 figure 5: multicast filter exam ple 6.2.1.16 test register (17h, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 mm [ 7 :6 ] ld rn d ldr nd: load r a ndom num ber i n t o m a c ? s exponent i a l back-off t i m er. user wri t e s a ?1? t o enabl e t h e asic t o l o ad a sm all random num ber into mac?s back-off tim er to shorten the back-off duration in each retry after co llisio n . th is reg i ster is u s ed fo r test p u r p o s e. defau lt v a lu e = 0 . m m [7:6] : reserved. 6.2.1.17 ethernet / hom e pna phy address register (19h, read only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 secphyt y pe [2:0] secphyid [4:0] priph y t y p e [2 :0 ] priph y id [4 :0 ] secphy ty pe, secphy id: the secondary phy address l o aded from seri al eepr o m ? s offset address 11h. pri p hy ty pe, pri p hy id: the pri m ari l y phy address l o aded from seri al eepr o m ? s offset address 11h. asix electronics corporation 23
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.1.18 medium status register (1ah, read only) and medium mode register (1bh, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 p f 0 tfc r f c 0 1 f d 0 r e s e r v e d s m s b p reserved p s r e aa [7: 0 ] = {pf, jfe, tfc , r f c , en125, ac , fd, gm }. bb [7:0] = {reserved, sm, sbp, je, ps, re}. bit 0 : please always write 0 to th is b it. ps: port speed in mii m ode 1: 100 m bps (defaul t ) . 0: 10 m bps. fd: ful l dupl ex m ode 1: ful l dupl ex m ode (defaul t ) . 0: hal f dupl ex m ode. bit 2 : please always write 1 to th is b it. bit 3 : please always write 0 to th is b it. rfc: rx flo w co n t ro l en ab le. 1: enable receiving of pause fram e on rx direction during full duplex m ode (default). 0: di sabl ed. tfc : tx fl ow c ont rol enabl e . 1: enable transm itting pause fram e on tx direction during full duplex m ode (default). 0: di sabl ed. bit 6 : please always write 0 to th is b it. pf: c h eck onl y ?l engt h/ t y p e? field for pause fram e. 1: enabl e , i . e., pause fram e s are i d ent i f i e d onl y based on l/ t fi l e d. 0: di sabl ed, i . e., pause fram e s are i d ent i f i e d based on bot h da and l/ t fi el ds (defaul t ) . re: receive enable. 1: enable rx path of the asic. 0: disabled (default). sbp: stop backpressure. 1: w h en tfc bi t = 1, set t i ng t h i s bi t enabl e s backpressure on tx di rect i on ?cont i nuousl y ? duri ng r x buffer ful l condi t i on i n hal f dupl ex m ode. 0 : w h en tfc b it = 1 , settin g th is b it en ab le b ack p r essu re o n tx d i rectio n ?in t erm itten tly? d u r in g rx b u ffer fu ll condi t i on i n hal f dupl ex m ode (defaul t ) . sm : super m ac support . 1: enabl e super m ac t o short e n exponent i a l back-off t i m e duri ng t r ansm i t ret r y . 0: disabled (default). 6.2.1.19 monitor mode status register (1ch, read only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 reser v ed u s reser v ed r w m p r w lu mo m mo m: mo n ito r mo d e . 1: enable. all received packets will be ch ecked on da and crc but not buffered into m e m o ry. 0: disabled (default). r w lu: r e m o t e w a keup t r i gger by et hernet li nk-up. 1: enable 0: disabled (default). r w m p : r e m o t e w a keup t r i gger by m a gi c packet . 1: enabl e 0: disabled (default). us: usb speed. 1: high speed m ode. 0: fs speed m ode. asix electronics corporation 24
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.1.20 monitor mode register (1dh, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 reser v ed r w m p r w lu mo m mo m: mo n ito r mo d e . 1: enable. all received packets will be ch ecked on da and crc but not buffered into m e m o ry. 0: disabled (default). r w lu: r e m o t e w a keup t r i gger by et hernet li nk-up. 1: enable. 0: disabled (default). r w m p : r e m o t e w a keup t r i gger by m a gi c packet . 1: enable. 0: disabled (default). aa [7:3] : reserved. 6.2.1.21 gpio status register (1eh, read only) bit7 bit6 bit5 b i t 4 bit3 bit2 bit1 b i t 0 g p i _ 2 gpo_2_en g pi_1 gpo_1_en g pi_0 g p o _ 0 _ e n gpo_0_en: c u rrent l e vel of pi n gpio0? s out put enabl e . gpi_0: input l e vel on gpio0 pi n when gpio0 i s as an i nput pi n. gpo_1_en: c u rrent l e vel of pi n gpio1? s out put enabl e . gpi_1: input l e vel on gpio1 pi n when gpio1 i s as an i nput pi n. gpo_2_en: c u rrent l e vel of pi n gpio2? s out put enabl e . gpi_2: input l e vel on gpio2 pi n when gpio2 i s as an i nput pi n. 6.2.1.22 gpio register (1fh, write only) bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 r s e g p o _ 2 gpo2en g p o _ 1 gpo1en g p o _ 0 g p o 0 e n gpo0en: pin gpio0 output enable. 1: out put i s enabl e d (m eani ng gpio0 i s used as an out put pi n). 0: out put i s t r i - st at ed (m eani ng gpio0 i s used as an i nput pi n) (defaul t ) . gpo_0: pi n gpio0 out put v a l u e. gpo1en: pin gpio1 output enable. 1: out put i s enabl e d (m eani ng gpio1 i s used as an out put pi n). 0: out put i s t r i - st at ed (m eani ng gpio1 i s used as an i nput pi n) (defaul t ) . gpo_1: pi n gpio1 out put v a l u e. 0: (default). gpo2en: pin gpio2 output enable. 1: out put i s enabl e d (m eani ng gpio2 i s used as an out put pi n). 0: out put i s t r i - st at ed (m eani ng gpio2 i s used as an i nput pi n) (defaul t ) . gpo_2: pi n gpio2 out put v a l u e. 0: (default). rse: relo ad serial eeprom. 1: enable. 0: disabled (default) 6.2.1.23 software reset register (20h, write only) asix electronics corporation 25
AX88772 usb to 10/100 fast ethernet/homepna controller bit7 bit6 bit5 bit4 bit3 b i t 2 b i t 1 bit0 reserv ed i p p d i p r l b z p r l pr t e r t r r rr: clear fram e length error for bulk in. 1: set high to clear state. 0: set low to exit clear state (default). r t : clear fram e length error for bulk out. 1: set high to enter clear state. 0: set low to exit clear state (default). pr te: external phy reset pin tri-state enable. 1 : en ab le, i.e., th e ex tern al phyrst_ n p i n is tri-stated (d efau lt). th is allo ws th e phyrst_ n p i n ? s activ e lev e l to be cont rol l e d by ext e rnal pul l e d-up (act i v e hi gh duri ng power-on) or pul l e d-down resi st or (act i v e l o w duri ng power-on). 0: di sabl ed, i . e., t h e ext e rnal phyr st_n pi n?s l e vel i s dri v en by ei t h er pr l bi t or i n t e rnal ?usb r e set? based on th e settin g in scpr b it in flag b y te o f eeprom. pr l: ext e rnal phy r e set pi n level . w h en sc pr bi t = 1 and pr te = 0, t h i s bi t cont rol s t h e out put l e vel of ext e rnal phyr st_n pi n. 1: set t o hi gh (defaul t ) . 0 : set to lo w. bz: fo rce bu lk in to re turn a zero-length packet. 1: software can force bulk in to return a zero-length usb packet. 0: norm al operat i on m ode (defaul t ) . iprl: in tern al ph y reset co n t ro l. w h en scpr b it = 1 , th is b it acts as reset sig n a l o f in tern al eth e rn et ph y. 1: int e rnal et hernet phy i s i n operat i ng st at e. 0: internal ethernet phy in reset state (default). ippd: internal ethernet phy power down control. 1: int e rnal et hernet phy i s i n power down m ode (defaul t ) . 0: int e rnal et hernet phy i s i n operat i ng m ode. 6.2.1.24 software phy select status register (21h, read only) and so ftware phy select register 22h, write only) bit7 bit6 bit5 bit4 bit3 b i t 2 b i t 1 bit0 reserved asel psel psel: phy select, when as el = 0 (m an u a lly select th e ph y to o p e rate) 1: sel ect em bedded 10/ 100 et hernet phy (defaul t ) . 0: select external ph y, which is attached to the mii interface asel: au to select o r man u a l select 1: aut o m a t i cal l y sel ect based on l i nk st at us of em bedded 10/ 100 et hernet phy (defaul t ) . 0: m a nual l y sel ect bet w een t h e em bedded 10/ 100 et hernet phy and t h e ext e rnal one. asix electronics corporation 26
AX88772 usb to 10/100 fast ethernet/homepna controller 6.2.2 remote wakeup description aft e r AX88772 ent e rs i n t o suspend m ode, ei t h er t h e usb host or AX88772 i t s el f can awake i t up and resum e back t o t h e ori g i n al operat i on m ode before i t ent e red suspend. fol l o wi ng t r ut h t a bl e shows t h e chi p set t i ng, wakeup event , and devi ce response support e d by t h i s asic . not e t h at ?x? st ands for don?t - care. s e t t i n g w a k e u p e v e n t d e v i c e aw ak es up? wak e up by r w u bit of flag byte in eepro m set_feature standar d c o mma n d rw l u o f monitor m ode register r w mp o f monitor m ode reg i ster host send resu m e signal receiving mag i c packet extwake up_n pin l i nkup detected on prim ary phy l i nkup detected on secondar y phy host x x x x j -> k y e s d e v i c e 0 0 x x x x x x n o d e v i c e 1 1 0 1 y e s y e s d e v i c e 1 1 1 0 y e s y e s d e v i c e 1 1 1 0 y e s y e s d e v i c e 1 1 x x l o w- pulse y e s table 5: rem o te w a keup t r uth t a ble 6.3 interrupt endpoint the int e rrupt endpoi nt cont ai ns 8 by t e s of dat a and i t s fram e form at i s defi ned as: a100_b b 00_c c dd_eeff. w h ere bb b y te in b y te 3 : bit7 bit6 b i t 5 bit4 bit3 bit2 bit1 b i t 0 r e s e r v e d m d i n t f l e s p l s p p l s ppls: prim arily phy link state. 1: li nk i s up. 0: li nk i s down. spls: secondary phy li nk st at e. 1: li nk i s up. 0: li nk i s down. fle: bulk out ethernet fram e length error. 1: propri e t a ry lengt h fi el d has pari t y error duri ng b u l k out t r ansact i on. 0: propri e t a ry lengt h fi el d has no pari t y error duri ng b u l k out t r ansact i on. m d int: input l e vel of m d int pi n. the m d int pi n can be connect ed t o m d int# pi n of et hernet phy . 1: w h en m d int i nput pi n = 1. 0: w h en m d int i nput pi n = 0. c c dd by t e i n by t e 5 and 6: pri m ary phy ? s regi st er val u e, whose offset i s gi ven i n hi gh by t e of eepr o m offset 0fh. eeff by t e i n by t e 7 and 8: pri m ary phy ? s regi st er val u e, whose offset i s gi ven i n low by t e of eepr o m offset 0fh. asix electronics corporation 27
AX88772 usb to 10/100 fast ethernet/homepna controller 7.0 embedded ethernet phy register description a d d r e s s r e g i s t e r n a m e d e s c r i p t i o n 0h bmcr b a si c m ode cont rol regi st er, basi c regi st er. 1h b m sr b a si c m ode st at us regi st er, basi c regi st er. 2h phyidr 1 phy i d ent i f i e r regi st er 1, ext e nded regi st er. 3h phyidr 2 phy i d ent i f i e r regi st er 2, ext e nded regi st er. 4h anar auto negotiation advertisem ent register, extended register. 5 h anlpar au to n e g o tiatio n lin k p a rtn e r ab ility reg i ster, ex ten d e d reg i ster. 6h aner aut o negot i a t i on expansi on regi st er, ext e nded regi st er. 7h r e served r e served and current l y not support e d. 8h-fh ieee reserved ieee 802.3u reserved. table 6: em bedded ethernet phy register map 7.1 detailed register description the fol l o wi ng abbrevi a t i ons appl y t o fol l o wi ng s ect i ons for det a i l e d regi st er descri pt i on. reset value: 1 : bit set to lo g i c o n e 0 : bit set to lo g i c zero x: no set value pi n#: val u e l a t c hed from pi n # at reset t i m e access type: ro: read o n l y rw : read o r write attribute: sc: self-clearin g ps: valu e is p e rm an en tly set ll: latch low lh: lat c h hi gh 7.1.1 basic mode control register (bmcr) address 00h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 1 5 reset 0 , rw / sc reset: 1 = software reset 0 = norm al operat i on 1 4 l o o p b a c k 0, r w loopback: 1 = loopback enabl e d 0 = norm al operat i on 13 speed sel ect i on 1, r w speed sel ect i on: 1 = 100 m b / s 0 = 10 m b / s 1 2 a u t o -negot i a t i o n enable 1 , rw au to -n eg o tiatio n en ab le: 1 = aut o -negot i a t i on enabl e d. b i t s 8 and 13 of t h i s regi st er are i gnored when t h i s bi t i s set . 0 = aut o -ne g ot i a t i on di sabl ed. b i t s 8 and 13 of t h i s re g iste r asix electronics corporation 28
AX88772 usb to 10/100 fast ethernet/homepna controller det e rm i n e t h e l i nk speed and m ode. 11 power down 0, r w power down: 1 = power down 0 = norm al operat i on 10 isol at e (phyad = 00000), rw isolate: 1 = isol at e 0 = norm al operat i on 9 r e st art au to -n eg o tiatio n 0 , rw / sc restart au to -n eg o tiatio n : 1 = restart au to -n eg o tiatio n 0 = norm al operat i on 8 dupl ex m ode 1, r w dupl ex m ode: 1 = ful l dupl ex operat i on 0 = norm al operat i on 7 co llisio n test 0 , rw co llisio n test: 1 = co llisio n test en ab led 0 = norm al operat i on 6 : 0 r e s e r v ed x, r o reserv ed : w r i t e as 0, read as ?don?t care?. 7.1.2 basic mode status register (bmsr) address 01h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 15 100b ase-t4 0, r o / ps 100b ase-t4 capabl e : 0 = thi s phy i s not abl e t o perform i n 100b ase-t4 m ode. 1 4 1 0 0 b ase-tx ful l dupl ex 1, r o / ps 100b ase-tx ful l - dupl ex capabl e : 1 = thi s phy i s abl e t o perform i n 100b ase-tx ful l - dupl ex m ode. 1 3 1 0 0 b ase-tx hal f dupl ex 1, r o / ps 100b ase-tx hal f-dupl ex capabl e : 1 = thi s phy i s abl e t o perform i n 100b ase-tx hal f-dupl ex m ode. 1 2 1 0 b ase-t ful l dupl ex 1, r o / ps 10b ase-t ful l - dupl ex capabl e : 1 = thi s phy i s abl e t o perform i n 10b ase-t ful l - dupl ex m ode. 1 1 1 0 b ase-t hal f dupl ex 1, r o / ps 10b ase-t hal f-dupl ex capabl e : 1 = thi s phy i s abl e t o perform i n 10b ase-t hal f-dupl ex m ode. 10: 7 r e s e r v e d 0, r o r e served: w r i t e as 0, read as ?don?t care?. 6 m f pream bl e suppressi on 0, r o / ps m a nagem e nt fram e pream bl e suppressi on: 0 = this phy will not accept m a nagem e nt fram e s with pream ble suppressed. 5 a u to -n eg o tiatio n co m p lete 0 , ro au to -n eg o tiatio n co m p letio n : 1 = aut o -negot i a t i on process com p l e t e d 0 = aut o -negot i a t i on process not com p l e t e d 4 rem o te fau lt (no t support e d) 0 , ro / lh rem o te fau lt: 1 = r e m o t e faul t condi t i on det ect ed (cl eared on read or by a chi p reset) 0 = no rem o t e faul t condi t i on det ect ed 3 a u to -n eg o tiatio n ab ility 1 , ro / ps au to co n f ig u r atio n ab ility: 1 = th is phy is ab le to p e rfo rm au to -n eg o tiatio n . 2 li nk st at us 0, r o / ll li nk st at us: 1 = val i d l i nk est a bl i s hed (100m b/ s or 10m b/ s operat i on) 0 = li nk not est a bl i s hed 1 jabber det ect 0, r o / lh jabber det ect i on: 1 = jabber condi t i on det ect ed 0 = no jabber condi t i on det ect ed 0 ex ten d e d cap ab ility 1 , ro / ps ex ten d e d cap ab ility: asix electronics corporation 29
AX88772 usb to 10/100 fast ethernet/homepna controller 1 = ext e nded regi st er capabl e 0 = basic register capable only 7.1.3 phy identifier register 1 address 02h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 15: 0 oui_m sb 003b hex, r o / ps oui m o st si gni fi cant bi t s : b i t s 3 t o 18 of t h e oui are m a pped t o bi t s 15 t o 0 of t h i s regi st er respect i v el y . the m o st si gni fi cant t w o bi t s of t h e oui are i gnored. 7.1.4 phy identifier register 2 address 03h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 15: 10 oui_lsb 00_0110, r o / ps oui l east si gni fi cant bi t s : b i t s 19 t o 24 of t h e oui are m a pped t o bi t s 15 t o 10 of t h i s regi st er respectively. 9: 4 vndr_m dl 00_0001, ro / ps vendor m odel num ber. 3: 0 m d l_r e v 0001, r o / ps m odel revi si on num ber. 7.1.5 auto negotiation advertisement register (anar) address 04h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 15 np 0, r o / ps next page i ndi cat i on: 0 = no next page avai l a bl e the phy does not support t h e next page funct i on. 1 4 a c k 0, r o acknowl e dgem e nt : 1 = link partner ability da ta reception acknowledged 0 = not acknowl e dged 1 3 rf 0 , rw rem o te fau lt: 1 = faul t condi t i on det ect ed and advert i s ed 0 = no faul t det ect ed 12: 1 1 r e s e r v e d x, r w r e served: w r i t e as 0, read as ?don?t care?. 1 0 p a u s e 0, r w pause: 1 = pause operat i on enabl e d for ful l - dupl ex l i nks 0 = pause operat i on not enabl e d 9 t4 0, r o / ps 100b ase-t4 support : 0 = 100b ase-t4 not support e d 8 tx_fd 1, r w 100b ase-tx ful l - dupl ex support : 1 = 100b ase-tx ful l - dupl ex support e d by t h i s devi ce 0 = 100b ase-tx ful l - dupl ex not support e d by t h i s devi ce 7 tx_hd 1, r w 100b ase-tx hal f-dupl ex support : 1 = 100b ase-tx hal f-dupl ex support e d by t h i s devi ce 0 = 100b ase-tx hal f-dupl ex not support e d by t h i s devi ce 6 10_fd 1, r w 10b ase-t ful l - dupl ex support : 1 = 10b ase-t ful l - dupl ex support e d by t h i s phy 0 = 10b ase-t ful l - dupl ex not support e d by t h i s phy 5 10_hd 1, r w 10b ase-t hal f-dupl ex support : 1 = 10b ase-t hal f-dupl ex support e d by t h i s phy 0 = 10b ase-t hal f-dupl ex not support e d by t h i s phy 4: 0 sel ect or 0_0001, r w prot ocol sel ect i on bi t s : asix electronics corporation 30
AX88772 usb to 10/100 fast ethernet/homepna controller these bi t s cont ai n t h e bi nary encoded prot ocol sel ect or support e d by this phy. [0 0001] indicates that this phy supports ieee 802.3u c s m a / c d. 7.1.6 auto negotiation link part ner ability register (anlpar) address 05h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 15 np 0, r o next page i ndi cat i on: 1 = li nk part ner next page enabl e d 0 = li nk part ner not next page enabl e d 14 ac k 0, r o acknowl e dgem e nt : 1 = link partner ability for recep tion of data word acknowledged 0 = not acknowl e dged 1 3 rf 0 , ro rem o te fau lt: 1 = r e m o t e faul t i ndi cat ed by l i nk part ner 0 = no rem o t e faul t i ndi cat ed by l i nk part ner 12: 1 1 r e s e r v e d x, r o r e served: w r i t e as 0, read as ?don?t care?. 1 0 p a u s e 0, r o pause: 1 = pause operat i on support e d by l i nk part ner 0 = pause operat i on not support e d by l i nk part ner 9 t4 0, r o 100b ase-t4 support : 1 = 100b ase-t4 support e d by l i nk part ner 0 = 100b ase-t4 not support e d by l i nk part ner 8 tx_fd 0, r o 100b ase-tx ful l - dupl ex support : 1 = 100b ase-tx ful l - dupl ex support e d by l i nk part ner 0 = 100b ase-tx ful l - dupl ex not support e d by l i nk part ner 7 tx_hd 0, r o 100b ase-tx hal f-dupl ex support : 1 = 100b ase-tx hal f-dupl ex support e d by l i nk part ner 0 = 100b ase-tx hal f-dupl ex not support e d by l i nk part ner 6 10_fd 0, r o 10b ase-t ful l - dupl ex support : 1 = 10b ase-t ful l - dupl ex support e d by l i nk part ner 0 = 10b ase-t ful l - dupl ex not support e d by l i nk part ner 5 10_hd 0, r o 10b ase-t hal f-dupl ex support : 1 = 10b ase-t hal f-dupl ex support e d by l i nk part ner 0 = 10b ase-t hal f-dupl ex not support e d by l i nk part ner 4: 0 sel ect or 0_0000, r o prot ocol sel ect i on bi t s : li nk part ner?s bi nary encoded prot ocol sel ect or. 7.1.7 auto negotiation expansion register (aner) address 06h b i t b i t n a m e d e f a u l t d e s c r i p t i o n 15: 5 r e s e r v e d 0, r o r e served: w r i t e as 0, read as ?don?t care?. 4 pdf 0 , ro / lh parallel d e tectio n fau lt: 1 = faul t det ect ed vi a t h e paral l e l det ect i on funct i on 0 = no faul t det ect ed 3 lp_np_ab 0, r o li nk part ner next page enabl e : 1 = li nk part ner next page enabl e d 0 = li nk part ner not next page enabl e d 2 np_ab 0, r o / ps phy next page enabl e : 0 = phy not next page enabl e d 1 page_rx 0, ro / lh new page reception: asix electronics corporation 31
AX88772 usb to 10/100 fast ethernet/homepna controller 1 = new page received 0 = new page not received 0 lp_an_ab 0, r o li nk part ner aut o -negot i a t i on enabl e : 1 = aut o -negot i a t i on support e d by l i nk part ner asix electronics corporation 32
AX88772 usb to 10/100 fast ethernet/homepna controller 8.0 electrical specifications 8.1 dc characteristics 8.1.1 absolute maximum ratings s y m b o l p a r a m e t e r r a t i n g u n i t vddk di gi t a l core power suppl y - 0.3 t o vddk + 0.3 v vdd2 power suppl y of 2.5v i/ o - 0.3 t o vdd2 + 0.3 v vdd3 power suppl y of 3.3v i/ o - 0.5 t o vdd3 + 0.5 v avddk anal og core power suppl y - 0.3 t o avddk + 0.3 v avdd3 power suppl y of anal og i/ o - 0.5 t o avdd3 + 0.5 v input vol t a ge of 2.5v i/ o - 0.3 t o vdd2 + 0.3 v v in2 input vol t a ge of 2.5v i/ o wi t h 3.3v t o l e rant - 0.3 t o 3.9 v input vol t a ge of 3.3v i/ o - 0.3 t o vdd3 + 0.3 v v in3 input vol t a ge of 3.3v i/ o wi t h 5v t o l e rant - 0.3 t o 5.5 v t stg st orage t e m p erat ure - 40 t o 150 note: perm anent device dam a ge m a y occu r if absolute m a xim u m ratings are exceeded. functional operation should be restricted in the optional sections of this datasheet. exposure to absolute m a xim u m rating condition for extended periods m a y affect d e v i ce reliab ility. 8.1.2 recommended operating condition s y m b o l p a r a m e t e r m i n t y p m a x u n i t vddk di gi t a l core power suppl y 2.25 2.5 2.75 v vdd2 power suppl y of 2.5v i/ o 2.25 2.5 2.75 v vdd3 power suppl y of 3.3v i/ o 3.0 3.3 3.6 v avddk anal og core power suppl y 2.25 2.5 2.75 v avdd3 power suppl y of anal og i/ o 3.0 3.3 3.6 v input vol t a ge of 2.5 v i/ o 0 2.5 2.75 v v in2 input vol t a ge of 2.5 v i/ o wi t h 3.3 v to leran ce 0 2 . 5 3 . 6 v input vol t a ge of 3.3 v i/ o 0 3.3 3.6 v v in3 input vol t a ge of 3.3 v i/ o wi t h 5 v to leran ce 0 3 . 3 5 . 2 5 v t j c o m m e rci a l junct i on operat i ng tem p erature 0 - 1 1 5 t c c o m m e rci a l operat i ng t e m p erat ure 0 - 70 8.1.3 leakage current and capacitance s y m b o l p a r a m e t e r c o n d i t i o n min t yp m a x u n i t i in input current no pul l - up or pul l - down - 10 1 10 a i oz tri-state leakage current -10 1 10 a c in input capaci t a nce - 3.1 - pf c out output capacitance - 3.1 - pf c bid bi-directional buffer capacitance - 3.1 - pf asix electronics corporation 33
AX88772 usb to 10/100 fast ethernet/homepna controller not e : the capaci t a nce l i s t e d above does not i n cl ude pad cap aci t a nce and package capaci t a nce. one can est i m at e pi n capaci t a nce by addi ng a pad capaci t a nce of about 0.5pf and t h e package capaci t a nce. 8.1.4 dc characteristics of 2.5v i/o pins s y m b o l p a r a m e t e r c o n d i t i o n min t yp m a x u n i t vdd2 power suppl y of 2.5v i/ o 2.25 2.5 2 .75 v tem p j u n c t i on t e m p erat u r e 0 25 1 1 5 vi l input l o w vol t a ge - - 0.7 v vi h input hi gh vol t a ge cmos 1.7 - - v v t - sch m itt trig g e r n e g a tiv e g o i n g t h reshol d vol t a ge 0.7 1 .0 - v v t + sch m itt trig g e r p o s itiv e g o i n g t h reshol d vol t a ge cmos - 1 . 5 1 . 7 v vol out put l o w vol t a ge | i ol | = 2~ 16m a - - 0.4 v voh out put hi gh vol t a ge | i oh| = 2~ 16m a 1.85 - - v r pu input pul l - up resi st ance 40 75 190 k r pd input pul l - down resi st ance 40 75 190 k ii n input l eakage current vi n = vdd2 or 0 -10 1 10 a ioz tri-state output leakage current -10 1 10 a 8.1.5 dc characteristics of 3.3v i/o pins s y m b o l p a r a m e t e r c o n d i t i o n min t yp m a x u n i t vdd3 power suppl y of 3.3v i/ o 3.3v i/ o 3.0 3 .3 3.6 v tem p j u n c t i on t e m p erat u r e 0 25 1 1 5 vi l input l o w vol t a ge - - 0.8 v vi h input hi gh vol t a ge lvttl 2.0 - - v v t - sch m itt trig g e r n e g a tiv e g o i n g t h reshol d vol t a ge 0.8 1 .1 - v v t + sch m itt trig g e r p o s itiv e g o i n g t h reshol d vol t a ge lvttl - 1 . 6 2 . 0 v vol out put l o w vol t a ge | i ol | = 2~ 16m a - - 0.4 v voh out put hi gh vol t a ge | i oh| = 2~ 16m a 2.4 - - v r pu input pul l - up resi st ance 40 75 190 k r pd input pul l - down resi st ance 40 75 190 k ii n input l eakage current vi n = vdd3 or 0 -10 1 10 a ioz tri-state output leakage current -10 1 10 a 8.2 pow er consumption s y m b o l d e s c r i p t i o n c o n d i t i o n min t y p m a x units i vddk2 current consum ption of v d d k / v d d 2 , 2.5v - 2 5 . 4 - m a i vdd3 current consum ption of vdd3, 3.3v - < 1 - m a i avddk current consum ption of avddk, 2.5v - 69.3 - m a i avdd3 current consum ption of avdd3, 3.3v operating at ethernet 100m bps ful l dupl ex m ode and usb hi gh speed m ode - 5 1 . 1 - m a jc therm a l resi st ance of junct i on t o case 16.5 c / w ja th erm a l resistan ce o f j u n c tio n to am b i en t s till air 4 6 c/w asix electronics corporation 34
AX88772 usb to 10/100 fast ethernet/homepna controller 8.3 pow er-up sequence at power-up, AX88772 requi res t h e vdd3/ avdd3 power suppl y t o ri se t o nom i n al operat i ng vol t a ge wi t h i n tri s e3 and t h e vddk/ avdd2/ avddk power suppl y t o ri se t o nom i n al operat i ng vol t a ge wi t h i n tri s e2. tdelay32 trise2 trise3 3.3v vdd3/avdd3 0v 2.5v vddk/vdd2/avddk 0v s y m b o l p a r a m e t e r c o n d i t i o n m i n t y p m a x u n i t t rise3 3.3v power suppl y ri se t i m e from 0v t o 3.3v - - 10 m s t rise2 2.5v power suppl y ri se t i m e from 0v t o 2.5v - - 10 m s t delay 3 2 3.3v ri se t o 2.5v ri se t i m e del a y -5 - 5 m s 8.4 ac timing characteristics 8.4.1 clock timing 8.4.1.1 xin12m t p_xin12m t h_xin12m t l_xin12m t r_xin12m t f_xin12m v ih v il s y m b o l p a r a m e t e r c o n d i t i o n min t y p m a x u n i t t p_xin12m xin12m cl ock cy cl e t i m e - 83.33 - ns t h_xin12m xin12m cl ock hi gh t i m e - 41.6 - ns t l_xin12m xin12m cl ock l o w t i m e - 41.6 - ns t r_xin12m xin12m rise tim e v il (m ax) to v ih (m i n ) - - 1 . 0 n s t f_xin12m xin1 2 m fall tim e v ih (m in) to v il (m ax) - - 1 . 0 n s asix electronics corporation 35
AX88772 usb to 10/100 fast ethernet/homepna controller 8.4.1.2 xin25m t p_xin25m t h_xin25m t l_xin25m t r_xin25m t f_xin25m v ih v il s y m b o l p a r a m e t e r c o n d i t i o n min t y p m a x u n i t t p_xin25m xin25m cl ock cy cl e t i m e - 40.0 - ns t h_xin25m xin25m cl ock hi gh t i m e - 20.0 - ns t l_xin25m xin25m cl ock l o w t i m e - 20.0 - ns t r_xin25m xin25m rise tim e v il (m ax) to v ih (m i n ) - - 1 . 0 n s t f_xin25m xin2 5 m fall tim e v ih (m in) to v il (m ax) - - 1 . 0 n s 8.4.2 reset timing xin12m reset_n s y m b o l d e s c r i p t i o n m i n typ m a x u n i t s trst reset pulse width (6ms ~10ms) after xin12m is running 72000 - - xin12m cl ock cy cl e 8.4.3 mii timing (100mbps) ttclk ttch ttcl tx_clk tts tth txd [3:0] tx_en, tx_er trs t s y m b o l d e s c r i p t i o n m i n t y p m a x u n i t s ttclk tx_clk clock cy cle tim e *1 - 4 0 . 0 - n s ttch tx_clk clock high time *2 - 2 0 . 0 - n s ttcl tx_clk clock low time *2 - 2 0 . 0 - n s tts txd [3:0] , tx_en, tx_er setup time 2 8 . 0 - - n s tth txd [3:0] , tx_en, tx_er hold time 5 . 0 - - n s asix electronics corporation 36
AX88772 usb to 10/100 fast ethernet/homepna controller trclk trch trcl rx_ c lk trs trh rxd [3:0] rx_ dv, rx_ e r s y m b o l d e s c r i p t i o n m i n t y p m a x u n i t s trclk rx_clk clock cy cle tim e *1 - 4 0 . 0 - n s trch rx_clk clock high time *2 - 2 0 . 0 - n s trcl rx_clk clock low time *2 - 2 0 . 0 - n s trs rxd [3:0] , rx_dv, and rx_er setup time 3 . 0 - - n s trh rxd [3:0] , rx_dv, and rx_er hold time 0 . 5 - - n s *1: for 10m bps, t h e t y pi cal val u e of tt cl k and trcl k shal l scal e t o 400ns. *2: for 10m bps, t h e t y pi cal val u e of tt ch, tt cl , trch, and trcl shal l scal e t o 200ns. 8.4.4 station management timing mdc tod tcl k tch tcl th ts m d io (as out put ) m d io (as i nput ) s y m b o l d e s c r i p t i o n m i n t y p m a x u n i t s tcl k m d c cl ock cy cl e t i m e - 666 - ns tch m d c cl ock hi gh t i m e - 333 - ns tcl m d c cl ock l o w t i m e - 333 - ns tod m d c cl ock fal l i ng edge t o m d io out put del a y 0 - 2 ns ts m d io dat a i nput set up t i m e 10 - - ns th m d io dat a i nput hol d t i m e 0 - - ns asix electronics corporation 37
AX88772 usb to 10/100 fast ethernet/homepna controller 8.4.5 serial eeprom timing tch tclk data valid ts th thcs tlcs tscs valid valid tdv tod tcl eeck eedi (out put ) eecs eedo (i nput ) s y m b o l d e s c r i p t i o n m i n t y p m a x u n i t s tcl k eec k cl ock cy cl e t i m e - 5333 - ns tch eec k cl ock hi gh t i m e - 2666 - ns tcl eec k cl ock l o w t i m e - 2666 - ns tdv eedi out put val i d t o eec k ri si ng edge t i m e 2666 - - ns tod eec k ri si ng edge t o eedi out put del a y t i m e 2666 - - ns tscs eec s out put val i d t o eec k ri si ng edge t i m e 2666 - - ns thcs eec k fal l i ng edge t o eec s i nval i d t i m e 0 - - ns tl cs m i ni m u m eec s l o w t i m e 23904 - - ns ts eedo i nput set up t i m e 10 - - ns th eedo i nput hol d t i m e 100 - - ns asix electronics corporation 38
AX88772 usb to 10/100 fast ethernet/homepna controller 9.0 package information b e d hd e he pin 1 a2 a1 l l1 a millimeter symbol min ty p max a1 0.05 - - a2 1.35 1.40 1.45 a - - 1.60 b 0.13 0.18 0.23 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e - 0.4 bsc - hd 15.85 16.00 16.15 he 15.85 16.00 16.15 l 0.45 0.60 0.75 l1 - 1.00 ref - 0 3.5 7 asix electronics corporation 39
AX88772 usb to 10/100 fast ethernet/homepna controller 10.0 ordering information a x 8 8 7 7 2 l f product name package lqfp lead free asix electronics corporation 40
AX88772 usb to 10/100 fast ethernet/homepna controller appendix a: system applications som e typical applications fo r AX88772 are illustrated bellow. a.1 usb to fast ethernet converter a.2 usb to fast ethernet and/or homelan combo solution usb i/f m agnetic r j 45 hom e lan phy m agnetic rj1 1 AX88772 usb i/f eeprom 10/ 100 et hernet phy m agnetic rj4 5 c u rrent dri v er do not support for t h i s m agnetic r j 45 eeprom AX88772 c u rrent dri v er do not support for t h i s asix electronics corporation 41
AX88772 usb to 10/100 fast ethernet/homepna controller revision history revision date comment v 0 . 1 1 / 5 / 0 4 in itial release. v 0.2 4/ 16/ 04 added power consum pt i on da t a and updat e d pi n descri pt i on for pi n usb_speed_led. v 0.3 8/ 9/ 04 c h anged b u l k in t r ansfer t o endpoi nt 2 and b u l k out t r ansfer t o endpoi nt 3 i n sect i on 5.3. v 0.4 12/ 23/ 04 added t h erm a l dat a i n sect i on 8.2. v 0.5 1/ 6/ 05 added operat i ng t e m p erat ure i n feat ure and sect i on 8.1.2. v 0.6 3/ 23/ 05 added power-up sequence i n sect i on 8.3. v 0.7 6/21/05 changed the support to 1 usb interface in section 5.2. 4f, no. 8, hsin ann rd., science-based industrial park, hsinchu, taiw an, r.o.c. tel: 886-3-5799500 fax: 886-3-5799558 email: support@asix.com.tw web: http://www.asix.com .tw/ 42

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