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exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 xr68c92/192 rev. p2.10 plcc package dual universal asynchronous receiver and transmitter description the xr68c92/192 is a dual universal asynchronous receiver and transmitter with 8 (xr68c92) or 16 (xr68c192) bytes of transmit and receive fifos. the xr68c92/192 is pin-to-pin and functionally compatible to the xr68c681 and philips scc68681 uart with additional features. the operating speed of the receiver and transmitter can be selected independently from a table of twenty four fixed baud rates, a 16x clock derived from a programmable counter/ timer, or an external 1x or 16x clock. the baud rate generator and counter/timer can operate directly from a crystal or from external clock input. the xr68c92/192 provides a power down mode in which the oscillator is stopped but the register contents are retained. the xr68c92/192 is fabricated in an advanced cmos process to achieve low power and high speed requirements. features pin to pin and functionally compatible to xr68c681 and scc68692 full duplex transmit and receive operation 8 bytes of transmit/receive fifos (xr68c92) 16 bytes of transmit/receive fifos (xr68c192) programmable character lengths (5, 6, 7, 8) parity, framing, and over run error detection programmable 16-bit timer/counter on-chip crystal oscillator single interrupt output with eight selectable interrupt- ing conditions external 1x or 16x clock data rate up to 1mbps independent transmit and receive baud rates from 50bps to 230.4kbps 6 general purpose inputs 8 general purpose outputs ttl compatible inputs, outputs 4 transmit/receive trigger levels watch dog timer multi-drop mode compatible with 8051 nine bit mode 3.3 or 5 volts operation loopback modes power down mode ordering information part number pins package operating temperature xr68c92cp 40 pdip 0 c to + 70 c xr68c92cj 44 plcc 0 c to + 70 c xr68c92cv 44 tqfp 0 c to + 70 c xr68c92ip 40 pdip -40 c to + 85 c xr68c92ij 44 plcc -40 c to + 85 c xr68c92iv 44 tqfp -40 c to + 85 c part number pins packageoperating temperature xr68c192cp 40 pdip 0 c to + 70 c xr68c192cj 44 plcc 0 c to + 70 c xr68c192cv 44 tqfp 0 c to + 70 c XR68C192IP 40 pdip -40 c to + 85 c xr68c192ij 44 plcc -40 c to + 85 c xr68c192iv 44 tqfp -40 c to + 85 c may 2000 www.exar.com 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 a4 ip 0 r/-w -d tac k rxb n.c. txb op1 op3 op5 op7 -c s -reset xtal2 xtal1 rxa n.c. txa op0 op2 op4 op6 d1 d3 d5 d7 gnd n.c. -int d6 d4 d2 d0 a3 ip1 a2 ip3 a1 n.c. vcc ip4 ip5 -iack ip2 xr68c92 xr68c192
xr68c92/192 2 rev. p1.10 40 pin dip package 44 pin tqfp package package description 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 a3 ip 0 r/-w -d ta ck rxb txb op1 op3 op5 op7 n.c. -c s -reset xtal2 xtal1 rxa txa op0 op2 op4 op6 n.c. a2 ip1 a1 ip3 a0 vcc vcc ip4 ip5 -iack ip2 d1 d3 d5 d7 gnd gnd -int d6 d4 d2 d0 xr68c92 xr68c192 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1 ip3 a2 ip1 a3 a4 ip0 r/-w -dtack rxb txb op1 op3 op5 op7 d1 d3 d5 d7 gnd vcc ip4 ip5 -iack ip2 -cs -reset xtal2 xtal1 rxa txa op0 op2 op4 op6 d0 d2 d4 d6 -int xr68c92 xr68c192
xr68c92/192 3 rev. p1.10 b b b b b lock diagram d0-d7 r/-w -reset -dtack -iack a1-a4 -cs -in t op0-op7 ip0-ip5 tx a/b rx a/b xtal1 xtal2 data bus & control logic register select logic i/o control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals clock & baud rate generator
xr68c92/192 4 rev. p1.10 symbol description (* 44 tqfp package) symbol pin signal pin description 44 40 44* type - dtack 10 9 4 o data transfer acknowledge (three-state active low output). during read, write, or interrupt cycle goes low to indicate proper transfer of data between the cpu and xr68c92/ 192. rx a/b 35,11 31,10 29,5 i serial data input. the serial information (data) received from serial port to xr68c92/192 receive input circuit. a mark (high) is logic one and a space (low) is logic zero. tx a/b 33,13 30,11 28,6 o serial data output. the serial data is transmitted via this pin with additional start , stop and parity bits. the tx will be held in mark (high) state during reset, local loop back mode or when the transmitter is disabled. op0 32 29 27 o multi-purpose output. general purpose output or channel a request-to-send (-rtsa active low). op1 14 12 7 o multi-purpose output. general purpose output or channel b request-to-send (-rtsb active low). op2 31 28 26 o multi-purpose output. general purpose output or one of the following functions can be selected for this output pin by programming the output port configuration register bits 1,0: txaclk1 -transmit 1x clock. txaclk16 -transmit 16x clock rxaclk1 -receive 1x clock op3 15 13 8 o multi-purpose output. general purpose output or one of the following functions can be selected for this output pin by programming the output port configuration register bits 3,2: c/t -counter timer output (open drain output) txbclk1 -transmit 1x clock rxbclk1 -receive 1x clock op4 30 27 25 o multi-purpose output. general purpose output or one of the following functions can be selected for this output pin by programming the output port configuration register bit 4: - rxardy -receive ready signal (open drain output) -rxafull - receive fifo full signal (open drain output)
xr68c92/192 5 rev. p1.10 symbol description (* 44 tqfp package) symbol pin signal pin description 44 40 44* type op5 16 14 9 o multi-purpose output. general purpose output or one of the following functions can be selected for this output pin by programming the output port configuration register bit 5: - rxbrdy - receive ready signal (open drain output) -rxbfull - receive fifo full signal (open drain output) op6 29 26 24 o multi-purpose output. general purpose output or transmit a holding register empty interrupt ( -txardy open drain output). op7 17 15 10 o multi-purpose output. general purpose output or transmit b holding register empty interrupt ( -txbrdy open drain output). a1-a4 2,4, 1,3, 40,42, 6,7 5,6 44,1 i address select lines. to select internal registers. xtal1 36 32 30 i crystal input 1 or external clock input. a crystal can be connected to this pin and xtal2 pin to utilize the internal oscillator circuit. an external clock can be used to clock internal circuit and baud rate generator for custom transmis- sion rates. xtal2 37 33 31 o crystal input 2 or buffered clock output. see xtal1. -reset 38 34 32 i master reset. (active low) a low on this pin will reset all the outputs and internal registers. the transmitter output and the receiver input will be disabled during reset time. gnd 22 20 16,17 pwr signal and power ground. -int 24 21 18 o interrupt output (open drain active low) this pin goes low upon occurrence of one or more of eight maskable interrupt condi- tions (when enabled by the interrupt mask register) . cpu can read the interrupt status register to determine the interrupting condition(s). this output requires a pull-up resistor. ip0 8 7 2 i multi-purpose input or channel a clear-to-send (-ctsa active low). ip1 5 4 43 i multi-purpose input or channel b clear-to-send (-ctsb
xr68c92/192 6 rev. p1.10 symbol description (* 44 tqfp package) symbol pin signal pin description 44 40 44* type active low). ip2 40 36 34 i multi-purpose input or timer/counter external clock input. ip3 3 2 41 i multi-purpose input or channel a transmit external clock input. the transmit data is clocked on the falling edge of the clock. ip4 43 39 37 i multi-purpose input or channel a receive external clock input. the received data is clocked on the rising edge of the clock. ip5 42 38 36 i multi-purpose input or channel b transmit external clock input. the transmit data is clocked on the falling edge of the clock. -iack 41 37 35 i interrupt acknowledge (active low). indicating an interrupt acknowledge cycle. xr68c92/192 will place the interrupt vector on the data bus and will set -dtack low if it has a pending interrupt. -cs 39 35 33 i chip select (active low). a low at this pin enables the serial port / cpu data transfer operation. d0-d7 28,18 25,16 22,12 bi-directional data bus. eight bit, three state data bus to 27,19 24,17 21,13 i/o transfer information to or from the cpu. d0 is the least 26,20 23,18 20,14 significant bit of the data bus and the first serial data bit to be 25,21 22,19 19,15 received or transmitted. r/-w 9 8 3 i read/write strobe. when -cs is asserted, a high level on this pin transfers the contents of the xr68c92/192 data bus to the cpu, and a low level on this pin will transfer the contents of the cpu data bus to the addressed register. vcc 44 40 38,39 pwr power supply input. n.c. 1,12 11,23 no connection. 23,34
xr68c92/192 7 rev. p1.10 internal control logic the internal control logic receives operation commands from the central processing unit (cpu) and generates appropriate signals to the internal sections to control device operation. the internal control logic allows ac- cess to the registers within the xr68c92/192 and performs various commands by decoding the four reg- ister-select lines (a1 through a4). besides the four register-select lines, there are three other inputs to the internal control logic from the r/-w (read/write), which allows read and write transfers between the cpu and xr68c92/192 via the data bus buffer, -cs (chip-select), which is the xr68c92/192 chip-select, and -reset (reset), which initializes or resets. the -dtack (data transfer acknowledge) signal, which is asserted during read, write, or interrupt-acknowledge cycles, is the internal control logic output. the -dtack signal indi- cates to the cpu that data has been latched on a cpu write cycle or that valid data is present on the data bus during a cpu read cycle or -iack (interrupt-acknowl- edge) cycle. timing logic the timing logic consists of a crystal oscillator, a baud- rate generator (brg), a programmable 16-bit counter/timer (c/t), and four clock selectors. the crystal oscillator operates directly from a 3.6864 mhz crystal connected across the xtal1 and xtal2 in- puts or from an external clock of the appropriate frequency connected to xtal1. the xtal1 clock serves as the basic timing reference for the baud-rate generator, the c/t, and other internal circuits. the baud-rate generator operates from the xtal1 clock input and can generate 28 commonly used data communication baud rates ranging from 50 to 230.4k by producing internal clock outputs at 16 times the actual baud rate. the c/t can produce a 16x clock for other baud rates by counting down its programmed clock source. other baud rates can also be derived by connecting 16x or 1x clocks to certain input port pins that have alternate functions as receiver or transmitter clock inputs. four clock selectors allow the indepen- dent selection of any of these baud rates for each receiver and transmitter. users can program the 16 bit c/t within the xr68c92/192 to use one of several clock sources as its input. the output of the c/t is available to the internal clock selectors and can also be pro- grammed to appear at parallel output op3. in the timer mode, the c/t acts as a programmable divider and can generate a square-wave output at op3. in the counter mode, the c/t can be started and stopped under program control. when stopped, the cpu can read its contents. the counter counts down the number of pulses stored in the concatenation of the c/t upper register and c/t lower register and produces an inter- rupt. this is a system-oriented feature that can be used to record timeouts when implementing various applica- tion protocols. interrupt control logic the following registers are associated with the interrupt control logic: interrupt mask register (imr) interrupt status register (isr) auxiliary control register (acr) interrupt vector register (ivr) a single active-low interrupt output (-int) can notify the processor that any of eight internal events has occurred. these eight events are described in the discussion of the interrupt status register (isr). user can program the interrupt mask register (imr) to allow only certain conditions to cause -int to be asserted while the cpu can read the isr to determine all currently active interrupting conditions. when an ac- tive-low interrupt acknowledge signal (-iack) from the processor is asserted while the xr68c92/192 has an interrupt pending, the xr68c92/192 will place the contents of the interrupt vector register (ivr) on the data bus and assert the data transfer acknowledge signal (-dtack). if the xr68c92/192 has no pending interrupt, it ignores -iack cycles. in addition, users can program the interrupt outputs from the transmitters, the receivers, and the c/t to appear at the parallel output pins op3 through op7. data bus buffer the data bus buffer provides the interface between the external and internal data buses. it is controlled by the internal control logic to allow read and write data transfer operations to occur between the controlling cpu and xr68c92/192 via the eight parallel data lines (d0 through d7).
xr68c92/192 8 rev. p1.10 figure 1: crystal connection communication channels a and b each communication channel includes a full-duplex asynchronous receiver/transmitter (uart). the operat- ing frequency for each receiver and each transmitter can be selected independently from the baud-rate genera- tor, the c/t, or from an external clock. the transmitter accepts parallel data from the cpu, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, and outputs a composite serial stream of data on the tx output pin. the receiver accepts serial data on the rx pin, converts this serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), or break condition, and transfers an assembled character to the cpu during read opera- tions. input port the cpu reads the inputs to this 6-bit port (ip0 through ip5). high or low inputs to the input port result in the cpu reading a logic one or logic zero, respectively. each input port bit also has an alternate control function capability. the alternate functions can be enabled/ disabled on a bit-by-bit basis. 1 four change-of-state detectors are associated with inputs ip0, ip1, ip2, and ip3. if a high-to-low or low-to- high transition occurs on any of these inputs and the new level is stable for more than 25 to 50 microsec- onds (best-to-worst case times), the corresponding bit in the input port change register (ipcr) will be set. the sampling clock of the change detectors is the xtal1/ 96 tap of the baud-rate generator, which is 38.4khz if xtal1 is 3.6864mhz. a new input level must be sampled on two consecutive sample clocks to pro- duce a change detect. also, users can program the xr68c92/192 to allow a change of state to generate an interrupt to the cpu. the ipcr bits are cleared when the cpu reads the register. output port the 8 output port pins can either be used as a general- purpose output port or can be controlled using internal registers to generate signals representing various con- ditions. associated with the output port is an output port register (opr) that can be bit-wise programmed. a bit is set (logical 1) by performing a write operation at address 0xe with the data having that bit-location to be 1 (0 means no change). similarly, a bit is reset (logical 0) by performing a write operation at address 0xf with the data having that bit-location as 1 (0 means no change). however, it is to be noted that the outputs are complements of the data contained in the opr (eg., 0x05 in opr actually means 0xfa at the output pins). besides general-purpose outputs, the outputs can be individually assigned specific auxiliary functions serv- ing the communication channels. the assignment is accomplished by appropriately programming the channel a and b mode registers (mr0a, mr0b, mr1a, mr1b, mr2a, and mr2b) and the output port configuration register (opcr). note: the terms assertion and negation will be used extensively to avoid confusion when dealing with a mixture of active low and active high signals. the term assert or assertion indicates that a signal is active or true, independent of whether that level is repre- sented by a high or low voltage. the term negate or negation indicates that a signal is inactive or false. crystal input (xtal2) if a crystal is used, it is connected between xtal1 and this input, in which case a capacitor of approximately 15 to 33pf should be connected from this pin to ground. if an external cmos-level clock is used, this pin must be left open. -reset (reset) the xr68c92/192 can be reset by asserting the - x1 3.6863mhz c1 22 p f c2 33 p f xtal1 xtal2
xr68c92/192 9 rev. p1.10 reset signal or soft-reset by programming the appro- priate command register. a hardware reset (assertion of reset) clears the following registers: status registers a and b (sra and srb) interrupt mask register (imr) interrupt status register (isr) output port register (opr) output port configuration register (opcr) reset performs the following operations: initializes the interrupt vector register (ivr) to 0f hex places parallel outputs op0 through op7 in the high state places the counter/timer in timer mode places channels a and b in the inactive state with the transmitter serial-data outputs (txa and txb) in the mark (high) state. software resets are not as encompassing and are achieved by appropriately programming the channel a and/or b command registers. reset commands can be programmed through the command register to reset the receiver, transmitter, error status, or break- change interrupts for each channel chip-select (-cs) this active-low input signal, when low, enables data transfers between the cpu and xr68c92/192 on the data lines (d0 through d7). these data transfers are controlled by read/write (r/-w) and the register-select inputs (a1 through a4). when chip-select is high, the d0 through d7 data lines are placed in the high- impedance state. read/write (r/-w) when high, this input indicates a read cycle, when low, it indicates a write cycle. assertion of the chip-select input initiates a cycle. 2 data transfer ackowledge (-dtack) this three-state active low output is asserted in read, write, or interrupt-acknowledge (-iack) cycles to indi- cate the proper transfer of data between the cpu and xr68c92/192. if there is no pending interrupt on an - iack cycle, -dtack is not asserted. at the end of a transfer, it drives high momentarily, then is three-stated so that it can be wire-and-ed with other -dtack sources, like an open-drain signal. interupt ackowledge (-iack) this active-low input indicates an interrupt-acknowl- edge cycle. if there is an interrupt pending (-int as- serted) and this pin is asserted, the xr68c92/192 responds by placing the interrupt vector on the data bus and then asserting -dtack. if there is no interrupt pending (-int negated), the xr68c92/192 ignores this signal. 2 register-select bus (a1Ca4) the register-select bus lines during read/write opera- tions select the xr68c92/192 internal registers or ports. interupt request (-int) this active-low, open-drain output signals the cpu that one or more of the eight maskable interrupting conditions is true. channel a/b transmitter serial-data output (txa/txb) the independent transmitter serial-data outputs for channel a and b transmit the least-significant bit first. the output is held high (mark condition) when its associated transmitter is disabled, idle, or operating in the local loopback mode. (mark is high and space is low). data is shifted out from this pin on the falling edge of the programmed clock source. channel a/b receiver serial-data input (rxa/rxb) the independent receiver serial-data inputs for chan- nel a and b receive the least-significant bit first. data on these pins is sampled on the rising edge of the programmed clock source. input ports (ip0Cip5) the input ports can be used as general-purpose inputs. however, each pin also has an alternate function(s) described below: ip0 this input can be used as the channel a clear-to-send active-low input (-ctsa). a change-of-state detector (input port configuration register bit-4) is also associ- ated with this input. 2 ip1 this input can be used as the channel b clear-to-send active-low input (-ctsb). a change-of-state detector
xr68c92/192 10 rev. p1.10 (ipcr bit-5) is also associated with this input. ip2 this input can be used as the channel b receiver external clock input (rxbclk1), or the counter/timer external clock input. when this input functions as the external clock to the receiver, the received data is sampled on the rising edge of the clock. a change-of- state detector (ipcr bit-6) is also associated with this input. ip3 this input can serve as the channel a transmitter external clock input (txaclk1). when this input func- tions as the external clock to the transmitter, the transmitted data is clocked on the falling edge of the clock. a change-of-state detector (ipcr bit-7) is also associated with this input. ip4 this input can be used as the channel a receiver external clock input (rxaclk1). when this input func- tions as the external clock to the receiver, the received data is sampled on the rising edge of the clock. ip5 this input can serve as the channel b transmitter external clock (txbclk1). when this input is used as the external clock to the transmitter, the transmitted data is clocked on the falling edge of the clock. output ports (op0Cop7) the output ports can be used as general-purpose outputs however, each pin also has an alternate function(s), described below. op0 this output can function as the channel a transmitter active-low request-to-send output, or as the channel a receiver active-low request-to-send (-rtsa) output. this pin, if asserted by programming the corresponding bit in opcr, is used by the transmitter (mra2 bit-5 = 1) to indicate end of transmission by negating it. this is useful because, even when a command to disable the transmitter is sent before the data is fully transmitted, the transmitter sends all the data, negates op0 and then gets disabled. when used by the receiver (mra1 bit-7 = 1), this pin is automatically negated and reas- serted depending on the fifo space available. op1 this output is identical to op0 and is meant for channel b of the duart. 2 op2 this output can be programmed (bits 0 & 1 of opcr) to represent the channel a transmitter 1x-clock or 16x- clock output or the channel a receiver 1x-clock output. op3 this output can be used (when bits 2 & 3 of opcr are programmed) as the open-drain active-low counter- ready output, the open-drain timer output, the channel b transmitter 1x-clock output, or the channel b receiver 1x-clock output. op4 this output, when programmed using bit-4 of opcr, can serve as the channel a open-drain active-low receiver-ready or buffer-full interrupt outputs (rxardy/ rxafull). one of rxardy or rxafull can be se- lected using bit-6 of mra1. op5 this output, when programmed using bit-5 of opcr can be used as the channel b open-drain active-low receiver- ready or buffer-full interrupt outputs (rxrdyb/ rxbfull). one of rxbrdy or rxbfull can be se- lected using bit-6 of mrb1. op6 this output can function as the channel a open-drain active-low transmitter-ready interrupt output (txardy). op7 this output can serve as the channel b open-drain active-low transmitter-ready interrupt output (txbrdy). transmitter the channel a and b transmitters are enabled for data transmission through their respective command reg- isters. the xr68c92/192 signals the cpu that it is ready to accept a character by setting the transmitter- ready bit in the channel's status register. users can program this condition to generate an interrupt re- quest on the -int output, an interrupt request for channel as transmitter on parallel output op6, or for channel bs transmitter on parallel output op7. when a charac- ter is loaded into the transmit buffer, the above condition
xr68c92/192 11 rev. p1.10 for the respective channel is negated. data is trans- ferred from the transmit holding register to the transmit shift register when the shift register is idle or has completed transmission of the previous character. the transmitter ready conditions are then reasserted, pro- viding one full character time of buffering. characters cannot be loaded into the transmit buffer while the transmitter is disabled. the transmitter converts the parallel data from the cpu to a serial bit stream on the transmitter serial-data output pin. it automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. the least- significant bit is sent first. data is shifted out the transmit serial data output pin on the falling edge of the programmed clock source. after the transmission of the stop bits, and a new character is not available in the transmit holding register, the transmitter serial-data output remains high and the transmitter-empty bit in the status register (sra and srb) will be set to one. transmission resumes and the transmitter-empty bit is cleared when the cpu loads a new character into the transmit buffer. if the transmitter receives a disable command, it will continue operating until the character in the transmit shift register is completely sent out. other characters in the holding register are neither sent nor discarded, but will be sent when the transmitter is re-enabled. users can program the transmitter to auto- matically negate the request-to-send (rts) output (al- ternate function of op0 and op1) on completion of a message transmission. if the transmitter is pro- grammed to operate in this manner, the rts output must be manually asserted before each message is transmitted. if op0 (or op1) is programmed in auto- matic rts mode, the rts output will be automatically negated when the transmitter is disabled and the transmit-shift register and holding register are both empty. in automatic rts mode, a character in the holding register is not held back by a disable, but no more characters can be written to the holding register after the transmitter is disabled. if clear-to-send (cts) operation is enabled, the cts input (alternate function of ip0 or ip1) must be low in order for the character to be transmitted. if it goes high in the middle of a transmission, the character in the shift register is transmitted and tx then remains in the marking state until cts again goes low. the transmitter can also be forced to send a continuous low condition by issuing a send-break command. the state of cts is ignored by the transmitter when it is set to send break. a send break is deferred as long as the transmitter has characters to send, but if normal character transmis- sion is inhibited by cts, the send-break will proceed. the send-break must be terminated by a stop-break, disable, or reset before normal character transmission can resume. the transmitter can be reset through a software com- mand. if it is reset, operation ceases immediately and must be enabled through the command register before resuming operation. reset also discards any character in the holding register. receiver the channel a and b receivers are enabled for data reception through the respective channels command register. the channels receiver looks for the high-to- low (mark-to-space) transition of a start bit on the receiver serial-data input pin. if operating in 16x clock mode, the serial input data is re-sampled on the next 7 clocks. if the receiver serial data is sampled high, the start bit is invalid and the search for a valid start bit begins again. if receiver serial data is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity bit (if any) have been as- sembled and one stop bit has been detected. data on the receiver serial data input pin is sampled on the rising edge of the programmed clock source. during this process, the least-significant bit is re- ceived first. the data is then transferred to a receive holding register (rhr) and the receiver-ready bit in the status register (sra or srb) is set to one. this condition can be programmed to generate an interrupt request on the -int output, an interrupt request for channel a receiver on output pin( op4), or an interrupt request for channel b receiver on output pin (op5). if the character length is less than eight bits, the most significant unused bits in the receive holding register (rhr) are set to zero. if the stop bit is sampled as a 1, the receiver will immediately look for the next start bit. however, if the stop bit is sampled as a 0, either a framing error or a received break has occurred. if the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing
xr68c92/192 12 rev. p1.10 error, the damaged character is transferred to a holding register with the framing error flag set. if the receiver serial data remains low for one-half of the bit period after the stop bit was sampled, the receiver operates as if a new start bit transition has been detected. if the stop bit is 0 and the data and parity (if any) are also all zero, it is a break. a character consisting of all zeros will be loaded into a receive holding register (rhr) with the received-break bit (but not the framing error bit) set to one. the receiver serial-data input must return to a high condition for at least one-half bit time before a search for the next start bit begins. 3 the receiver can detect a break that starts in the middle of a character provided the break persists completely through the next character time or longer. when the break begins in the middle of a character, the receiver will place the damaged character in a holding register with the framing error bit set. then, provided the break persists through the next character time, the receiver will also place an all-zero character in the next holding register with the received-break bit set. the parity error, framing error, overrun error, and received-break conditions (if any) set error and break flags in the status register at the received character boundary and are valid only when the receiver-ready bit (rxrdy) in the status register is set. a first-in first- out (fifo) stack is used in each channels receive buffer logic and consists of 8 (16 for xr68c192) receive holding registers. the receiver buffer is composed of the fifo and a receive shift register connected to the receiver serial- data input. data is assembled in the shift register and loaded into the top most empty fifo receive holding register position. the receiver-ready bit in the status register (sra or srb) is set whenever one or more characters are available to be read. a read of the receiver buffer produces an output of data from the top of the fifo stack. after the read cycle, the data at the top of the fifo stack and its associated status bits are popped and new data can be added at the bottom of the stack by the receive shift register. the fifo-full status bit is set if all eight stack positions are filled with data. either the receiver-ready or the fifo-full status bits can be selected to cause an interrupt. in addition to the data byte, three status bits (parity error, framing error, and received break) are appended to each data character in the fifo (overrun is not). by program- ming the error-mode control bit in the mode register, status can be provided for character or block modes. in the character mode, the status register (sra or srb) is updated on a character-by-character basis and applies only to the character at the top of the fifo. thus, the status must be read before the character is read. reading the character pops it and its error flags off the fifo. in the block mode, the status provided in the status register for the parity error, framing error, and received-break conditions are the logical or of these respective bits, for all characters coming to the top of the fifo stack since the last reset error com- mand was issued. that is, starting at the last reset-error command, a continuous logical-or function of corre- sponding status bits is produced in the status register as each character comes to the top of the fifo stack. the block mode is useful in applications requiring the exchange of blocks of information where the software overhead of checking each characters error flags cannot be tolerated. in this mode, entire messages can be received and only one data integrity check is performed at the end of each message. although data reception in this manner has speed advantages, there are also disadvantages. because each character is not individually checked for error conditions by the software, if an error occurs within a message the error will not be recognized until the final check is per- formed. also, there is no indication of which character(s) is in error within the message. 3 reading the status register (sr) does not affect the fifo. the fifo is popped only when the receive buffer is read. if all 8/16 of the fifos receive holding registers are full when a new character is received, that character is held in the receive shift register until a fifo position is available. if an additional character is re- ceived while this state exists, the contents of the fifo are not affected, but the character previously in the shift register is lost and the overrun-error status bit will be set upon receipt of the start bit of the new overrunning character. to support flow control, a receiver can automatically negate and reassert the request-to-send (rts) output (alternate function of output ports op0 and op1). the request-to-send output will automatically be negated by the receiver when a valid start bit is received and the fifo stack is full. when a fifo position becomes available, the request-to-send output will be reasserted
xr68c92/192 13 rev. p1.10 automatically by the receiver. connecting the request- to-send output to the clear-to-send (cts) input of a transmitting device, prevents overrun errors in the re- ceiver. the rts output must be manually asserted the first time. thereafter, the receiver will control the rts output. if the fifo stack contains characters and the receiver is then disabled, the characters in the stack can still be read but no additional characters can be received until the receiver is again enabled. if the receiver is dis- abled while receiving a character, or while there is a character in the shift register waiting for a fifo opening, these characters are lost. if the receiver is reset, the fifo stack and all of the receiver status bits, the corresponding output ports, and the interrupt request are reset. no additional characters can be received until the receiver is again enabled. loopback modes besides the normal operation mode in which the receiver and transmitter operate independently, each xr68c92/192 channel can be configured to operate in various looping modes that are useful for local and remote system diagnostic functions. 3 automatic echo mode in this mode, the channel automatically retransmits the received data on a bit-by-bit basis. the local cpu- to-receiver communication continues normally but the cpu-to-transmitter link is disabled. local loopback mode in this mode, the transmitter output is internally con- nected to the receiver input. the external tx pin is held in the mark (high) state in this mode. this mode is useful for testing the operation of a local xr68c92/ 192 channel. by sending data to the transmitter and checking that the data assembled by the receiver is the same data that was sent, proper channel operation can be ensured. in this mode the cpu-to-transmitter and cpu-to-receiver communications continue nor- mally. remote loopback mode in this mode, the channel automatically retransmits the received data on a bit-by-bit basis. the local cpu-to- receiver and cpu-to-transmitter links are disabled. this mode is useful in testing the receiver and transmitter operation of a remote channel. this mode requires the remote channel receiver to be enabled. multidrop mode users can program the channel to operate in a wake-up mode for multidrop applications. this mode is selected by setting bits 3 & 4 in mode register 1 (mr1). in this mode of operation, a master station channel, connected to several slave stations (a maximum of 256 unique slave stations), transmits an address character fol- lowed by a block of data characters targeted for one or more of the slave stations. in this mode, the channel receivers within the slave stations are disabled, but they continuously monitor the data stream sent out from the master station. when the slave stations channel receiv- ers detect any address character in the data stream, each receiver notifies its respective cpu by setting receiver ready (rxrdy) and generating an interrupt, if programmed to do so. each slave station cpu then compares the received address to its station address and enables its receiver if it wants to receive the subsequent data from the master station. slave stations that are not addressed continue moni- toring the data stream for the next address character. an address character flags the end of one block of data and the start of another. after receiving a block of data, the slave stations cpu may disable the channel receiver and re-initiate the process. a transmitted character from the master station consists of a start bit, the programmed number of data bits, an address/ data (a/d) bit flag, and the programmed number of stop bits. the address/data bit identifies to the slave stations channel whether the character should be interpreted as an address character or a data charac- ter. the character is interpreted as an address charac- ter if the a/d bit is set to a one or interpreted as a data character if it is set to a zero. the polarity of the transmitted address/data bit is selected by program- ming bit two in mode register 1 (mr1) to a '1' for an address character and to a '0' for data characters. users should program the mode register prior to loading the corresponding data or address characters into the transmit buffer. 3 in the multidrop mode, the receiver continuously monitors the received data stream regardless of whether it is enabled or disabled. if the receiver is disabled, it sets the receiver ready status bit and loads the character into the fifo receive holding register stack provided the received address/data bit is a one
xr68c92/192 14 rev. p1.10 (address tag). the received character is discarded if the received address/data bit is a zero (data tag). if the receiver is enabled, all received characters are trans- ferred to the cpu by way of the receive holding register stack during read operations. in either case, the data bits are loaded into the data portion of the fifo stack while the address/data bit is loaded into the status portion of the fifo stack normally used for parity error (status register bit-5). framing error, overrun error, and break-detection operate normally regardless of whether the receiver is enabled or disabled. the address/data bit takes the place of the parity bit and parity is neither calculated nor checked for characters in this mode. counter/timer the 16-bit counter/timer (c/t) can operate in a counter mode or a timer mode. in either mode, users can program the c/t input (clock source) to come from several sources and program the c/t output to appear at output port pin op3. the value (pre-load value) stored in the concatenation of the c/t upper register (ctur) and the c/t lower register (ctlr) can be from 0x0001 through 0xffff and can be changed at any time. in counter mode, the cpu can start and stop the c/t. this mode allows the c/t to function as a system stopwatch, a real-time single interrupt generator, or a device watch- dog. in timer mode, the c/t runs continuously, the cpu cannot start or stop it. instead, the cpu only resets the c/t interrupt. this mode allows the c/t to be used as a programmable clock source for channels a and b, or periodic interrupt generator. at power-up and after reset, the c/t operates in timer mode. counter mode in counter mode, the c/t counts down from the pre-load value using the programmed counter clock source. the counter clock source can be the channel a transmitter clock, the channel b transmitter clock, the external clock on the xtal1 pin divided by sixteen, or an external clock on the input port pin ip2. the cpu can start and stop the counter, and can read the count value (cur:clr) if the counter is stopped. when a read at the start counter command address is performed, the counter is initialized to the pre-load value and begins a countdown sequence. when the counter counts from 0x0001 to 0x0000 (terminal count), the c/t-ready bit in the interrupt status register (isr bit-3) is set. 3 users can program the counter to generate an interrupt request for this condition on the -int output or output pin op3. after 0x0000 the counter counts to 0xffff, and continues counting down from there. if the cpu changes the pre-load value, the counter will not recog- nize the new value until it receives the next start counter command (and is reinitialized). when a read at the stop counter command address is performed, the counter stops the countdown sequence and clears isr bit-3. the count value should only be read while the counter is stopped because only one of the count registers (either cur or clr) can be read at a time. if the counter is running, a decrement of clr that requires a borrow from the cur could take place between the two reads. timer mode in timer mode, the c/t generates a square-wave output derived from the programmed timer input (clock source). the timer clock source can be the external clock on the xtal1 input pin divided by one or sixteen, or it can be an external input on input port pin ip2 divided by one or sixteen. the square wave generated by the timer has a period of 2x (pre-load value) x (period of clock source), is available as a clock source for both communications channels and can be programmed to appear on output pin op3. the timer runs continuously, the cpu cannot stop it. because the timer cannot be stopped, the count value (cur:clr) should not be read. when a read at the start counter command address is performed, the timer terminates the current countdown sequence, sets its output to 1 (appears un-inverted at op3), is initialized to the pre-load value, and begins a new countdown sequence. when the counter counts from 0x0001 (terminal count), it inverts its output, is re- initialized to the pre-load value and repeats the count- down sequence. after reaching terminal count a second time, the timer sets the c/t-ready bit in the interrupt status register (isr bit-3), inverts its output, is re-initialized again, and begins a new countdown sequence. users can program the timer to generate an interrupt request for this condition (every second countdown cycle) on the - int output. if the cpu changes the pre-load value, the timer will not recognize the new value until either (a) it reaches the next terminal count and is reinitialized automatically, or (b) it is forced to re-initialize by a start command. when a read at the stop counter command address is performed, the timer clears isr bit-3 but does not stop. because in timer mode the c/t runs continuously, it should be completely configured (pre-
xr68c92/192 15 rev. p1.10 load value loaded and start counter command issued) before programming the timer output to appear on op3. use caution if the contents of a register are changed during receiver/ transmitter operation as certain changes can produce undesired results. for example, changing the number of bits per character while the transmitter is active can transmit an incorrect charac- ter. the contents of the clock-select register (csr) and acr bit-7 should only be changed after the receiver(s) and transmitter(s) have been issued software rx and tx reset commands. most bits of the mode registers should not be changed during receiver/transmitter op- eration, except that in multidrop parity mode, the address/data parity type bit can be changed at any time. 44 similarly, certain changes to the auxiliary control regis- ter (acr bits 4-6) should only be made while the counter/timer (c/t) is not used. channel a mode regis- ters mr1a and mr2a are accessed via an auxiliary pointer. the pointer is set to mode register one (mr1a) by reset or by issuing a reset pointer command via the channel a command register. any read or write of the mode register switches the pointer to mode register two (mr2a). all subsequent accesses will address mr2a unless the pointer is reset to mr1a as described above. the channel b mode registers mr1b and mr2b programming and register descriptions a3 a2 a1 a0 read w rite 0000 mode register a (mr1a, mr2a) mode register a (mr1a, mr2a) 0001 status register a (sra) clock-select register a (csra) 0010 reserved command register a (cra) 0011 receiver buffer a (rba) transmitter buffer a (tba) 0100 input port change register (ipcr) auxiliary control register (acr) 0101 interrupt status register (isr) interrupt mask register (imr) 0110 counter/timer msb (cur) counter/ timer upper register (ctur) 0111 counter/timer lsb(clr) counter/ timer lower register (ctlr) 1000 mode register b (mr1b, mr2b) mode register b (mr1b, mr2b) 1001 status register b (srb) clock-select register b (csrb) 1010 reserved command register b (crb) 1011 receiver buffer b (rbb) transmitter buffer b (tbb) 1100 interrupt-vector register (ivr) interrupt-vector register (ivr) 1101 input port (ip) output port configuration register (opcr) 1110 start-counter command set output port register (opr) bits 1111 stop-counter command reset output port register (opr) bits are accessed by an identical pointer independent of the channel a pointer. mode, command, clock-select, and status registers are duplicated for each channel to allow independent operation and control (except that both channels are restricted to baud rates that are in the same set).
xr68c92/192 16 rev. p1.10 a3 a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] 0000 mra0 [00] watch rx tx tx not baud not baud 1000 mrb0[00] dog timer trigger trigger trigger used rate used rate level level level ext. 2 ext. 1 0000 mra1[00] rx rx error parity parity parity word word 1000 mrb1[00] rts trigger mode mode mode type length length control level 0000 mra2[00] channel channel tx tx stop stop stop stop 1000 mrb2[00] mode mode rts cts bit bit bit bit select select control control length length length length 0001 csra[00] rx rx rx rx tx tx tx tx 1001 csrb[00] clock clock clock clock clock clock clock clock 0001 sra[00] received framing parity overrun tx tx rx rx 1001 srb[00] break error error error empty ready fifo ready full 0010 cra[00] misc. misc. misc. misc. tx tx rx rx 1000 crb[00] command command command command disable enable disable enable 0011 rhra[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1011 rhrb[xx] 0011 thra[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1011 thrb[xx] 0100 acr[00] baud c/t c/t c/t delta delta delta delta rate mode mode mode ip3 ip2 ip1 ip0 set int int int int select 0100 ipcr[00] d elta delta delta delta ip3 ip2 ip1 ip0 ip3 ip2 ip1 ip0 input input input input 0101 isr[00] input d elta rxb txb c/t delta rxa txa port break b ready/ ready ready break a ready/ ready change fifo full fifo full 0101 imr[00] input d elta rxb txb c/t delta rxa txa port break b ready/ ready ready break a ready/ rdy change fifo full fifo full 0110 ctu[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 0111 ctl[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1101 ipr[xx] not not ip5 ip4 ip3 ip2 ip1 ip0 used used 1101 opcr[00] op7 op6 op5 op4 op3 op3 op2 op2 1110 stcc[xx] xxxxxxxx 1110 sopb[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1111 spcc[xx] xxxxxxxx 1111 ropb bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr68c92/192 17 rev. p1.10 mr0 a/b mode register 0. this register is accessed only when command is applied via cr a/b register. after reading or writing to mr0 a/b register, the pointer will point to mr1 a/b register. mr0 a/b bit-0. extended baud rate table selection. 0 = normal baud rate tables 1 = extend baud rate tables (1) mr0 a/b bit-1. 0 = regular operation 1 = factory test mode mr0 a/b bit-2. extended baud rate table selection. 0 = normal baud rate tables 1 = extend baud rate tables (2) mr0 a/b bit-3. not used. mr0 a/b bits 5-4 transmit trigger levels: mr0 mr0 bit-5 bit-4 xr68c92 0 0 8 fifo locations empty 0 1 4 fifo locations empty 1 0 6 fifo locations empty 1 1 1 fifo location empty mr0 mr0 bit-5 bit-4 xr68c192 0 0 16 fifo locations empty 0 1 6 fifo locations empty 1 0 12 fifo locations empty 1 1 1 fifo location empty mr0 a/b bit-6. receive trigger levels: mr0 mr1 bit-6 bit-6 xr68c92 0 0 1 byte in fifo 0 1 3 bytes in fifo 1 0 6 bytes in fifo 1 1 8 bytes in fifo mr0 mr1 bit-6 bit-6 xr68c192 0 0 1 byte in fifo 0 1 6 bytes in fifo 1 0 12 bytes in fifo 1 1 16 bytes in fifo mr0 a/b bit-7. receive time-out (watch dog timer). 0 = disabled 1 = enabled mr1 a/b mode register 1. mr1 a/b are accessed after reset or by command applied via cr a/b register. after read- ing or writing to mr1 a/b register, the pointer will point to mr2 a/b register. mr1 a/b bits 1-0. character length 0 0 = 5 0 1 = 6 1 0 = 7 1 1 = 8 mr1 a/b bit-2. parity type 0 = even parity 1 = odd parity mr1 a/b bit 4-3. parity mode 00 = with parity 01 = force parity 10 = no parity 11 = multidrop mode mr1 a/b bit-5. data error mode 0 = single character mode 1 = block (fifo) mode mr1 a/b bit-6. receive interrupt mode select. 0 = single character mode (rxrdy) 1 = fifo full mode (ffull) mr1 a/b bit-7. auto rts flow control.
xr68c92/192 18 rev. p1.10 0 = normal. no rts control function. 1 = auto rts control function mr2 a/b mode register 2. this register is accessed after any read or write operation to mr1 a/b register is performed. access to mr2 a/b does not change the pointer. mr2 a/b bits 3-0. stop bit length 0000 = 0.563 0001 = 0.625 0010 = 0.668 0011 = 0.750 0100 = 0.813 0101 = 0.875 0110 = 0.938 0111 = 1.000 1000 = 1.563 1001 = 1.625 1010 = 1.668 1011 = 1.750 1100 = 1.813 1101 = 1.875 1110 = 1.938 1111 = 2.000 mr2 a/b bit-4. auto cts flow control 0 = normal. no cts control function 1 = auto cts control function. mr2 a/b bit-5. transmit rts control. 0 = normal. no control function 1 = transmit rts function enable. mr2 a/b bit 7-6. channel mode. 0 0 = normal 0 1 = automatic echo 1 0 = local loopback 1 1 = remote loopback clock select register-csr a/b transmit / receive baud rates can be selected via this register. csr a/b bits 3-0. transmit clock select (see baud rate table) csr a/b bits 7-4. receive clock select (see baud rate table) miscellaneous command register cr a/b cr a/b register is used to supply commands to a/b channels. multiple commands can be specified in a single write to cr a/b as long as commands are non- conflicting. cr a/b bits 1-0. receiver commands 0 0 = no action, stays in present mode 0 1 = receiver enabled 1 0 = receiver disabled 1 1 = not used cr a/b bits 3-2. transmitter commands 0 0 = no action, stays in present mode 0 1 = transmitter enabled 1 0 = transmitter disabled 1 1 = not used cr a/b bits 7-4. miscellaneous commands. 0 0 0 0 = no command. 0 0 0 1 = reset mr pointer to mr1. 0 0 1 0 = reset receiver. receiver is disabled and fifo is flushed. 0 0 1 1 = reset transmitter. transmitter is disabled and fifo is flushed. 0 1 0 0 = reset error status. clears channel a/b, break, parity, and over-run error bits in the status register. 0 1 0 1 = reset channels break-change interrupt. clears channel a/b break detect change bit in the interrupt status register (isr bit-2). 0 1 1 0 = start break. forces the transmitter output to go low and stay low. if transmitter is empty the start of the break condition will be de- layed up to two bit times. if transmitter is active, the break begins when transmission of the character is completed. all contents of the fifo has to be transmitted before break signal takes place. transmitter must to be enabled for this command to be accepted. 0 1 1 1 = stop break. transmit output will go high within two bit times. 1 0 0 0 = set -rts output to low. 1 0 0 1 = reset -rts output to high.
xr68c92/192 19 rev. p1.10 1 01 0 = set timeout mode on. the receiver in this channel will restart the c/t as each receive character is transferred from the shift register to the receive fifo. the c/t is placed in the counter mode, the start/stop counter commands are disabled, the counter is stopped, and the counter ready bit, isr bit- 3 is reset. (see also watchdog timer de- scription in the receiver section.) 1 0 1 1 = set mr pointer to mr0. 1 1 0 0 = disable timeout mode. this command re- turns control of the c/t to the regular start/ stop counter commands. it does not stop the counter, or clear any pending interrupts. after disabling the timeout mode, a stop counter command should be issued to force a reset of the isr bit-3. 1 1 0 1 = not used. 1 1 1 0 = power down mode on. in this mode, the duart oscillator is stopped and all func- tions requiring this clock are suspended. the execution of commands other than disable power down mode (1111) requires a xtal1. while in the power down mode, do not issue any commands to the cr a/b except the disable power down mode command. the contents of all registers will be saved while in this mode. it is recommended that the trans- mitter and receiver be disabled prior to plac- ing the duart into power down mode. this command is in cra only. 1 1 1 1 = disable power down mode. this command restarts the oscillator. after invoking this command, wait for the oscillator to start up before writing further commands to the cr a/ b. this command is in cra only. for maxi- mum power reduction input pins should be at gnd or vcc. status register (sra/srb) sr a/b bit-0. receive ready. this bit indicates that one or more character(s) has been received and is waiting in the fifo for the cpu to read it. it is set when the first character is transferred baud rate table (based on a 3.6864mhz clock) mr0 bits mr0 bit-0=1 mr0 bit-2=1 2,0=0 (extended 1) (extended 2) csr set-1 set-2 set-1 set-2 set-1 set-2 a/b acr acr acr acr acr acr bit-7=0 bit-7=1 bit-7=0 bit-7=1 bit-7=0 bit-7=1 0000 50 75 300 450 4800 7200 0001 110 110 110 110 680 680 0010 134.5 134.5 134.5 134.5 1076 1076 0011 200 150 1200 900 19.2k 14.4k 0100 300 300 1800 1800 28.8k 28.8k 0101 600 600 3600 3600 57.6k 57.6k 0110 1200 1200 7200 7200 115.2k 115.2k 0111 1050 2000 1050 2000 1050 2000 1000 2400 2400 14.4k 14.4k 57.6k 57.6k 1001 4800 4800 28.8k 28.8k 4800 4800 1010 7200 1800 7200 1800 57.6k 14.4k 1011 9600 9600 57.6k 57.6k 9600 9600 1100 38.4k 19.2k 230.4k 115.2k 38.4k 19.2k 1101 timer timer timer timer timer timer 1110 ip4-16x ip4-16x ip4-16x ip4-16x ip4-16x ip4-16x 1111 ip4-1x ip4-1x ip4-1x ip4-1x ip4-1x ip4-1x
xr68c92/192 20 rev. p1.10 from the receive shift register to the empty fifo, and cleared when the cpu reads the receiver buffer, if there are no more characters in the fifo after the read. sr a/b bit-1. receive fifo full. this bit is set when a character is transferred from the receive shift register to the receiver fifo and the transfer fills the fifo. all eight fifo holding register positions are occupied. it is cleared when the cpu reads the receiver buffer, unless a ninth character is in the receive shift register waiting for an empty fifo slot. sr a/b bit-2. transmit ready. this bit (when set) indicates that the transmit holding register is empty and ready to be loaded with a charac- ter. transmitter ready is set when the character is transferred to the transmit shift register. this bit is cleared when the cpu loads the transmit holding register, or when the transmitter is disabled. sr a/b bit-3. transmit empty. this bit will be set when the channel a/b transmitter under-runs (empty). both the transmit holding register and the transmit shift register are empty. it is set after transmission of the last stop bit of a character if no character is in the transmit holding register awaiting transmission. it is cleared when the cpu loads the transmit holding register or when the transmitter is disabled. sr a/b bit-4. overrun error. this bit (when set) indicates one or more characters in the received data stream have been lost. it becomes set on receipt of a valid start bit when the fifo is full and a character is already in the receive shift register waiting for an empty fifo position. when this occurs, the character in the receive shift register (and its break detect, parity error, and framing error status, if any) is lost. a reset error status command clears this bit. sr a/b bit-5. parity error. this bit becomes set when the with parity or force parity mode is programmed by mode register one and the corresponding character in the fifo is received with incorrect parity. in the multidrop mode, the parity error bit position stores the received address/data bit. this bit is valid only when the rxrdy bit is set (sr a/b bit-0 = 1). sr a/b bit-6. framing error. this bit (when set) indicates that a stop bit was not detected when the corresponding data character in the fifo was received. the stop bit check is made in the middle of the first stop bit position. this bit is valid only when the rxrdy bit is set (sr a/b bit-0 = 1). framing error and break are exclusive: at least one data bit and/ or the parity bit must have been a 1 to signal a framing error. after a framing error, the receiver does not wait for the line to return to the marking state (high), if the line remains low for 1/2 a bit time after the stop bit sample (that is, the nominal end of the first stop bit), the receiver treats it as the beginning of a new start bit. sr a/b bit-7. received break. this bit indicates an all-zero character of the pro- grammed length has been received without a stop bit. this bit is valid only when the rxrdy bit is set (sr a/ b bit-0 = 1). only a single fifo position is occupied when a break is received, additional entries to the fifo are inhibited until the channel a/b receiver serial data input line returns to the marking state. the break- detect circuitry can detect a break that starts in the middle of a received character, however, the break condition must persist completely through the end of the current character and the next character time to be recognized. output port configuration register (opcr) this register selects following options for output ports. 4 alternate functions of op1 and op0 are con- trolled by the mode registers, not the opcr. mr1a bit- 7 and mr2a bit-5 control op0, mr1b bit-7 and mr2b bit-5 control op1. op2 output select 0 0 = the complement of opr 0 1 = txaclk16-transmit a 16x clock 1 0 = txaclk1-transmit a 1x clock 1 1 = rxaclk1- receive a 1x clock
xr68c92/192 21 rev. p1.10 op3 output select 0 0 = the complement of opr 0 1 = c/t output 1 1 0 = txbclk1-transmit b 1x clock 1 1 = rxbclk1- receive b 1x clock if op3 is to be used for the timer output, users should program the counter/timer for timer mode (acr bit-6 = 1), initialize the counter/timer pre-load registers (ctur and ctlr), and the start counter command issued before setting opcr bits 3-2 = 01. op4 output select 0 = the complement of opr 1 = -rxardy/-rxafull op5 output select 0 = the complement of opr 1 = -rxbrdy/-rxbfull op6 output select 0 = the complement of opr 1 = -txardy op7 output select 0 = the complement of opr 1 = -txbrdy output port register (opr) all bits, unless programmed for alternate function, can be set high or low individually: 0 = sets output port high 1 = sets output port low for example, setting bit-4 to 1 will set op4 low. auxiliary control register (acr) acr bits 3-0. this field selects which bits of the input port change register (ipcr) cause the input change bit in the interrupt status register (isr bit-7) to be set. 0 = disabled 1 = enabled acr bits 6-4. counter/timer mode and clock source. should only be altered while the c/t is not in use (stopped if in counter mode, output and/or interrupt masked if in timer mode). mode clock source 0 0 0 counter external (ip2) 0 0 1 counter txaclk1-transmit a 1x clock 0 1 0 counter txbclk1-transmit b 1x clock 0 1 1 counter crystal or external clock (xtal1/clk) divided by 16 1 0 0 timer external (ip2) 1 0 1 timer external (ip2) divided by 16 1 1 0 timer crystal or external clock (xtal1/clk) 1 1 1 timer crystal or external clock (xtal1/clk) divided by 16 acr bit-7 baud rate table select. should only be changed after both channels have been reset and are disabled. 0 = set 1 1 = set 2 input port change register (ipcr) ip level bits 3-0. 0 = low 1 = high ip delta bits 7-4. 0 = no 1 = yes interrupt status register (isr) this register provides the status of all potential interrupt sources. the contents of this register are logically and-ed with the contents of the interrupt mask regis- ter, and the results are "nor"-ed to produce the -int output. all active interrupt sources are visible by reading the isr, regardless of the contents of the interrupt mask register. reading the isr has no effect on any interrupt source. each active interrupt source must be cleared in a source-specific fashion to clear the isr. all interrupt sources are cleared when the xr68c92/192 is reset. 4 isr bit-0. transmit ready a. this bit is the channel a equivalent of isr bit-4. isr bit-1. receive ready a or fifo full. the function of this bit is
xr68c92/192 22 rev. p1.10 programmed by mr1a bit-6. if programmed as receiver ready, it is a copy of the sra bit-0. if programmed as fifo full, it is a copy of the sra bit-1. isr bit-2. channel a change in break. this bit (when set) indi- cates that the channel a receiver has detected the beginning or the end of a break condition. it is reset when the cpu issues a channel a reset break change interrupt command. isr bit-3. counter/timer ready. in counter mode, this bit is set when the counter reaches terminal count. in timer mode, this bit is set each time the timer output switches from low to high. isr bit-4. transmit ready b. this bit is a duplicate of the channel b status register transmitter ready bit. isr bit-5. receive ready b or fifo full. the function of this bit is programmed by mr1b bit-6. if programmed as receiver ready, it is a copy of the srb bit-0. if programmed as fifo full, it is a copy of the srb bit- 1. isr bit-6. channel b change in break. this bit (when set) indicates that the channel b receiver has detected the beginning or the end of a break condition. it is reset when the cpu issues a channel b reset break change interrupt com- mand. isr bit-7. input port change status. this bit is a 1 when a change of state has occurred at the ip0, ip1, ip2, or ip3 inputs and that event has been enabled to cause an interrupt by the programming of acr bits 3-0. this bit is cleared when the cpu reads the input port change register. interrupt mask register (imr) this register selects which bits in the interrupt status register can cause an interrupt output. if a bit in the interrupt status register is a 1 and the corresponding bit in this register is also a 1, the -int output will be asserted. if the corresponding bit in this register is a zero, the state of the bit in the interrupt status register has no effect on the -int output. note that the interrupt mask register does not mask the programmable inter- rupt outputs op7 through op3 or the value read from the interrupt status register. imr bit-0. 0 = normal, no interrupt. 1 = enable channel a transmit ready interrupt. imr bit-1. 0 = normal, no interrupt. 1 = enable channel a receive ready or fifo full interrupt. rxrdy or fifo-full is selected via mr1a bit-6. imr bit-2. 0 = normal, no interrupt. 1 = enable channel a received break signal interrupt. imr bit-3. 0 = normal, no interrupt. 1 = enable timer/counter interrupt. imr bit-4. 0 = normal, no interrupt. 1 = enable channel b transmit ready interrupt. imr bit-5. 0 = normal, no interrupt. 1 = enable channel b receive ready or fifo full interrupt. rxrdy or fifo-full is selected via mr1b bit- 6. imr bit-6. 0 = normal, no interrupt. 1 = enable channel b received break signal interrupt. imr bit-7. 0 = normal, no interrupt. 1 = enable input port state change interrupt. input port register state of the input ports (ip0-ip6) can be read via this register. ipr bit 0-6. 0 = inputs are in low state. 1 = inputs are in high state.
xr68c92/192 23 rev. p1.10 ipr bit-7. not used and set to 0. counter register (cur and clr) the count upper register (cur) and count lower register (clr) hold the most-significant byte and the least-significant byte, respectively, of the current counter value. these registers should only be read when the c/t is in counter mode and the counter is stopped. start counter / timer register reading from this register will start timer counter function. returned data values should be ignored. stop counter timer register reading from this register will issue a stop command to timer counter function. returned data values should be ignored. set output port register output ports (op0-op7) can be set to low by writing a 1 to each individual bits. outputs will change state only when opcr register bits are assigned to general purpose output pins. when output is set to low, it can not change state to high unless reset output port command is issued. sopr bit 0-7. 0 = no change. 1 = set output port to low. reset output port bits register each output port bit can be changed to high state by writing a 1 to each individual bit. sopr bit 0-7. 0 = no change. 1 = reset output port to high. 4 interrupt vector register (ivr) this register contains the interrupt vector. when the xr68c92 responds to a valid interrupt acknowledge (- iack) cycle, the contents of this register are placed on the data bus. at reset, this register will contain 0f hex, which is the m68000 exception vector assignment for un-initialized interrupt vectors.
xr68c92/192 24 rev. p1.10 ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 1w, t 2w clock pulse duration 17 17 ns t 3w oscillator/clock frequency 8 24 mhz t as address valid to -cs low 0 0 ns t ah -cs high to address invalid 0 0 ns t rws r/-w setup time to -cs low 0 0 ns t rwh r/-w hold time from -cs high 0 0 ns t dd -cs low to data valid (read) 51 32 ns t ds data valid to -cs high (write) 20 10 ns t dh -cs high to data invalid (write) 1 1 ns t df -cs high to data hi-z (read) 30 20 ns t akl -cs low to -dack low 70 42 ns t akh -cs high to -dack high 45 27 ns t akt -cs high to -dack hi-z 70 43 ns t csl -cs low pulse width 100 70 ns t csh -cs high pulse width 100 70 ns t 9s port input setup time 0 0 ns t 9h port input hold time 0 0 ns t 10d delay from r/-w to output 110 110 ns t 11d delay to reset interrupt from r/-w 100 100 ns t r reset pulse width 2 2 clks n baud rate divisor 1 2 16 -1 1 2 16 -1 clks symbol parameter limits limits units conditions 3.3 5.0 min max min max
xr68c92/192 25 rev. p1.10 absolute maximum ratings supply range 7 volts voltage at any pin gnd - 0.3 v to vcc +0.3 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c package dissipation 500 mw dc electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. symbol parameter limits limits units conditions 3.3 5.0 min max min max v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low level -0.3 0.8 -0.5 0.8 v v ih input high level 2.0 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 5 ma v ol output low level on all outputs 0.4 v i ol = 4 ma v oh output high level 2.4 v i oh = -5 ma v oh output high level 2.0 v i oh = -1 ma i il input leakage 10 10 m a i cl clock leakage 10 10 m a i cc avg power supply current 3 6 ma xr68c92 i sb avg stand by supply current 100 150 m a typ.@25 o c5070 m a xr68c192 i sb avg stand by supply current 200 300 m a typ.@25 o c 100 140 m a c p input capacitance 5 5 pf
xr68c92/192 26 rev. p1.10 figure 2: bus timing (read/write cycle) read cycle timing write cycle timing a4-a1 -cs d7-d0 r/-w -dack t as t ah t rws t rwh t dd t akh t akl t akt a4-a1 -cs d7-d0 r/-w -dack t as t ah t rws t rwh t akh t akl t csl t csh t csl t csh valid d ata t dh t ds t akt t df
xr68c92/192 27 rev. p1.10 figure 3: receive timing figure 4: transmit timing xr6892-rx d1 d2 d8 d9 d10 d11 d12 d13 rx rx enable -rxrdy -ffull -rxrdy/ -ffull -cs overrun error -rts status data (d1) status data (d2) status data (d3) status data (d10) d11 will be lost due to overrun reset by command d12, d13 will be lost due to rx disable xr6892-tx d1 d2 d3 d4 break d5 tx tx enable -txrdy r/-w -cts -rts
xr68c92/192 28 rev. p1.10 figure 5: input port timing figure 6: output port timing t9s t9h ip6-ip0 xr6892-ip -cs t10d op7-op0 xr6892-op r/-w old data new data exclk xr92-ck t1w t2w t3w figure 7: interrupt timing figure 8: external clock timing t11d -cs xr6892-nt r/-w -int t11d
xr68c92/192 29 rev. p1.10 40 1 21 20 d e a 1 e 1 e a l seating plane a 2 a b 1 b c e b e a 40 lead plastic dual-in-line (600 mil pdip) rev. 1.00 millimeters symbol min max min max a 0.16 0.25 4.06 6.35 a1 0.015 0.07 0.38 1.78 a2 0.125 0.195 3.18 4.95 b 0.014 0.024 0.36 0.56 b1 0.03 0.07 0.76 1.78 c 0.008 0.014 0.2 0.38 d 1.98 2.095 50.29 53.21 e 0.6 0.625 15.24 15.88 e1 0.485 0.58 12.32 14.73 e ea eb 0.6 0.7 15.24 17.78 l 0.115 0.2 2.92 5.08 a 0 15 0 15 inches 0.100 bsc 0.600 bsc 2.54 bsc 15.24 bsc note: the control dimension is the inch column
xr68c92/192 30 rev. p1.10 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1 symbol min max min max a 0.165 0.18 4.19 4.57 a1 0.09 0.12 2.29 3.05 a2 0.02 ---. 0.51 --- b 0.013 0.021 0.33 0.53 b1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.4 17.65 d1 0.65 0.656 16.51 16.66 d2 0.59 0.63 14.99 16 d3 e h1 0.042 0.056 1.07 1.42 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 1.27 bsc 0.050 bsc inches millimeters 0.500 typ. 12.70 typ. note: the control dimension is the inch column
xr68c92/192 31 rev. p1.10 44 lead thin quad flat pack (10 mm x 10 mm x 1.4 mm, tqfp) rev. 1.00 33 23 22 12 111 34 44 d d 1 d d 1 b e a a 2 a 1 a seating plane l c inches millimeters symbol min max min max a 0.055 0.063 1.4 1.6 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.012 0.018 0.3 0.45 c 0.004 0.008 0.09 0.2 d 0.465 0.48 11.8 12.2 d1 0.39 0.398 9.9 10.1 e l 0.018 0.03 0.45 0.75 a 0 7 0 7 0.0315 bsc 0.80 bsc note: the control dimension is the inch column
xr68c92/192 32 rev. p1.10 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2000 exar corporation datasheet may 2000 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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