1 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hi-reliability product EDI88512C 512kx8 monolithic sram cmos features n 512kx8 bit cmos static n random access memory ? access times of 70, 85, 100ns ? data retention function (lp version) ? ttl compatible inputs and outputs ? fully static, no clocks n 32 lead jedec approved evolutionary pinout ? ceramic sidebrazed 600 mil dip (package 9) ? ceramic soj (package 140) n single +5v ( 10%) supply operation september 2000 rev. 10 pin description i/o 0-7 data inputs/outputs a 0-18 address inputs we write enables cs chip selects oe output enable v cc power (+5v 10%) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a -18 i/o -7 we cs oe fig. 1 pin configuration the EDI88512C is a 4 megabit monolithic cmos static ram. the 32 pin dip pinout adheres to the jedec evolutionary standard for the four megabit device. both the dip and csoj packages are pin for pin upgrades for the single chip enable 128k x 8, the edi88128c. pins 1 and 30 become the higher order addresses. a low power version with data retention (edi88512lp) is also available for battery backed applications. military product is available compliant to appendix a of mil-prf-38535. top view 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a i/o i/o1 i/o2 v ss
2 white electronic designs corporation ? phoenix, az ? (602) 437-1520 EDI88512C absolute maximum ratings parameter unit voltage on any pin relative to vss -0.5 to 7.0 v operating temperature t a (ambient) commercial 0 to +70 c industrial -40 to +85 c military -55 to +125 c storage temperature, plastic -65 to +150 c power dissipation 1 w output current 20 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 vcc +0.5 v input low voltage v il -0.3 +0.8 v parameter symbol condition max unit address lines c i v in = vcc or vss, f = 1.0mhz 12 pf data lines c o v out = vcc or vss, f = 1.0mhz 14 pf these parameters are sampled, not 100% tested. capacitance (t a = +25 c) truth table oe cs we mode output power x h x standby high z icc 2 , icc3 h l h output deselect high z icc 1 l l h read data out icc 1 x l l write data in icc 1 note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 w vcc q figure 1 figure 2 255 w 5pf 480 w vcc q 255 w ac test conditions parameter symbol conditions units min typ* max input leakage current i li v in = 0v to v cc 10 m a output leakage current i lo v i/o = 0v to v cc 10 m a operating power supply current i cc1 we, cs = v il , i i/o = 0ma, min cycle (70-100ns) 45 75 ma standby (ttl) power supply current i cc2 cs 3 v ih , v in v il , v in 3 v ih 3 10ma full standby power supply current i cc3 cs 3 v cc -0.2v c 5 ma v in 3 vcc -0.2v or v in 0.2v lp 2 ma output low voltage v ol i ol = 2.1ma 0.4 v output high voltage v oh i oh = -1.0ma 2.4 v note: dc test conditions: v il = 0.3v, v ih = vcc -0.3v dc characteristics (v cc = 5v, *t a = -55 c to +125 c)
3 white electronic designs corporation ? phoenix, az ? (602) 437-1520 EDI88512C ac characteristics C read cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time t avav t rc 70 85 100 ns address access time t avqv t aa 70 85 100 ns chip enable access time t elqv t acs 70 85 100 ns chip enable to output in low z (1) t elqx t clz 10 10 10 ns chip disable to output in high z (1) t ehqz t chz 25 30 30 ns output hold from address change t avqx t oh 10 10 10 ns output enable to output valid t glqv t oe 35 45 50 ns output enable to output in low z (1) t glqx t olz 55 5 ns output disable to output in high z(1) t ghqz t ohz 025030 030 ns 1. this parameter is guaranteed by design but not tested. ac characteristics C write cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time t avav t wc 70 85 100 ns chip enable to end of write t elwh t cw 60 70 80 ns t eleh t cw 60 70 80 ns address setup time t avwl t as 00 0 ns t avel t as 00 0 ns address valid to end of write t avwh t aw 65 70 80 ns t aveh t aw 65 70 80 ns write pulse width t wlwh t wp 50 55 60 ns t wleh t wp 50 55 60 ns write recovery time t whax t wr 00 0 ns t ehax t wr 00 0 ns data hold time t whdx t dh 00 0 ns t ehdx t dh 00 0 ns write to output in high z (1) t wlqz t whz 025030 0 30ns data to write time t dvwh t dw 40 40 40 ns t dveh t dw 30 35 40 ns output active from end of write (1) t whqx t wlz 55 5 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? phoenix, az ? (602) 437-1520 EDI88512C address data i/o read cycle 1 (we high; oe, cs low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data out read cycle 2 (we high) t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz oe cs ws32k32-xhx fig. 2 timing waveform - read cycle fig. 4 write cycle - cs controlled fig. 3 write cycle - we controlled address data in write cycle 2, cs controlled t aveh t eleh t ehax t wleh t dveh t ehdx t avav data valid high z we cs data out t avel address data in write cycle 1, we controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we cs data out
5 white electronic designs corporation ? phoenix, az ? (602) 437-1520 EDI88512C characteristic sym conditions min typ max units low power version only data retention voltage v dd v dd = 2.0v 2 C C v data retention quiescent current i ccdr cs 3 v dd -0.2v C C 185 m a chip disable to data retention time t cdr v in 3 v dd -0.2v 0 C C ns operation recovery time t r or v in 0.2v t avav CCns data retention characteristics (edi88512lpa only) (t a = -55 c to +125 c) ws32k32-xhx fig. 5 data retention - cs controlled data retention, cs controlled data retention mode t r vcc cs t cdr cs = v dd -0.2v v dd 4.5v 4.5v
6 white electronic designs corporation ? phoenix, az ? (602) 437-1520 EDI88512C package 9: 32 lead sidebrazed ceramic dip all dimensions are in inches pin 1 indicator 0.020 0.016 0.175 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 package 140: 32 lead ceramic soj all dimensions are in inches 0.108 0.088 0.050 typ 0.440 0.430 0.840 0.820 0.155 0.120 0.040 0.030 0.379 ref
7 white electronic designs corporation ? phoenix, az ? (602) 437-1520 EDI88512C ordering information white electronic designs sram organization, 512kx8 technology: c = cmos standard power lp = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) n = 32 lead ceramic soj (package 140) device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 8 512 c x x x
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