View AD9851_6207808.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9851 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 cmos 180 mhz dds/dac synthesizer functional block diagram 32-bit tuning word phase and control words frequency/phase data register data input register 10-bit dac dac r set analog out analog in clock out clock out high speed dds frequency update/data register reset word load clock master reset ref clock in 6 3 refclk multiplier comparator serial load 1 bit 3 40 loads parallel load 8 bits 3 5 loads frequency, phase and control data input AD9851 +v s gnd features 180 mhz clock rate with selectable 6 3 reference clock multiplier on-chip high performance 10-bit dac and high speed comparator with hysteresis sfdr >43 db @ 70 mhz a out 32-bit frequency tuning word simplified control interface: parallel or serial asynchronous loading format 5-bit phase modulation and offset capability comparator jitter <80 ps p-p @ 20 mhz +2.7 v to +5.25 v single supply operation low power: 555 mw @ 180 mhz power-down function, 4 mw @ +2.7 v ultrasmall 28-lead ssop packaging applications frequency/phase-agile sine wave synthesis clock recovery and locking circuitry for digital communications digitally controlled adc encode generator agile l.o. applications in communications quadrature oscillator cw, am, fm, fsk, msk mode transmitter general description the AD9851 is a highly integrated device that uses advanced dds technology, coupled with an internal high speed, high performance d/a converter, and comparator, to form a digitally- programmable frequency synthesizer and clock generator func- tion. when referenced to an accurate clock source, the AD9851 generates a stable frequency and phase-programmable digitized analog output sine wave. this sine wave can be used directly as a frequency source, or internally converted to a square wave for agile-clock generator applications. the AD9851s innovative high speed dds core accepts a 32-bit frequency tuning word, which results in an output tuning resolution of approximately 0.04 hz with a 180 mhz system clock. the AD9851 contains a unique 6 refclk multiplier circuit that eliminates the need for a high speed reference oscillator. the 6 refclk multiplier has minimal impact on sfdr and phase noise characteristics. the AD9851 provides five bits of programmable phase modula- tion resolution to enable phase shifting of its output in incre- ments of 11.25 . the AD9851 contains an internal high speed comparator that can be configured to accept the (externally) filtered output of the dac to generate a low jitter output pulse. the frequency tuning, control and phase modulation words are asynchronously loaded into the AD9851 via parallel or serial loading format. the parallel load format consists of five itera- tive loads of an 8-bit control word (byte). the first 8-bit byte controls output phase, 6 refclk multiplier, power-down enable and loading format; the remaining bytes comprise the 32-bit frequency tuning word. serial loading is accomplished via a 40-bit serial data stream e ntering through one of the parallel input bus lines. the AD9851 u ses advanced cmos technology to provide this breakthrough level of functionality on just 555 mw of power dissipation (+5 v su pply), at the maximum clock rate of 180 mhz. the AD9851 is available in a space-saving 28-lead ssop, sur- face mount package that is pin-for-pin compatible with the popular ad9850 125 mhz dds. it is specified to operate over the extended industrial temperature range of C40 c to +85 c.
C2C rev. 0 AD9851Cspecifications test AD9851brs p arameter temp level min typ max units clock input characteristics frequency range (6 refclk multiplier disabled) +5.0 v supply full iv 1 180 mhz +3.3 v supply full iv 1 125 mhz +2.7 v supply full iv 1 100 mhz frequency range (6 refclk multiplier enabled) +5.0 v supply full iv 5 30 mhz +3.3 v supply full iv 5 20.83 mhz +2.7 v supply full iv 5 16.66 mhz input resistance +25 cv 1 m w minimum switching thresholds 2 logic 1, +5.0 v supply +25 civ 3.5 v logic 1, +3.3 v supply +25 civ 2.3 v logic 0, +5.0 v supply +25 civ 1.5 v logic 0, +3.3 v supply +25 civ 1 v dac output characteristics full-scale output current +25 c iv 5 10 20 ma gain error +25 c i C10 10 % fs output offset +25 ci 10 m a differential nonlinearity +25 c i 0.75 lsb integral nonlinearity +25 c i 1 lsb residual phase noise, 5.2 mhz, 1 khz offset pll on +25 c v C125 dbc/hz pll off +25 c v C132 dbc/hz output impedance +25 c v 120 k w voltage compliance range +25 c i C0.5 1.5 v wideband spurious-free dynamic range 1.1 mhz analog out (dc to 72 mhz) +25 c iv 60 64 dbc 20.1 mhz analog out (dc to 72 mhz) +25 c iv 51 53 dbc 40.1 mhz analog out (dc to 72 mhz) +25 c iv 51 55 dbc 50.1 mhz analog out (dc to 72 mhz) +25 c iv 46 53 dbc 70.1 mhz analog out (dc to 72 mhz) +25 c iv 42 43 dbc narrowband spurious-free dynamic range 1.1 mhz ( 50 khz) +25 c v 85 dbc 1.1 mhz ( 200 khz) +25 c v 80 dbc 40.1 mhz ( 50 khz) +25 c v 85 dbc 40.1 mhz ( 200 khz) +25 c v 80 dbc 70.1 mhz ( 50 khz) +25 c v 85 dbc 70.1 mhz ( 200 khz) +25 c v 73 dbc comparator input characteristics input capacitance +25 cv 3 pf input resistance +25 c iv 500 k w input bias current +25 ci 12 m a input voltage range +25 civ 0 5 v comparator output characteristics logic 1 voltage +5 v supply +25 c vi +4.8 v logic 1 voltage +3.3 v supply +25 c vi +3.1 v logic 1 voltage +2.7 v supply +25 c vi +2.3 v logic 0 voltage +25 c vi +0.4 v continuous output current +25 civ 20 ma hysteresis +25 civ 10 mv propagation delay +25 civ 7 ns toggle frequency (1 v p-p input sine wave) +25 c iv 200 mhz rise/fall time, 15 pf output load +25 civ 7 ns output jitter (p-p) 3 +25 c iv 80 ps (p-p) clock output characteristics output jitter (clock generator configuration, 40 mhz 1 v p-p input sine wave) +25 c v 250 ps (p-p) clock output duty cycle full iv 50 10 % (v s 1 = +5 v 6 5%, r set = 3.9 k v , 6 3 refclk multiplier disabled, external reference clock = 30 mhz except as noted)
C3C rev. 0 AD9851 test AD9851brs parameter temp level min typ max units timing characteristics 4 t wh , t wl (w_clk min pulsewidth high/low) full iv 3.5 ns t ds , t dh (data to w_clk setup and hold times) full iv 3.5 ns t fh , t fl (fq_ud min pulsewidth high/low) full iv 7 ns t cd (refclk delay after fq_ud) 5 full iv 3.5 ns t fd (fq_ud min delay after w_clk) full iv 7 ns t cf (output latency from fq_ud) frequency change full iv 18 sysclk cycles phase change full iv 13 sysclk cycles t rh (clkin delay after reset rising edge) full iv 3.5 ns t rl (reset falling edge after clkin) full iv 3.5 ns t rr (recovery from reset) full iv 2 sysclk cycles t rs (minimum reset width) full iv 5 sysclk cycles t ol (reset output latency) full iv 13 sysclk cycles wake-up time from power-down mode 6 +25 cv 5 m s cmos logic inputs logic 1 voltage, +5 v supply +25 c i 3.5 v logic 1 voltage, +3.3 v supply +25 c i 3.0 v logic 1 voltage, +2.7 v supply +25 c i 2.4 v logic 0 voltage +25 ci 0.4 v logic 1 current +25 ci 12 m a logic 0 current +25 ci 12 m a rise/fall time +25 c iv 100 ns input capacitance +25 cv 3 pf power supply v s 6 current @: 62.5 mhz clock, +2.7 v supply +25 cvi 3035ma 100 mhz clock, +2.7 v supply +25 cvi 4050ma 62.5 mhz clock, +3.3 v supply +25 cvi 3545ma 125 mhz clock, +3.3 v supply +25 cvi 5570ma 62.5 mhz clock, +5 v supply +25 cvi 5065ma 125 mhz clock, +5 v supply +25 cvi 7090ma 180 mhz clock, +5 v supply +25 c vi 110 130 ma power dissipation @ : 62.5 mhz clock, +5 v supply +25 c vi 250 325 mw 62.5 mhz clock, +3.3 v supply +25 c vi 115 150 mw 62.5 mhz clock, +2.7 v supply +25 cvi 8595mw 100 mhz clock, +2.7 v supply +25 c vi 110 135 mw 125 mhz clock, +5 v supply +25 c vi 365 450 mw 125 mhz clock, +3.3 v supply +25 c vi 180 230 mw 180 mhz clock, +5 v supply +25 c vi 555 650 mw p diss power-down mode @: +5 v supply +25 cvi 1755mw +2.7 v supply +25 cvi 4 20 mw notes 1 +v s collectively refers to the positive voltages applied to dvdd, pvcc and avdd. voltages applied to these pins should be of the s ame potential. 2 indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. this specifies the p-p signal level and dc offset needed when the clocking signal is not of cmos/ttl origin, i.e., a sine wave with 0 v dc offset. 3 the comparators jitter contribution to any input signal. this is the minimum jitter on the outputs that can be expected from a n ideal input. considerably more output jitter is seen when nonideal input signals are presented to the comparator inputs. nonideal characteristics include the presence of extraneous, nonharmonic signals (spurs, noise), slower slew rate and low comparator overdrive. 4 timing of input signals fq_ud, wclk, reset are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those functions. in the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the ic, includ ing the comparator, inoperable until a reference clock is restored. very high speed updates of frequency/phase word will require fq_ud and wclk to be externa lly synchronized with the exter- nal reference clock to assure proper timing. 5 not applicable when 6 refclk multiplier is engaged. 6 assumes no capacitive load on dacbp (pin 17). specifications subject to change without notice.
AD9851 C4C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9851 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* maximum junction temperature . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v operating temperature . . . . . . . . . . . . . . . . . C40 c to +85 c digital inputs . . . . . . . . . . . . . . . . . . . C0.7 v to +v s + 0.7 v lead temperature (10 sec) soldering . . . . . . . . . . . . . +300 c digital output current . . . . . . . . . . . . . . . . . . . . . . . . 30 ma ssop q ja thermal impedance . . . . . . . . . . . . . . . . . . 82 c/w dac output current . . . . . . . . . . . . . . . . . . . . . . . . . .30 ma *absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. explanation of test levels test level i C 100% production tested. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C devices are 100% production tested at +25 c and guaranteed by design and characterization testing for industrial operating temperature range. ordering guide model temperature range package description package option AD9851brs C40 c to +85 c shrink small outline (ssop) rs-28
AD9851 C5C rev. 0 pin function descriptions pin no. mnemonic function 4C1 d0Cd7 8-bit data input. the data port for loading the 32-bit frequency and 8-bit phase/control words. 28C25 d7 = msb; d0 = lsb. d7, pin 25, also serves as the input pin for 40-bit serial data word. 5 pgnd 6 refclk multiplier ground connection. 6 pvcc 6 refclk multiplier positive supply voltage pin. 7 w_clk word load clock. rising edge loads the parallel or serial frequency/phase/control words asynchronously into the 40-bit input register. 8 fq_ud frequency update. a rising edge asynchronously transfers the contents of the 40-bit input register to be acted upon by the dds core. fq_ud should be issued when the contents of the input register are known to contain only valid, allowable data. 9 refclock reference clock input. cmos/ttl-level pulse train, direct or via the 6 refclk multiplier. in direct mode, this is also the system clock. if the 6 refclk multiplier is engaged, then the output of the multiplier is the system clock. the rising edge of the system clock initiates operations. 10, 19 agnd analog ground. the ground return for the analog circuitry (dac and comparator). 11, 18 avcc positive supply voltage for analog circuitry (dac and comparator, pin 18) and bandgap voltage reference, pin 11. 12 r set the dacs external r set connectionnominally a 3.92 k w resistor to ground for 10 ma out. this sets the dac full-scale output current available from iout and ioutb. r set = 39.93/iout 13 voutn voltage output negative. the comparators complementary cmos logic level output. 14 voutp voltage output positive. the comparators true cmos logic level output. 15 vinn voltage input negative. the comparators inverting input. 16 vinp voltage input positive. the comparators noninverting input. 17 dacbp dac bypass connection. this is the dac voltage reference that is externally bypassed with at least 10 m f capacitor to +v s for optimized sfdr performance. 20 ioutb the complementary dac output with same characteristics as iout except that ioutb = (full-scale outputCiout) . output load should equal that of iout for best sfdr performance. 21 iout the true o utput of the balanced dac. current is sourcing and requires cu rrent-to-voltage conversion, usually a resistor or transformer referenced to gnd. iout = (full-scale outputCioutb) 22 reset master reset pin; active high; clears dds accumulator and phase offset register to achieve 0 hz and 0 output phase. sets programming to parallel mode and disengages the 6 refclk multiplier. reset does not clear the 40-bit input register. on power-up, asserting reset should be the first priority before pro- gramming commences. 23 dvdd positive supply voltage pin for digital circuitry. 24 dgnd digital ground. the ground return pin for the digital circuitry. pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD9851 voutp voutn r set avdd agnd refclock fq ud d3 d2 d1 lsb d0 pvcc pgnd vinn vinp dacbp avdd agnd ioutb iout d4 d5 d6 d7 msb/serial load reset dvdd dgnd w clk
AD9851 C6C rev. 0 both iout and ioutb are equally loaded with 100 w . two 100 k w resistors sample each output and average the two voltages. the result is filtered with the 470 pf capacitor and applied to one comparator input as a dc switching threshold. the filtered dac sine wave output is applied to the other com- parator input. the comparator will toggle with nearly 50% duty cycle as the sine wave alternately traverses the center point threshold. AD9851 dds reference clock if frequency in filter filter tuning word rf frequency out figure 3. frequency/phase-agile local oscillator for frequency mixing/multiplying filter phase comparator divide-by-n loop filter vco AD9851 dds reference clock tuning word rf frequency out figure 4. frequency/phase-agile reference for pll i/q mixer and low pass filter i q ad9059 dual 8-bit adc 8 8 digital demodulator adc encode agc 32 chip/symbol/pn rate data adc clock frequency locked to tx chip/symbol/pn rate 180mhz or 30mhz reference clock rx baseband digital data out rx rf in vca AD9851 clock generator figure 1. chip rate clock generator application in a spread spectrum receiver microprocessor or microcontroller data bus 180mhz or 30mhz reference clock 8-bit parallel data, or 1-bit 3 40 serial data, reset, w clk and fq ud iout 100k v 100k v 470pf 100 v ioutb r set 3.9k v cmos outputs qoutb qout low-pass filter 7th order elliptical 70mhz low pass 200 v impedance 200 v voltage here = center point of sine wave (0.5v typically) using passive "averaging" circuit 0 to 1v p-p sine wave AD9851 200 v figure 2. basic clock generator configuration phase comparator loop filter vco AD9851 dds reference clock tuning word rf frequency out filter ref clk in programmable "divide-by-n" function (where n = 2 32 /tuning word) figure 5. digitally-programmable divide-by-n function in pll AD9851 dds fm rf output adsp-2181 dsp processor adsp-2181 bus input/ output decode logic 8-bit data bus ad1847 stereo codec l & r audio in ref osc dac out AD9851/fspcb evaluation board ez-kit lite dsp figure 6. high quality, all-digital rf frequency modulation high quality, all digital rf frequency modulation generation with the adsp-2181 dsp and the AD9851 dds. this applica- tion is well documented in analog devices application note an-543, and uses an image of the dds output as illustrated in figure 8.
AD9851 C7C rev. 0 ref clock 90 phase difference 8-bit data bus fq ud reset w clk AD9851 #2 iout AD9851 #1 w clk fq ud reset iout reset fq ud reset fq ud w clk #2 w clk #1 microprocessor or microcontroller w clk #2 w clk #1 figure 7. application showing synchronization of two AD9851 ddss to form a quadrature oscillator after a common reset command is issued, separate w_clks allow independent programming of each AD9851 40-bit input register via the 8-bit data bus or serial input pin. a common fq_ud pulse is issued after programming is completed to simultaneously engage both oscillators at their specified fre- quency and phase. AD9851 iout 30mhz clock bandpass filter 50 v 50 v fundamental f clk image f c C f o image f c + f o amplitude 60 120 180 240 frequency C mhz 240 frequency C mhz image f c + f o bandpass filter amplitude 3 6 amplifier 240mhz AD9851 spectrum final output spectrum figure 8. deriving a high frequency output signal from the AD9851 by using an alias or image signal differential dac output connection (figure 9) for reduction of common-mode signals and to allow highly reactive filters to be driven without a filter input termination resistor (see above single-ended example, figure 8). a 6 db power advantage is obtained at the filter output as compared with the single-ended example, since the filter need not be doubly terminated. reference clock filter differential transformer-coupled output 50 v 1:1 transformer i.e., mini-circuits t1C1t 50 v AD9851 dds 21 20 figure 9. differential dac output connection for reduc- tion of common-mode signals. the AD9851 r set input being driven by an external dac (figure 10) to provide amplitude modulation or fixed, digital amplitude control of the dac output current. full description of this application is found as a technical note on the AD9851 web page (site address is www.analog.com) under related information. an analog devices application note for the ad9850, an-423, describes another method of amplitude control using an enhancement-mode mosfet that is equally applicable to the AD9851. note: if the 6 refclk multiplier of the AD9851 is en- gaged, the 125 mhz clocking source shown in figure 10 can be reduced by a factor of six. AD9851 dds differential transformer-coupled output 50 v 1:1 transformer 50 v iout iout r set +5v 21 20 12 9 4k v 200 v 330 v +5v 20ma max 10-bit dac ad9731 +5v C5v 125mhz 10 bits data generator e.g., dg-2020 computer control data figure 10. the AD9851 r set input being driven by an external dac
AD9851 C8C rev. 0 theory of operation and application the AD9851 uses direct digital synthesis (dds) technology, in the form of a numerically-controlled oscillator (nco), to gen- erate a frequency/phase-agile sine wave. the digital sine wave is converted to analog form via an internal 10-bit high speed d/a converter. an on-board high-speed comparator is provided to translate the analog sine wave into a low-jitter ttl/cmos- compatible output square wave. dds technology is an innova- tive circuit architecture that allows fast and precise manipu lation of its output word, under full digital control. dds also enables very high resolution in the incremental selection of output fre- quency. the AD9851 allows an output frequency resolution of approximately 0.04 hz at 180 msps clock rate with the option of directly using the reference clock or by engaging the 6 refclk multiplier. the AD9851s output waveform is phase-continu- ous from one output frequency change to another. the basic functional block diagram and signal flow of the AD9851 configured as a clock generator is shown in figure 11. the dds circuitry is basically a digital frequency divider func- tion whose incremental resolution is determined by the frequency of the system clock, and n (number of bits in the tuning word). the phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. when the counter reaches full scale it wraps around, making the phase accumulators output phase-continuous. the frequency tuning word sets the modulus of the counter, which effectively determines the size of the increment ( d phase) that will be added to the value in the phase accumulator on the next clock pulse. the larger the added increment, the faster the accumulator wraps around, which results in a higher output frequency. the AD9851 uses an innovative and proprietary angle rota tion algorithm that mathematically converts the 14-bit truncated value of the 32-bit phase accumulator to the 10-bit quantized amplitude that is passed to the dac. this unique algorithm uses a much-reduced rom look-up table and dsp to perform this function. this contributes to the small size and low power dissipation of the AD9851. the relationship between the output frequency, system clock and tuning word of the AD9851 is determined by the expression: f out = ( d phase system clock)/ 2 32 where: d phase = decimal value of 32-bit frequency tuning word. system clock = direct input reference clock (in mhz) or 6 the input clock (in mhz) if the 6 refclk multiplier is engaged. f out = frequency of the output signal in mhz. the digital sine wave output of the dds core drives the internal high-speed 10-bit d/a converter that will construct the sine wave in analog form. this dac has been optimized for dynamic performance and low glitch energy, which results in the low spurious and jitter performance of the AD9851. the dac can be operated in either the single-ended, figures 2 and 8, or dif- ferential output configuration, figures 9 and 10. dac output current and r set values are determined using the following expressions: i out = 39.93/ r set r set = 39.93/ i out since the output of the AD9851 is a sampled signal, its output spectrum follows the nyquist sampling theorem. specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at integer multiples of the system clock frequency the selected output frequency. a graphical repre- sentation of the sampled spectrum, with aliased images, is shown in figure 12. normal usable bandwidth is considered to extend from dc to 1/2 the system clock. in the example shown in figure 12, the system clock is 100 mhz and the output frequency is set to 20 mhz. as can be seen, the aliased images are very prominent and of a relatively high energy clock out amplitude/sine conv algorithm phase accumulator dds circuitry d/a converter lp comparator n reference clock tuning word specifies output frequency as a fraction of ref clock frequency in digital domain figure 11. basic dds block diagram and signal flow of AD9851 120mhz 2nd image f out f c +f o 2f c Cf o 2f c +f o 3f c Cf o 180mhz 3rd image 220mhz 4th image 280mhz 5th image 80mhz 1st image 20mhz 0hz (dc) f c f c Cf o sin (x)/ 3 envelope 3 = ( p )f/f c 100mhz system clock frequency signal amplitude figure 12. output spectrum of a sampled sin(x)/x signal
AD9851 C9C rev. 0 level as determined by the sin(x)/x roll-off of the quantized d/a converter output. in fact, depending on the f/system clock rela- tionship, the 1st aliased image can equal the fundamental amplitude (when f out = 1/2 system clock). a low-pass filter is generally placed between the output of the d/a converter and the input of the comparator to suppress the jitter-producing effects of non-harmonically related aliased images and other spurious signals. consideration must be given to the relationship of the selected output frequency, the system clock frequency and alias frequencies to avoid unwanted output anomalies. images need not be thought of as useless by-products of a dac. in fact, with bandpass filtering around an image and some amount of post-filter amplification, the image can become the primary output signal (see figure 8). since images are not har- monics, they retain a 1:1 d frequency relationship to the funda- mental output. that is, if the fundamental is shifted 1 khz, then the image is also shifted 1 khz. this relationship accounts for the frequency stability of an image, which is identical to that of the fundamental. users should recognize that the lower image of an image pair surrounding an integer multiple of the system clock will move in a direction opposite the fundamental. images of an image pair located above an integer multiple of the system clock will move in the same direction as a fundamental movement. the frequency band where images exist is much richer in spuri- ous signals and therefore, more hostile in terms of sfdr. users of this technique should empirically determine what frequencies are usable if their sfdr requirements are demanding. a good rule-of-thumb for applying the AD9851 as a clock generator is to limit the fundamental output frequency to 40% of reference clock frequency to avoid generating aliased sig nals that are too close to the output band of interest (generally dc highest selected output frequency) to be filtered. this practice will ease the complexity and cost of the external filter require- ment for the clock generator application. the reference clock input of the AD9851 has minimum limita- tion of 1 mhz without 6 refclk multiplier engaged and 5 mhz with multiplier engaged. the device has internal cir- cuitry that senses when the clock rate has dropped below the minimum and a utomatically places itself in the power-down mode. in this m ode, the on-chip comparator is also disabled. this is important information for those who may wish to use the on-chip comparator for purposes other than squaring the dds sine wave output. when the clock frequency returns above the minimum threshold, the device resumes normal operation after 5 m s (typically). this shutdown mode prevents excessive current leakage in the dynamic registers of the device. the impact of reference clock phase noise in dds systems is actually reduced, since the dds output is the result of a division of the input frequency. the amount of apparent phase noise reduction, expressed in db, is found using: 20 log f out /f clk . where f out is the fundamental dds output frequency and f clk is the system clock frequency. from this standpoint, using the highest system clock input frequency makes good sense in reduc- ing the effects of reference clock phase noise contribution to the output signals overall phase noise. as an example, an osc illa- tor with C100 dbc phase noise operating at 180 mhz would appear as a C125 db contribution to dds overall phase noise for a 10 mhz output. engaging the 6 refclk multiplier has generally been found to increase overall output phase noise. this increase is due to the inherent 6 (15.5 db) phase gain transfer function of the 6 refclk multiplier, as well as noise gener- ated internally by the clock multiplier circuit. by using a low phase noise reference clock input to the AD9851, users can be assured of better than C100 dbc/hz phase noise performance for output frequencies up to 50 mhz at offsets from 1 khz to 100 khz. programming the AD9851 the AD9851 contains a 40-bit register that stores the 32-bit frequency co ntrol word, the 5-bit phase modulation w ord, 6 refclk multiplier enable and the power-down function. this register can be loaded in parallel or serial mode. a logic high engages functions; for example, to power-down the ic (sleep mode), a logic high must be programmed in that bit location. those users who are familiar with the ad9850 dds will find only a slight change in programming the AD9851, specifically, data[0] of w0 (parallel load) and w32 (serial load) now contains a 6 refclk multiplier enable bit that needs to be set high to enable or low to disable the internal reference clock multiplier. note: setting data[1] high in programming word w0 (paral- lel mode) or word w33 high in serial mode is not allowed (see tables i and iii). this bit controls a factory test mode that will cause abnormal operation in the AD9851 if set high. if erroneously entered (as evidenced by pin 2 changing from an input pin to an output signal), an exit is provided by asserting reset. unintentional entry to the factory test mode can occur if an fq_ud pulse is sent after initial pow er-up and reset of the AD9851. since reset does not clear the 40- bit input register, this will transfer the random power-up values of the input register to the dds core. the random values may invoke the factory test mode or power-down mode. never issue an fq_ud command if the 40-bit input register contents are unknown. in the default parallel load mode, the 40-bit input register is loaded using an 8-bit bus. w_clk is used to load the register in five iterations of eight bytes. the rising edge of fq_ud transfers the contents of the register into the device to be acted upon and resets the word address pointer to w0. subsequent w_clk rising edges load 8-bit data, starting at w0 and then move the word pointer to the next word. after w0 through w4 are loaded, additional w_clk edges are ignored until either a reset is asserted or an fq_ud rising edge resets the address pointer to w0 in preparation for the next 8-bit load. see fig- ure 13. in serial load mode, forty subsequent rising edges of w_clk will shift and load the 1-bit data on pin 25 (d7) through the 40-bit register in shift-register fashion. any further w_clk rising edges after the register is full will shift data out causing data that is left in the register to be out-of-sequence and cor- rupted. the serial mode must be entered from the default parallel mode, see figure 17. data is loaded beginning with w0 and ending with w39. one note of caution: the 8-bit parallel word (w0)xxxxx011that invokes the serial mode should be overwritten with a valid 40-bit serial word immedi- ately after entering the serial mode to prevent unintended engaging of the 6 refclk multiplier or entry into the fac- tory test mode. exit from serial mode to parallel mode is only possible using the reset command.
AD9851 C10C rev. 0 table i. 8-bit parallel-load data/control word functional assignment word data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] w0 phaseCb4 (msb) phaseCb3 phaseCb2 phaseCb1 phaseCb0 (lsb) power-down logic 0* 6 refclk multiplier enable w1 freqCb31 (msb) freqCb30 freqCb29 freqCb28 freqCb27 freqCb26 freqCb25 freqCb24 w2 freqCb23 freqCb22 freqCb21 freqCb20 freqCb19 freqCb18 freqCb17 freqCb16 w3 freqCb15 freqCb14 freqCb13 freqCb12 freqCb11 freqCb10 freqCb9 freqCb8 w4 freqCb7 freqCb6 freqCb5 freqCb4 freqCb3 freqCb2 freqCb1 freqCb0 (lsb) *this bit is always logic 0 unless invoking the serial mode (see figure 17). after serial mode is entered, this data bit must b e set back to logic 0 for proper operation. w0* w1 w2 w3 w4 t cd t dh t ds t wl t wh t fd t fh t fl *output update can occur after any word load and is asynchronous with reference clock t cf valid data sysclk data w clk fq ud a out figure 13. parallel-load frequency/phase update timing sequence note: to update w0 it is not necessary to load w1 through w4. simply load w0 and assert fq_ud. to update w1, reload w0 then w1 . . . users do not have random access to programming words. table ii. timing specifications symbol definition min t ds data setup time 3.5 ns t dh data hold time 3.5 ns t wh w_clk high 3.5 ns t wl w_clk low 3.5 ns t cd refclk delay after fq_ud 3.5 ns* t fh fq_ud high 7.0 ns t fl fq_ud low 7.0 ns t fd fq_ud delay after w_clk 7.0 ns t cf output latency from fq_ud frequency change 18 sysclk cycles phase change 13 sysclk cycles *specification does not apply when the 6 refclk multiplier is engaged. the function assignments of the data and control words are shown in tables i and iii; the detailed timing sequence for updating the output frequency and/or phase, resetting the de- vice, engaging the 6 refclk multiplier, and powering up/ down, are shown in the timing diagrams of figures 13C20. as a programm ing example for the following dds characteristics: 1. phase set to 11.25 degrees. 2. 6 refclk multiplier engaged. 3. powered-up mode selected. 4. output = 10 mhz (for 180 mhz system clock). in parallel mode, user would program the 40-bit control word (composed of five 8-bit loads) as follows: w0 = 00001001 w1 = 00001110 w2 = 00111000 w3 = 11100011 w4 = 10001110 if in serial mode, load the 40 bits starting from the lsb location of w4 in the above array, loading from right to left, and end- ing with the msb of w0.
AD9851 C11C rev. 0 results of reset, figure 14 C phase accumulator zeroed such that the output = 0 hertz (dc). C phase offset register set to zero such that dac iout = full- scale output and ioutb = zero ma output. C internal programming address pointer reset to w0. C power-down bit reset to 0 (power-down disabled). C 40-bit data input register is not cleared. C6 reference clock multiplier is disabled. C parallel programming mode selected by default. xxxxx10x fq ud w clk sysclk dac strobe data (w0) internal clocks disabled figure 15. parallel-load power-down sequence/internal operation xxxxx00x fq ud w clk data (w0) internal clocks enabled sysclk figure 16. parallel-load power-up sequence (to recover from power-down)/internal operation sysclk reset a out t rs t rh t rl t ol cos (0 8 ) symbol definition min spec t rh clk delay after reset rising edge 3.5ns* t rl reset falling edge after clk 3.5ns* t rr recovery from reset 2 sysclk cycles t rs minimum reset width 5 sysclk cycles t ol reset output latency 13 sysclk cycles * specifications do not apply when the ref clock multiplier is engaged t rr figure 14. master reset timing sequence entry to the serial mode, figure 17, is via the parallel mode which is selected by default after a reset is asserted. one needs only to program the first eight bits (word w0) with the sequence xxxxx011as shown in figure 17 to change from paral- lel to serial mode. the w0 programming word may be sent over the 8-bit data bus or hardwired as shown in figure 18. after serial mode is achieved, the user must follow the programming sequence of figure 19. xxxxx011 fq ud w clk data (w0) enable serial mode figure 17. serial-load enable sequence note: after serial mode is invoked, it is best to immediately write a valid 40-bit serial word (see figure 19), even if it is all zeros, followed by a fq_ud rising edge to flush the residual data left in the dds core. a valid 40-bit serial word is any word where w33 is logic 0. 28 27 26 25 1 2 3 4 AD9851 d3 d2 d1 d0 d4 d5 d6 d7 10k v +v supply figure 18: hardwired xxxxx011 configuration for serial- load enable word w0 in figure 17
AD9851 C12C rev. 0 fq ud w2 data 40 w clk cycles w clk w1 w3 w39 w0 figure 19. serial-load frequency/phase update sequence table iii. 40-bit serial-load word functional assignment w0 freqCb0 (lsb) w1 freqCb1 w2 freqCb2 w3 freqCb3 w4 freqCb4 w5 freqCb5 w6 freqCb6 w7 freqCb7 w8 freqCb8 w9 freqCb9 w10 freqCb10 w11 freqCb11 w12 freqCb12 w13 freqCb13 w14 freqCb14 w15 freqCb15 w16 freqCb16 w17 freqCb17 w18 freqCb18 w19 freqCb19 w20 freqCb20 w21 freqCb21 w22 freqCb22 w23 freqCb23 w24 freqCb24 w25 freqCb25 w26 freqCb26 w27 freqCb27 w28 freqCb28 w29 freqCb29 w30 freqCb30 w31 freqCb31 (msb) w32 6 refclk multi- plier enable w33 logic 0* w34 power-down w35 phaseCb0 (lsb) w36 phaseCb1 w37 phaseCb2 w38 phaseCb3 w39 phaseCb4 (msb) *this bit is always logic 0. fq ud w34 = 1 or 0 data (7) C 40 w_clk rising edges w clk w33 = 0 w35 = x w39 = x w38 = x w0 = x figure 20. serial-load power-down\power-up sequence digital out v dd iout ioutb v dd vinp/ vinn v dd digital in v dd a. dac output b. comparator output c. comparator input d. digital input figure 21. i/o equivalent circuits figure 20 shows a normal 40-bit serial word load sequence with w33 always set to logic 0 and w34 set to logic 1 or logic 0 to control the power-down function. the logic states of the remain- ing 38 bits are unimportant and are marked with an x, indicating dont care status. to power down, set w34 = 1. to power up from a powered down state, change w34 to logic 0. wake-up from power-down mode requires approximately 5 m s. note: the 40-bit input register of the AD9851 is fully program- mable while in the power-down mode.
AD9851 C13C rev. 0 pcb layout information the AD9851/cgpcb and AD9851/fspcb evaluation boards (figures 22C25) represent typical implementations of the AD9851 and exemplify the use of high frequency/high resolution design and layout practices. the printed circuit board that contains the AD9851 should be a multilayer board that allows dedicated power and ground planes. the power and ground planes should (as much as possible) be free of etched traces that cause dis- continuities in the planes. it is recommended that the top layer of the board also contain an interspatial ground plane that makes ground available without vias for the surface-mount devices. if separate analog and digital system ground planes exist, they should be connected together at the AD9851 evaluation board for optimum performance. avoid running digital lines under the device as these will couple unnecessary noise onto the die. the power supply lines to the AD9851 should use as large a trace as possible to provide a low- impedance path and reduce the effects of switching currents on the power supply line. fast switching signals like clocks should use microstrip, controlled impedance techniques where possible. avoid crossover of digital and analog signal paths. traces on opposite sides of the board should run at right angles to each other. this will reduce crosstalk between the lines. good power supply decoupling is also an important consider- ation. the analog (avdd) and digital (dvdd) supplies to the AD9851 are independent and separately pinned-out to mini- mize coupling between analog and digital sections of the device. all analog and digital supply pins should be decoupled to agnd and dgnd respectively, with high quality ceramic chip capaci- tors. to achieve best performance from the decoupling capaci- tors, they should be placed as close as possible to the device. in systems where a common supply is used to drive both the avdd and dvdd supplies of the AD9851, it is recommended that the systems avdd supply be used. analog devices applications engineering support is available to answer additional questions on grounding and pcb layout. call 1-800-analogd. evaluation boards two versions of the AD9851 evaluation board are available. the evaluation boards facilitate easy implementation of the device for bench-top analysis and serve as a reference for pcb layout. the AD9851/fspcb is intended for applications where the device will primarily be used as a frequency synthesizer. this version is optimized for connection of the AD9851 internal d/a converter output to a 50 w spectrum analyzer input. the inter- nal comparator of the AD9851 is made available for use via wire hole access. the comparator inputs are externally pulled to opposing voltages to prevent comparator chatter due to floating inputs. the dds dac output is unfiltered and no reference oscillator is provided. this is done in recognition of the fact that many users may find their presence to be a liability rather than an asset. see figure 22 for electrical schematic. the AD9851/cgpcb is intended for applications using the device as a cmos output clock generator. it connects the AD9851 dac output to the internal comparator input via a single-ended, 70 mhz low pass, 7th order, elliptic filter. to minimize output jitter of the comparator, special attention has been given to the low pass filter design. primary considerations were input and output impedances (200 w ) and a very steep roll-off characteristic to attenuate unwanted, nearby alias sig- nals. the high impedance of the filter allows the dac to de- velop 1 v p-p (with 10 ma) across the two 200 w resistors at the input and output of the filter. this voltage is entirely suffi- cient to optimally drive the AD9851 comparator. this filter was designed with the assumption that the AD9851 dds is at full clock speed (180 mhz). if this is not the case, filter specifica- tions may need to change to achieve proper attenuation of anticipated alias signals. bnc connectors allow convenient observation of the comparator cmos output and input, as well as that of the dac. no reference oscillator is provided for reasons stated above. this model allows easy evaluation of the AD9851 as a frequency and phase-agile cmos output clock source (see figure 24 for electrical schematic). jitter reduction note the AD9851/cgpcb has a wideband dds fundamental out- put, dc to 70 mhz, and the on-chip comparator has even more bandwidth. to optimize low jitter performance users should consider bandpass filtering of the dac output if only a narrow bandwidth is required. this will reduce jitter caused by spuri- ous, nonharmonic signals above and below the desired signal. lowering the applied v dd helps in reducing comparator switch- ing noise by reducing d v/ d t of the comparator outputs. for optimum jitter performance, users should avoid the very busy digital environment of the on-chip comparator and opt for an external, high speed comparator. both versions of the AD9851 evaluation boards are designed to interface to the parallel printer port of a pc. the operating software (c++) runs under microsoft windows ? (3.1 and windows 95, nt is not supported) and provides a user- friendly and intuitive format for controlling the functionality and observing the performance of the device. the 3.5" disk provided with the evaluation board contains an executable file that d isplays the AD9851 function-selection screen. the evaluation board may be operated with +3.0 v or +5 v sup- plies. evaluation boards are configured at the factory for an external clock input. if the optional on-board crystal clock source is installed, resistor r2 (50 w ) must be removed. evaluation board instructions required hardware/software personal computer operating in windows 3.1 or 95 environ- ment (does not support windows nt). printer port, 3.5" floppy drive, mouse and centronics compat- ible printer cable, +3 v to +5 v voltage supply. crystal clock oscillator or high frequency signal generator (sine wave output) with dc offset capability. AD9851 evaluation board software disk and AD9851/fspcb or AD9851/cgpcb evaluation board setup copy the contents of the AD9851 disk onto the host pcs hard drive (there are two files, win9851.exe version 1.x and bwcc.dll). c onnect the printer cable from computer to the evaluation board. use a good quality cable as some cables do not connect every wire that the printer port supports. windows is a registered trademark of microsoft corportaion. all other trademarks are the property of their respective holders.
AD9851 C14C rev. 0 apply power to AD9851 evaluation board. the AD9851 is powered separately from the other active components on the board via connector marked dut +v. the connector marked +5 v is used to power the cmos latches, optional crystal oscil lator and pull-up resistors. both +5 v and dut +v may be tied together for ease of operation without adverse affects. the AD9851 may be pow ered with +2.7 v to +5.25 v. connect an external 50 w z clock source or remove r2 and install a suitable crystal clock oscillator with cmos output levels at y1. a sine wave signal generator may be used as a clock source at frequencies >50 mhz by dc offsetting the output signal to 1/2 the supply voltage to the AD9851. this method requires a minimum of 2 v p-p signal and that the 6 refclk multiplier function be disabled. locate the file called win9851.exe and execute that program. the computer monitor should show a control panel which allows operation of the AD9851 evaluation board by use of a mouse. operation on the control panel locate the box labeled computer i/o. click the correct parallel printer port for the host computer and then click the test box. a message will appear indicating if the selection of output port is correct. choose other ports as necessary to achieve a correct port setting. click the master reset button. this will reset the part to 0 hz, 0 degrees phase, parallel programming mode. the output from the dac iout should be a dc voltage equal to the full- scale output of the AD9851 (1 volt for the AD9851/cgpcb and 0.5 volts for the AD9851/fspcb) while the dac ioutb should be 0 volts for both evaluation boards. reset should always be the first command to the AD9851 following power-up . locate the clock section and place the cursor in the frequency box. enter the clock frequency (in mhz) that will be applied to the reference clock input of the AD9851. click the pll box in the control function menu if the 6 reference clock multiplier is to be engaged . . . a check mark will appear when engaged. when the reference clock multi- plier is engaged, software will multiply the value entered in the frequency box by six; otherwise, the value entered is the value used. click the load button or press the enter key. move the cursor to the output frequency box and type in the desired frequency (in mhz). click the load button or press the enter key. the bus monitor section of the control panel will show the 32-bit frequency word and 8-bit phase/ control word. upon completion of this step, the AD9851 output should be active at the programmed frequency/phase. changing the output phase is accomplished by clicking the down arrow in the output phase delay box to make a selection and then clicking the load button. note: clicking the load buttons of either the clock frequency box, the output frequency box or the phase box will automatically initiate a re- loading of all three boxes and issuance of a fq_ud (frequency update) pulse. to bypass this automatic reloading and fre- quency update sequence, refer to the note below. other operational modes (frequency sweeping, sleep, serial input) are available. frequency sweeping allows the user to enter a start and stop frequency and to specify the frequency step size. sweeping begins at the start frequency, proceeds to the stop frequency in a linear manner, reverses direction and sweeps back to the start frequency repeatedly. note: for those who may be operating multiple AD9851 evalua- tion boards from one computer, a manual frequency update option exists. by eliminating the automatic issuance of an fq_ud, the user can load the 40-bit input registers of multiple AD9851s without transferring that data to the internal accumulators. when all input registers are loaded, a single frequency update pulse can be issued to all AD9851s. a block diagram of this technique is shown in the AD9851 data sheet as a quadrature oscillator application. this single pulse synchronizes all the units so that their particular phases and frequencies take effect simultaneously. proper synchronization requires that each AD9851 be clocked by the same reference clock source and that each oscillator be in an identical state while being programmed. reset command assures identical states. when manual frequency update is selected, a new box labeled frequency update will appear just above the frequency sweeping menu. clicking the box initiates a single fq_ud pulse. note: reset can be used to synchronize multiple oscillators. if several oscillators have already been programmed at various phases or frequencies, issuance of a reset pulse will set their outputs to 0 hz and 0 phase. by issuing a common fq_ud, the previously programmed information in the 40-bit input registers will transfer once again to the dds core and take effect in 18 clock cycles. this is due to the fact that reset does not affect the contents of the 40-bit input register in any way. the AD9851/fspcb provides access into and out of the on- chip comparator via test point pairs (each pair has an active input and a ground connection). the two active inputs are labeled tp1 and tp2. the unmarked hole next to each labeled test point is a ground connection. the two active outputs are labeled tp5 and tp6. adjacent those test points are unmarked ground connections. to prevent unwanted comparator chatter when not in use, the two inputs are pulled either to ground or +v via 1 k w resistors. the AD9851/cgpcb provides bnc inputs and outputs associated with the on-chip comparator and an onboard, 7th order, 200 w input /output z, elliptic 70 mhz low pass filter. jumpering (soldering a wire) e1 to e2, e3 to e4 and e5 to e6 connects the onboard filter and the midpoint switching voltage to the comparator. users may elect to insert their own filter and comparator threshold voltage by removing the jumpers and inserting a filter between j7 and j6 and providing a comparator threshold voltage at e1. use of the xtal oscillator socket on the evaluation board to supply the clock to the AD9851 requires the removal r2 (a 50 w chip resistor) unless the oscillator can drive a 50 w load. the crystal oscillator should be either ttl or cmos (preferably) compatible.
AD9851 C15C rev. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 11 1 strobe d0 d1 d2 d3 d4 d5 d6 d7 u2 74hct574 j1 c36cprx rrset 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe ffqud wwclk check strobe 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe 11 1 strobe reset wclk fqud check u3 74hct574 rreset wwclk ffqud rreset v cc y1 out gnd 7 8 14 +5v xtal osc (optional) r2 50 v j5 clkin remove when using y1 c2 0.1 m f c3 0.1 m f c4 0.1 m f c5 0.1 m f c8 0.1 m f c9 0.1 m f c10 0.1 m f +v +5v c6 10 m f c7 10 m f +v +5v h1 #6 h2 #6 h3 #6 h4 #6 r3 2.2k v strobe +5v wwclk ffqud rreset r8 2.2k v r9 2.2k v r10 2.2k v j2 +v j3 +5v j4 gnd banana jacks 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 voutp voutn r set avdd agnd refclock fq ud d3 d2 d1 d0 w clk pvcc pgnd vinn vinp dacbp avdd agnd ioutb iout d4 d5 d6 d7 reset dvdd dgnd u1 AD9851 +v gnd clkin fqud d3 d2 d1 d0 wclk +v gnd +v gnd d4 d5 d6 d7 reset +v gnd r5 25 v r4 50 v gnd gnd tp1 tp3 tp2 tp4 r5 1k v +v r7 1k v gnd comparator inputs j6 dac out to 50 v r1 3.9k v gnd gnd tp5 tp6 tp7 tp8 10ma reset mounting holes AD9851/fspcb frequency synthesizer evaluation board 10 m f +v c1 figure 22. fspcb electrical schematic
AD9851 C16C rev. 0 a. fspcb top layer b. fspcb power plane c. fspcb ground plane d. fspcb bottom layer figure 23. fspcb evaluation board four-layer pcb layout patterns AD9851/fspcb evaluation board parts listgso 0516(a) miscellaneous hardware ref . des. 1 amp 552742-1, 36-pin plastic, right angle, pc mount, female j1 1 banana jackCcolor not important j2 1 yellow banana jack j3 1 black banana jack j4 2 bnc coax. connector, pc mount j5, j6 1 AD9851/fspcb evaluation board gso 0516(a) none 4 amp 5-330808-6, open-ended pin socket none 2 #2-56 hex nut (to fasten j1) none 2 #2-56 3/8 binder head machine screw (to fasten j1) none 4 #4-40 hex nut (to fasten standoffs to board) none 4 #4 1 inch metal stand-off none miscellaneous hardware ref . des. decoupling capacitors 7 size 1206 chip capacitor, 0.1 m f c2Cc5, c8Cc10 2 tantalum capacitors, 10 m f c6, c7 1 size 1206 chip capacitor, 10 m fc1 resistors 1 25 w chip resistor, size 1206 r5 2 50 w chip resistor, size 1206 r2, r4 1 3.9 k w chip resistor, size 1206 r1 42 k w or 2.2 k w chip resistor, size 1206 r3, r8, r9, r10 21 k w chip resistor, size 1206 r6, r7 integrated circuits 1 AD9851 direct digital synthesizer, surface mount u1 2 74hct574an hcmos octal flip-flop, through-hole mount u2, u3
AD9851 C17C rev. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 11 1 strobe d0 d1 d2 d3 d4 d5 d6 d7 u2 74hct574 j1 c36cpr2 rrset 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe ffqud wwclk check strobe v cc y1 out gnd 7 8 14 +5v xtal osc (optional) r2 50 v j5 clkin remove when using y1 h1 #6 h2 #6 h3 #6 h4 #6 mounting holes r3 2.2k v strobe +5v wwclk ffqud rreset r11 2.2k v r9 2.2k v r10 2.2k v j2 +v j3 +5v j4 gnd banana jacks 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 voutp voutn r set avdd agnd refclock fq ud d3 d2 d1 d0 w clk pvcc pgnd vinn vinp dacbl avdd agnd ioutb iout d4 d5 d6 d7 reset dvdd dgnd u1 AD9851 +v gnd clkin fqud d3 d2 d1 d0 wclk +v gnd +v gnd d4 d5 d6 d7 reset +v gnd r5 100k v r12 j7 bnc r1 3.9k v 10ma reset c1 470pf e1 e2 r4 100k v e6 e5 r6 200 v c11 22pf c12 1pf l1 470nh c13 33pf c14 5.6pf l2 390nh c15 22pf c16 4.7pf l3 390nh c17 22pf r7 200 v 70mhz elliptical low pass filter 7th order 200 v z to bypass on board filter 1. remove e6 to e5 jumper 2. install appropriate r12 for iout termination r8 100 v j6 e4 e3 j8 bnc j9 bnc 9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q ck oe 11 1 strobe reset wclk fqud check u3 74hct574 rreset wwclk ffqud rreset AD9851/cgpcb clock generator evaluation board (ssop package) c2 0.1 m f c3 0.1 m f c4 0.1 m f c5 0.1 m f c8 0.1 m f c9 0.1 m f c10 0.1 m f +v +5v c6 10 m f c7 10 m f +v +5v +v c18 10 m f figure 24. cgpcb electrical schematic
AD9851 C18C rev. 0 a. cgpcb top layer c. cgpcb ground plane b. cgpcb power plane d. cgpcb bottom layer figure 25. cgpcb evaluation board four-layer pcb layout patterns
AD9851 C19C rev. 0 cgpcb evaluation board parts listgso 0515(b) miscellaneous hardware ref . des. 1 amp 552742-1, 36-pin plastic, right angle, pc mount, female j1 1 banana jackcolor not important j2 1 yellow banana jack j3 1 black banana jack j4 5 bnc coax. connector, pc mount j5, j6, j7, j8, j9 1 AD9851/cgpcb evaluation board gso 0515(b) none 4 amp 5-330808-6, open-ended pin socket none 2 #2-56 hex nut (to fasten j1) none 2 #2-56 3/8 binder head machine screw (to fasten j1) none 4 #4-40 hex nut (to fasten stand-offs to board) none 4 #4 1-inch metal stand-off none decoupling capacitors 1 size 1206, chip capacitor, 470 pf c1 7 size 1206 chip capacitor, 0.1 m f c2Cc5, c8Cc10 2 tantalum capacitors, 10 m f c6, c7 1 size 1206, chip capacitor, 10 m f c18 resistors 1 3.9 k w chip resistor, size 1206 r1 1 50 w chip resistor, size 1206 r2 42 k w or 2.2 k w chip resistor, size 1206 r3, r9, r10, r11 2 100 k w chip resistor, size 1206 r4, r5 2 200 w chip resistor, size 1206 r6, r7 1 100 w chip resistor, size 1206 r8 1 dummy resistor (for optional installation) r12 filter capacitors (70 mhz 7-pole elliptic filter) 3 22 pf chip capacitor, size 1206 c11, c15, c17 1 1 pf chip capacitor, size 1206 c12 1 33 pf chip capacitor, size 1206 c13 1 5.6 pf chip capacitor, size 1206 c14 1 4.7 pf chip capacitor, size 1206 c16 inductors (70 mhz 7-pole elliptic filter) 1 470 nh chip inductor, coil craft 1008cs l1 2 390 nh chip inductor, coil craft 1008cs l2, l3 integrated circuits 1 AD9851 direct digital synthesizer, surface mount u1 2 74hct574an hcmos octal flip-flop, through-hole mount u2, u3 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 0hz start 72mhz stop 7.2mhz/ rbw = 5khz vbw = 5khz swt = 7.2s rf att = 20db ref lvl = C7dbm 2ap figure 26. wideband (dc to 72 mhz) output sfdr for a 1.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s = +5 v. 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 0hz start 72mhz stop 7.2mhz/ rbw = 5khz vbw = 5khz swt = 7.2s rf att = 20db ref lvl = C7dbm figure 27. wideband (dc to 72 mhz) output sfdr for a 40.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s = +5 v. 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 0hz start 72mhz stop 7.2mhz/ rbw = 5khz vbw = 5khz swt = 7.2s rf att = 20db ref lvl = C7dbm figure 28. wideband (dc to 72 mhz) output sfdr for a 70.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s = +5 v.
AD9851 C20C rev. 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 1.1mhz center 200khz span 20khz/ rbw = 300hz vbw = 300hz swt = 11.5s rf att = 20db ref lvl = C7dbm figure 29. narrowband (1.1 0.1 mhz) output sfdr for a 1.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s = +5 v. 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 40.1mhz center 200khz span 20khz/ rbw = 300hz vbw = 300hz swt = 11.5s rf att = 20db ref lvl = C7dbm figure 30. narrowband (40.1 0.1 mhz) output sfdr for a 40.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s = +5 v. 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 2ap 70.1mhz center 200khz span 20khz/ rbw = 300hz vbw = 300hz swt = 11.5s rf att = 20db ref lvl = C7dbm figure 31. narrowband (70.1 0.1 mhz) output sfdr for a 70.1 mhz fundamental output signal. system clock = 180 mhz (6 refclk multiplier engaged), v s = +5 v. 1 ch1 200mv v t [] tek run 4.00gs/s sample m 12.5ns ch 1 C200mv d 200ps runs after d : 208ps @ : 1.940ns figure 32. typical cmos comparator p-p output jitter with the AD9851 configured as a clock generator, dds f out = 10.1 mhz, v s = +5 v, system clock = 180 mhz, 70 mhz lpf. graph details the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. cursors show 208 ps p-p jitter. 1 ch1 200mv v t [] tek run 4.00gs/s sample m 12.5ns ch 1 C200mv d 200ps runs after d : 204ps @ : 3.672ns figure 33. typical cmos comparator p-p output jitter with the AD9851 configured as a clock generator, dds f out = 40.1 mhz, v s = +5 v, system clock = 180 mhz, 70 mhz lpf. graph details the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. cursors show 204 ps p-p jitter.
AD9851 C21C rev. 0 1 ch1 200mv v t [] tek run 4.00gs/s sample d : 280ps @ : 2.668ns m 12.5ns ch 1 C200mv d 200ps runs after figure 34. typical cmos comparator p-p output jitter with the AD9851 configured as a clock generator, dds f out = 70.1 mhz, v s = +5 v, system clock = 180 mhz, 70 mhz lpf. graph details the center portion of a rising edge with scope in delayed trigger mode, 200 ps/div. cursors show 280 ps p-p jitter. frequency offset C hz C145 100 magnitude C Cdbc/hz 1k 10k 100k C135 C130 C125 C120 C115 C100 AD9851 phase noise C140 figure 35. output phase noise (5.2 mhz a out ), 6 refclk multiplier enabled, system clock = 180 mhz, reference clock = 30 mhz frequency offset C hz C155 100 magnitude C Cdbc/hz 1k 10k 100k C145 C140 C135 C130 C125 C120 AD9851 residual phase noise C150 figure 36. output residual phase noise (5.2 mhz a out ), 6 refclk multiplier disabled, system clock = 180 mhz, reference clock = 180 mhz system clock frequency C mhz 45 10 sfdr C Cdbc 20 40 60 80 100 120 140 160 180 50 55 60 65 70 75 v s = +3.3v v s = +5v fundamental output = system clock/3 figure 37. spurious-free dynamic range (sfdr) is gener- ally a function of the dac analog output frequency. ana- log output frequencies of 1/3 the system clock rate are considered worst case. plotted below are typical worst case sfdr numbers for various system clock rates. 1 ch1 100mv v t [] tek stop 2.50gs/s 22 acgs d : 2.0ns @ : 105.2ns c1 rise 2.03ns m 20.0ns ch 1 252mv d 5.00ns runs after figure 38. comparator rise time, 15 pf load 1 ch1 100mv v t [] tek stop 2.50gs/s 2227 acgs d : 2.3ns @ : 103.6ns c1 fall 2.33ns m 20.0ns ch 1 252mv d 5.00ns runs after figure 39. comparator fall time, 15 pf load
AD9851 C22C rev. 0 analog output frequency C mhz 30 10 supply current C ma 20 30 40 50 60 070 50 70 80 90 110 120 v s = +3.3v v s = +5v 100 60 40 figure 40. supply current variation with analog output frequency at 180 mhz system clock (upper trace) and 125 mhz system clock (lower trace). system clock C mhz 0 140 supply current C ma 20 40 60 100 80 120 0 20 40 60 80 100 120 v s = +3.3v v s = +5v 160 180 figure 41. supply current variation with system clock frequency. maximum dac i out C ma 40 5 sfdr C Cdbc 10 15 20 45 50 55 60 65 70 1.1mhz 40.1mhz 70.1mhz figure 42. effect of dac maximum output current on wideband (0 to 72 mhz) sfdr at three representative dac output frequencies: 1.1 mhz, 40.1 mhz and 70.1 mhz. v s = +5 v, 180 mhz system clock (6 refclk multiplierr dis- abled). currents are set using appropriate values of r set . input frequency C mhz 0 0 p-p amplitude C mv 20 40 60 80 100 120 140 160 100 200 300 400 500 600 v s = +3.3v v s = +5v figure 43. minimum p-p input signal needed to toggle the AD9851 comparator output. comparator input is a sine wave compared with a fixed voltage threshold. use this data in addition to sin(x)/x roll-off and any filter losses to determine if adequate signal is being presented to the AD9851 comparator.
AD9851 C23C rev. 0 28-lead shrink small outline package (rs-28) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558)

▲Up To Search▲

Price & Availability of AD9851

	To Download AD9851 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .