855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 1 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary g eneral d escription the ICS855011 is a low skew, high perfor- mance 1-to-2 differential-to-2.5v/3.3v cml fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the ICS855011 is characterized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ICS855011 ideal for those clock distribution applications demanding well defined performance and repeatability. f eatures ? 2 differential 2.5v/3.3v cml outputs ? 1 differential pclk, npclk input pair ? pclk, npclk pair can accept the following differential input levels: lvpecl, lvds, cml, sstl ? output frequency: >3ghz ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on npclk input ? output skew: 5ps (typical) ? part-to-part skew: tbd ? propagation delay: 242ps (typical) ? operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? -40c to 85c ambient operating temperature b lock d iagram p in a ssignment ICS855011 8-lead soic 3.90mm x 4.90mm x 1.37mm package body m package top view q0 nq0 q1 nq1 1 2 3 4 hiperclocks? ics vcc pclk npclk v ee 8 7 6 5 q0 nq0 q1 nq1 pclk npclk the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 2 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l m c . r i a p t u p t u o l a i t n e r e f f i d 4 , 31 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i l m c . r i a p t u p t u o l a i t n e r e f f i d 5v e e r e w o p. n i p y l p p u s e v i t a g e n 6k l c p nt u p n ip u l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i 7k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d l c e p v l g n i t r e v n i - n o n 8v c c r e w o p. n i p y l p p u s e v i t i s o p : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 7k ? r p u l l u p r o t s i s e r p u l l u p t u p n i 5 7k ?
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 3 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary t able 3a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.8v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 5a m a bsolute m aximum r atings t able 3b. lvpecl dc c haracteristics , v cc = 2.375v to 3.8v; v ee = 0v note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v (cml mode, v ee = 0) inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 20ma surge current 40ma operating temperature range , ta -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 112.7c/w (0 lfpm) (junction-to-ambient) t able 3c. cml dc c haracteristics , v cc = 2.375v to 3.8v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 0 2 0 . 0 -v c c 0 1 0 . 0 -v c c v v t u o g n i w s e g a t l o v t u p t u o 5 2 30 0 4v m v t u o _ f f i d g n i w s e g a t l o v t u p t u o l a i t n e r e f f i d 0 5 60 0 8v m r t u o e c n a d e p m i e c r u o s t u p t u o0 40 50 6 ? 0 0 1 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? . r i a p t u p t u o l a i t n e r e f f i d s s o r c a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c pv c c v = n i v 8 . 3 =0 5 1a k l c p nv c c v = n i v 8 . 3 =5a i l i t n e r r u c w o l t u p n i k l c pv c c v , v 8 . 3 = n i v 0 =5 -a k l c p nv c c v , v 8 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 01v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 1 +v c c v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c p n d n a k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 +
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 4 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary t able 4. ac c haracteristics , v cc = 0v; v ee = -3.8v to -2.375v or v cc = 2.375 to 3.8v; v ee = 0v l o b m y sr e t e m a r a pn o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 3 >z h g t d p ; ) l a i t n e r e f f i d ( ; y a l e d n o i t a g a p o r p 1 e t o n 2 4 2s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 5s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p d b ts p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 4 1s p c d oe l c y c y t u d t u p t u o 0 5s p t a d e z i r e t c a r a h c s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u z h g 1 r l 0 0 1 = ? . r i a p t u p t u o h c a e r e t f a . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 5 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary p arameter m easurement i nformation o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew p art - to -p art s kew o utput r ise /f all t ime p ropagation d elay v cmr cross points v pp v ee npclk v cc pclk t sk(pp) t sk(o) nqx qx nqy qy pa r t 1 pa r t 2 nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v swing t pd npclk q0, q1 nq0, nq1 pclk o utput d uty c ycle /p ulse w idth /p eriod pulse width t period t pw t period odc = q0, q1 nq0, nq1 scope nqx qx power supply v ee v cc float gnd gnd 3.3v 5% or 2.5v 5% cml with internal pullup + -
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 6 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary a pplication i nformation f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels vcc r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609.
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 7 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver ter- mination requirements. f igure 2a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 2b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 2c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 2f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 2e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 2d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 8 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary r eliability i nformation t ransistor c ount the transistor count for ICS855011 is: 109 t able 6. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 9 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary p ackage o utline - m s uffix for 8 l ead soic t able 7. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
855011am www.icst.com/products/hiperclocks.html rev. a august 18, 2004 10 integrated circuit systems, inc. ICS855011 l ow s kew , 1- to -2 d ifferential - to -2.5v/3.3v cml f anout b uffer preliminary t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t m a 1 1 0 5 5 8 s c ia 1 1 0 5 5 8c i o s d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - t m a 1 1 0 5 5 8 s c ia 1 1 0 5 5 8l e e r d n a e p a t n o c i o s d a e l 80 0 5 2c 5 8 o t c 0 4 - the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.
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