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password access security supervisor ?icor, inc. 1994, 1995, 1996 patents pending 7002-2.2 4/30/97 t3/c0/d0 sh 1 characteristics subject to change without notice 4k x76f041 4 x 128 x 8 bit pass tm secureflash features 64-bit password security three password modes secure read access secure write access secure con?uration access programmable con?uration read, write and con?uration access passwords multiple array access/functionality retry register/counter 8 byte sector write (4) 1k memory arrays iso response to reset low power cmos ?0 m a standby current 3ma active current 1.8v to 3.6v or 5v ?nivolt read and program power supply versions high reliability endurance: 100,000 cycles data retention: 100 years esd protection: 2000v on all pins description the x76f041 is a password access security supervisor device, containing four 128 x 8 bit secureflash arrays. access can be controlled by three 64-bit programmable passwords, one for read operations, one for write opera- tions and one for device con?uration. the x76f041 features a serial interface and software protocol allowing operation on a simple two wire bus. the bus signals are a clock input (scl) and a bidirectional data input and output (sda). access to the device is con- trolled through a chip select input (cs ), allowing any number of devices to share the same bus. the x76f041 also features a synchronous response to reset; providing an automatic output of a pre-con?ured 32-bit data stream conforming to the iso standard for memory cards. the x76f041 utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. functional diagram interface logic chip enable (4) 16 x 64 secureflash arrays 180?ff 100?7f 080?ff 000?7f sda scl rst cs 7002 ill f01 data transfer array access enable password array and password verification logic iso reset response data register configuration register retry counter a pplication n ote a v a i l a b l e an83 ?development tools xk76c
x76f041 2 pin description serial data input/output (sda) sd a is a tr ue three state ser ial data input/output pin. dur ing a read cycle , data is shifted out on this pin. dur ing a wr ite cycle , data is shifted in on this pin. in all other cases this pin is in a high impedance state . serial clock (scl) the ser ial cloc k controls the ser ial b us timing f or data input and output. chip select ( cs ) when cs is high, the x76f041 is deselected and the sd a pin is at high impedance and unless an inter nal wr ite oper ation is underw a y the x76f041 will be in the standb y po w er mode . cs lo w enab les the x76f041, placing it in the activ e po w er mode . reset (rst) rst is a de vice reset pin. when rst is pulsed high while cs is lo w the x76f041 will output 32 bits of x ed data which conf or ms to the iso standard f or ?ynchronous response to reset? cs m ust remain lo w and the par t m ust not be in a wr ite cycle f or the response to reset to occur . if at an y time dur ing the response to reset cs goes high, the response to reset will be abor ted and the par t will retur n to the standb y mode . pin configuration 7002 frm t01 symbol description cs chip select input sda serial data input/output rst reset input scl serial clock input v ss ground v cc supply voltage nc no connect 7002 ill f02 v cc rst scl nc 1 2 3 4 8 7 6 5 v ss cs sda nc x76f041 dip/soic
x76f041 3 device operation there are three pr imar y modes of oper ation f or the x76f041; read , write and configura tion. the read and write modes ma y be perf or med with or without an 8-b yte pass w ord. the configura tion mode alw a ys requires an 8-b yte pass w ord. the basic method of comm unication is estab lished b y rst enab ling the de vice ( cs lo w), gener ating a star t condition and then tr ansmitting a command and address eld f ollo w ed b y the correct pass w ord (if con gured to require a pass w ord). all par ts will be shipped from the f actor y in the non-pass w ord mode . the user m ust per- f or m an a ck p olling routine to deter mine the v alidity of the pass w ord and star t the data tr ansf er (see ac kno wl- edge p olling). only after the correct pass w ord is accepted and an a ck p olling has been perf or med can the data tr ansf er occur . t o ensure correct comm unication, rst m ust remain lo w under all conditions e xcept when initiating a ?esponse to reset sequence? figure 1. x76f041 device operation data is tr ansf erred in 8-bit segments , with each tr ansf er being f ollo w ed b y an a ck, gener ated b y the receiving de vice . if the x76f041 is in a non v olatile wr ite cycle a ?o a ck (sd a high) response will be issued in response to load- ing of the command + high order address b yte . if a stop condition is issued pr ior to the non v olatile wr ite cycle the wr ite oper ation will be ter minated and the par t will reset and enter into a standb y mode . the basic sequence is illustr ated in figure 1. after each tr ansaction is completed, the x76f041 will reset and enter into a standb y mode . this will also be the response if an attempt is made to access an y limited arr a y . password registers the three pass w ords , read, wr ite and con gur ation are stored in three 64 bit wr ite only registers as illus- tr ated in gure 2. figure 2. password registers device configuration fiv e 8-bit con gur ation registers are used to con gure the x76f041. these are sho wn in gure 3. figure 3. configuration registers load low order address / configuration instruction byte load 8?yte password (if applicable) verify password acceptance by use of ack polling (if applicable) read / write data bytes load command+high order address byte 7002 ill f03 64 bit write password 64 bit read password 64 bit configuration password 63 0 7002 ill f04 acr1 acr2 cr rr rc res res res reserved retry register configuration register array control register 2 array control register 1 retry counter 7002 ill f04b 63 0
x76f041 4 array control the f our 1k arr a ys , are each prog r ammab le to diff erent le v els of access and functionality . each arr a y can be pro- g r ammed to require or not require the read/wr ite pass- w ords . the functional options are: read and wr ite access . read access with all wr ite oper ations loc k ed out. read access and prog r am only (wr iting a ? to a ??. if an attempt to change a ? to a ? occurs the x76f041 will reset, issue a ?o a ck and enter the standb y po w er mode . no read or wr ite access to the memor y . access only through use of the con gur ation pass w ord. array map 8 bit array control register 1 8 bit array control register 2 functional bits 7002 frm t02 z t functionality 0 0 read and write unlimited 1 0 read only, write limited 0 1 program & read only, erase limited 1 1 no read or write, fully limited addresses 000 07f (hex) addresses 080 0ff (hex) addresses 100 17f (hex) addresses 180 1ff (hex) first ?k second ?k third ?k fourth ?k high-order addresses 7002 ill f04a x2 y2 z2 t2 x1 y1 z1 t1 second 1k first 1k access function access function msb lsb 7002 ill f05a x4 y4 z4 t4 x3 y3 z3 t3 upper 1k third 1k access function access function msb lsb 7002 ill f05b access bits 7002 frm t03 8-bit configuration register unauthorized access bits (ua1, ua2): 1 0 access is f orbidden if retr y register equals the retr y counter (pro vided that the retr y counter is enab led) and no fur ther access of an y kind will be allo w ed. 0 1, 0 0, 1 1 only con gur ation oper ations are allo w ed if the retr y reg- ister equals the retr y counter (pro vided that the retr y counter is enab led). retry counter reset bit (rcr): if the retr y counter reset bit is a ? then the retr y counter will be reset f ollo wing a correct pass w ord, pro vided the retr y counter is enab led. if the retr y counter reset bit is a ? then the retr y counter will not be reset f ollo wing a correct pass w ord, pro vided the retr y counter is enab led. retry counter enable bit (rce): if the retr y counter enab le bit is a ?? then the retr y counter is enab led. an initial compar ison betw een the retr y register and retr y counter deter mines whether the n umber of allo w ed incorrect pass w ord attempts has been reached. if not, the protocol contin ues and in case of a wrong pass w ord, the retr y counter is incremented b y one . if the pass w ord is correct then the retr y counter will either be reset or unchanged, depending on the reset bit. x y read password write password 0 0 not required not required 1 0 not required required 0 1 required not required 1 1 required required ua1 ua2 1 0 rcr rce 0 0 reserved retry counter reset reserved reserved unauthorized access bit 2 retry counter enable unauthorized access bit 1 msb lsb 7002 ill f06
x76f041 5 the retr y register m ust ha v e a higher v alue than the retr y counter f or correct de vice oper ation. if the retr y counter v alue is larger than the retr y register and the retr y counter is enab led, the de vice will wr ap around allo wing up to an additional 255 incorrect access attempts . if the retr y counter enab le bit is a ?? then the retr y counter is disab led. retry register/counter both the retr y register and retr y counter are accessib le in the con gur ation mode and ma y be prog r ammed with a v alue of 0 to 255. the diff erence betw een the retr y register and the retr y counter is the n umber of access attempts allo w ed, there- f ore the retr y counter m ust be prog r ammed to a smaller v alue than the retr y register to pre v ent wr ap around. device protocol the x76f041 suppor ts a bidirectional b us or iented pro- tocol. the protocol de nes an y de vice that sends data onto the b us as a tr ansmitter , and the receiving de vice as the receiv er . the de vice controlling the tr ansf er is a mas- ter and the de vice being controlled is the sla v e . the mas- ter will alw a ys initiate data tr ansf ers , and pro vide the cloc k f or both tr ansmit and receiv e oper ations . theref ore , the x76f041 will be considered a sla v e in all applica- tions . start condition all commands e xcept f or response to reset are preceded b y the star t condition, which is a high to lo w tr ansition of sd a when scl is high. the x76f041 contin uously monitors the sd a and scl lines f or the star t condition and will not respond to an y command until this condition has been met. figure 4. data validity during write figure 5. definition of start and stop no te: the par t requires the scl input to be lo w dur ing non-activ e per iods of oper ation. in other w ords , the scl will need to be lo w pr ior to an y st ar t condition and lo w after a st op condition. this is also re ected in the timing diag r am. scl sda data stable data change 7002 ill f07 scl sda st ar t bit st op bit 7002 ill f08
x76f041 6 stop condition all comm unications m ust be ter minated b y a stop condi- tion, which is a lo w to high tr ansition of sd a when scl is high. a stop condition can only be issued after the tr ansmitting de vice has released the b us . acknowledge ac kno wledge is a softw are con v ention used to indicate successful data tr ansf er . the tr ansmitting de vice , either master or sla v e , will release the b us after tr ansmitting eight bits . dur ing the ninth cloc k cycle the receiv er will pull the sd a line lo w to ac kno wledge that it receiv ed the eight bits of data. operational modes 7002 frm t04 the first byte in the protocol the second byte in the protocol command description password used: 0 0 0xxxxa write address write (sector) write 0 0 1xxxxa read address read (random / sequential) read 0 1 0xxxxa write address write (sector) configuration 0 1 1xxxxa read address read (random / sequential) configuration 1 0 0xxxxx 0 0 0 0 0 0 0 0 program write-password write 1 0 0xxxxx 0 0 0 1 0 0 0 0 program read-password read 1 0 0xxxxx 0 0 1 0 0 0 0 0 program configuration-password configuration 1 0 0xxxxx 0 0 1 1 0 0 0 0 reset write password (all 0?) configuration 1 0 0xxxxx 0 1 0 0 0 0 0 0 reset read password (all 0?) configuration 1 0 0xxxxx 0 1 0 1 0 0 0 0 program configuration registers configuration 1 0 0xxxxx 0 1 1 0 0 0 0 0 read configuration registers configuration 1 0 0xxxxx 0 1 1 1 0 0 0 0 mass program configuration 1 0 0xxxxx 1 0 0 0 0 0 0 0 mass erase configuration all the rest reserved
x76f041 7 write operation sector write the sector wr ite mode requires issuing the 3-bit wr ite command f ollo w ed b y the address , pass w ord if required and then the data b ytes tr ansf erred as illustr ated in fig- ure 6. eight b ytes m ust be tr ansf erred. after the last b yte to be tr ansf erred is ac kno wledged, a stop condition is issued, which star ts the non v olatile wr ite cycle . if more than 8 b ytes are tr ansf erred the data will wr ap around and pre vious data will be o v erwr itten. all data will be wr it- ten to the same sector as de ned b y a 8 ? 3 . figure 6. sector write s t a r t s c m d a x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k write password 7 a c k a c k a c k a c k write password 0 wait t wc /ack polling data 0 a c k a c k s t o p sda line if password match then s data 7 wait t wc data 1 data 2 a c k a c k a c k 7002 ill f10.1
x76f041 8 ack polling once a stop condition is issued to indicate the end of the host s wr ite sequence , the x76f041 initiates the inter nal non v olatile wr ite cycle . in order to tak e adv antage of the typical 5ms wr ite cycle , a ck polling can be initiated immediately . this in v olv es issuing the star t condition f ol- lo w ed b y the ne w command code of eight bits (1st b yte of the protocol). if the x76f041 is still b usy with the non v ol- atile wr ite oper ation, it will issue a ?o a ck in response . if the non v olatile wr ite oper ation has completed, an ? ck will be retur ned and the host can then proceed with the rest of the protocol. ref er to the f ollo wing o w: ack polling sequence 7002 ill f12a write sequence completed enter ack polling issue a start issue new command code (1st byte) ack returned proceed no ack (sda high) yes (sda low) after a pass w ord sequence , there is alw a ys a non v olatile wr ite cycle . in order to contin ue the tr ansaction, the x76f041 requires the master to perf or m an a ck polling with the speci c code of c0h. as with regular ac kno wl- edge polling the user can either time out f or 10ms , and then issue the a ck polling once , or contin uously loop as descr ibed in the o w . as with regular ac kno wledge polling, if the user chooses to loop , then as long as the non v olatile wr ite cycle is activ e , a no a ck will be issued in response to each poll- ing cycle . if the pass w ord that w as inser ted w as correct, then an ? ck will be retur ned once the non v olatile wr ite cycle is o v er , in response to the a ck polling cycle immediately f ollo wing it. if the pass w ord that w as inser ted w as incorrect, then a ?o a ck will be retur ned e v en if the non v olatile wr ite cycle is o v er . theref ore , the user cannot be cer tain that the pass w ord is incorrect until the 10ms wr ite cycle time has elapsed. figure 7. acknowledge polling scl sda 8th clk. of 8th pwd. byte ?ck clk 8th clk ack clk 8th bit ?ck ack or no ack start condition 7002 ill f11
x76f041 9 read operation random read with password random read with pass w ord oper ations are initiated with a st ar t command f ollo w ed b y the read command and the address of the rst b yte of the b loc k in which data is to be read: bloc k 0 = 000h bloc k 1 = 080h bloc k 2 = 100h bloc k 3 = 180h this is f ollo w ed b y the eight b yte read pass w ord sequence which includes the 10ms w ait time and the pass w ord ac kno wledge polling sequence . if the pass- w ord is accepted an ? ck will be retur ned f ollo w ed b y eight bits of ?ecure read setup which is to be ignored. at this point a st ar t is issued f ollo w ed b y the address and data to be read within the or iginal 1k b loc k. see gure 8. once the rst b yte has been read, another star t can be issued f ollo w ed b y a ne w 8-bit address . random reads are allo w ed only within the or iginal 1k-bit b loc k. t o access another 1k-bit b loc k, a stop m ust be issued f ol- lo w ed b y a ne w command/b loc k address/pass w ord sequence . figure 8. random read with password s t a r t s c m d a x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k read password 7 a c k a c k a c k a c k read password 0 secure read setup a c k s t a r t sda line if password match then data 0 a c k s t a r t s s 7 00 2 ill f1 3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 wait t wc /ack polli n a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 1 a c k s t o p s first byte block address x x x x x x x x
x76f041 10 random read without password random read oper ations without a pass w ord do not require the rst b yte b loc k initiation address . t o perf or m a r andom read without pass w ord, a st ar t is f ollo w ed b y the read command plus address location of the b yte to be read. this is f ollo w ed b y an ? ck and the eight bits of data to be read. other b ytes within the same 1k-bit b loc k ma y be read b y issuing another st ar t f ollo w ed b y a ne w 8-bit address as sho wn in gure 9. sequential read once past the pass w ord acceptance sequence (when required) and ?ecure read setup? the host can read sequentially within the or iginally addressed 1k-bit arr a y . the data output is sequential, with the data from address n f ollo w ed b y the data from address n+1. the address counter f or read oper ations increments the address , allo wing the 1k memor y contents to be ser ially read dur- ing one oper ation. at the end of the address space (address 127), the counter ?olls o v er to address space 0 within the 1k bloc k and the x76f041 contin ues to output data f or each ac kno wledge receiv ed. ref er to gure 10 f or the address , ac kno wledge and data tr ansf er sequence . an ac kno wledge m ust f ollo w each 8-bit data tr ansf er . after the last bit has been read, a stop condition is gener ated without a preceding ac kno wledge . figure 9. random read without password figure 10. sequential read with password s t a r t s c m d a x a x a x a x a 8 a c k a c k sda line a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 0 s t a r t s 7002 ill f13a.2 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 1 a c k s t o p s s t a r t s c m d a x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k read password 7 a c k a c k a c k a c k read password 0 wait t wc /ack polling secure read setup a c k s t a r t s t o p sda line if password match then s data x data 0 a c k a c k 7002 ill f12.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 1 s x x x x x x x x first byte block address
x76f041 11 configuration operations con gur ation commands gener ally require the con gu- r ation pass w ord. the e xception is that prog r amming a ne w read/wr ite pass w ord requires the old read/wr ite pass w ord and not the con gur ation pass w ord. in most cases these oper ations will be perf or med b y the equip- ment man uf acturer or end distr ib utor of the equipment or card. configuration read/write con gur ation read/wr ite allo ws access to all of the non- v olatile memor y arr a ys regardless of the contents of the con gur ation registers . access includes sector wr ites , r andom and sequential reads using the same f or mat as nor mal reads and wr ites . in gener al, the con gur ation read/wr ite oper ation enab les access to an y memor y location that ma y otherwise be limited. the con gur ation pass w ord, in this sense , is lik e a master k e y that can o v err ide the limits caused b y the control par titioning of the arr a ys . figure 11. configuration write figure 12. configuration sequential read s t a r t s c m d a x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling data 0 a c k a c k s t o p sda line if password match then s data x wait t wc data 1 data 2 a c k a c k 7002 ill f14.1 a c k s t a r t s c m d a x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling secure read setup a c k s t a r t s t o p sda line if password match then s data x data 0 a c k a c k 7002 ill f15.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s data 1 first byte block address x x x x x x x x
x76f041 12 configuration of passwords the sequence in gure 14 will change (prog r am) the wr ite , read and con gur ation pass w ords . the prog r am- ming of pass w ords is done twice pr ior to the non v olatile wr ite cycle in order to v er ify that the ne w pass w ord is consistent. after the eight b ytes are entered in the sec- ond pass , a compar ison tak es place . a mismatch will cause the par t to reset and enter into the standb y mode and a ?o a ck will be issued. there is no w a y to read the read/wr ite/con gur ation pass w ords . program configuration registers this mode allo ws prog r amming of the v e con gur ation/ control registers using the con gur ation pass w ord. the retr y counter m ust be prog r ammed with a v alue less than the retr y register . if it is prog r ammed with a v alue larger than the retr y register there will be a wr ap around. read configuration registers this mode allo ws reading of the 5 con gur ation/control registers with the con gur ation pass w ord. it ma y be use- ful f or monitor ing pur poses . figure 13. configuration random read figure 14. program passwords s t a r t s c m d a x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling secure read setup a c k s t a r t sda line if password match then s a c k 7002 ill f16.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 first byte block address data 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s t a r t s a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k data 1 s t o p s x x x x x x x x s t a r t s c m d a x a x a x a x a 8 a c k old password 7 a c k a c k a c k old password 0 wait t wc /ack polling new password 7 a c k a c k sda line if password match then new password 7 new password 0 a c k a c k read/write/ configuration instruction s t o p s new password 0 wait t wc a c k a c k 7002 ill f17.1
x76f041 13 read password reset this mode allo ws resetting of the read pass w ord to all ?? in case re-prog r amming is needed and the old pass- w ord is not kno wn. write password reset this mode allo ws resetting of the write pass w ord to all ?? in case re-prog r amming is needed and the old pass- w ord is not kno wn. mass program this mode allo ws mass prog r amming of the arr a y , con- gur ation registers and pass w ord to all ?? using a spe- cial con gur ation command. all par ts are shipped mass prog r ammed. mass erase this mode allo ws mass er ase of the arr a y , con gur ation register and pass w ord to all ?? using a special con gu- r ation command. figure 15. program configuration registers figure 16. read configuration registers s t a r t s c m d a x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling bcr 1 byte a c k a c k s t o p sda line if password match then s bcr 2 byte cr byte a c k a c k configuration instruction rc byte a c k a c k wait t wc rr byte 7002 ill f18.1 s t a r t s c m d a x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling bcr 1 byte a c k a c k s t o p sda line if password match then s bcr 2 byte cr byte a c k a c k rc byte a c k rr byte 7002 ill f19.1 configuration instruction
x76f041 14 absolute maximum ratings* t emper ature under bias ..................... ?5 c to +135 c stor age t emper ature .......................... ?5 c to +150 c v oltage on an y pin with respect to v ss ..................................... ?v to +7v d .c . output current ................................................. 5ma lead t emper ature (solder ing, 10 seconds) ................................. 300 c *comment stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those listed in the oper ational sections of this speci cation is not implied. exposure to absolute maxim um r ating condi- tions f or e xtended per iods ma y aff ect de vice reliability . figure 17. read/write password reset figure 18. mass program/erase symbol table s t a r t s c m d a x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc sda line configuration instruction s s t o p 7002 ill f20.1 wait t wc /ack polling s t a r t s c m d a x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc sda line configuration instruction s s t o p 7002 ill f20a.1 wait t wc /ack polling w a veform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x76f041 15 recommended operating conditions 7002 frm t05 7002 frm t06.1 temp min. max. commercial 0 c +70 c extended ?0 c +85 c supply voltage limits x76f041 4.5v to 5.5v x76f041 ?3 3v to 3.6v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) 7002 frm t07.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v 7002 frm t08 no tes: (1) must perf or m a stop command after a read command pr ior to measurement (2) v il min. and v ih max. are f or ref erence only and are not tested. (3) this par ameter is per iodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 2 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 1mhz, sda = open rst = cs = v ss i cc2 (3) v cc supply current (write) 3 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 1mhz, sda = open rst = cs = v ss i sb1 (1) v cc supply current (standby) 100 m a scl = v ss , cs = v cc ?0.3v sda = open, rst = v cc = 5.5v i sb2 (1) v cc supply current (standby) 50 m a scl = v ss , cs = v cc ?0.3v sda = open, rst = v ss , v cc = 3v i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v il1 (2) input low voltage ?.5 v cc x 0.3 v v cc = 5.5v v ih1 (2) input high voltage v cc x 0.7 v cc + 0.5 v v cc = 5.5v v il2 (2) input low voltage ?.5 v cc x 0.1 v v cc = 3.0v v ih2 (2) input high voltage v cc x 0.9 v cc + 0.5 v v cc = 3.0v v ol output low voltage 0.4 v i ol = 2ma v oh output high voltage v cc ?0.8 v i oh = ?ma symbol test max. units conditions c out (3) output capacitance (sda) 10 pf v i/o = 0v c in (3) input capacitance (rst, scl, cs ) 10 pf v in = 0v equivalent a.c. load circuit a.c. test conditions 7002 frm t09 3v 1.3k w output 100pf 7002 ill f21.1 5v 2.3k w output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf
x76f041 16 a.c. characteristics (over recommended operating conditions, unless otherwise specified) read & write cycle limits 7002 frm t10 no tes: (4) this par ameter is per iodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 1 mhz ti noise suppression time constant at scl & sda inputs 20 ns t dv scl high to sda data valid 450 ns t low clock low period 500 ns t high clock high period 500 ns t stas1 start condition setup time to rising edge of scl 150 ns t stas2 start condition setup time to falling edge of scl 150 ns t stah1 start condition hold time to rising edge of scl 50 ns t stah2 start condition hold time to falling edge of scl 50 ns t stps1 stop condition setup time to rising edge of scl 150 ns t stps2 stop condition setup time to falling edge of scl 150 ns t stph1 stop condition hold time to rising edge of scl 50 ns t stph2 stop condition hold time to falling edge of scl 50 ns t hd:dat data in hold time 10 ns t su:dat data in setup time 150 ns t rscl (4) scl rise time 90 ns t fscl (4) scl fall time 90 ns t r (4) sda, cs , rst rise time 90 ns t f (4) sda, cs , rst fall time 90 ns t dh data out hold time 0 ns t hz1 scl low to high impedance 150 ns t lz scl high to output active 0 ns t vccs v cc to cs setup time 5 ms t su:cs cs setup time 200 ns t hd:cs cs hold time 100 ns t hz2 cs deselect time 150 ns t su:scl scl setup time to cs low after power up 200 ns t rst rst high time 1500 ns t su:rst rst setup time 500 ns f scl:rst scl frequency during response to reset 1 mhz t low:rst scl low time during response to reset 500 ns t high:rst scl high time during response to reset 500 ns t pd scl low to sda valid during response to reset 450 ns t nol rst to scl non-overlap 500 ns t wc nonvolatile write cycle 10 ms
x76f041 17 bus timing (1) ?sda driven by the bus master bus timing (2) ?sda driven by the slave start condition timing no tes: (1) the master ma y issue a st op condition at an y giv en time in which it is dr iving the sd a line . in other w ords , when the par t is sending a ck or data the master ma y no t issue a st op condition. the par t will not respond to an y such attempt which also causes b us con- tention. at an y other time , a st op condition will cause the par t to reset and stop (enter a stand-b y mode). wr ite oper ations will ter mi- nate pr ior to enter ing the stand-b y mode . (2) when the par t dr iv es the sd a line , it will tr i-state the b us only after the last bit of the sequence . in other w ords , after the 8th bit of a b yte that is read or after a ck betw een incoming b ytes . in all other cases when the par t dr iv es the b us (betw een successiv e bits) it will con- tin ue to dr iv e the b us also dur ing the cloc k lo w per iods . scl sda (in) from master t fscl t rscl t low t high t su:dat t hd:dat t f t r start bit 7002 ill f22 1st clock pulse of sequence t dh t dv t lz t hz1 7002 ill f23 last clock pulse of sequence scl sda (out) from slave scl t stas1 t stah1 t stas2 t stah2 start bit 7002 ill f24 sda (in) from master
x76f041 18 stop condition timing acknowledge response from slave (same timing as data out) acknowledge response from master cs timing diagram (selecting/deselecting the part) scl t stps1 t stph1 t stps2 t stph2 stop bit 7002 ill f25 sda (in) from master scl sda (out) from slave (acknowledge) t lz t dv t dh t hz1 7002 ill f26 scl sda (out) from master (acknowledge) t su:dat t hd:dat 7002 ill f27 scl t su:cs t hd:cs cs from master 7002 ill f28
x76f041 19 v cc to cs setup timing diagram cs deselect rst timing diagram ?response to a synchronous reset (iso) no tes: (1) the reset oper ation results in an ans w er from the par t containing a header tr ansmitted from the par t to the master . the header has a x ed length of 32 bits and begins with tw o mandator y elds of eight bits : h1 and h2. (2) the chronological order of tr ansmission of the inf or mation bits shall correspond to bit identi cation b1 to b32 with the least signi cant bit tr ansmitted rst. (3) the current v alues are: h1 : 19 h h2 : 55 h h3 : aa h h4 : 55 h vcc cs t su:scl v ccmin t su:cs scl t vccs 7002 ill f29 cs sda (out) from slave t hz2 7002 ill f29a scl sda t nol t pd (low) 1st data bit 2nd data bit cs rst t rst 1st clk. pulse 2nd clk. pulse 3rd clk. pulse t su:rst t high_rst f scl_rst t low_rst t pd 7002 ill f30
x76f041 20 note: 1. all dimensions in inches (in p arentheses in millimeters) 2. p ackage dimensions exclude molding flash 0.020 (.508) 0.012 (.305) .080 (2.03) .070 (1.78) .213 (5.41) .205 (5.21) 0 8 .330 (8.38) .300 (7.62) .212 (5.38) .203 (5.16) .035 (.889) .020 (.508) .010 (.254) .007 (.178) ref pin 1 id .050 (1.27) bsc 8-lead plastic, 0.200?wide small outline gullwing package typ ??(eiaj soic) .013 (.330) .004 (.102) 3926 ill f33.1 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
x76f041 21 x76f041 x x ? ordering information v cc limits blank = 5v 10% 3 = 3v to 3.6v temperature range blank = commercial = 0 c to +70 c e = extended = ?0 c to +85 c package p = 8-lead plastic dip a = 8-lead soic (eiaj) h = die in waffle packs w = die in wafer form device limited w arranty de vices sold b y xicor , inc. are co v ered b y the w arr anty and patent indemni cation pro visions appear ing in its t er ms of sale only . xicor , inc. mak es no w arr anty , e xpress , statutor y , implied, or b y descr iption regarding the inf or mation set f or th herein or regarding the freedom of the descr ibed de vices from patent infr ingement . xicor , inc. mak es no w arr anty of merchantability or tness f or an y pur pose . xicor , inc. reser v es the r ight to discontin ue production and change speci cations an d pr ices at an y time and without notice . xicor , inc. assumes no responsibility f or the use of an y circuitr y other than circuitr y embodied in a xicor , inc. product. no other circuits , patents , licenses are implied. u .s. p a tents xicor products are co v ered b y one or more of the f ollo wing u .s . p atents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. f oreign patents an d additional patents pending. life rela ted policy in situations where semiconductor component f ailure ma y endanger lif e , system designers using this product should design the system with appropr iate error detec - tion and correction, redundancy and bac k-up f eatures to pre v ent such an occurence . xicor s products are not author iz ed f or use in cr itical components in lif e suppor t de vices or systems . 1. lif e suppor t de vices or systems are de vices or systems which, (a) are intended f or surgical implant into the body , or (b) suppor t or sustain lif e , and whose f ailur e to perf or m, when proper ly used in accordance with instr uctions f or use pro vided in the labeling, can be reasonab ly e xpected to result in a signi cant injur y to th e user . 2. a cr itical component is an y component of a lif e suppor t de vice or system whose f ailure to perf or m can be reasonab ly e xpected to cause the f ailure of the lif e sup - por t de vice or s y stem, or to aff ect its saf et y or eff ectiv eness .

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