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september 2012 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 fsl206mr ? green mode fairchild power switch (fps?) fsl206mr green mode fairchild power switch (fps?) features ? internal avalanche-rugged sensefet: 650v ? precision fixed oper ating frequency: 67khz ? no-load <150mw at 265v ac without bias winding; <25mw with bias winding for fsl206mr, <30mw with bias winding for FSL206MRBN ? no need for auxiliary bias winding ? frequency modulation for attenuating emi ? line under-voltage protection (luvp) ? pulse-by-pulse current limiting ? low under-voltage lockout (uvlo) ? ultra-low operating current: 300a ? built-in soft-start and startup circuit ? various protections: overload protection (olp), over-voltage protection (ovp), thermal shutdown (tsd), abnormal over-current protection (aocp) auto-restart mode for all protections applications ? smps for stb, dvd, and dvcd player ? smps for auxiliary power description the fsl206mr integrated pu lse-width modulator (pwm) and sensefet is specifically designed for high- performance offline switched-mode power supplies (smps) while minimizing external components. this device integrates high-vo ltage power regulators that combine an avalanche-rugged sensefet with a current-mode pwm control block. the integrated pwm controller includes: a 7.8v regulator, eliminating the need for auxilliary bias winding; under-voltage lock out (uvlo) protection; leading-edge blanking (leb); an optimized gate turn- on/turn-off driver; emi attenuator; thermal shutdown (tsd) protection; temperat ure-compensated precision current sources for loop com pensation; soft-start during startup; and fault-pr otection circuitry such as overload protection (olp), over-v oltage protection (ovp), abnormal over-current protection (aocp), and line under-voltage protection (luvp). the internal high-voltage st artup switch and the burst- mode operation with very lo w operating current reduce the power loss in standby mode. as a result, it is possible to reach a power loss of 150mw with no bias winding and 25mw (for fs l206mr) or 30mw (for FSL206MRBN) with a bias winding under no-load conditions when the input voltage is 265v ac . related resources ? fairchild power supply webdesigner ? flyback design and simulation ? in minutes at no expense ? an-4137 ? design guidelines for offline flyback converters using fps? ? an-4141 ? troubleshooting and design tips for fairchild power switch (fps?) flyback applications ? an-4147 ? design guidelines for rcd snubber of flyback ? an-4150 ? design guidelines for flyback converters using fsq-series fairchild power switch (fps?)
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 2 fsl206mr ? green mode fairchild power switch (fps?) ordering information part number operating temperature top mark pkg packing method output power table (1) current limit r ds(on),max 230v ac 15% (2) 85 ~ 265v ac open frame (3) open frame (3) fsl206mrn -40 ~ 115c fsl206mr 8-dip rail 0.6a 19 ? 12w 7w fsl206mrl 8-lsop FSL206MRBN l206mrb 8-dip notes: 1. the junction temperature can limit the maximum output power. 2. 230v ac or 100/115v ac with doubler. the maximum power with ccm operation. 3. maximum practical continuous power in an open-frame design at 50c ambient. application diagram drain gnd v fb v cc ac in dc out pwm v str ls drain gnd v fb v cc ac in dc out pwm v str ls (a) with bias winding (b) without bias winding figure 1. typical application internal block diagram figure 2. internal block diagram
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 3 fsl206mr ? green mode fairchild power switch (fps?) pin configuration figure 3. pin configuration pin definitions pin # name description 1 gnd ground . sensefet source terminal on primar y side and internal control ground. 2 v cc positive supply voltage input . although connected to an auxiliary transformer winding, current is supplied from pin 5 (v str ) via an internal switch during startup (see internal block diagram section) . it is not until v cc reaches the uvlo upper thres hold (8v) that the internal startup switch opens and device power is s upplied via the auxiliary transformer winding. 3 v fb feedback voltage . non-inverting input to the pwm com parator, with a 0.11ma current source connected internally and a capacit or and opto-coupler typically c onnected externally. there is a delay while charging external capacitor c fb from 2.4v to 5v using an internal 2.7 a current source. this delay prevents false triggering under transient conditions, but allows the protection mechanism to operate under true overload conditions. 4 ls line sense pin . this pin is used to protect the devic e when the input volt age is lower than the rated input voltage range. if this pi n is not used, connect to ground. 5 v str startup . connected to the rectified ac line voltage s ource. at startup, the internal switch supplies internal bias and charges an exte rnal storage capacitor placed between the v cc pin and ground. once v cc reaches 8v, all internal blocks are ac tivated. after that, the internal high- voltage regulator (hv reg) turns on and off irregularly to maintain v cc at 7.8v. 6, 7, 8 drain drain . designed to connect directly to the prim ary lead of the transformer and capable of switching a maximum of 650v. minimizing the lengt h of the trace connecti ng these pins to the transformer decreases leakage inductance.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 4 fsl206mr ? green mode fairchild power switch (fps?) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. t a = 25c unless otherwise specified. symbol parameter min. max. unit v str v str pin voltage -0.3 650.0 v v ds drain pin voltage -0.3 650.0 v v cc supply voltage 26 v v ls ls pin voltage -0.3 internally clamped voltage (4) v v fb feedback voltage range -0.3 internally clamped voltage (4) v i dm drain current pulsed (5) 1.5 a e as single-pulsed avalanche energy (6) 11 mj p d total power dissipation 1.3 w t j operating junction te mperature -40 +150 c t a operating ambient te mperature -40 +125 c t stg storage temperature -55 +150 c esd human body model, jesd22-a114 4 kv charged device model, jesd22-c101 2 notes: 4. v fb is clamped by internal clamping diode (13v i clamp_max < 100 a). after shutdown, before v cc reaching v stop , v sd < v fb < v cc . 5. repetitive rating: pulse-width limit ed by maximum junction temperature. 6. l=21mh, starting t j =25c. thermal impedance t a =25c unless otherwise specified. symbol parameter value unit ja junction-to-ambient thermal impedance (7) 93 c/w notes: 7. jedec recommended environment, jesd51-2 and test board, jesd51-10 with minimum land pattern for 8dip and jesd51-3 with minimum land pattern for 8lsop.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 5 fsl206mr ? green mode fairchild power switch (fps?) electrical characteristics t a = 25c unless otherwise specified. symbol parameter condition min. typ. max. unit sensefet section bv dss drain-source breakdown voltage v cc = 0v, i d = 250a 650 v i dss zero gate voltage drain current v ds = 650v, v gs = 0v 50 a v ds = 520v, v gs = 0v, t a = 125c (8) 250 a r ds(on) drain-source on-state resistance (9) v gs = 10v, i d = 0.3a 14 19 ? c iss input capacitances v gs = 0v, v ds = 25v, f = 1mhz 162 pf c oss output capacitance v gs = 0v, v ds = 25v, f = 1mhz 14.9 pf c rss reverse transfer capacitance v gs = 0v, v ds = 25v, f = 1mhz 2.7 pf t r rise time v ds = 325v, i d = 0.5a, r g = 25 ? 6.1 ns t f fall time v ds = 325v, i d = 0.5a, r g = 25 ? 43.6 ns control section f osc switching frequency v fb = 4v, v cc = 10v 61 67 73 khz ? f osc switching frequency variation -25c < t j < 85c 5 10 % f m frequency modulation (8) 3 khz d max maximum duty cycle v fb = 4v, v cc = 10v 66 72 78 % d min minimum duty cycle v fb = 0v, v cc = 10v 0 0 0 % v start uvlo threshold voltage v fb = 0v, v cc sweep 7 8 9 v v stop after turn on 6 7 8 v i fb feedback source current v fb = 0v, v cc = 10v 90 110 130 a t s/s internal soft-start time v fb = 4v, v cc = 10v 10 15 20 ms burst mode section v burh burst-mode high threshold voltage v cc = 10v, v fb increase fsl206mr 0.66 0.83 1.00 v fsl206mrb 0.40 0.50 0.60 v v burl burst-mode low threshold voltage v cc = 10v, v fb decrease fsl206mr 0.59 0.74 0.89 v fsl206mrb 0.28 0.35 0.42 v hys bur burst-mode hysteresis fsl206mr 90 mv fsl206mrb 150 mv protection section i lim peak current limit v fb = 4v, di/dt = 300ma/s, v cc = 10v 0.54 0.60 0.66 a t cld current limit delay (8) 100 ns v sd shutdown feedback voltage v cc = 10v 4.5 5.0 5.5 v i delay shutdown delay current v fb = 4v 2.1 2.7 3.3 a t leb leading-edge blanking time (8) 250 ns v aocp abnormal over-current protection (8) 0.7 v v ovp over-voltage protection v fb = 4v, v cc increase 23.0 24.5 26.0 v v ls_off line-sense protection on to off v fb = 3v, v cc = 10v, v ls decrease 1.9 2.0 2.1 v v ls_on line-sense protection off to on v fb = 3v, v cc = 10v, v ls increase 1.4 1.5 1.6 v tsd thermal shutdown temperature (8) 125 135 150 c hys tsd tsd hysteresis temperature (8) 60 c continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 6 fsl206mr ? green mode fairchild power switch (fps?) electrical characteristics (continued) t a = 25 c unless otherwise specified. symbol parameter conditions min. typ. max. units high voltage regulator section v hvr hv regulator voltage v fb = 0v, v str = 40v 7.8 v total device section i op1 operating supply current (control part only, without switching) v cc = 15v, 0v 40v 1.6 1.9 2.2 ma i start startup current v cc = before v start , v fb = 0v 100 150 a v str minimum v str supply voltage v cc = v fb = 0v, v str increase 26 v notes: 8. though guaranteed by design, not 100% tested in production. 9. pulse test: pulse width=300ms, duty cycle=2%.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 7 fsl206mr ? green mode fairchild power switch (fps?) typical performance characteristics 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 ( \ 25 ( 0 ( 25 ( 50 ( 75 ( 90 ( 110 ( 115 ( operating ? frequency ? (f osc ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 ( \ 25 ( 0 ( 25 ( 50 ( 75 ( 90 ( 110 ( hv ? regulator ? voltage ? (v hvr ) figure 4. operating frequency vs. temperature fi gure 5. hv regulator voltage vs. temperature 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 start ? theshold ? voltage ? (v start ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 stop ? theshold ? voltage ? (v stop ) figure 6. start threshold voltage vs. temperature figure 7. stop threshold voltage vs. temperature 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 feedback ? source ? current ? (i fb ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 peak ? current ? limit ? (i lim ) figure 8. feedback source current vs. temperature figure 9. peak current limit vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 8 fsl206mr ? green mode fairchild power switch (fps?) typical performance characteristics (continued) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 ( \ 25 ( 0 ( 25 ( 50 ( 75 ( 90 ( 110 ( startup ? charging ? current ? (i ch ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 operating ? supply ? current ? (iop1) ? figure 10. startup charging current vs. temperature figure 11. operating supply current 1 vs. temperature 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 operating ? supply ? current ? (iop2) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 ( \ 25 ( 0 ( 25 ( 50 ( 75 ( 90 ( 110 ( over \ voltage ? protection ? (v ovp ) figure 12. operating supply current 2 vs. temperature figure 13. over-voltage protection voltage vs. temperature 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 \ 40 \ 25 0 25 50 75 90 110 suntdown ? delay ? current ? (i delay ) figure 14. shutdown delay current vs. temperature
? 2011 fairchild semiconductor corporation fsl206mr ? rev. 1.0.5 www.fairchildsemi.com fsl206mr ? green mode fairchild power switch (fps?) functional description startup at startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (c a ) connected to the v cc pin, as illustrated in figure 15. an internal high- voltage regulator (hv reg) located between the v str and v cc pins regulates the v cc to 7.8v and supplies operat ing current. therefore, fsl206mr needs no auxiliary bias winding. v ref uvlo hv/reg 7.8v 2 v str 3 v cc c a v dc,link i ch i start figure 15. startup block oscillator block the oscillator frequency is set internally and the fps? has a random frequency fluc tuation function. fluctuation of the switch ing frequency can reduce emi by spreading the energy ov er a wider frequency range than the bandwidth measur ed by the emi test equipment. the amount of emi reduction is directly related to the range of t he frequency variation. the range of frequency variation is fixed internally; however, its selection is randomly c hosen by the combination of an external feedback voltage and internal free-running oscillator. this randomly chosen switching frequency effectively spreads the emi noise near switching frequency and allows the use of a cost-effective inductor instead of an ac input line f ilter to satisfy world-wide emi requirements. figure 16. frequency fluctuation waveform feedback control fsl206mr employs current-mode control, as shown in figure 17. an opto-coupler (such as the fod817a) and shunt regulator (such as t he ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the r sense resistor makes it possible to control the switching duty cycle. when the shunt regul ator reference pin voltage exceeds the internal refer ence voltage of 2.5v; the opto- coupler led current in creases, feedback voltage v fb is pulled down, and the duty cy cle is reduced. this typically occurs when input voltage is increased or output load is decreased. figure 17. pulse-width-modulation (pwm) circuit leading-edge blanking (leb) at the instant the internal sensefet is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically cause a high-current spike through the sensefet. excessive voltage across the r sense resistor leads to incorrect feedback operation in the current-mode pwm cont rol. to counter this effect, the fps employs a leading-edge blanking (leb) circuit ( see figure 17 ). this circuit inhibits the pwm comparator for a short time (t leb ) after the sensefet is turned on. protection circuits the protective functions include overload protection (olp), over-voltage prot ection (ovp), under-voltage lockout (uvlo), line under-voltage protection (luvp), abnormal over-current protection (aocp), and thermal shutdown (tsd). because thes e protection circuits are fully integrated inside t he ic without external components, reliability is im proved without increasing cost. once a fault condition occurs, switching is terminated and the sensefet remains off. this causes v cc to fall. when v cc reaches the uvlo stop voltage v stop (7v), the protection is reset and the internal high- voltage current sour ce charges the v cc capacitor via the v str pin. when v cc reaches the uvlo start voltage v start (8v), the fps resumes normal operation. in this manner, auto-restart can al ternately enable and disable the switching of the power sensefet until the fault condition is eliminated.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 10 fsl206mr ? green mode fairchild power switch (fps?) figure 18. auto-restart protection waveforms overload protection (olp) overload is defined as the load current exceeding a pre- set level due to an unexpected event. in this situation, the protection circuit should be activated to protect the smps. however, even w hen the smps is operating normally, the overload protection (olp) circuit can be activated during the load transit ion or startup. to avoid this undesired operation, the olp circuit is activated after a specified time to determine whether it is a transient situation or a tr ue overload situation. the current-mode feedback path limit s the current in the sensefet when the maximum pwm duty cycle is attained. if the output c onsumes more than this maximum power, the output voltage (v o ) decreases below its rating voltage. th is reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor curr ent, increasing the feedback voltage (v fb ). if v fb exceeds 2.4v, the feedback input diode is blocked and the 2. 7a current source (i delay ) starts to charge c fb slowly up. in this condition, v fb increases until it reaches 5v, when the switching operation is terminated, as shown in figure 19. the shutdown delay is the time required to charge c fb from 2.4v to 5v with 2.7a current source. figure 19. overload protection (olp) figure 20. abnormal over-current protection abnormal over-current protection (aocp) when the secondary rectifier diodes or the transformer pin are shorted, a steep current with extremely high di/dt can flow through the sensefet during the leb time. even though the fps has overl oad protection, it is not enough to protect the fps in that abnormal case, since severe current stress is imposed on the sensefet until olp triggers. the fps includes the internal aocp (abnormal over-current protection) circuit shown in figure 20. when the gate turn- on signal is applied to the power sense, the aocp bl ock is enabled and monitors the current through the sens ing resistor. the voltage across the resistor is com pared with a preset aocp level. if the sensing-resistor voltage is greater than the aocp level, the set signal is applied to the latch, resulting in the shut down of the smps. thermal shutdown (tsd) the sensefet and control ic being integrated makes it easier to detect the temper ature of the sensefet. when the junction temper ature exceeds ~135c, thermal shutdown is activat ed and the fps is restarted after temperature decreases to 60c. over-voltage protection (ovp) in the event of a malfunc tion in the secondary-side feedback circuit or an open feedback loop caused by a soldering defect, the current through the opto-coupler transistor becomes almost zero ( refer to figure 17 ). then v fb climbs up in a similar manner to the overload situation, forcing the pres et maximum current to be supplied to the smps until t he overload protection is activated. because excess energy is provided to the output, the output voltage ma y exceed the rated voltage before the overload pr otection is activated, resulting in the breakdown of t he devices in the secondary side. to prevent this situation, an over-voltage protection (ovp) circuit is employed. in general, v cc is proportional to the output voltage and the fps uses v cc instead of directly monitoring the output voltage. if v cc exceeds 24.5v, ovp circuit is activated, re sulting in termination of the switching operation. to av oid undesired activation of ovp during normal operation, v cc should be designed to be below 24.5v.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 11 fsl206mr ? green mode fairchild power switch (fps?) line under-voltage protection (luvp) if the input voltage of the c onverter is lower than the minimum operating voltage, t he converter input current increases too much, causing components failure. if the input voltage is low, the c onverter should be protected. in the fsl206mr, the luvp ci rcuit senses the input voltage using the ls pin and, if this voltage is lower than 1.5v, the luvp signal is generated. the comparator has 0.5v hysteresis. if the luvp signal is generated, the output drive block is shut down and the output voltage feedback loop is saturated. ? ? figure 21. line uvp circuit soft-start the fsl206mr has an internal soft-start circuit that slowly increases the feedback voltage, together with the sensefet current, after it starts. the typical soft-start time is 15ms, as shown in figure 22, where progressive increments of the sensefet current are allowed during the startup phase. the pul se width to the power switching device is progressi vely increased to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing t he required output voltage. it also helps prevent transformer saturation and reduce the stress on the secondary diode. figure 22. internal soft-start burst operation to minimize power dissipation in standby mode, the fps enters burst mode. as the load decreases, the feedback voltage decreases. as shown in figure 23, the device automatically ent ers burst mode when the feedback voltage drops below v burh . switching continues until the feedba ck voltage drops below v burl . at this point, switching stops and the out put voltages start to drop at a rate dependent on the standby current load. this causes the feedba ck voltage to rise. once it passes v burh , switching resumes. the feedback voltage then falls and the proce ss repeats. burst mode alternately enables and dis ables switching of the sensefet and reduces switching loss in standby mode. v fb v ds v burl v burh i ds v o vo set time switching disabled t1 t2 t3 switching disabled t4 figure 23. burst-mode operation
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 12 fsl206mr ? green mode fairchild power switch (fps?) physical dimensions 5.08 max 0.33 min 2.54 7.62 0.56 0.355 1.65 1.27 3.683 3.20 3.60 3.00 6.67 6.096 9.83 9.00 7.62 9.957 7.87 0.356 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and toleranc es per asme y14.5m-1994 8.255 7.61 e) drawing filename and revsion: mkt-n08frev2. (0.56) figure 24. 8-lead, dual in-line package (dip) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 13 fsl206mr ? green mode fairchild power switch (fps?) physical dimensions (continued) mkt-mlsop08areva figure 25. 8-lead, .300" wide , surface mount package (lsop) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsl206mr ? rev. 1.0.5 14 fsl206mr ? green mode fairchild power switch (fps?)

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