w24l010a 128k 8 high speed cmos static ram publication release date: september 1999 - 1 - revision a2 general description the w24l010a is a high speed, low power cmos static ram organized as 131072 8 bits that operates on a single 3.3-volt power supply. this device is manufactured using winbond's high performance cmos technology. features ? high speed access time:10/12/15 ns (max.) ? low power consumption: ? active: 300 mw (typ.) ? single +3.3v power supply ? fully static operation ? all inputs and outputs directly ttl/lvttl compatible ? three-state outputs ? available packages: 32-pin 300 mil soj, skinny dip and tsop pin configuratiions v a8 a9 we 1 2 3 4 5 24 25 26 27 28 nc a7 a6 a5 a12 a4 a3 a2 a1 6 7 8 9 20 21 22 23 a11 oe a10 cs1 i/o 8 i/o 7 i/o 6 i/o 5 10 11 12 13 16 17 18 19 a0 i/ o 2 i/ o 3 i/ o 1 14 15 i/o 4 a13 v a14 a16 32 31 30 29 a15 cs2 dd ss 1 2 3 4 5 6 7 8 9 11 12 14 15 16 a15 a12 a7 a6 a5 a4 a3 a2 a1 v cs2 we a13 a8 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 dq3 dd 32-pin tsop a11 a9 nc 32 31 30 29 27 26 25 24 23 22 21 20 19 18 17 a14 i/o8 a16 v ss dq2 dq1 10 13 a0 28 block diagram a0 . cs1 a16 we i/o1 i/o8 oe core v v . . data i/o array decoder core cs2 . control dd ss pin description symbol description a0 ? a16 address inputs i/o1 ? i/o8 data inputs/outputs cs1 , cs2 chip select inputs we write enable input oe output enable input v dd power supply v ss ground nc no connection
w24l010a - 2 - dc characteristics absolute maximum ratings parameter rating unit supply voltage to v ss potential -0.5 to +4.6 v input/output to v ss potential -0.5 to v dd +0.5 v allowable power dissipation 1.0 w storage temperature -65 to +150 c operating temperature 0 to +70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. truth table cs1 cs2 oe we mode i/o1 ? i/o8 v dd current h x x x not selected high z i sb , i sb1 x l x x not selected high z i sb , i sb1 l h h h output disable high z i dd l h l h read data out i dd l h x l write d ata in i dd operating characteristics (v dd = 3.3v 5%, v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions min. typ. max. unit input low voltage v il - -0.5 - +0.8 v input high voltage v ih - +2.0 - v dd +0.5 v input leakage current i li v in = v ss to v dd -10 - +10 a output leakage current i lo v i/o = v ss to v dd cs1 = v ih or cs2 = v il or oe = v ih or we = v il -10 - +10 a output low voltage v ol i ol = +8.0 ma - - 0.4 v output high voltage v oh i oh = -4.0 ma 2.4 - - v 10 - - 130 ma operating power supply current i dd cs1 = v il , cs2 = v ih i/o = 0 ma 12 - - 120 ma cycle = min duty = 100% 15 - - 100 ma standby power i sb cs1 = v ih , or cs2 = v il - - 15 ma supply current i sb1 cs1 v dd -0.2v or - - 5 ma cs2 0.2v note: typical characteristics are at v dd = 3.3v, t a = 25 c.
w24l010a publication release date: september 1999 - 3 - revision a2 capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter sym. conditions max. unit input capacitance c in v in = 0v 8 pf input/output capacitance c i/o v out = 0v 10 pf note: these parameters are sampled but not 100% tested. ac test conditions parameter conditions input pulse levels 0v to 3v input rise and fall times 3 ns input and output timing reference level 1.5v output load c l = 30 pf, i oh /i ol = -4 ma/8 ma ac test loads and waveform 90% 90% 3 ns 10% 3 ns 10% r1 320 ohm 3.3v output r2 350 ohm 30 pf including jig and scope 3.0v 0v 3.3v output r1 320 ohm 5 pf including jig and scope r2 350 ohm (for t clz1, clz2, olz, chz1, chz2, ohz, whz, ow t t t tt tt )
w24l010a - 4 - ac characteristics (v dd = 3.3v 5%, v ss = 0v, t a = 0 to 70 c) read cycle parameter sym. w24l010a- 10 w24l010a- 12 w24l010a- 15 unit min. max. min. max. min. max. read cycle time t rc 10 - 12 - 15 - ns address access time t aa - 10 - 12 - 15 ns chip select access time cs1 t acs1 - 10 - 12 - 15 ns cs2 t acs2 - 10 - 12 - 15 ns output enable to output valid t aoe - 5 - 6 - 7 ns chip selection to output in cs1 t clz1* 3 - 3 - 3 - ns low z cs2 t clz2* 3 - 3 - 3 - ns output enable to output in low z t olz* 0 - 0 - 0 - ns chip deselection to output in cs1 t chz1* - 5 - 6 - 7 ns high z cs2 t chz2* - 5 - 6 - 7 ns output disable to output in high z t ohz* - 5 - 6 - 7 ns output hold from address change t oh 3 - 3 - 3 - ns * these parameters are sampled but not 100% tested. write cycle parameter sym. w24l010a- 10 w24l010a- 12 w24l010a- 15 unit min. max. min. max. m in. max. write cycle time t wc 10 - 12 - 15 - ns chip selection to end of cs1 t cw1 9 - 10 - 13 ns write cs2 t cw2 9 - 10 - 13 - ns address valid to end of write t aw 9 - 10 - 13 - ns address setup time t as 0 - 0 - 0 ns write pulse width t wp 9 - 10 - 10 - ns write recovery cs1 , we t wr1 0 - 0 - 0 - ns time cs2 t wr2 0 - 0 - 0 - ns data valid to end of write t dw 5 - 7 - 9 - ns data hold from end of write t dh 0 - 0 - 0 - ns write to output in high z t whz * - 5 - 6 - 8 ns output disable to output in high z t ohz * - 5 - 6 - 8 ns output active from end of write t ow 0 - 0 - 0 - ns * these parameters are sampled but not 100% tested.
w24l010a publication release date: september 1999 - 5 - revision a2 timing waveforms read cycle 1 (address controlled) address t t t t d oh aa rc oh out read cycle 2 (chip select controlled) cs1 cs2 d t t t t t t acs1 acs2 clz1 clz2 chz1 chz2 out read cycle 3 (output enable controlled) address t oe cs1 cs2 d t t t t t t t t t t t oh chz1 chz2 ohz aa rc aoe clz1 acs1 acs2 clz2 olz out
w24l010a - 6 - timing waveforms, continued write cycle 1 ( oe clock) address oe cs1 cs2 we d d t t (1, 4) out in ohz wc t wr1 t cw1 t cw2 t aw t wp t wr2 t as t dw t dh write cycle 2 ( oe = v il fixed) address cs1 cs2 we d d t t t t t t t t t t t (2) (3) t t wc cw1 wr1 cw2 aw wp wr2 ow whz (1, 4) dw dh oh as out in notes: 1. during this period, i/o pins are in the output state, so input signals of opposite phase to the outputs should not be applie d. 2. the data output from d out are the same as the data written to d in during the write cycle. 3. dout provides the read data for the next address. 4. transition is measured 500 mv from steady state with c l = 5 pf. this parameter is guaranteed but not 100% tested.
w24l010a publication release date: september 1999 - 7 - revision a2 ordering information part no. access time (ns) operating current max. (ma) standby current max. (ma) package w24l010ak-10 10 130 5 300 mil skinny dip w24l010ak-12 12 120 5 300 mil skinny dip w24l010ak-15 15 100 5 300 mil skinny dip W24L010AJ-10 10 130 5 300 mil soj W24L010AJ-12 12 120 5 300 mil soj W24L010AJ-15 15 100 5 300 mil soj w24l010at-10 10 130 5 type one tsop w24l010at-12 12 120 5 type one tsop w24l010at-15 15 100 5 type one tsop notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
- 8 - package dimensions 32-pin soj d h b b e e 1 16 17 32 e y a a a seating plane c l s symbol dimension in mm dimension in inches min. nom. max. min. nom. max. a a a b b c d e e e h l s y 0.140 0.020 0.095 0.100 0.105 0.0320.0280.026 0.0220.0180.016 0.0140.010 0.008 0.8350.825 0.305 0.3000.295 0.0560.0500.044 0.2870.2670.247 0.3450.3350.325 0.080 0.045 0.004 010 0.815 3.556 0.508 2.413 2.540 2.667 0.8130.7110.660 0.559 0.4570.406 0.356 0.2540.203 21.20920.955 7.7477.6207.493 1.4221.2701.118 7.2906.7826.274 8.7638.509 8.255 2.032 1.143 0.102 0 10 20.701
w24l010a publication release date: september 1999 - 9 - revision a2 package dimensions, continued 32-pin tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeter dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792647 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.
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