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1 ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1113, rev. a cat24c03 2-kb i 2 c cmos serial eeprom with partial array write protection pin configuration functional symbol features supports standard and fast i 2 c protocol 1.8 v to 5.5 v supply voltage range 16-byte page write buffer hardware write protection for upper half of memory schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda). low power cmos technology 1,000,000 program/erase cycles 100 year data retention rohs compliant & 8-pin pdip, soic, tssop and tdfn packages industrial temperature range pdip (l) soic (w) tssop (y) tdfn (vp2) v cc v ss sd a scl wp cat24c0 3 a 2 , a 1 , a 0 device description the cat24c03 is a 2-kb serial cmos eeprom, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. it features a 16-byte page write buffer and supports both the standard (100 khz) as well as fast (400 khz) i 2 c protocol. write operations can be inhibited by taking the wp pin high (this protects the upper half of the memory). the cat24c03 is available in rohs compliant green and gold 8-lead pdip, soic, tssop and tdfn packages. 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4 for the location of pin 1, please consult the corresponding package drawing. pin functions a 0 , a 1 , a 2 device address sda serial data scl serial clock wp write protect v cc power supply v ss ground * catalyst carries the i 2 c protocol under a license from the philips corporation.
cat24c03 2 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings* storage temperature -65c to +150c voltage on any pin with respect to ground (1) -0.5 v to +6.5 v * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci?cation is not implied. exposure to any absolute maximum rating for extended periods may af fect device performance and reliability. reliability characteristics (2) symbol parameter min units n end (*) endurance 1,000,000 program/ erase cycles t dr data retention 100 years (*) page mode, v cc = 5 v, 25c d.c. operating characteristics v cc = 1.8 v to 5.5 v, t a = -40c to 85c, unless otherwise speci?ed. symbol parameter test conditions min max units i cc supply current read or write at 400 khz 1 ma i sb standby current all i/o pins at gnd or v cc 2 a i l i/o pin leakage pin at gnd or v cc 2 a v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc > 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc > 1.8 v, i ol = 1.0 ma 0.2 v pin impedance characteristics t a = 25c, f = 400 khz, v cc = 5 v symbol parameter conditions min max units c in (2) sda i/o pin capacitance v in = 0 v 8 pf c in (2) input capacitance (other pins) v in = 0 v 6 pf z wpl wp input low impedance v in < 0.5 v 5 70 k i lwph wp input high leakage v in > v cc x 0.7 2 a note: (1) the dc input voltage on any pin should not be lower than -0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than -1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. (2) these parameters are tested initially and after a design or process change that affects the parameter according to appropriate aec-q100 and jedec test methods.
cat24c03 3 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics v cc = 1.8 v to 5.5 v, t a = -40 c to 85 c, unless otherwise speci?ed. symbol parameter 1.8 v - 5.5 v 2.5 v - 5.5 v units min max min max f scl clock frequency 100 400 khz t i (1) noise suppression time constant at scl, sda inputs 0.1 0.1 s t aa (2) scl low to sda data out 3.5 0.9 s t buf (1) time the bus must be free before a new transmission can start 4.7 1.3 s t hd:sta start condition hold time 4 0.6 s t low clock low period 4.7 1.3 s t high clock high period 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 0.25 0.1 s t r (1) sda and scl rise time 1 0.3 s t f (1) sda and scl fall time 0.3 0.3 s t su:sto stop condition setup time 4 0.6 s t dh data out hold time 0.1 0.1 s t wr write cycle time 5 5 ms t pu (1), (3) power-up to ready mode 1 1 ms note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) for timing measurements the sda line capacitance is ~ 100 pf; the scl input is driven with rise and fall times of < 50 ns; the sda i/o is pulled-up by a 3 ma current source; input driving signals swing from 20% to 80% of v cc . output level reference levels are 30% and respectively 70% of v cc . (3) t pu is the delay required from the time v cc is stable until the device is ready to accept commands. power-on reset (por) the cat24c03 incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the cat24c03 will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por feature protects the device against brown-out failure following a temporary loss of power. the por circuitry triggers at the minimum v cc level required for proper initialization of the internal state machines. the por trigger level automatically tracks the internal cmos device thresholds, and is naturally well below the minimum recommended v cc supply voltage.
cat24c03 4 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice pin description scl: the serial clock input pin accepts the serial clock generated by the master. sda: the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address pins accept the device ad - dress. these pins have on-chip pull-down resistors. wp: the write protect input pin inhibits all write opera - tions to the upper half of the memory array, when pulled high. (locations 80h to ffh)this pin has an on-chip pull-down resistor. functional description the cat24c03 supports the inter-integrated circuit (i 2 c) bus data transmission protocol, which de?nes a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data ?ow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat24c03 acts as a slave device. master and slave alternate as either transmitter or receiver. up to 8 devices may be connected to the bus as determined by the device address inputs a 0 , a 1 , and a 2 . i 2 c bus protocol the i 2 c bus consists of two wires, scl and sda. the two wires are connected to the v cc supply via pull-up resistors. master and slave devices connect to the 2- wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to transmit a 0 and releases it to transmit a 1. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high . an sda transition while scl is high will be interpreted as a start or stop condition (figure 1). start the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a wake-up call to all receivers. absent a start, a slave will not respond to commands. stop the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. the stop starts the internal write cycle (when follow - ing a write command) or sends the slave into standby mode (when following a read command). device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8-bit serial slave address. the ?rst 4 bits of the slave address are set to 1010, for normal read/write opera - tions (figure 2). the next 3 bits, a 2 , a 1 and a 0 , select one of 8 possible slave devices. the last bit, r/w, speci?es whether a read (1) or write (0) operation is to be performed. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 3). the slave will also acknowledge the byte address and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. if the master acknowledges the data, then the slave continues transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by sending a stop to the slave. bus timing is illustrated in figure 4.
cat24c03 5 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 3. acknowledge timing figure 2. slave address bits ac kn ow ledge 1 st ar t scl fr om master 8 9 da ta outpu t fr om transmitter da ta outpu t fr om receiver st ar t bit sd a st op bit scl figure 1. start/stop timing figure 4. bus timing t high scl sda in sda out t low t f t low t r t buf t su:st o t su:da t t hd:da t t hd:st a t su:st a t aa t dh 1 0 1 0 device address a 2 a 1 a 0 r/w
cat24c03 6 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice write operations byte write in byte write mode the master sends a start, followed by slave address, byte address and data to be written (figure 5). the slave acknowledges all 3 bytes, and the master then follows up with a stop, which in turn starts the internal write operation (figure 6). during internal write, the slave will not acknowledge any read or write request from the master. page write the cat24c03 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. a page is selected by the 4 most signi?cant bits of the address byte following the slave address, while the 4 least signi?cant bits point to the byte within the page. up to 16 bytes can be written in one write cycle (figure 7). the internal byte address counter is automatically in - cremented after each data byte is loaded. if the master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around fashion (within the selected page). the internal write cycle starts immediately following the stop. acknowledge polling acknowledge polling can be used to determine if the cat24c03 is busy writing or is ready to accept com - mands. polling is implemented by interrogating the device with a selective read command (see read operations). the cat24c03 will not acknowledge the slave address, as long as internal write is in progress. hardware write protection with the wp pin held high, the entire memory is pro - tected against write operations. if the wp pin is left ?oating or is grounded, it has no impact on the operation of the cat24c03.
cat24c03 7 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 7. page write timing figure 6. write cycle timing bus ac tivity : master sd a lin e da ta n+ p byte address (n) a c k a c k da ta n a c k s t o p s a c k da ta n+1 a c k s t a r t p sla ve address no te: in this example n = xxxx 0000(b); x = 1 or 0 t wr st op condition st ar t condition address ac k 8 th bi t byte n scl sd a figure 5. byte write timing byte address sla ve address s a c k a c k da ta a c k s t o p p bus ac tivity : master sd a lin e s t a r t
cat24c03 8 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice read operations immediate address read in standby mode, the cat24c03 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. if that previous byte was the last byte in memory, then the address counter will point to the 1 st memory byte, etc. when, following a start, the cat24c03 is presented with a slave address containing a 1 in the r/w bit position (figure 8), it will acknowledge (ack) in the 9 th clock cycle, and will then transmit data being pointed at by the internal address counter. the master can stop further transmission by issuing a noack, followed by a stop condition. selective read the read operation can also be started at an address different from the one stored in the internal address coun - ter. the address counter can be initialized by performing a dummy write operation (figure 9). here the start is followed by the slave address (with the r/w bit set to 0) and the desired byte address. instead of follow - ing up with data, the master then issues a 2 nd start, followed by the immediate address read sequence, as described earlier. sequential read if the master acknowledges the 1 st data byte transmitted by the cat24c03, then the device will continue trans - mitting as long as each data byte is acknowledged by the master (figure 10). if the end of memory is reached during sequential read, then the address counter will wrap-around to the beginning of memory, etc. sequential read works with either immediate address read or selective read, the only difference being the starting byte address.
cat24c03 9 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice figure 10. sequential read timing bus ac tivity : master sd a lin e da ta n+x da ta n a c k a c k da ta n+1 a c k s t o p n o a c k da ta n+2 a c k p sla ve address figure 9. selective read timing sla ve address s a c k n o a c k s t o p p bus ac tivity : master sd a lin e s t a r t byte address (n) s a c k da ta n sla ve address a c k s t a r t figure 8. immediate address read timing scl sd a 8 th bit st op no ac k da ta out 8 9 sla ve address s a c k da ta n o a c k s t o p p bus ac tivity : master sd a lin e s t a r t
cat24c03 10 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 300 mil wide plastic dip (l) a e b e1 b2 l a2 a1 e d eb symbol a a1 b b2 d d2 e e1 e eb l mi n 0.120 0.015 0.014 0.355 0.300 0.300 0.310 0.240 0.115 0.130 0.150 nom 0.018 0.060 0.070 0.045 0.365 0.250 0.430 max 0.210 a2 0.115 0.130 0.195 0.022 0.400 0.325 0.325 0.280 0.100 bs c notes: 1. complies with jedec standard ms001. 2. all dimensions are in inches. 3. dimensioning and tolerancing per ansi y14.5m-1982
cat24c03 11 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 150 mil wide soic (w) symbol a1 a2 b c d e e1 e f mi n 0.0040 0.0532 0.013 0.1890 02284 0.149 0.0099 nom 0.0098 0.0075 0.050 bs c max 0.0098 0.0688 0.020 0.1968 0.2440 0.1574 0.0196 1 0 8 e e1 d a1 e l 1 c b a notes: 1. complies with jedec speci?cation ms-012 dimensions. 2. all linear dimensions in millimeters.
cat24c03 12 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead tssop (y) 8 5 1 4 e e1 e/ 2 pin #1 ident. d b l 1 e a a1 a2 see detail a see detail a seating plane c gage plane 0.25 symbol a a1 a2 b c d e e1 e l 1 mi n 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 nom 0.90 0.30 0.19 3.00 4.40 0.60 0.7 5 0.50 max 1.20 0.15 1.05 0.20 3.10 6.50 4.50 0.65 bs c notes: 1. all dimensions in millimeters.
cat24c03 13 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice 8-pad tdfn 2x3 package (vp2) e2 a2 e pin 1 index area l a3 pin 1 id e b a1 3 x e d2 d a note: 1. all dimensions in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the termnals. coplanarity shall not exceed 0.08 mm. 3. warpage shall not exceed 0.10 mm. 4. package length / package width are considered as special characteristic. 5. refer jedec mo-229. symbol a a1 a2 a3 b d d2 e e2 e l mi n 0.70 0.00 0.45 0.20 1.90 1.30 1.40 2.90 1.20 0.20 0.30 0.40 nom 0.75 0.02 0.55 0.20 re f 0.25 2.00 3.00 0.50 typ max 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 1.30
cat24c03 14 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice ordering information notes: (1) the device used in the above example is a cat24c03yi-gt3 (tssop, industrial temperature, 1.8 volt to 5.5 volt operating voltage, tape & reel) (2) for additional package and temperature options, please contact your nearest catalyst semiconductor sales of? ce. prefix device # suffix 24c03 y i gt3 C product number cat temperature range i = industrial (-40 c to +85 c) company id package l: pdip (lead-free, halogen-free) w: soic, jedec (lead-free, halogen-free) y: tssop (lead-free, halogen-free) vp2: tdfn (lead-free, halogen-free) lead finish/tape & reel g: nipdau lead plating t: tape & reel 3: 3000/reel
cat24c03 15 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice package marking ymg 24c03i y = production year m = production month g = die revision 24c03 = device code i = industrial temperature range 8-lead tssop 8-lead tdfn e m = device code n = traceability code y = production year m = production month e m n n n n y m notes: (1) the circle on the package marking indicates the location of pin 1. 8-lead pdip 8-lead soic csi = catalyst semiconductor, inc. 24c03w = device code i = temperature range yy = production year ww = production week g = product revision yywwg 24c03wi csi = catalyst semiconductor, inc. 24c03l = device code i = temperature range yy = production year ww = production week g = product revision yywwg 24c03li
cat24c03 16 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice tape and reel direction of feed device orientation reel dimensions (1) embossed carrier dimensions tape size a b min c d* min n min g t max max qty/reel 8mm 330 (13.00) 3000 1.5 (0.059) 12.80 (0.504) 13.20 (0.5200) 20.2 (0.795) 50 (1.969) 8.4 (0.328) 9.9 (1.389) 14.4 (0.566) 12mm 12.4 (0.488) 14.4 (0.558) 18.4 (0.724) embossed carrier dimensions component package type tape size (w) part pitch (p) 8l soic w, y 12mm 8mm 8l tdfn 2x3mm vp2 8mm 4mm note: (1) metric dimensions will govern; english measurements rounded, for reference only and in parentheses. embossed carrier to p cover t ape thickness (t 1 ) 0.10mm (0.004) max thick embossmen t device orientation soi c spr oket hol e tssop tdfn pin 1 pin 1 pin 1 a d* b* drive spokes optional, if used asterisked dimensions appl y. * full radius* t ape slot in core for t ape st ar t. 2.5mm (0.098) min width 10mm (0.394) min depth g (measured at hub) c n t 40mm (1.575) min. access hole at slot loca tion
cat24c03 17 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice embossed tapeconstant dimensions (1) tape sizes d e p 0 t max. d 1 min. a 0 b 0 k 0 (2) 12mm 1.5 (0.059) 1.6 (0.063) 1.65 (0.065) 1.85 (0.073) 3.9 (0.153) 4.1 (0.161) 400 (0.016) 1.5 (0.059) embossed carrier dimensions (12 tape only) tape sizes b 1 max. f k max. p 2 r min. w p 12mm 8.2 (0.0323) 5.45 (0.0215) 5.55 (0.219) 4.5 (0.177) 1.95 (0.077) 2.05 (0.081) 30 (1.181) 11.7 (0.460) 12.3 (0.484) 7.9 (0.275) 8.1 (0.355) note: (1) metric dimensions will govern; english measurements rounded, for reference only and in parentheses. (2) a0 b0 k0 are determined by component size. the clearance between the component and the cavity must be within 0.05 (0.002) min. to 0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for 24mm tape and larger. the component cannot rotate more than 20 within the determined cavity, see component rotation. embossed carrier dimensions (12 tape only) w e f b 0 a 0 p d p 0 p 2 d 1 for components 2.0mm x 1.2mm and larger 10 pitches cumula tive t olerance on t ape 0.2mm( 0.008) embossment (2) k 0 b 1 k t for machine reference onl y including draft and radii concentric about b 0 user direction of feed center lines of ca vity (2) to p cover t ape
cat24c03 18 doc. no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice revision history date revision comments 03/08/06 a initial issue
cat24c03 19 doc no. 1113, rev. a ? 2006 by catalyst semiconductor, inc. characteristics subject to change without notice copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ? ae 2 ? minipot? catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. products with data sheets labeled advance information or preliminary and other products described herein may not be in production or offered for sale. catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing orders. cir cuit diagrams illustrate typical semiconductor applications and may not be complete.
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 1113 revison: a issue date: 03/08/06

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