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d a t a sh eet product speci?cation supersedes data of 2002 sep 24 2004 mar 05 integrated circuits pcf8813 (67 + 1) 102 pixels matrix lcd driver
2004 mar 05 2 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 i/o buffer and interface 7.2 oscillator 7.3 address counter 7.4 display data ram 7.5 timing generator 7.6 display address counter 7.7 lcd row and column drivers 7.8 lcd waveforms and ddram to data mapping 7.9 ddram addressing 7.10 data order 7.11 mirror x 7.12 mirror y 7.13 bottom row swap 7.14 output row order 8 parallel interfaces 8.1 6800-type parallel interface 8.2 8080-type parallel interface 9 serial interfaces 9.1 serial peripheral interface 9.1.1 write mode 9.1.2 read mode 9.2 serial interface (3-line) 9.2.1 write mode 9.2.2 read mode 10 i 2 c-bus interface (hs-mode) 10.1 characteristics of the i 2 c-bus (hs-mode) 10.1.1 system configuration 10.1.2 bit transfer 10.1.3 start and stop conditions 10.1.4 acknowledge 10.2 i 2 c-bus hs-mode protocol 10.3 command decoder 11 instructions 11.1 initialization 11.2 reset function 11.3 power-down mode 11.4 display control 11.5 set y address of ram 11.6 set x address of ram 11.7 set maximum x address or y address 11.8 set display start line, initial start row and row 0 11.9 set normal or partial display mode 11.10 free programmable multiplex rate 11.11 set hv generator stages 11.12 bias system 12 temperature compensation 13 limiting values 14 handling 15 dc characteristics 16 ac characteristics 17 module maker programming 17.1 lcd voltage calibration 17.2 manufacturer identity 17.3 seal bit 17.4 one time programming 17.4.1 architecture 17.4.2 operations 17.5 interface commands 17.5.1 disable otp command 17.5.2 module maker calibration 17.5.3 refresh 17.6 filling the shift register 17.7 programming flow 17.8 programming specification 17.9 programming examples 18 application information 18.1 protection from light 18.2 application examples 18.3 chip-on-glass applications 19 device protection diagram 20 bonding pad information 21 tray information 22 data sheet status 23 definitions 24 disclaimers 25 purchase of philips i 2 c components
2004 mar 05 3 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 1 features single-chip lcd controller or driver 67 row + 1 icon row, 102 column outputs (the icon row is available twice to allow icons to be displayed at the top or at the bottom of the display) very low power consumption, optimized for battery operated systems on-chip: C display data ram 68 102 bits C configurable voltage multiplier ( 5, 4, 3 and 2) generating highly accurate v lcd and includes booster capacitors (external v lcd is also possible) C temperature compensation of v lcd with four selectable temperature coefficients C generation of intermediate lcd bias voltages C highly-accurate built-in oscillator requiring no external components (an external clock is also possible) high integration level resulting in minimum number of external capacitors and resistors selectable 8-bit parallel interface, 3-line or 4-line serial peripheral interface (spi), 3-line serial interface and high-speed i 2 c-bus interface external reset input cmos compatible inputs mux rates: 1 : 9 to 1 : 65 in steps of 8 an d1:68 logic supply voltage range 1.7 to 3.3 v high voltage generator supply voltage range 2.4 to 4.5 v display supply voltage range 3.0 to 9.0 v one time programmable (otp) v lcd trimming horizontal and vertical mirroring status read which allows chip recognition and content checking of some registers start address line which allows, for instance, scrolling of the displayed image programmable display ram pointers for various display sizes slim chip layout optimized for chip-on-glass applications operating temperature range - 40 to +85 c very close tolerance on v lcd and frame frequency for excellent optical performance support for lcd cell tolerance compensation of v lcd by otp storage. 2 applications telecom equipment portable instruments point of sale terminals. 3 general description the pcf8813 is a low power cmos lcd controller driver designed to drive a graphic display of 67 rows and 102 columns plus an icon row of up to 102 symbols. all necessary functions for the display are provided in a single chip, including on-chip generation of the lcd supply and bias voltages, resulting in a minimum of external components and low power consumption. the pcf8813 can interface to microcontrollers via a parallel, serial or i 2 c-bus interface. 4 ordering information type number package name description version pcf8813u/2da/2 - chip with bumps in tray for cog -
2004 mar 05 4 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 5 block diagram handbook, full pagewidth mgu619 display data ram 68 102 bits data processing column drivers shift register reset row drivers c0 to c101 pcf8813 r0 to r67 102 t1 t2 t3 t4 t5 timing generator address counter command decoder display address counter oscillator osc i/o buffer parallel / serial / i 2 c-bus interface db7/sdata db6/sclk db5/sdout db4 db3/sa1 db2/sa0 db1 db0 v lcdout v lcdsense v lcdin ext e/rd sdah sdahout v ss2 v otpprog v ss1 v dd1 v dd2 v dd3 four-stage high- voltage generator bias voltage generator res 68 3 ps [ 2:0 ] d/c r/w/wr sclh/sce fig.1 block diagram.
2004 mar 05 5 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 6 pinning symbol pad (1) description r15 to r0 7 to 22 lcd row driver outputs r16 to r31 23 to 38 c0 to c101 39 to 140 lcd column driver outputs r67 141 lcd row driver output for row 67 (used only for icons) r66 to r48 142 to 160 lcd row driver outputs r32 to r47 161 to 176 r67 177 duplicated lcd row driver output for row 67 (used only for icons) sdahout 183 data output for i 2 c-bus interface; notes 2 and 3 sdah 184 to 185 data output for i 2 c-bus interface; note 2 v dd1 186 to 191 supply voltage 1; note 4 v dd3 192 to 196 supply voltage 3; note 4 v dd2 197 to 206 supply voltage 2; note 4 v dd1 207 supply voltage 1; notes 4 and 5 r/ w/ wr 208 read/ write (6800) or write (8080 interface) input; note 6 e/ rd 209 clock enable (6800 interface) or read (8080 interface) input; note 7 db0 210 parallel data input/output; note 8 db1 211 parallel data input/output; note 8 db2/sa0 212 parallel data input/output or i 2 c-bus slave address input (bit 0) db3/sa1 213 parallel data input/output or i 2 c-bus slave address input (bit 1) db4 214 parallel data input/output; note 8 db5/sdout 215 parallel data input/output or serial output (sdout) db6/sclk 216 parallel data input/output or output or serial clock input (sclk) db7/sdata 217 parallel data input/output or serial data input (sdata) v ss1 218 ground voltage 1; notes 5 and 9 d/ c 219 data/ command; note 10 sce/sclh 220 to 221 chip enable or clock input for i 2 c-bus interface v otpprog 222 to 224 voltage inputs for otp programming; see note 11 v dd1 225 supply voltage 1; notes 4 and 5 osc 226 oscillator input; note 12 v ss2 227 to 236 ground voltage 2; note 9 v ss1 237 to 246 ground voltage 1; note 9 t5 247 test input 5; note 13 t1 248 test input 1; note 13 t2 249 test input 2; note 13 ps0 250 parallel/serial/i 2 c-bus data input selection pad 0 ps1 251 parallel/serial/i 2 c-bus data input selection pad 1 ps2 252 parallel/serial/i 2 c-bus data input selection pad 2 v dd1 253 supply voltage 1; notes 4 and 5 t4 254 test output 4; note 13 t3 255 test output 3; note 13
2004 mar 05 6 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 notes 1. dummy pads are located at positions 1, 2, 3, 5, 6, 179, 180, 181, 182 and 274; dummy and alignment pads are located at positions 4 and 178. 2. when not in use, this pad must be connected to v dd1 or v ss1 . 3. output sdahout is used as the data acknowledge output when the i 2 c-bus is selected. by connecting sdahout to sdah externally, the sdah line becomes fully i 2 c-bus compatible. having the acknowledge output separated from the serial data line is advantageous in cog applications because where the track resistance from the sdahout pad to the sdah line can be significant, a potential divider is generated by the bus pull-up resistor and the ito track resistance. therefore it is possible during the acknowledge cycle that the pcf8813 will not create a logic low level. by splitting the sdah input from the sdahout output, the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdahout pad to the system sdah line to guarantee a valid low level. 4. v dd2 and v dd3 supply the internal voltage generator, both have the same voltage and may be connected together outside of the chip; v dd1 supplies the remainder of the chip. v dd1 , v dd2 and v dd3 can be connected together but then care must be taken with respect to the supply voltage range. if the internal voltage generator is not used, pads v dd2 and v dd3 must be connected to pads v dd1 . 5. this pad can be used to tie-off unused input pads to the power supply voltage or to ground. 6. this input is not used in serial and i 2 c-bus mode and must therefore be connected to either v dd1 or v ss1 . 7. this input is not used when the serial or i 2 c-bus interface is selected and must therefore be connected to v dd1 or v ss1 . 8. when serial or i 2 c-bus mode is selected, the unused parallel pads must be connected to v dd1 or v ss1 . 9. supply rails v ss1 and v ss2 must be connected together. 10. this input is not used with the 3-line serial interface and must therefore be connected to v dd1 or v ss1 . 11. this pad can be connected externally to the sce/sclh pad to reduce the number of pads routed in cog applications. when not connected in this configuration, v otpprog must be connected to either v dd1 or v ss1 after completion of otp programming and after the seal bit has been set. 12. when the on-chip oscillator is used, the osc input must be connected to v dd1 . if an external clock signal is used, then this is connected to the osc input. if both the oscillator and external clock are inhibited by connecting pad osc to v ss1 , the display is not clocked and may be in a dc state. to avoid this, the chip should always be put into power-down mode before stopping the clock. 13. test pads t1 to t5 are not accessible to users: t1, t2 and t5 must be connected to v ss ; t3 and t4 must be open-circuit. 14. positive power supply for the liquid crystal display (see also figs 51, 52 and 53): a) if the internal voltage generator is used, pads v lcdin ,v lcdsense and v lcdout must be connected together. b) an external lcd supply voltage can be supplied using the v lcdin pad, this requires that pad v lcdout is open-circuit, pad v lcdsense is connected to the v lcdin input, and the internal voltage generator is switched off. in power-down mode, the external lcd supply voltage must be switched off. v lcdin 256 to 262 lcd supply voltage input; note 14 v lcdout 263 to 271 generated lcd supply voltage; note 14 v lcdsense 272 voltage multiplier (v lcd ) regulation input; note 14 res 273 external reset input symbol pad (1) description
2004 mar 05 7 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7 functional description 7.1 i/o buffer and interface one of five industrial standard interfaces can be selected using the interface configuration inputs ps2, ps1 and ps0. table 1 parallel/serial/i 2 c-bus interface selection 7.2 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required. an external clock signal, if used, is connected to this input. 7.3 address counter the address counter (ac) assigns addresses to the display data ram for writing. the x address x[6:0] and the y address y[3:0] are set separately. 7.4 display data ram the pcf8813 contains a 68 102 bit static ram which stores the display data. the display data ram (ddram) is divided into eight banks of 102 bytes (8 8 102 bits), one bank of 1 3 102 bits and a separate bank of 1 1 102 for icons. during ram access, data is transferred to the ram via any of the four interfaces. there is a direct correspondence between the x address and the column output number. 7.5 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not affected by operations on the data buses. 7.6 display address counter the display is generated by continuously shifting rows of ram data to the dot matrix lcd via the column outputs. the display status (all dots on/off and normal/inverse video) is set by bits d and e in the display control command. 7.7 lcd row and column drivers the pcf8813 contains 68 row and 102 column drivers, which connect the appropriate lcd bias voltages in a sequence to the display in accordance with the data that is to be displayed. figure 2 shows typical waveforms. unused outputs should be left unconnected. ps2 ps1 ps0 interface 0 0 0 3-line spi 0 0 1 4-line spi 0 1 0 8080 parallel interface 0 1 1 6800 parallel interface 100 high-speed i 2 c-bus interface 110 101 3-line serial interface 111
2004 mar 05 8 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7.8 lcd waveforms and ddram to data mapping mgu620 row 0 r0 (t) row 1 r1 (t) col 0 c0 (t) col 1 c1 (t) 0 v 0 v v 3 - v ss frame n frame n + 1 01234567 8... ... 67 01234567 8... ... 67 v state1 (t) v state0 (t) v state1 (t) v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd v 2 v 3 v 4 v 5 v ss v lcd - v ss v lcd - v 2 v 4 - v 5 v ss - v 5 v 4 - v lcd v 3 - v 2 v ss - v lcd 0 v 0 v v 3 - v ss v state2 (t) v lcd - v ss v lcd - v 2 v 4 - v 5 v 4 - v lcd v 3 - v 2 v ss - v 5 v ss - v lcd fig.2 typical lcd driver waveforms. v state0 (t) = c1(t) - r0(t). v state1 (t) = c1(t) - r1(t).
2004 mar 05 9 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 top of lcd mgu621 dpram bank 0 bank 1 bank 2 r0 r8 r16 r24 r64 r67 bank 3 bank 8 lcd bank 10 fig.3 display data ram.
2004 mar 05 10 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7.9 ddram addressing handbook, full pagewidth mgu622 0 10 8 0 101 x address icon data y address msb lsb msb lsb msb lsb fig.4 sequence of writing data bytes into the ram. data is downloaded in bytes into the ram matrix of the pcf8813 as indicated in fig.4. the display data ram has a matrix of 68 by 102 bits. the columns are addressed by the x address pointer whilst the rows are addressed in groups of 8 by the y address pointer. however, there are only three rows in bank 8 and one row in bank 10. there is no bank 9. thus the address ranges are: x = 0 to 101 (1100101) and y = 0 to 8 and then 10 (1010). the pcf8813 is limited to 102 columns by 68 rows, addressing the ram outside this area is not allowed. two different addressing modes are possible; horizontal addressing and vertical addressing. in the horizontal addressing mode (v = 0) the x address increments after each byte. after the last x address (x = 101), x wraps-around to 0 and y increments to address the next row (see fig.5) until bank 8 is filled. in the vertical addressing mode (v = 1) the y address increments after each byte. after the y address (y = 8), there is y wraparound to 0 and x increments to address the next column (see fig.6). after the very last address (x = 101 and y = 8) the address pointers wraparound to address x = 0 and y = 0 in both addressing modes. addressing in bank 10 is a special case as these ram locations are not automatically accessed. bank 10 is reserved for icons. icon locations must be addressed explicitly by setting the y address pointer to 10. the y address pointer does not auto-increment when the x address over?ows or under?ows (it stays in set to bank 9). writing icon data is independent of the horizontal or vertical addressing (v-bit) but is affected by the mirror x (mx) and mirror y (my) bits. mx and my are described in sections 7.11 and 7.12.
2004 mar 05 11 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth mgu623 012 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 0 10 8 0 101 x address icons y address 612 613 614 714 715 716 816 817 818 918 919 1019 917 fig.5 sequence of writing data bytes into ram with horizontal addressing (v = 0). handbook, full pagewidth mgu624 09 110 2 3 4 5 0 10 8 0 101 x address icons y address 6 7 8 918 1019 917 fig.6 sequence of writing data bytes into the ram with vertical addressing (v = 1).
2004 mar 05 12 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7.10 data order the data order bit (do) defines the bit order (msb on top or lsb on top) for writing in the ram; see figs 7 and 8. handbook, full pagewidth mgw739 msb lsb msb lsb fig.7 display data ram byte organisation; do = 1. handbook, full pagewidth mgw738 lsb msb lsb msb fig.8 display data ram byte organisation; do = 0.
2004 mar 05 13 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7.11 mirror x the mx bit allows horizontal mirroring. when mx = 1, the x address space is mirrored (see fig.9). the addres sx=0is then located at the right side (column 101) of the display. when mx = 0, mirroring is disabled and the address x = 0 is located at the left side (column 0) of the display (see fig.10). handbook, full pagewidth mgu626 0 10 8 0 101 x address y address fig.9 display data ram format addressing; mx = 1. handbook, full pagewidth mgu625 0 10 8 0 101 x address y address fig.10 display data ram format addressing; mx = 0.
2004 mar 05 14 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7.12 mirror y the my bit allows vertical mirroring. when my = 1, the y address space is mirrored resulting in an upside-down display. the addres sy=0is then located at the bottom of the display (see fig.11). when my = 0, the mirroring is disabled and the address y = 0 is located at top of the display (see fig.12). a change in the state of my has an immediate effect on the display and the effect of my is visible immediately the bit is modified. this feature makes it possible to mount the device at the top or bottom of the display. handbook, full pagewidth mgu628 10 0 8 0 101 x address y address fig.11 display data ram format addressing; my = 1. handbook, full pagewidth mgu627 0 10 8 0 101 x address y address fig.12 display data ram format addressing; my = 0.
2004 mar 05 15 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 7.13 bottom row swap this mode swaps the order of the order of the rows; see figs 13 and 14. the mode is useful to aide routing to displays when it is not possible to pass tracks under the device, as in the case of tape carrier packages (tcp). 7.14 output row order the order in which the rows are activated is a function of bits bottom row swap (brs), mirror y (my) and normal partial mode (n/ p). this has important implications when the device is used either in cog or tcp applications. when my is set to 0, the ram is accessed in a linear manner, starting at r0, counting to r66, then jumping to the end for the icon data. when my is set to 1, the ram is still accessed in a linear manner but starting from the last row, counting down to zero and then jumping to the icon data. when n/ p is set to 1, the free programmable mux rate (fpmr) mode is disabled and row addressing is in normal mode (see section 11.9), therefore counting is the same as for my = 0 and brs = 0. when n/ p is 0, fpmr mode is enabled. only 65 rows are addressed/read in fpmr mode. figures 13 and 14 show the possibility of connecting the icon row (row r67) at the top or bottom of the display. handbook, full pagewidth mgw793 interface columns r15 r0 r47 r32 r15 r16 ram r31 r32 r47 r48 r63 r0 r67 r16 r31 r63 r67 r48 r67 r66 r67 fig.13 row order and interconnection with brs = 0, my = 0 and n/ p=1.
2004 mar 05 16 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 mgw794 handbook, full pagewidth interface columns r35 ram r66 r0 r34 r0 r1 r2 r67 r67 r66 r51 r34 r19 r50 r35 r3 r67 r18 r67 fig.14 row order and interconnection with brs = 1, my = 0 and n/ p=1.
2004 mar 05 17 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 8 parallel interfaces the parallel interface is an 8-bit bidirectional interface for communication between the microcontroller and the lcd driver chip. two different parallel interfaces can be selected by the inputs ps2, ps1 and ps0. 8.1 6800-type parallel interface the interface functions of the 6800-type parallel interface are shown in table 2. table 2 6800-type parallel interface function the 6800-type parallel interface can be configured to have the clock connected to the enable input (e) with timing as shown in fig.38, or with the clock connected to the chip select input ( sce) and the enable (e) is tied high with timing as shown in fig.39. the pcf8813 is capable of detecting these different modes automatically. 8.2 8080-type parallel interface table 3 shows the interface functions of the 8080-type parallel interface. table 3 6800-type parallel interface function 9 serial interfaces communication with the microcontroller can also be via a clock-synchronized serial peripheral interface. it is possible to select two different 3-line interfaces (spi and serial interface) or a 4-line serial interface (spi). selection of the interface is made with the inputs ps2, ps1 and ps0 (see section 7.1). 9.1 serial peripheral interface the serial peripheral interface (spi) is a 3-line or 4-line interface for communication between the microcontroller and the lcd driver. the 3-line interface requires a chip enable input ( sce), serial clock (sclk) and serial data (sdata). for the 4-line serial interface, a separate d/ c line is added. the pcf8813 is connected to the serial data i/o (sdata) of the microcontroller via the pads data input (sdata) and data output (sdout) connected together. 9.1.1 w rite mode the display data/command indication may be controlled via software or by the d/ c select input. when the d/ c input is used, display data is transmitted when d/ c is high, and command data is transmitted when d/ c is low (see figs 15 and 16). when d/ c is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 256) are to be transmitted (see fig.17). the byte that follows the display data string is handled as an instruction command. if sce is pulled high during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. the next byte received will be handled as an instruction command (see fig.18). d/ cr/ wr operation 0 0 command data write 0 1 read status register 1 0 display data write 1 1 none d/ c rd wr operation 0 1 0 command data write 0 0 1 read status register 1 1 0 display data write 1 1 1 none
2004 mar 05 18 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth sce d/c sclk sdata db7 db6 db5 db4 db3 db2 db1 db0 mgw744 fig.15 serial bus protocol; transmission of one byte. handbook, full pagewidth sce d/c sclk sdata db7 db6 db5 db4 db3 db2 db1 db0 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 mgw745 fig.16 serial bus protocol; transmission of several bytes. handbook, full pagewidth sce sclk sdata db7 db6 db5 db4 display length instruction and length data (two bytes) db2 db1 db0 db2 data data last data db7 db6 db5 db4 db3 db1 db0 mgw746 instruction display data string fig.17 transmission of several bytes.
2004 mar 05 19 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth mgw747 sce sclk sdata data data data data data data db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 db5 db4 instruction display data string fig.18 transmission interrupted by sce. 9.1.2 r ead mode the interface read mode means that the microcontroller reads data from the pcf8813. to do so the microcontroller first has to send a command, the read status command, and then the pcf8813 will respond by transmitting data on the sdout line. after that sce is required to go high before a new command is sent (see fig.17). the pcf8813 samples sdata at rising sclk edges, but shifts sdout data at falling sclk edges. thus the microcontroller reads sdout data at rising sclk edges. after the read status command has been sent, the sdata line must be set to 3-state not later then at the falling sclk edge of the last bit (see fig.19). handbook, full pagewidth res sclk sdata db7 db6 db5 db4 db2 db3 db1 db0 sdo instruction db2 db7 db6 db5 db4 db3 db1 db0 mgu629 read out data sce fig.19 spi 3-line and 4-line read mode.
2004 mar 05 20 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 9.2 serial interface (3-line) handbook, full pagewidth mgw713 transmission byte d7 d6 d5 d4 d3 d2 d1 d0 msb lsb transmission byte (1) d/c transmission byte d/c d/c transmission byte d/c fig.20 serial data stream, write mode. (1) a transmission byte may be a command byte or a data byte. the serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the lcd driver chip. the three lines are: sce (chip enable), sclk (serial clock) and sdata (serial data). the pcf8813 is connected to the sda of the microcontroller by the sdata (data input) and sdout (data output) pads which are connected together. 9.2.1 w rite mode in the write mode of the interface, the microcontroller writes commands and data to the pcf8813. each data packet contains a control bit d/ c and a transmission byte. if d/ c is low, the following byte is interpreted as a command byte. if d/ c is high, the following byte is stored in the display data ram. the address counter is incremented automatically after every data byte. figure 20 shows the general format of the write mode and the definition of the transmission byte. any instruction can be sent in any order to the pcf8813. the msb of a byte is transmitted first. the serial interface is initialized when sce is high. in this state, sclk clock pulses have no effect and no power is consumed by the serial interface. a falling edge on sce enables the serial interface and indicates the start of data transmission. figures 21, 22 and 23 show the protocol of the write mode: when sce is high, sclk clocks are ignored; the serial interface is initialized during the high time of sce (see fig.21) at the falling sce edge sclk must be low (see fig.41) sdata is sampled at the rising edge of sclk d/ c indicates whether the byte is a command (d/ c=0) or ram data (d/ c = 1); it is sampled with the first rising sclk edge if sce stays low after the last bit of a command/data byte, the serial interface is ready for the d/ c-bit of the next byte at the next rising edge of sclk (see fig.22). a reset pulse with res interrupts the transmission and the data being written into the ram may be corrupted. the registers are cleared. if sce is low after the rising edge of res, the serial interface is ready to receive the d/ c-bit of a command/data byte (see fig.23).
2004 mar 05 21 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth sce d/c sclk sdata db7 db6 db5 db4 db3 db2 db1 db0 mgu630 fig.21 serial interface (3-line), write mode - control bit followed by a transmission byte. handbook, full pagewidth sce sclk sdata db7 d/c db6 db5 db4 db3 db2 transmission byte db1 db0 mgu631 db7 d/c db6 db5 db4 db3 db2 db1 db0 d/c transmission byte fig.22 serial interface (3-line), write mode - transmission of several bytes. handbook, full pagewidth mgu632 sce res sclk sdata db7 d/c db6 db5 db4 db7 db7 db6 db5 db4 db3 db2 db1 db0 db6 d/c d/c fig.23 serial interface (3-line), write mode - interrupted by reset ( res).
2004 mar 05 22 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 9.2.2 r ead mode handbook, full pagewidth mgu633 sce sclk sdata sdout db7 d/c db6 db5 db4 db7 db6 db5 db4 db3 db2 db1 db0 db3 db2 db1 db0 d/c fig.24 serial interface (3-line), read mode. in the read mode of the interface, that the microcontroller reads data from the pcf8813. to do this the microcontroller has first to send a command, then the read status command, and then the pcf8813 will respond by transmitting data on the sdout line. after that, sce is required to go high before a new command is sent (see fig.24). the pcf8813 samples the sdata data at rising sclk edges, but shifts sdout data at falling sclk edges. thus the microcontroller reads sdout data at rising sclk edges. after the read status command has been sent, the sdata line must be set to 3-state not later than at the falling sclk edge of the last bit. the 8th read bit is shorter than the others because it is terminated by the rising sclk edge (see fig.24). the last rising sclk edge sets sdout to 3-state after a delay time (see time t 4 in fig.44).
2004 mar 05 23 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 10 i 2 c-bus interface (hs-mode) 10.1 characteristics of the i 2 c-bus (hs-mode) the i 2 c-bus hs-mode is for bidirectional, two-line communication between different ics or modules with speeds up to 3.4 mhz. the only difference between hs-mode slave devices and fast-mode slave devices is the speed at which they operate, therefore the buffers on the slch and sdah outputs (1) have an open-drain. this is the same for i 2 c-bus master devices which have an open-drain sdah output and a combination of open-drain pull-down and current source pull-up circuits on the sclh output. only the current source of one master is enabled at any one time, and only during hs-mode. both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 10.1.1 s ystem configuration transmitter: the device that sends the data to the bus receiver: the device that receives the data from the bus master: the device which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronisation: procedure to synchronize the clock signals of two or more devices. (1) in hs-mode, scl and sda lines operating at the higher frequency are referred to as sclh and sdah. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.25 system configuration. 10.1.2 b it transfer one data bit is transferred during each clock pulse (see fig.26). the data on the sdah line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.26 bit transfer.
2004 mar 05 24 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 10.1.3 s tart and stop conditions both data and clock lines remain high when the bus is not busy (see fig.27). a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.27 definition of start and stop conditions. 10.1.4 a cknowledge each byte of eight bits is followed by an acknowledge bit (see fig.28). the acknowledge bit is a high signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.28 acknowledge on the i 2 c-bus.
2004 mar 05 25 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 10.2 i 2 c-bus hs-mode protocol the pcf8813 is a slave receiver/transmitter. if data is to be read from the device the sdah pad must be connected, otherwise sdahout may be unused. hs-mode can only commence after the following conditions: start condition (s) 8-bit master code (00001xxx) not-acknowledge bit ( a). the master code has two functions, as shown in figs 29 and 30, it allows arbitration and synchronization between competing masters at fast-mode speeds, resulting in one winner. also the master code indicates the beginning of an hs-mode transfer. as no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge ( a). after this a-bit, and the sclh line has been pulled up to a high level, the active master switches to hs-mode and enables at t h the current-source pull-up circuit for the sclh signal (see fig.30). the active master will then send a repeated start condition (sr) followed by a 7-bit slave address with a r/ w-bit, and receives an acknowledge bit (a) from the selected slave. after each acknowledge bit (a) or not-acknowledge bit ( a) the active master disables its current-source pull-up circuit. the active master re-enables its current source again when all devices have released and the sclh signal reaches a high level. the rising of the sclh is done by a resistor pull-up and so slower, the last part of the sclh rise time is speeded up because the current-source is enabled. data transfer only switches back to fast-mode after a stop condition (p). a write sequence after the hs-mode is selected is given in fig.29. the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, all the others will ignore the i 2 c-bus transfer. after acknowledgement of a write (w) cycle, one or more command words follow which define the status of the addressed slaves. a command word consists of a control byte, which defines co and d/ c, plus a data byte (see fig.31 and table 4). the last control byte is tagged with a cleared most significant bit, the continuation bit co. the control and data bytes are also acknowledged by all addressed slaves on the bus. table 4 co and d/ c de?nition bit 0/1 r/ w action co 0 n/a last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a stop or re-start condition 1 another control byte will follow the data byte unless a stop or re-start condition is received d/ c 0 0 data byte will be decoded and used to set-up the device 1 data byte will return the status byte 1 0 data byte will be stored in the display ram 1 ram read back is not supported after the last control byte, depending on the d/ c bit setting, a series of display data bytes or command data bytes may follow. if the d/ c-bit was set to logic 1, these display bytes are stored in the display ram at the address specified by the data pointer. the data pointer is updated automatically and the data is directed to the intended pcf8813. if the d/ c-bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. the acknowledgement after each byte is made only by the addressed pcf8813. at the end of the transmission the i 2 c-bus master issues a stop condition (p) and switches back to fast-mode, however, to reduce the overhead of the master code, its possible that a master links a number of hs-mode transfers, separated by repeated start conditions (sr). a read sequence (see fig.32) follows after the hs-mode is selected. the pcf8813 will immediately start to output the requested data until a not acknowledge is transmitted by the master. before the read access, the user has to set the d/ c-bit to the appropriate value by a preceding write access. the write access should be terminated by a re-start condition so that the hs-mode is not disabled.
2004 mar 05 26 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth f/s-mode hs-mode (current-source for sclh enabled) f/s-mode msc616 a a a/a data (n bytes + ack.) s r/w master code sr slave add. hs-mode continues sr slave add. p fig.29 data transfer format in hs-mode. msc618 8-bit master code 00001xxx a t h t 1 s fs mode hs-mode if p then fs mode if sr (dotted lines) then hs mode 16789 6789 1 1 2 to 5 2 to 5 2 to 5 67 89 sdah sclh sdah sclh t h t fs sr sr p n (8-bit data + a/a) 7-bit sla r/w a = mcs current source pull-up = rp resistor pull-up fig.30 complete data transfer in hs-mode.
2004 mar 05 27 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth mgu634 sr01111 s a 0 s a 1 0a acknowledge from pcf8813 acknowledge from pcf8813 acknowledge from pcf8813 acknowledge from pcf8813 acknowledge from pcf8813 1 control byte a data byte data byte n 3 0 bytes 1 byte slave address msb . . . . . . . . . . . lsb 2n 3 0 bytes a co co 0a ap control byte d/c d/c r/w fig.31 master transmits in hs-mode to slave receiver; write mode. handbook, full pagewidth mgu635 sr01111 s a 0 s a 1 1a acknowledgement from pcf8813 not acknowledgement from master status information a slave address stop condition p r/w fig.32 master receives from slave transmitter (status register is read); read mode. 10.3 command decoder the command decoder identifies command words that arrive on the i 2 c-bus. pairs of bytes C first byte determines whether information is display or instruction data C second byte contains information. stream of information bytes after co = 0; display or instruction data depending on last d/ c-bit. the most significant bit of a control byte is the continuation bit co. if this bit is logic 1, it indicates that only one data byte, either command or ram data, will follow. if the bit is logic 0, it indicates that a series of data bytes, either command or ram data, may follow. the db6 bit of a control byte is the ram data/command bit d/ c. when this bit is logic 1, it indicates that a ram data byte will be transferred next. if the bit is at logic 0, it indicates that a command byte will be transferred next.
2004 mar 05 28 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 11 instructions the pcf8813 interfaces via the 8-bit parallel interface, two different 3-line serial interfaces, 4-wire serial interface or an i 2 c-bus interface. processing of the instructions does not require the display clock. in the case of the parallel and 4-wire serial interface, data accesses to the pcf8813 can be divided into two areas; those that define the operating mode of the device, and those that fill the display ram; the distinction being the d/ c input. when the d/ c input is set to logic 0, the chip will respond to instructions as defined in table 5. when the d/ c bit is at logic 1, the chip will send data into the ram. when the 3-wire serial interface or the i 2 c-bus interface is used, the distinction between instructions that define the operating mode of the device and those that fill the display ram is made respectively by the display data length instruction (4-line spi) or by d/ c bit in the data stream (3-line serial interface and i 2 c-bus interface). there are four types of instructions: defining pcf8813 functions such as display configuration, etc. setting internal ram addresses performing data transfer with internal ram other instructions. in normal use, category 3 instructions are used most frequently. to lessen the mpu program load, automatic incrementing by one of the internal ram address pointers after each data write is implemented. table 5 instruction set instructions not expressly de?ned in this table and reserved instructions are not allowed in pcf8813 applications. instruction d/ cr/ w command byte description db7 (msb) db6 db5 db4 db3 db2 db1 db0 (lsb) h=0or1 nop 000 000000 0no operation function set 0 0 0 0 1 mx my pd v h power-down control; entry mode read status byte 0 1 0 00110 d (1) d (1) read status byte for serial and i 2 c-bus interfaces read status byte 0 1 busy don res mf2 mf1 mf0 ds1 ds0 reads parallel interface status byte write data 1 0 d7 d6 d5 d4 d3 d2 d1 d0 writes data to ram h=0 reserved 0 0 0 00001xxdo not use display control 0 0 0 0 0 0 1 d 0 e sets display con?guration set lower/higher program range 000 001000prsv lcd programming range set power control hvgen on/off 000 001001pcs witch hvgen on/off display con?guration 0 0 0 001011 d (1) double command byte: set data order; top/bottom row swap mode 000 0000d00brs
2004 mar 05 29 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 set display data length 000 111 d (1) d (1) d (1) d (1) double command byte; set display data length, only used in 3-line spi 00 0 d6d5d4d3d2d1 d0 set y address of ram 000 100y 3 y 2 y 1 y 0 sets y address of ram: 0 y 9 set maximum y address 000 101 d (1) d (1) d (1) d (1) double command byte: set maximum y: 0 y 8 000 000y max3 y max2 y max1 y max0 set maximum x address 000 110 d (1) d (1) d (1) d (1) double command byte: set maximum x: 0 y 101 00 0x max6 x max5 x max4 x max3 x max2 x max1 x max0 set x address of ram 00 1 x 6 x 5 x 4 x 3 x 2 x 1 x 0 sets x address of ram: 0 x 101 h=1 reserved 0 0 0 000000 1 reserved 0 0 0 000001 x temperature compensation 000 00001tc 1 tc 0 set temperature coef?cient (tcx) set hvgen stages 0 0 0 00010s 1 s 0 set multiplication factor bias system 0 0 0 0010bs 2 bs 1 bs 0 set bias system (bsx) reserved 0 0 0 1100 d (1) d (1) d (1) double command byte: do not use 000 000 d (1) d (1) d (1) d (1) normal or partial display mode 000 1010 d (1) d (1) d (1) double command byte: set normal or partial display mode 000 000000n/ p free programmable mux rate 000 1101 d (1) d (1) d (1) double command byte: set mask register for fpmr mode (1 : 9, 17, and 25 to 64) 00 m 7 m 6 m 5 m 4 m 3 m 2 m 1 m 0 set initial row to be displayed 000 1001 d (1) d (1) d (1) double command byte: set start row 0 x 66 00 0 c 6 c 5 c 4 c 3 c 2 c 1 c 0 set ram line address for initial row 000 1011 d (1) d (1) d (1) double command byte; sets ram line address to be displayed 0 l 66 00 0 l 6 l 5 l 4 l 3 l 2 l 1 l 0 instruction d/ cr/ w command byte description db7 (msb) db6 db5 db4 db3 db2 db1 db0 (lsb)
2004 mar 05 30 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 note 1. d = dont care. table 6 explanation of mnemonics used in table 5 disable otp circuitry 0 0 0 001110 0 disable otp circuitry enter module maker calibration mode 000 001111 0 module maker calibration software reset 0 0 0 111000 1 enable software reset set v pr 00 1v pr6 v pr5 v pr4 v pr3 v pr2 v pr1 v pr0 write v pr to register bit 0 1 reset state pd chip active chip is in power-down mode 1 h basic command set extended command set 0 v horizontal addressing vertical addressing 0 pc power control off power control on 1 mx normal x addressing x address is mirrored 0 my display is not vertically mirrored display is vertically mirrored 0 trs top rows are not mirrored top rows are mirrored 0 brs bottom rows are not mirrored bottom rows are mirrored 0 do lsb is on top msb is on top 1 prs v lcd programming range low v lcd programming range high 0 n/ p partial display driving mode normal display driving mode 1 c[6:0] sets the initial r0 of the display.; this command cannot access r67 (icon row) 0000000 l[6:0] sets the line address of the display ram to be displayed on the initial r0; this command cannot access r67 0000000 y max [3:0] sets maximum y address for wraparound 1000 x max[ 6:0] sets the maximum x address 1100101 d, e display control; see table 8 00 tc[1:0] set temperature coef?cient; see table 9 00 s[1:0] set voltage multiplication factor; see table 10 00 bs[2:0] bias system 000 v pr [6:0] v lcd programming 0000000 m[7:0] set partial display (full display = 11111111) 11111111 instruction d/ cr/ w command byte description db7 (msb) db6 db5 db4 db3 db2 db1 db0 (lsb)
2004 mar 05 31 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 table 7 read status byte bit function busy 0 = chip is able to accept new commands; 1 = chip is unable to accept new commands don 0 = display off; 1 = display on res 0 = reset not in progress; 1 = reset in progress mf[2:0] manufacturer identi?cation bits ds[1:0] device recognition; currently has a ?xed value of 00 (recognition bits for a driver with 64 to 67 rows) table 8 display control; bits d and e table 9 set temperature coef?cient; bits tc[1:0] table 10 set voltage multiplication factor; bits s[1:0] 11.1 initialization immediately following power-on, all internal registers as well as the ram content are undefined. a res pulse must be applied to the reset input. reset is accomplished by applying an external reset pulse (active low) at the pad res. when reset occurs within the specified time all internal registers are reset, however the ram is still undefined. the res input must be 0.3v dd when v dd reaches v dd(min) (or higher) within a maximum time t vhrl after v dd going high (see fig.37). a reset can also be made by sending a reset command. this command can be used during normal operating but not to initialize the chip after power-on. 11.2 reset function after reset the lcd driver has the following state: power-down mode (pd = 1) horizontal addressing (v = 0) normal instruction set (h = 0) display blank (d an de=00) address counter x[6:0] = 0000000 and y[3:0] = 0000 temperature control mode tc[1:0] = 00 v lcd is equal to 0 and prs = 0 power control is enabled (pc = 1) normal row driving of display (n/ p=1) partial mode set for all rows available (m[7:0] = 11111111) hv generator programmed off (v pr [6:0] = 0000000) 2 voltage multiplier (s[1:0] = 00) after power-on, ram data is undefined, the reset signal does not change the content of the ram data order do = 0 all lcd outputs at v ss (display off) bias system (bs[2:0] = 000 display start line set to r0 (c[6:0] = 000000) ram line address set to 0 (l[6:0] = 000000) maximum x address = 101 (x max [6:0] = 1100101) maximum y address = 8 (y max [3:0] = 1000) display is not mirrored (mx = 0; my = 0 and brs = 0). 11.3 power-down mode power-down mode gives the following circuit status: v lcd discharges to v ss as power-down mode occurs all lcd outputs go to v ss (display off) bias generator and v lcd generator switch-off, v lcd can be disconnected oscillator switches off (external clock is possible) ram contents are not cleared; ram data can be written. d e function 0 0 display blank 1 0 normal mode 0 1 all display segments on 1 1 inverse video mode tc 1 tc 0 function 00v lcd temperature coef?cient 0 01v lcd temperature coef?cient 1 10v lcd temperature coef?cient 2 11v lcd temperature coef?cient 3 s 1 s 0 function 002 voltage multiplier 013 voltage multiplier 104 voltage multiplier 115 voltage multiplier
2004 mar 05 32 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 11.4 display control bits d and e (see table 8) select the display mode. when bit mx = 0, the display ram is written from left to right (x = 0 is on the left side and x = 101 is on the right side of the display). when bit mx = 1, the display ram is written from right to left (x = 0 is on the right side and x = 101 is on the left side of the display). the bit mx has an impact on the way the ram is written. so if horizontal mirroring of the display is required, the ram must first be rewritten. when bit my = 1, the display is mirrored vertically. a change of bit my has an immediate effect on the display. when bi tv=0, horizontal addressing is selected and data is written into the ddram as shown in fig.5. when bit v = 1, vertical addressing is selected, then data is written into the ddram as shown in fig.6. 11.5 set y address of ram bits y[3:0] define the y address vector address of the display ram. table 11 range of y address and allowable x range in bank 8 only three bits are accessed, and in bank 10 only one bit is accessed. 11.6 set x address of ram the x address points to the columns. the range of x is 0 to 101 (65h). 11.7 set maximum x address or y address these two commands (x max [6:0] and y max [3:0]) set the maximum address for wraparound to occur for the columns. the range of x max is 0 to 101. the maximum y address also sets the y address for wraparound to occur. the range of y max is 0 to 8. by design, the maximum y setting cannot access bank 10. x max and y max together also define when wraparound-to-zero takes place. these two commands are effective only when writing to the ram. 11.8 set display start line, initial start row and row 0 set display start line l[6:0] allows the display line address of the display ram to be chosen. the range is from line 0 to line 66 inclusive. the ram address line 67 is not available for this command as it is reserved for icons. this command has an effect on the mapping between the data of the ram and the display. the l address specifies which rows of the ram are output to which row outputs of the display. the value of the l address defines which row of the ram will be row 0. row 0 of the display can in turn be set by the set initial row command c[6:0]. figure 33 shows an example of how ram data is mapped onto the display. in this example, the l command sets the data on line 8 of the ram to be displayed. this data is displayed on a row set by the c command (16). when l and c are set to 8 and 16 respectively, data from ram lines 4 to 7 is displayed on display rows 12 to 15 and ram data from lines 15 to 18 is displayed on display lines 23 to 26. when my is active (my = 1), the data from fig.33 is mapped from the ram to the display as shown in fig.34. note the new location of c after my. 11.9 set normal or partial display mode when n/ p = 1, the pcf8813 can operate only as a 67 + 1 row driver operating with a 1 : 68 multiplex rate. when n/ p = 0, the driver is used in free programmable multiplex rate where up to eight different multiplex rates can be selected in steps of 8, depending on the mask register value m[7:0]. when the pcf8813 is operating in fpmr mode, only the first 64 rows plus the icon row are available to the user. table 12 normal or partial mode display y address ram content allowed x range 3210 0 0 0 0 bank 0 (display ram) 0 to 101 0 0 0 1 bank 1 (display ram) 0 to 101 0 0 1 0 bank 2 (display ram) 0 to 101 0 0 1 1 bank 3 (display ram) 0 to 101 0 1 0 0 bank 4 (display ram) 0 to 101 0 1 0 1 bank 5 (display ram) 0 to 101 0 1 1 0 bank 6 (display ram) 0 to 101 0 1 1 1 bank 7 (display ram) 0 to 101 1 0 0 0 bank 8 (display ram) 0 to 101 1 0 1 0 bank 10 (display ram) 0 to 101 n/ p action 0 partial mode display: 65 rows available 1 normal mode display: 68 rows available
2004 mar 05 33 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 11.10 free programmable multiplex rate the free programmable multiplex rate concept allows the user to limit the number of rows selected to groups of eight. any, or all of these groups of rows can be enabled or disabled. the mask register command (m[7:0]) allows the user to turn-on or turn-off blocks of eight rows. each mask value controls a block of eight rows, thus in partial mode the maximum number of rows available is 64 plus the icon row. a logic 1 in the mask register enables the rows available within that block of rows, and a logic 0 disables them. the mask register causes the row counter to count eight bits and then jump to the next enabled 8-bit group. for example, if the mask register value is 00001101, then the rows available will be 0 to 7, 16 to 23, 24 to 31 and 67. rows 8 to 15 and 32 to 63 have been skipped. this information is also mapped to the ram so that only the contents of active rows are displayed. table 13 range of free programmable multiplex rates mask register rows available m0 r0 to r7 + icon row m1 r8 to r15 + icon row m2 r16 to r23 + icon row m3 r24 to r31 + icon row m4 r32 to r39 + icon row m5 r40 to r47 + icon row m6 r48 to r55 + icon row m7 r56 to r63 + icon row table 14 examples of display normal driving mode and partial display driving mode mask register mask value row sequence normal display n/ p=1 (the mask value is dont care when n/p = 1 because all rows are enabled) m0 1 0 to 7 battery status: xxx m1 0 8 to 15 address book m2 0 16 to 23 connection time m3 1 24 to 31 network: yyy m4 0 32 to 39 reception strength m5 0 40 to 47 2 june; 15:25 m6 0 48 to 55 m7 1 56 to 63 keyboard locked not available in mask register 64 to 66 not available in mask register 67 (icon row) n/ p=0 m0 1 0 to 7 battery status: xxx m1 0 8 to 15 m2 0 16 to 23 m3 1 24 to 31 network: yyy m4 0 32 to 39 m5 0 40 to 47 m6 0 48 to 55 m7 1 56 to 63 keyboard locked not available in mask register 67 (icon row)
2004 mar 05 34 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 mgu636 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 56 57 58 59 60 61 62 63 64 65 66 67 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 row 3 row 1 row 0 row 2 row 7 row 5 row 4 row 6 row 11 row 9 row 8 row 10 row 15 row 13 row 12 row 14 row 23 row 21 row 20 row 22 row 27 row 25 row 24 row 26 row 31 row 29 row 28 row 30 row 35 row 33 row 32 row 34 row 19 row 17 row 16 row 18 row 39 row 37 row 36 row 38 row 67 row 65 row 64 row 66 l-address = 8 c-address = 16 ram display 0 y address icons only icons only set initial display line and start row when my = 0 1 2 3 7 9 8 fig.33 effect of l address when my = 0.
2004 mar 05 35 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 mgu637 handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 56 57 58 59 60 61 62 63 64 65 66 67 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 row 3 row 1 row 0 row 2 row 17 row 21 row 19 row 18 row 20 row 25 row 23 row 22 row 24 row 43 row 41 row 30 row 42 row 47 row 45 row 44 row 46 row 51 row 49 row 48 row 50 row 55 row 53 row 52 row 54 row 29 row 27 row 26 row 28 row 59 row 60 row 61 row 62 row 63 row 57 row 56 row 58 row 67 row 65 row 64 row 66 l-address = 8 effective c-address ram display 0 y address icons only icons only set initial display line and start row when my = 1 1 2 3 7 9 8 fig.34 effect of l address when my = 1.
2004 mar 05 36 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 11.11 set hv generator stages the pcf8813 incorporates a software-configurable voltage multiplier. after reset ( res) the voltage multiplier is set to 2 v dd2 . other voltage multiplier factors are set via the set hvgen stages command bits s[1:0]. 11.12 bias system the bias voltage levels are set in the ratio of r-r-nr-r-r giving a 1/(n + 4) bias system. different multiplex rates require different n factors. this is programmed by bs[2:0] (see table 15). for multiplex rates of 1 : 68 the optimum bias value n is given by: resulting in 1 / 9 bias. changing the bias system from the optimum value will have a consequence for the contrast and viewing angle. one reason to depart from the optimum would be to reduce the required operating voltage. a compromise between contrast and operating voltage must be found for any particular application. table 15 bias system programming table 16 lcd bias voltage notes 1. operation of bias level v4 is given for v4 > v ss + 0.9 v. for higher multiplex rates, v lcd has to be selected accordingly. 2. for multiplex rates equal to or lower than 1 : 24 (n = 2) operation of the bias level v5 is limited to voltages v5 < v dd2,3 - 1.1 v. v lcd has to be selected accordingly. the operating voltage can be set by software through the interface. the binary number v op representing the operating voltage can be set according to the following formula: where: v op is an 8-bit unsigned number used internally for generation of the lcd supply voltage v lcd v cal is a 5-bit twos complement number set by the module maker; see table 17 v pr is an 8-bit unsigned number composed of prs and v pr* set by an interface command. the corresponding voltage at the reference temperature, t cut , can be calculated as: bs[2] bs[1] bs[0] n recommended multiplex rates 00071:100 00161:80 0 1 0 5 1:65or1:67 01141:48 1 0 0 3 1:34or1:40 10121:24 1 1 0 1 1:18or1:16 1 1 1 0 1:10,1:9or1:8 n683 C 5.246 5 === symbol bias voltages bias voltages for 1 / 9 bias v1 v lcd v lcd v2 8 / 9 v lcd v3 7 / 9 v lcd v4 (1) 2 / 9 v lcd v5 (2) 1 / 9 v lcd v6 v ss v ss n3 + () n4 + () ----------------- n2 + () n4 + () ----------------- 2 n4 + () ----------------- 1 n4 + () ----------------- v op v cal 4:0 [] v pr * + = v lcd tcut () av op b + () =
2004 mar 05 37 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 the generated voltage at v lcd is dependent on the temperature, programmed temperature coefficient (tc) and the programmed voltage at the reference temperature (t cut ): t cut and voltages a and b for each temperature coefficient are quoted in table 17. the maximum voltage that can be generated is dependent on the voltage of v dd2 and the display load current. as the programming range for the internally generated v lcd allows values above the maximum allowed v lcd , the user must ensure that while setting the v pr register and selecting the temperature compensation, under all conditions and including all tolerances the v lcd maximum limit of 9.0 v will never be exceeded. for a particular liquid crystal, the optimum v lcd can be calculated for a given multiplex rate. for 1 : 68, the optimum operating voltage of the liquid crystal can be calculated as; where v th is the threshold voltage of the liquid crystal used. v lcd av op b + [] 1tc tt cut C () + [] = v lcd 168 + 21 1 68 ---------- C ? ?? --------------------------------------- v th 6.98 v th == table 17 parameters of hv generator programming (typical values) nominal temperature = 27 c; temperature coef?cients calculated at nominal v lcd = 8.6 v. symbol parameter tc0 tc1 tc2 tc3 unit a ?rst level v lcd voltage 4.57 4.27 4.01 3.84 v b programmed voltage step 30.5 28.5 26.7 25.6 mv t cut reference temperature 27 27 27 27 c tc temperature coef?cient 0.00 - 0.25 - 0.48 - 0.64 mv/k handbook, full pagewidth mgt847 00 01 02 a v lcd v op 03 04 05 06 . . . . . . fd fe ff b fig.35 v lcd as a function of v op [7:0] programming. if v pr [6:0] is set to zero, the charge pump is turned off. depending on v pr restrictions defined in table 17 and depending on v cal , not all v op [7:0] values can be selected.
2004 mar 05 38 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 12 temperature compensation due to the temperature dependency of the liquid crystal viscosity, the lcd controlling voltage v lcd must be increased at lower temperatures to maintain optimum contrast. figure 36 shows v lcd for high multiplex rates. in the pcf8813 the temperature coefficient to be applied to v lcd can be selected from four values by setting bits tc[1:0]. 13 limiting values in accordance with the absolute maximum rating system (iec 60134); see notes 1 and 2 notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified; all voltages are with respect to v ss unless otherwise specified. 3. v dd2 and v dd3 are always equal. 14 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd1 supply voltage - 0.5 +6.5 v v dd2 , v dd3 supply voltage (voltage multiplier); see note 3 - 0.5 +4.5 v v lcd lcd supply voltage - 0.5 +9.0 v v i input voltage (any pad) - 0.5 v dd + 0.5 v i ss ground supply current - 50 +50 ma i i , i o dc input or output current - 10 +10 ma p tot total power dissipation - 300 mw p o power dissipation per output - 30 mw t stg storage temperature - 65 +150 c t j junction temperature - 150 c handbook, full pagewidth mgt848 t v lcd fig.36 v lcd as a function of liquid crystal temperature.
2004 mar 05 39 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 15 dc characteristics v dd1 = 1.7 to 3.3 v; v ss =0v; v lcd = 3.0 to 9.0 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. v dd2 and v dd3 are always equal. 2. the maximum possible v lcd voltage that may be generated depends on voltage, temperature and load (display). 3. valid for the temperature, v pr and tc values used at calibration. 4. normal mode and internal clock. 5. conditions: v dd1 = 1.8 v; v dd2 = 2.70 v; v lcd = 7.6 v; voltage multiplier = 4 v dd2 ; bias system 1 / 9 ; inputs at v dd1 or v ss ; v lcd generation = internal; v lcd output loaded by 10 m a; t amb =25 c. 6. f intclk = 0 (no data bus clock). 7. power-down mode; during power-down all static currents are switched off. symbol parameter conditions min. typ. max. unit v dd1 supply voltage (logic circuits) 1.7 - 3.3 v v dd2 , v dd3 supply voltage (voltage multiplier) note 1 2.4 - 4.5 v v lcdin lcd supply voltage input 3.0 - 9.0 v v lcdout generated lcd supply voltage note 2 4.5 - 9.0 v v lcd(tol) tolerance of generated lcd supply voltage note 3 - 70 -+ 70 mv i dd(tot) total supply current (i dd1 +i dd2 +i dd3 ) normal mode; notes 4, 5, 6 - 100 300 m a power-down mode; note 7 - 0.5 10 m a i dd1 supply current external v lcd ; notes 4, 6, 8 - 10 35 m a i lcd lcd supply current external v lcd ; notes 4, 6, 8 - 30 -m a logic circuits v ol low-level output voltage i ol = 0.5 ma v ss - 0.2v dd v v oh high-level output voltage i oh = - 0.5 ma 0.8v dd - v dd v v il low-level input voltage v ss - 0.2v dd v v ih high-level input voltage 0.8v dd - v dd v i l leakage current v i =v dd or v ss - 1 - +1 m a column and row outputs r col column output resistance c0 to c101 v lcd = 7.6 v; note 9 - 520k w r row row output resistance r0 to r67 v lcd = 7.6 v; note 9 - 520k w v col(tol) bias tolerance c0 to c101 note 9 - 100 0 +100 mv v row(tol) bias tolerance r0 to r67 note 9 - 100 0 +100 mv lcd supply voltage generator tc v lcd temperature compensation v lcd(nom) = 8.6 v temperature coef?cient 0 - 0.00 - mv/k temperature coef?cient 1 -- 0.23 - mv/k temperature coef?cient 2 -- 0.48 - mv/k temperature coef?cient 3 -- 0.64 - mv/k
2004 mar 05 40 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 8. v lcd external voltage applied to v lcdin and v lcdsense inputs; v lcdout disconnected; v pr and pc set to 0 (charge pump off); display load current is not transmitted to i dd . 9. load current = 10 m a; outputs tested one at a time. 16 ac characteristics v dd1 = 1.7 to 3.3 v; v ss =0v; v lcd = 3.0 to 9.0 v; t amb = - 40 to +85 c; all timings speci?ed are based on 20% to 80% of v dd with an input voltage swing of v ss to v dd ; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit f ext external clock frequency note 1 20 38 65 khz f frame frame frequency internal oscillator note 2 56 66 76 hz note 3 62 69 76 hz t vhrl v dd on to res low time see fig.37 0 (4) - 1 m s t rw reset pulse width low time see fig.37 500 -- ns t r(oper) end of reset pulse to interface operational see fig.37 1000 -- ns 6800-type parallel bus ; v dd1 = 1.8 to 3.3 v; see figs 38 and 39 t dcsu data/ command set-up time 0 - 25 ns t dchd data/ command hold time 0 -- ns t ds(cyc) data strobe cycle time 1000 -- ns t dsl data strobe low time 300 -- ns t dsh data strobe high time 300 -- ns t rwsu read/ wr ite set-up time 0 -- ns t rwhd read/ wr ite hold time 0 -- ns t esu chip enable set-up time 0 -- ns t ehd chip enable hold time 0 -- ns t datsu data set-up time 80 -- ns t dathd data hold time 30 -- ns t datacc output access time -- 280 ns t datoh output disable time 10 - 200 ns 8080-type parallel bus ; v dd1 = 1.8 to 3.3 v; see fig.40 t dcsu data/ command set-up time 0 - 25 ns t dchd data/ command hold time 0 -- ns t ds(cyc) data strobe cycle time 1000 -- ns t dslr data strobe low time (read) 120 -- ns t dslw data strobe low time (write) 240 -- ns t dshr data strobe high time (read) 120 -- ns t dshw data strobe high time (write) 120 -- ns t datsu data set-up time 80 -- ns t dathd data hold time 30 -- ns t datacc output access time -- 280 ns t datoh output disable time 10 - 200 ns
2004 mar 05 41 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 3-line and 4-line spi and serial interface ; v dd1 = 1.8 to 3.3 v; figs 41 to 44; note 5 f sclk sclk frequency -- 9 mhz t cyc sclk cycle time 111 -- ns t pwh1 sclk pulse width high 45 -- ns t pwl1 sclk pulse width low 45 -- ns t pwh2 sce minimum high time 50 -- ns t s1 sdata set-up time 50 -- ns t h1 sdata hold time 50 -- ns t s2 sce set-up time 60 -- ns t h2 sce hold time 45 -- ns t s3 data/ command set-up time 50 -- ns t h3 data/ command hold time 50 -- ns t 1 sdout access time -- 80 ns t 2 sdout disable time note 6 -- 80 ns t 3 sce hold time 50 -- ns t 4 sdout disable time note 7 -- 80 ns c b capacitive load for sdout note 8 -- 30 pf r b series resistance for sdout note 8 -- 500 w i 2 c-bus interface in fast-mode ; v dd1 = 1.7 to 3.3 v; fig.45 f scl scl clock frequency 0 - 400 khz t low scl clock low period 1.3 --m s t high scl clock high period 0.6 --m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 - 0.9 m s c b capacitive load represented by each bus line -- 400 pf t su;sta set-up time for a repeated start condition 0.6 --m s t hd;sta start condition hold time 0.6 --m s t su;sto set-up time for stop condition 0.6 --m s t sp tolerable spike width on bus note 9 -- 50 ns i 2 c-bus interface in hs-mode ; v dd1 = 1.7 to 3.3 v; fig.46 f sclh sclh clock frequency 0 - 3.4 mhz t su;sta set-up time (repeated) start condition 160 - - ns t hd;sta hold time (repeated) start condition 160 -- ns t low low period of the sclh clock 160 -- ns t high high period of the sclh clock 60 -- ns t su;dat data set-up time 10 -- ns symbol parameter conditions min. typ. max. unit
2004 mar 05 42 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 notes 1. f frame = : (n depends on the multiplex rate, see table 18). 2. v dd1 = 1.7 v to 3.3 v; v ss = 0 v; v lcd = 3.0 to 9.0 v; t amb = - 40 to +85 c, all mux settings. 3. v dd1 = 2.4 v to 3.0 v; t amb = - 20 c to +70 c; mux = 68. 4. res may be low before v dd on. 5. maximum values are for f sclk = 9 mhz. series resistance includes ito track + connector resistance + printed-circuit board. 6. sdout disable time for spi 3-line or 4-line interface. 7. sdout disable time for serial 3-line interface. 8. typical conditions: v dd1 = 2.8 v, t amb =20 c, mux = 68; f frame =70 3.4 hz. 9. inputs sdah and sclh are filtered and will reject spikes on the bus lines with a width of less than t sw(max) . t hd;dat data hold time 0 - 70 ns t su;sto set-up time for stop condition 160 -- ns c b capacitive load for sdah and sclh lines total capacitance of one bus line -- 100 pf capacitive load for sdah + sda line and sclh + scl line -- 400 pf t sp tolerable spike width on bus note 9 -- 5ns symbol parameter conditions min. typ. max. unit f ext n ------- table 18 value of n as a function of multiplex rate multiplex rate n 68 483 65 462 57 464 49 500 41 504 33 476 25 468 17 505 9 500
2004 mar 05 43 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 t r(oper) sce handbook, full pagewidth mgu285 t vhrl t rw res v dd1 fig.37 reset timing. handbook, full pagewidth t ds(cyc) t rwhd t dcsu t esu t rwsu t dathd t ehd t datsu t dsl t dsh t datacc t datoh mgu638 d/c sce e r/w d0 to d7 (write) d0 to d7 (read) t dchd fig.38 parallel interface timing (6800-type) with clocking performed by enable input (e).
2004 mar 05 44 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth mgu639 t datsu t dathd t dsl t ds(cyc) t dsh t datacc t datoh t dchd t rwsu t rwhd t dcsu d0 to d7 (write) d0 to d7 (read) e d/c r/w sce fig.39 parallel interface timing (6800-type) with clocking performed by chip select input ( sce).
2004 mar 05 45 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth t ds(cyc) t dchd t dcsu t dathd t datsu t datacc t datoh t dshr , t dshw t dslr , t dslw mgu640 d/c sce wr, rd d0 to d7 (write) d0 to d7 (read) fig.40 parallel interface timing (8080-type).
2004 mar 05 46 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth mgu642 t h1 t pwh1 t pwl1 t s1 t s2 t s2 t h2 t cyc t pwh2 sce sclk sdata fig.41 3-line serial interface timing. handbook, full pagewidth mgu854 t pwh1 t pwl1 t h3 t s2 t s3 t s2 t h2 t cyc t pwh2 sce d/c sclk sdata fig.42 4-line serial interface timing.
2004 mar 05 47 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth mgw759 t 2 t 3 t 1 t h1 t s1 sce sclk sdout sdata fig.43 3-line and 4-line serial peripheral (spi) interface timing (read mode). handbook, full pagewidth mgw760 t 4 t 3 t 1 t h1 t s1 sce sclk sdout sdata fig.44 3-line serial interface timing (read mode).
2004 mar 05 48 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.45 i 2 c-bus timing diagram (fast-mode). handbook, full pagewidth mgk871 sdah sr sr p sclh = mcs current source pull-up = rp resistor pull-up t fda t rda t hd;sta t su;dat t rcl t low t high t hd;dat t low t high t rcl1 t fcl t su;sto t rcl1 (1) (1) t su;sta fig.46 i 2 c-bus timing diagram (hs-mode). (1) rising edge of the first sclh clock pulse after an acknowledge bit.
2004 mar 05 49 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 17 module maker programming one time programmable (otp) technology has been implemented on the pcf8813. this enables the module maker to program some features of the pcf8813 after it has been assembled on an lcd module. programming is made under the control of the interfaces and using the special pad v otpprog . this pad must be made available on the module glass but does not need to be accessed by the set maker. module maker programming is an extension of the normal functions of the pcf8813 and is effective until specifically instructed otherwise with the disable otp command. the pcf8813 features three module maker programmable parameters: v lcd calibration (5 bits) manufacturer identity (3 bits) seal bit (1-bit). 17.1 lcd voltage calibration referring to fig.47, the v lcd calibration parameter comprises a 5-bit code (v cal [4:0]). the code is implemented in twos complement notation giving a positive or negative offset to the v pr register. the range of the v pr [6:0] register is 0 to 127. the adder in the circuit takes this into account by having underflow and overflow protection added to it. in the event of an overflow, the output will be clamped to 255, and in the case of an underflow the output will be clamped to 0. given that and v lcd can be calculated using parameters a and b that are defined in table 17. an example of the relationship between v cal code and the v lcd calibration is shown in table 19, where b is assumed to be 25.6 mv. possible values for v cal are given in table 19. the default value for v cal when otp is disabled is v cal [4:0] = 00000. v op v cal v pr * + = v lcd av op b t(norm) + = handbook, full pagewidth mgu644 v op - 16 to + 15 0 to + 127 to high voltage generator v cal [ 4:0 ] v pr register: 7-bit unsigned value v lcd calibration: 5-bit signed value v pr [ 6:0 ] + fig.47 v lcd calibration.
2004 mar 05 50 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 table 19 v cal codes and associated nominal calibration voltage when the temperature coef?cient is set to tc3 17.2 manufacturer identity the second otp feature defines the manufacturer identity. a 3-bit code mf[2:0] is used to define this parameter. the default manufacturer identity is mf[2:0] = 000. 17.3 seal bit module maker programming is performed in a special mode; the calibration mode mm. this mode is entered via the interface command, mm. to prevent wrongful programming, a seal bit prevents the device from entering the calibration mode. this seal bit, once programmed, cannot be reversed, thus further changes in programmed values are not possible. however it is possible to disable all programmed values by applying the disable otp command. applying the programming voltages when not in mm mode will have no effect on the programmed values. table 20 seal bit de?nition 17.4 one time programming 17.4.1 a rchitecture the otp circuitry in the pcf8813 contains nine bits of data: five for v lcd calibration, three for the manufacturer identity and one for the seal bit. the circuitry for 1-bit is called an otp slice. each otp slice consists of two main parts: the otp cell (a non-volatile memory cell) and the shift register cell (a flip-flop). the otp cells are accessible only through their shift register cells; both reading-from and writing-to the otp cells are performed with the shift register cells, but only the shift register cells are visible to the rest of the circuit. the basic otp architecture is shown in fig.48. v cal v cal [4:0] v lcd calibration (mv) +0 00000 0 (default) +1 00001 +25.6 +2 00010 +51.2 +3 00011 +76.8 +4 00100 +102.4 +5 00101 +128.0 +6 00110 +153.6 +7 00111 +179.2 +8 01000 +204.8 +9 01001 +230.4 +10 01010 +256.0 +11 01011 +281.6 +12 01100 +307.2 +13 01101 +332.8 +14 01110 +358.4 +15 01111 +384.0 - 1 11111 - 25.6 - 2 11110 - 51.2 - 3 11101 - 76.8 - 4 11100 - 102.4 - 5 11011 - 128.0 - 6 11010 - 153.6 - 7 11001 - 179.2 - 8 11000 - 204.8 - 9 10111 - 230.4 - 10 10110 - 256.0 - 11 10101 - 281.6 - 12 10100 - 307.2 - 13 10011 - 332.8 - 14 10010 - 358.4 - 15 10001 - 384.0 - 16 10000 - 409.6 seal bit action 0 possible to enter calibration mode 1 calibration mode disabled
2004 mar 05 51 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth data to the circuit for configuration and calibration shift register flip-flop otp slice otp cell shift register shift register data input read data from the otp cell write data to the otp cell otp cells mgu289 fig.48 basic otp architecture. 17.4.2 o perations the otp architecture allows the following operations: the otp circuit in the pcf8813 is initialized when a reset is initiated. after the reset initiation, otp circuits can be disabled only by sending the disable otp command. reading data from the otp cells. the content of the non-volatile otp cells is transferred to the shift register where it may affect operation of the pcf8813. writing data to the otp cells. all 9 bits of data are shifted first into the shift register via the serial interface. then the content of the shift register is transferred to the otp cells (there are some limitations related to storing data in these cells; see section 17.6). checking calibration without writing to the otp cells. shifting data into the shift register allows the effects of the v lcd voltage to be observed. all otp circuitry of the pcf8813 is enabled until the disable otp command is given. once enabled, the reading of data from the otp cells is initiated by either: exit from power-down mode the refresh command (power control). this command works only when the driver is not in power-down. in both cases, the time required for the reading operation to complete is up to 5 ms. the shifting of data into the shift register is performed in the special mode mm. in the pcf8813, the mm mode is entered through the mm command. once in the mm mode, the data is shifted into the shift register via any of the interfaces at the rate of 1-bit per command. after transmitting the last (9th) bit and exiting the mm mode, the interface is again in the normal mode and all other commands can be sent. care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the mm mode, otherwise the bits will be in the wrong positions. the value of the seal bit in the shift register is always zero at reset (also applies to all other bits). to make sure the security feature works correctly, the mm command is disabled until a refresh has been made. once a refresh is completed, the seal bit value in the shift register is valid and permission to enter mm mode can thus be determined. the 9 bits are shifted into the shift register in a predefined order: first 5 bits of v cal [4:0], followed by 3 bits for mf[2:0] and then the seal bit. the msb is always first, that is the first bit shifted is v cal [4] and the seal bit is the last bit.
2004 mar 05 52 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 17.5 interface commands instructions additional to those of the instruction set (table 5) are given in table 21. table 21 additional instructions instruction d/ cr/ w command byte action d7 d6 d5 d4 d3 d2 d1 d0 reset enable otp circuitry function set 0000100000e xit power-down ref (refresh) 000001000pcs witch hvgen on/off to force refresh of shift register wait 5 ms for refresh to take effect function set 0000100101 set pd = 1 and h = 1 mm 0000011110 enter mm mode 17.5.1 d isable otp command this is a special instruction for the pcf8813 which disables all included otp circuitry. in this case, all otp-related commands are inactive. v cal and mf have no effect on v lcd and manufacture identification respectively. once disabled, the mode can only be enabled via a reset. 17.5.2 m odule maker calibration instruction (mm) enters the device into the calibration mode. this mode enables the shift register for loading and allows programming of the non-volatile otp cells to take place. if the seal bit is set, then this mode cannot be accessed and the instruction will be ignored. once in calibration mode all commands are interpreted as shift register data. the mode can only be exited by sending data with bit d7 set to logic 0. reset will also clear this mode. each shift register data byte is preceded by d/ c=0 and has only three significant bits, thus the remaining five bits are ignored. bit d7 is the continuation bit (d7 = 1 indicates remain in mm mode; d7 = 0 indicates exit mm mode). d6 has to be logic 0 until the last bit when the seal bit is set, in which case this is set to logic 1 (d6 is set to logic 1 only when the high voltage used for programming the cells is about to be applied). bit d0 is the data bit and its value is shifted into the otp shift register on the falling edge of the sclk clock. 17.5.3 r efresh the action of the refresh instruction (ref) is to force the otp shift register to re-load from the non-volatile otp cells. this instruction takes up to 5 ms to complete. during this time all other instructions may be sent. in the pcf8813, the refresh instruction is associated with the power control instruction so that the shift register is refreshed automatically every time the high voltage generator is enabled or disabled. however, if this instruction is sent while in power-down, the pc bits are updated but the refreshing is ignored. 17.6 filling the shift register an example of the sequence of commands and data for filling the shift register is shown in table 22. this example uses the values v cal = - 4 (11100b), mf = 4 (100b is the philips identifying code) and the seal bit is 0. it is assumed that the pcf8813 has just been reset. after transmitting the last bit the pcf8813 can exit or remain in mm mode (see table 22, step 1). when in mm mode, the interface does not recognize commands in the normal sense. after this sequence has been applied, it is possible to observe the impact of the data shifted in. the sequence described is not useful for otp programming because the number of bits with value = 1 is greater than that allowed for programming (see section 17.7). figure 49 shows the shift register after this action.
2004 mar 05 53 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 table 22 example sequence of shift register ?lling notes 1. x = dont care. 2. pd does not have to be set to 1 if the effects of v cal are intended to be observed on v lcdout . 3. bit data is not in the correct shift register position until all bits have been sent. step d/ cr/ w d7 d6 d5 d4 d3 d2 d1 d0 action 1 reset reset to enable otp circuitry 1 0000100000e xit power-down (pd = 0) 3 000001001pcs witch hvgen on/off to force refresh of shift register wait 5 ms for refresh to take effect 4 0000100101 set pd to 1 (2) and h to 1 5 0000011110 enter mm mode 6 0010 xxxxx1 shift-in data; v cal [4] is ?rst bit (3) 7 0010 xxxxx1v cal [3] 8 0010 xxxxx1v cal [2] 9 0010 xxxxx0v cal [1] 10 0010 xxxxx0v cal [0] 11 0010 xxxxx1 mf[2] 12 0010 xxxxx0 mf[1] 13 0010 xxxxx0 mf[0] 14 0010 xxxxx0 seal bit; remain in mm mode handbook, full pagewidth msb lsb shifting direction 0 mgu645 mmmf [ 2:0 ] seal bit = 0 0 1 msb lsb 0 mmvopcal [ 4:0 ] otp shift register 0 1 1 1 fig.49 shift register contents after example sequence of table 22.
2004 mar 05 54 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 17.7 programming ?ow programming is achieved in mm mode and with application of the programming voltages. since the data for programming the otp cell is contained in the corresponding shift register cell, the shift register cell must be loaded with a 1 in order to program the corresponding otp cell. if the shift register cell contains a 0, then no action will take place when the programming voltages are applied. once programmed, an otp cell cannot be de-programmed. also, a previously programmed cell that is an otp cell containing a 1 must not be re-programmed. during programming a substantial current flows in the v lcdin pad. for this reason programming only one otp cell at a time is recommended. this is achieved by filling all but one shift register cells with 0. the programming specification refers to the voltages at the chip pads, therefore contact resistance must be considered by the user. an example of the sequence of commands and data for otp programming is given in table 23. the order for programming cells is not significant but it is recommended that the seal bit is programmed last. once the seal bit has been programmed it is not possible to re-enter the mm mode. it is assumed that the pcf8813 has been reset just before the programming commences. table 23 example sequence for otp programming note 1. x = dont care. step d/ cr/ w d7 d6 d5 d4 d3 d2 d1 d0 action 1 reset enable otp by applying a reset 1 0000100000e xit power-down (pd = 0) 3 000001001pcs witch hvgen on/off to force refresh of shift register wait 5 ms for refresh to take effect 4 0000100101 re-enter power-down (pd=1andh=1) 5 0000011110 enter mm mode 6 0 0 1 0xxxxx1v cal [4] (the only bit with value of 1) 7 0 0 1 0xxxxx1v cal [3] 8 0 0 1 0xxxxx1v cal [2] 9 0 0 1 0xxxxx0v cal [1] 100 0 1 0xxxxx0v cal [0] 11 0 0 1 0 x x x x x 0 mf[2] 12 0 0 1 0 x x x x x 0 mf[1] 13 0 0 1 0 x x x x x 0 mf[0] 14 0 0 1 1 x x x x x 0 seal bit; remain in calmm mode 15 ---------- apply programming voltage at pads v otpprog and v lcdin repeat steps 6 to 15 for each bit that should be programmed to 1 15 ---------- apply external reset
2004 mar 05 55 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 17.8 programming speci?cation table 24 programming parameters notes 1. the voltage drop across the ito track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pads. 2. the high voltage generator must be disabled (v pr = 0 and prs = 0) when pad v lcdin is being driven. symbol parameter condition min. typ. max. unit v dd1 logic supply voltage 2.4 - 3.3 v v otpprog voltage applied to pad v otpprog v otpprog relative to v ss1 ; note 1 programming active 11.0 11.5 12.0 v programming inactive 0 - v dd1 v v lcdin voltage applied to pad v lcdin v lcdin relative to v ss1 ; notes 1, 2 programming active 9.0 9.50 10.5 v programming inactive 0 - v dd2 v i otpprog current drawn during programming - 100 200 m a i lcdin current drawn during programming when programming one bit to logic 1 - 850 1000 m a t prog ambient temperature during programming 02540 c t su(intclk) internal data set-up time after last clock 1 --m s t hd(intclk) internal data hold time before next clock 1 --m s t su(gate) v otpprog set-up time prior to programming 1 - 10 ms t hd(gate) v otpprog hold time after programming 1 - 10 ms t pw programming voltage pulse width 100 120 200 ms handbook, full pagewidth int_clk t su(intclk) t su(gate) t hd(gate) t hd(intclk) t pw mgu646 v votpprog v lcdin fig.50 programming waveforms.
2004 mar 05 56 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 17.9 programming examples table 25 programming example for pcf8813 with serial interface (3-line serial, 3-line spi or 4-line spi) step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 1 start sce is going low 2 0 0 0 1 0 0 0 0 1 function set: pd = 0, v = 0; select extended instruction set (h = 1) 3 0 0 0 0 1 0 0 0 1 set prs to higher programming range (prs = 1) 4 0 1 0 0 1 0 0 0 0 set v pr : v pr *= (a + 132* b) = 8.596 v (required voltage is dependent on liquid crystal operating environment) 5 0 0 0 1 0 0 0 0 0 function set: pd = 0, v = 0; select normal instruction set (h=0) 6 0 0 0 0 0 1 1 0 0 display control: set normal mode (d = 1 and e = 0) 7 0 0 0 0 1 0 1 1 0 set data order: do = 0 000000000 8 - 1 1 1 0 0 0 0 0 option available in 3-line spi for setting display data length command (7 shown) - 00000111 9 1 0 0 0 1 1 1 1 1 data write: y and x are initialized to 0 by default, so they are not set here 10 1 0 0 0 0 0 1 0 1 data write 11 1 0 0 0 0 0 1 1 1 data write 12 1 0 0 0 0 0 0 0 0 data write 13 1 0 0 0 1 1 1 1 1 data write mgs405 mgs406 mgs407 mgs407 mgs409
2004 mar 05 57 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 table 26 programming example for pcf8813 with i 2 c -bus 14 1 0 0 0 0 0 1 0 0 data write 15 1 0 0 0 1 1 1 1 1 data write 16 0 0 0 0 0 1 1 0 1 display control: set inverse video mode (d = 1 and e=1) 17 0 1 0 0 0 0 0 0 0 set x address of ram: set address to 0000000 18 1 0 0 0 0 0 0 0 0 data write step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 1i 2 c-bus start 2 - 0 1 1 1 1 sa1 sa0 0 slave address for write 3 - 0 0 0 0 0 0 0 0 control byte with cleared co bit and d/ c set to logic 0 4 - 0 0 1 0 0 0 0 1 function set: pd = 0, v = 0; select extended instruction set (h = 1) 5 - 0 0 0 1 0 0 0 1 set prs to higher programming range (prs = 1) 6 - 1 0 0 1 0 0 0 0 set v pr : v pr *= (a + 132* b) = 8.596 v (required voltage is dependent on liquid crystal operating environment) 7 - 0 0 1 0 0 0 0 0 function set: pd = 0; v = 0; select normal instruction set (h=0) step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 mgs410 mgs411 mgs412 mgs412 mgs414
2004 mar 05 58 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 8 - 0 0 0 0 1 1 0 0 display control: set normal mode (d = 1 and e = 0) 9 - 0 0 0 1 0 1 1 0 display con?guration (do = 0) - 00000100 10 - i 2 c-bus start restart: to write into the display ram the d/ c must be set to logic 1, therefore a control byte is needed 11 - 0 1 1 1 1 sa1 sa0 0 slave address for write 12 - 0 1 0 0 0 0 0 0 control byte with cleared co bit and d/ c set to logic 1 13 10001111 - data write: y and x are initialized to 0 by default, so they are not set here 14 10000001 - data write 15 10000011 - data write 16 10000000 - data write 17 10001111 - data write 18 10000010 - data write 19 10001111 - data write 20 i 2 c-bus start restart 21 - 0 1 1 1 1 sa1 sa0 0 slave address for write 22 - 1 control byte with set co bit and d/ c set to logic 0 step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 mgs405 mgs406 mgs407 mgs407 mgs409 mgs410 mgs411
2004 mar 05 59 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 23 - 0 0 0 0 1 1 0 1 display control: set inverse video mode (d = 1 and e=1) 24 - 1 0 0 0 0 0 0 0 control byte with set co bit and d/ c set to logic 0 25 - 1 0 0 0 0 0 0 0 set x address of ram: set address to 0000000 26 - 1 1 0 0 0 0 0 0 control byte with set co bit and d/ c set to logic 1 27 - 0 0 0 0 0 0 0 0 data write 28 - 1 0 0 0 0 0 0 0 control byte with set co bit and d/ c set to logic 0 29 - 1 0 0 0 0 0 0 0 set x address of ram: set address to 0000000 30 i 2 c-bus start restart 31 - 0 1 1 1 1 sa1 sa0 0 slave address for write 32 - 1 1 0 0 0 0 0 0 control byte with set co bit and d/ c set to logic 1 33 - 1 1 1 1 1 0 0 0 write data 34 - 1 0 0 0 0 0 0 0 control byte with set co bit and d/ c set to logic 0 step serial bus byte display operation d/ c db7 db6 db5 db4 db3 db2 db1 db0 mgs412 mgs412 mgs414 mgs414 mgs414
2004 mar 05 60 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 18 application information for additional application information, refer to application note an10170 . 18.1 protection from light semiconductors are light-sensitive. exposure to light sources can cause malfunctions, therefore the ic should be protected from light in the application. light protection needs to be applied to all sides of the ic (front, rear and all edges). 18.2 application examples in the following application examples, the required minimum values of the external capacitors are: c vlcd = 100 nf minimum c vdd ,c vdd1 and c vdd2 =1 m f minimum higher capacitor values are recommended for ripple reduction. handbook, full pagewidth mgu647 display 102 68 pixels v dd2, 3 v dd1 i/o 32 102 36 c vlcd v ss1 v ss2 v lcdin v lcdout v lcdsense pcf8813 v dd v ss c vdd fig.51 application example using the internal charge pump and a single v dd source.
2004 mar 05 61 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, full pagewidth v lcdin v lcdout v lcdsense display 102 68 pixels mgu648 v dd2, 3 v dd1 v dd2 v dd1 i/o 32 102 36 v ss c vlcd c vdd2 v ss1 v ss2 c vdd1 pcf8813 fig.52 application example using the internal charge pump and two separate v dd sources (v dd1 and v dd2 ). handbook, full pagewidth mgu649 display 102 68 pixels v dd2, 3 v dd1 i/o 32 102 36 v ss1 v ss2 v lcdin v lcdout v lcdin v lcdsense pcf8813 v dd v ss c vdd fig.53 application example using external high voltage generation.
2004 mar 05 62 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 19 device protection diagram handbook, full pagewidth mgw770 v dd1 v dd1 v ss1 v ss2 v ss1 t3, t4, v ss1 * , v dd * v ss1 v ss1 v dd1 osc, res, rd, d/c, ps [ 2:0 ], t1, t2, t5, e v lcdout v ss1 v lcdin , v lcdsense v ss1 v dd2 v ss1 v ss2 v lcdin v ss1 v dd1 db [ 7:0 ] , sclk, sdata, sdo, sa1, sa0, r/w, wr v ss1 v dd1 v ss1 v otpprog v ss1 lcd outputs i 2 c-bus pins v dd3 v ss1 fig.54 protection circuit diagrams. protection diode maximum forward current = 5 ma.
2004 mar 05 63 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 20 bonding pad information handbook, full pagewidth mgw797 x y 0, 0 pad 1 v lcdout v lcdin v ss1 v dd2 v dd3 v dd1 v ss2 votpprog v dd1 (1) v dd1 (1) v dd1 (1) v ss1 (1) r67 (icon row) pcf8813 sce/sclh t8 res t3 t2 t1 t5 osc dc t4 ps [ 2 ] ps [ 1 ] ps [ 0 ] db5/sd0 db3/sa1 db2/sa0 db4 db1 db0 db6/sclk db7/sdata r/w/wr sdah sdahout dummy dummy e/rd t8 t8 v lcdsense 8 rows 8 rows 8 rows 8 rows 32 columns 32 columns 38 columns 8 rows 8 rows 8 rows 8 rows alignment & dummy alignment mark alignment mark dummy dummy dummy alignment & dummy dummy r15 r0 r16 r31 c0 c101 r66 r63 r48 r32 r47 r67 (2) fig.55 bonding pad locations. (1) can be used to tie-off unused input pads to the power supply voltage or to ground. (2) used only for icons.
2004 mar 05 64 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 table 27 bonding pad locations all x and y coordinates are referenced to the centre of the chip; dummy bumps should never be connected to any electrical nodes; dimensions in m m; see fig.55. symbol pad coordinates xy dummy 1 - 5328 + 814.5 dummy 2 - 5328 - 814.5 dummy 3 - 5274 - 814.5 dummy and alignment 4 - 5175 - 814.5 dummy 5 - 5085 - 814.5 dummy 6 - 5031 - 814.5 r15 7 - 4869 - 814.5 r14 8 - 4815 - 814.5 r13 9 - 4761 - 814.5 r12 10 - 4707 - 814.5 r11 11 - 4653 - 814.5 r10 12 - 4599 - 814.5 r9 13 - 4545 - 814.5 r8 14 - 4491 - 814.5 r7 15 - 4437 - 814.5 r6 16 - 4383 - 814.5 r5 17 - 4329 - 814.5 r4 18 - 4275 - 814.5 r3 19 - 4221 - 814.5 r2 20 - 4167 - 814.5 r1 21 - 4113 - 814.5 r0 22 - 4059 - 814.5 r16 23 - 3843 - 814.5 r17 24 - 3789 - 814.5 r18 25 - 3735 - 814.5 r19 26 - 3681 - 814.5 r20 27 - 3627 - 814.5 r21 28 - 3573 - 814.5 r22 29 - 3519 - 814.5 r23 30 - 3465 - 814.5 r24 31 - 3411 - 814.5 r25 32 - 3357 - 814.5 r26 33 - 3303 - 814.5 r27 34 - 3249 - 814.5 r28 35 - 3195 - 814.5 r29 36 - 3141 - 814.5 r30 37 - 3087 - 814.5 r31 38 - 3033 - 814.5 c0 39 - 2871 - 814.5 c1 40 - 2817 - 814.5 c2 41 - 2763 - 814.5 c3 42 - 2709 - 814.5 c4 43 - 2655 - 814.5 c5 44 - 2601 - 814.5 c6 45 - 2547 - 814.5 c7 46 - 2493 - 814.5 c8 47 - 2439 - 814.5 c9 48 - 2385 - 814.5 c10 49 - 2331 - 814.5 c11 50 - 2277 - 814.5 c12 51 - 2223 - 814.5 c13 52 - 2169 - 814.5 c14 53 - 2115 - 814.5 c15 54 - 2061 - 814.5 c16 55 - 2007 - 814.5 c17 56 - 1953 - 814.5 c18 57 - 1899 - 814.5 c19 58 - 1845 - 814.5 c20 59 - 1791 - 814.5 c21 60 - 1737 - 814.5 c22 61 - 1683 - 814.5 c23 62 - 1629 - 814.5 c24 63 - 1575 - 814.5 c25 64 - 1521 - 814.5 c26 65 - 1467 - 814.5 c27 66 - 1413 - 814.5 c28 67 - 1359 - 814.5 c29 68 - 1305 - 814.5 c30 69 - 1251 - 814.5 c31 70 - 1197 - 814.5 c32 71 - 1035 - 814.5 c33 72 - 981 - 814.5 c34 73 - 927 - 814.5 c35 74 - 873 - 814.5 symbol pad coordinates xy
2004 mar 05 65 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 c36 75 - 819 - 814.5 c37 76 - 765 - 814.5 c38 77 - 711 - 814.5 c39 78 - 657 - 814.5 c40 79 - 603 - 814.5 c41 80 - 549 - 814.5 c42 81 - 495 - 814.5 c43 82 - 441 - 814.5 c44 83 - 387 - 814.5 c45 84 - 333 - 814.5 c46 85 - 279 - 814.5 c47 86 - 225 - 814.5 c48 87 - 171 - 814.5 c49 88 - 117 - 814.5 c50 89 - 63 - 814.5 c51 90 - 9 - 814.5 c52 91 +45 - 814.5 c53 92 +99 - 814.5 c54 93 +153 - 814.5 c55 94 +207 - 814.5 c56 95 +261 - 814.5 c57 96 +315 - 814.5 c58 97 +369 - 814.5 c59 98 +423 - 814.5 c60 99 +477 - 814.5 c61 100 +531 - 814.5 c62 101 +585 - 814.5 c63 102 +639 - 814.5 c64 103 +801 - 814.5 c65 104 +855 - 814.5 c66 105 +909 - 814.5 c67 106 +963 - 814.5 c68 107 +1017 - 814.5 c69 108 +1071 - 814.5 c70 109 +1125 - 814.5 c71 110 +1179 - 814.5 c72 111 +1233 - 814.5 c73 112 +1287 - 814.5 c74 113 +1341 - 814.5 symbol pad coordinates xy c75 114 +1395 - 814.5 c76 115 +1449 - 814.5 c77 116 +1503 - 814.5 c78 117 +1557 - 814.5 c79 118 +1611 - 814.5 c80 119 +1665 - 814.5 c81 120 +1719 - 814.5 c82 121 +1773 - 814.5 c83 122 +1827 - 814.5 c84 123 +1881 - 814.5 c85 124 +1935 - 814.5 c86 125 +1989 - 814.5 c87 126 +2043 - 814.5 c88 127 +2097 - 814.5 c89 128 +2151 - 814.5 c90 129 +2205 - 814.5 c91 130 +2259 - 814.5 c92 131 +2313 - 814.5 c93 132 +2367 - 814.5 c94 133 +2421 - 814.5 c95 134 +2475 - 814.5 c96 135 +2529 - 814.5 c97 136 +2583 - 814.5 c98 137 +2637 - 814.5 c99 138 +2691 - 814.5 c100 139 +2745 - 814.5 c101 140 +2799 - 814.5 r67 141 +2961 - 814.5 r66 142 +3015 - 814.5 r65 143 +3069 - 814.5 r64 144 +3123 - 814.5 r63 145 +3177 - 814.5 r62 146 +3231 - 814.5 r61 147 +3285 - 814.5 r60 148 +3339 - 814.5 r59 149 +3393 - 814.5 r58 150 +3447 - 814.5 r57 151 +3501 - 814.5 r56 152 +3555 - 814.5 symbol pad coordinates xy
2004 mar 05 66 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 r55 153 +3609 - 814.5 r54 154 +3663 - 814.5 r53 155 +3717 - 814.5 r52 156 +3771 - 814.5 r51 157 +3825 - 814.5 r50 158 +3879 - 814.5 r49 159 +3933 - 814.5 r48 160 +3987 - 814.5 r32 161 +4203 - 814.5 r33 162 +4257 - 814.5 r34 163 +4311 - 814.5 r35 164 +4365 - 814.5 r36 165 +4419 - 814.5 r37 166 +4473 - 814.5 r38 167 +4527 - 814.5 r39 168 +4581 - 814.5 r40 169 +4635 - 814.5 r41 170 +4689 - 814.5 r42 171 +4743 - 814.5 r43 172 +4797 - 814.5 r44 173 +4851 - 814.5 r45 174 +4905 - 814.5 r46 175 +4959 - 814.5 r47 176 +5013 - 814.5 r67 177 +5067 - 814.5 dummy and alignment 178 +5229 - 814.5 dummy 179 +5328 - 814.5 dummy 180 +5328 +814.5 dummy 181 +5274 +814.5 dummy 182 +4752 +814.5 sdahout 183 +4500 +814.5 sdah 184 +4122 +814.5 sdah 185 +4068 +814.5 v dd1 186 +3528 +814.5 v dd1 187 +3474 +814.5 v dd1 188 +3420 +814.5 v dd1 189 +3366 +814.5 v dd1 190 +3312 +814.5 v dd1 191 +3258 +814.5 symbol pad coordinates xy v dd3 192 +3204 +814.5 v dd3 193 +3150 +814.5 v dd3 194 +3096 +814.5 v dd3 195 +3042 +814.5 v dd3 196 +2988 +814.5 v dd2 197 +2934 +814.5 v dd2 198 +2880 +814.5 v dd2 199 +2826 +814.5 v dd2 200 +2772 +814.5 v dd2 201 +2718 +814.5 v dd2 202 +2664 +814.5 v dd2 203 +2610 +814.5 v dd2 204 +2556 +814.5 v dd2 205 +2502 +814.5 v dd2 206 +2448 +814.5 v dd1 207 +2286 +814.5 r/ w/ wr 208 +2124 +814.5 e/ rd 209 +1962 +814.5 db0 210 +1746 +814.5 db1 211 +1530 +814.5 db2/sa0 212 +1314 +814.5 db3/sa1 213 +1098 +814.5 db4 214 +882 +814.5 db5/sdout 215 +666 +814.5 db6/ sclk 216 +450 +814.5 db7/sdata 217 +234 +814.5 v ss1 218 +72 +814.5 d/ c 219 - 90 +814.5 sce/sclh 220 - 630 +814.5 sce/sclh 221 - 684 +814.5 v otpprog 222 - 792 +814.5 v otpprog 223 - 846 +814.5 v otpprog 224 - 900 +814.5 v dd1 225 - 1008 +814.5 osc 226 - 1296 +814.5 v ss2 227 - 1458 +814.5 v ss2 228 - 1512 +814.5 v ss2 229 - 1566 +814.5 v ss2 230 - 1620 +814.5 symbol pad coordinates xy
2004 mar 05 67 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 v ss2 231 - 1674 +814.5 v ss2 232 - 1728 +814.5 v ss2 233 - 1782 +814.5 v ss2 234 - 1836 +814.5 v ss2 235 - 1890 +814.5 v ss2 236 - 1944 +814.5 v ss1 237 - 1998 +814.5 v ss1 238 - 2052 +814.5 v ss1 239 - 2106 +814.5 v ss1 240 - 2160 +814.5 v ss1 241 - 2214 +814.5 v ss1 242 - 2268 +814.5 v ss1 243 - 2322 +814.5 v ss1 244 - 2376 +814.5 v ss1 245 - 2430 +814.5 v ss1 246 - 2484 +814.5 t5 247 - 2646 +814.5 t1 248 - 2808 +814.5 t2 249 - 2970 +814.5 ps0 250 - 3132 +814.5 ps1 251 - 3294 +814.5 ps2 252 - 3456 +814.5 symbol pad coordinates xy v dd1 253 - 3618 +814.5 t4 254 - 3780 +814.5 t3 255 - 3942 +814.5 v lcdin 256 - 3996 +814.5 v lcdin 257 - 4050 +814.5 v lcdin 258 - 4104 +814.5 v lcdin 259 - 4158 +814.5 v lcdin 260 - 4212 +814.5 v lcdin 261 - 4266 +814.5 v lcdin 262 - 4320 +814.5 v lcdout 263 - 4374 +814.5 v lcdout 264 - 4428 +814.5 v lcdout 265 - 4482 +814.5 v lcdout 266 - 4536 +814.5 v lcdout 267 - 4590 +814.5 v lcdout 268 - 4644 +814.5 v lcdout 269 - 4698 +814.5 v lcdout 270 - 4752 +814.5 v lcdout 271 - 4806 +814.5 v lcdsense 272 - 4860 +814.5 res 273 - 5076 +814.5 dummy 274 - 5274 +814.5 symbol pad coordinates xy
2004 mar 05 68 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 handbook, halfpage mgu650 10.845 mm 1.845 mm pcf8813 x y pitch fig.56 chip dimensions. mgu651 handbook, halfpage x center y center d fig.57 shape of alignment mark. d=90 m m; there are two 90 m m alignment marks. table 28 bump size parameter value ( m m) bump width 32 bump length 81 bump height 17.5 minimum pad pitch 54 pad size, aluminium 45 81 maximum wafer thickness, including bumps 430 typical wafer thickness, without bumps 381
2004 mar 05 69 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 21 tray information handbook, full pagewidth 1,1 x,1 1,2 1,y x,y x y f d b h a c g e mgw798 k l m j a a section a-a fig.58 tray details. table 29 tray dimensions dims description value a pocket pitch; x direction 14.66 mm b pocket pitch; y direction 3.76 mm c pocket width; x direction 10.95 mm d pocket width; y direction 1.95 mm e tray width; x direction 50.8 mm f tray width; y direction 50.8 mm g distance from cut corner to pocket (1, 1) centre 10.74 mm h distance from cut corner to pocket (1, 1) centre 4.72 mm j tray thickness 3.96 mm k tray cross section 1.78 mm l tray cross section 2.44 mm m pocket depth 0.89 mm x number of pockets in x direction 3 y number of pockets in y direction 12 handbook, halfpage mgw799 pcf8813 fig.59 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
2004 mar 05 70 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 22 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 23 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 mar 05 71 philips semiconductors product speci?cation (67 + 1) 102 pixels matrix lcd driver pcf8813 bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. 25 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r15/02/pp 72 date of release: 2004 mar 05 document order number: 9397 750 12934

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