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motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. document number 9S12H256BDGV1/d 1 mc9s12h256 device user guide v01.13 original release date: 29 sep 2000 revised: 08 mar 2002 motorola, inc
motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. document number 9S12H256BDGV1/d 2 revision history version number revision date effective date author description of changes v01.00 07 mar 2001 03 apr 2001 initial version. v01.01 10 mai 2001 10 may 2001 - minor formal corrections - changed atd coupling ratio to10 -2 - changed v dd5 to 4.5v v01.02 14 may 2001 14 may 2001 - removed 112-pin package references - changed atd electrical characteristics separate coupling ratio for positive and negative bulk current injection v01.03 30 may 2001 30 may 2001 - reinserted 112-pin package information. v01.04 11 jun 2001 11 jun 2001 - removed srsv2 comment from preface - corrected reset pin to active low in table 2-1 v01.05 18 jun 2001 18 jun 2001 - adapted style and wording to 9dp256 device user guide - minor format and wording improvements - added sram data retention disclaimer v01.06 28 jun 2001 28 jun 2001 - changed oscillator characteristics t cqout max 2.5s and replaced clock monitor time-out by clock monitor failure assert frequency - changed self clock mode frequency min 1mhz and max 5.5mhz - changed i ddps (rti and cop disabled) to 400 m a - corrected typo in figure 2-1 pin 76: pk3 -> pk2 v01.07 12 jul 2001 12 jul 2001 - added t extr and t extf to oscillator characteristics - added typ value for t uposc - corrected t extl and t exth values - updated thermal resistances as per thermal simulation report, july 10, 2001 v01.08 16 jul 2001 16 jul 2001 - updated eeprom size - added dc cutoff capacitor into layout proposals v01.09 03 aug 2001 03 aug 2001 - minor updates v01.10 29 aug 2001 29 aug 2001 - updated electrical spec
mc9s12h256 device user guide v01.13 3 v01.11 11 oct 2001 11 oct 2001 - replaced references w.r.t. new family name hcs12. - corrected xclks reference in crg electrical spec. v01.12 07 nov 2001 07 nov 2001 - added powered by column in pin list table v01.13 08 mar 2002 08 mar 2002 - new document numbering - removed document order number except from cover sheet - updated min vdd, vddpll - updated currents on v oh ,v ol for standard pins - updated c in , i dds , i ref , c ins , t extl , t exth - included missing lcd electrical spec - updated nvm spec version number revision date effective date author description of changes
mc9s12h256 device user guide v01.13 4
mc9s12h256 device user guide v01.13 5 section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.6 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 section 2 signal description 2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 signal properties summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.1 extal, xtal oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.2 reset external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3.3 test test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.4 xfc pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.5 bkgd / taghi / modc background debug, tag high, and mode pin. . . . . . . . . . . . . 30 2.3.6 pad[15:8] / an[15:8] port ad input pins [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.7 pad[7:0] / an[7:0] port ad input pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.8 pa[7:0] / fp[15:8] / addr[15:8] / data[15:8] port a i/o pins . . . . . . . . . . . . . . . . . . 30 2.3.9 pb[7:0] / fp[7:0] / addr[7:0] / data[7:0] port b i/o pins . . . . . . . . . . . . . . . . . . . . . . 30 2.3.10 pe7 / fp22 / xclks / noacc port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.11 pe6 / modb / ipipe1 port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.12 pe5 / moda / ipipe0 port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.13 pe4 / eclk port e i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.3.14 pe3 / fp21 / lstrb / taglo port e i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.15 pe2 / fp20 / r/w port e i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 2.3.16 pe1 / irq port e input pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.17 pe0 / xirq port e input pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.3.18 ph[7:0] / kwh[7:0] port h i/o pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.19 pj[3:0] / kwj[3:0] port j i/o pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.20 pk7 / fp23 / ecs / romone port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.21 pk[3:0] / bp[3:0] / xaddr[17:14] port k i/o pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.22 pl[7:4] / fp[31:28] port l i/o pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.23 pl[3:0] / fp[19:16] port l i/o pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.24 pm5 / txcan1 port m i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
mc9s12h256 device user guide v01.13 6 2.3.25 pm4 / rxcan1 port m i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.26 pm3 / txcan0 port m i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.27 pm2 / rxcan0 port m i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.28 pm1 / scl port m i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.29 pm0 / sda port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.30 pp[5:2] / pwm[5:2] port p i/o pins [5:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.31 pp[1:0] / pwm[1:0] port p i/o pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.32 ps7 / ss port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.33 ps6 / sck port s i/o pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.34 ps5 / mosi port s i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.35 ps4 / miso port s i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.36 ps3 / txd1 port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.37 ps2 / rxd1 port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.38 ps1 / txd0 port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.39 ps0 / rxd0 port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.40 pt[7:4] / ioc[7:4] port t i/o pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.41 pt[3:0] / ioc[3:0] / fp[27:24] port t i/o pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.42 pu[7:4] / m1c0m, m1c0p, m1c1m, m1c1p port u i/o pins [7:4] . . . . . . . . . . . . . . . . 35 2.3.43 pu[3:0] / m0c0m, m0c0p, m0c1m, m0c1p port u i/o pins [3:0] . . . . . . . . . . . . . . . . 35 2.3.44 pv[7:4] / m3c0m, m3c0p, m3c1m, m3c1p port v i/o pins [7:4] . . . . . . . . . . . . . . . . 35 2.3.45 pv[3:0] / m2c0m, m2c0p, m2c1m, m2c1p port v i/o pins [3:0] . . . . . . . . . . . . . . . . 35 2.3.46 pw[7:4] / m5c0m, m5c0p, m5c1m, m5c1p port w i/o pins [7:4] . . . . . . . . . . . . . . . 36 2.3.47 pw[3:0] / m4c0m, m4c0p, m4c1m, m4c1p port w i/o pins [3:0] . . . . . . . . . . . . . . . 36 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.1 vddr external power pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.2 vddx1, vddx2, vssx1, vssx2 external power and ground pins . . . . . . . . . . . . . . . 36 2.4.3 vdd1, vss1, vss2 core power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.4 vdda, vssa power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.5 vddm1, vddm2, vddm3 power supply pins for motor 0 to 5 . . . . . . . . . . . . . . . . . . 37 2.4.6 vssm1, vssm2, vssm3 ground pins for motor 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.7 vlcd power supply reference pin for lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.8 vrh, vrl atd reference voltage input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.9 vddpll, vsspll power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 section 3 system clock description 3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
mc9s12h256 device user guide v01.13 7 section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2.1 normal operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.2 special operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.3 test operating mode (motorola use only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 section 5 resets and interrupts 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.1 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 section 6 hcs12 core block description section 7 clock and reset generator (crg) block description 7.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1.1 xclks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 section 8 timer (tim) block description section 9 analog to digital converter (atd) block description section 10 inter-ic bus (iic) block description section 11 serial communications interface (sci) block description section 12 serial peripheral interface (spi) block description section 13 pulse width modulator (pwm) block description
mc9s12h256 device user guide v01.13 8 section 14 flash eeprom 256k block description section 15 eeprom 4k block description section 16 ram block description section 17 liquid crystal display driver (lcd) block description section 18 mscan block description section 19 pwm motor control (mc) block description section 20 port integration module (pim) block description section 21 voltage regulator (vreg) block description 21.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 21.1.1 vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 21.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 21.2 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 a.1.3 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a.2.1 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a.2.3 atd accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 a.3 nvm, flash and eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
mc9s12h256 device user guide v01.13 9 a.3.1 nvm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 a.3.2 nvm reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 a.4 reset, oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 a.4.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 a.4.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 a.4.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 a.5 mscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 a.6 spi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 a.6.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 a.6.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 a.7 lcd_32f4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 a.8 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 a.8.1 general muxed bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 appendix b package information b.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 b.2 112-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 b.3 144-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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mc9s12h256 device user guide v01.13 11 figure 1-1 mc9s12h256 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 1-2 mc9s12h256 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 2-1 pin assignments in 112-pin lqfp for mc9s12h256 . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 2-2 pin assignments in 144-pin lqfp for mc9s12h256 . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 3-1 clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21-1 lqfp112 recommended pcb layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 21-2 lqfp144 recommended pcb layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure a-1 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure a-2 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure a-3 jitter definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure a-4 maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure a-5 spi master timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure a-6 spi master timing (cpha =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure a-7 spi slave timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure a-8 spi slave timing (cpha =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure a-9 general external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure b-1 112-pin lqfp mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . . . . . . . 98 figure b-2 144-pin lqfp mechanical dimensions (case no. 918-03) . . . . . . . . . . . . . . . . . . . . . . 99
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mc9s12h256 device user guide v01.13 13 table 0-1 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 1-1 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 1-2 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 1-3 memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 2-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5-1 reset and interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 21-1 recommended components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table a-2 esd and latch-up test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table a-6 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table a-7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table a-8 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table a-9 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table a-10 atd conversion performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table a-11 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table a-12 nvm reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table a-13 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table a-14 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table a-15 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table a-16 mscan wake-up pulse characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table a-17 spi master mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table a-18 spi slave mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table a-19 lcd_32f4b driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table a-20 expanded bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
mc9s12h256 device user guide v01.13 14
mc9s12h256 device user guide v01.13 15 preface the device user guide provides information about the mc9s12h256 device made up of standard hcs12 blocks and the hcs12 processor core. this document is part of the customer documentation. a complete set of device manuals also includes the hcs12 core user guide and all the individual block user guides of the implemented modules. in an effort to reduce redundancy all module specific information is located only in the respective block user guide. if applicable, special implementation details of the module are given in the block description sections of this document. see table 0-1 for names and versions of the referenced documents throughout the device user guide. table 0-1 document references user guide version document order number hcs12 v1.5 core user guide 1.2 hcs12coreug crg block user guide v02 s12crgv2/d tim_16b8c block user guide v01 s12tim16b8cv1/d atd_10b16c block user guide v02 s12atd10b16cv2/d iic block user guide v02 s12iicv2/d sci block user guide v02 s12sciv2/d spi block user guide v02 s12spiv2/d pwm_8b6c block user guide v01 s12pwm8b6cv1/d fts256k block user guide v02 s12fts256kv2/d eets4k block user guide v02 s12eets4kv2/d lcd_32f4b block user guide v01 s12lcd32f4bv1/d mscan block user guide v02 s12mscanv2/d mc_10b12c block user guide v02 s12mc10b12cv2/d pim_9h256 block user guide v01 s12pimh256v1/d vreg block user guide v01 s12vregv1/d
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mc9s12h256 device user guide v01.13 17 section 1 introduction 1.1 overview the mc9s12h256 microcontroller unit (mcu) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (hcs12 cpu), 256k bytes of flash eeprom, 12k bytes of ram, 4k bytes of eeprom, two asynchronous serial communications interfaces (sci), a serial peripheral interface (spi), an iic-bus interface (iic), an 8-channel 16-bit timer (tim), a 16-channel, 10-bit analog-to-digital converter (atd), a six-channel pulse width modulator (pwm), and two can 2.0 a, b software compatible modules (mscan). in addition, it features a 32x4 liquid crystal display (lcd) controller/driver and a motor pulse width modulator (mc) consisting of 24 high current outputs suited to drive up to 6 stepper motors. system resource mapping, clock generation, interrupt control, and bus interfacing are managed by the hcs12 core. the mc9s12h256 has full 16-bit data paths throughout. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. in addition to the i/o ports available in each module, 12 general purpose i/o pins are available with interrupt and wake-up capability from stop or wait mode. 1.2 features ? hcs12 core C 16-bit hcs12 cpu i. upward compatible with m68hc11 instruction set ii. interrupt stacking and programmers model identical to m68hc11 iii. 20-bit alu iv. instruction queue v. enhanced indexed addressing C mebi (multiplexed external bus interface) C mmc (module mapping control) C int (interrupt control) C bkp (breakpoints) C bdm (background debug mode) ? crg (low current oscillator, pll, reset, clocks, cop watchdog, real time interrupt, clock monitor) ? 8-bit and 4-bit ports with interrupt functionality C digital filtering C programmable rising or falling edge trigger
mc9s12h256 device user guide v01.13 18 ? memory C 256k flash eeprom C 4k byte eeprom C 12k byte ram ? analog-to-digital converter C 16 channels, 10-bit resolution C external conversion trigger capability ? two 1m bit per second, can 2.0 a, b software compatible modules C five receive and three transmit buffers C flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit C four separate interrupt channels for rx, tx, error and wake-up C low-pass filter wake-up function C loop-back for self test operation ? timer C 16-bit main counter with 7-bit prescaler C 8 programmable input capture or output compare channels C two 8-bit or one 16-bit pulse accumulators ? 6 pwm channels C programmable period and duty cycle C 8-bit 6-channel or 16-bit 3-channel C separate control for each pulse width and duty cycle C center-aligned or left-aligned outputs C programmable clock select logic with a wide range of frequencies C fast emergency shutdown input ? serial interfaces C two asynchronous serial communications interfaces (sci) C synchronous serial peripheral interface (spi) C inter-integrated circuit interface (iic) ? liquid crystal display driver with variable input voltage C configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output C 5 modes of operation allow for different display sizes to meet application requirements C unused frontplane and backplane pins can be used as general purpose i/o
mc9s12h256 device user guide v01.13 19 ? 24 high current drivers suited for pwm motor control C each pwm channel switchable between two drivers in an h-bridge configuration C left, right and center aligned outputs C support for sine and cosine drive C dithering C output slew rate control ? 144-pin or 112-pin lqfp package C i/o lines with 5v input and drive capability C 5v a/d converter inputs C operation at 32mhz equivalent to 16mhz bus speed C development support C single-wire background debug? mode (bdm) C on-chip hardware breakpoints 1.3 modes of operation user modes ? normal and emulation operating modes C normal single-chip mode C normal expanded wide mode C normal expanded narrow mode C emulation expanded wide mode C emulation expanded narrow mode ? special operating modes C special single-chip mode with active background debug mode C special test mode ( motorola use only ) C special peripheral mode ( motorola use only ) low power modes ? stop mode ? pseudo stop mode ? wait mode
mc9s12h256 device user guide v01.13 20 1.4 block diagram figure 1-1 is a block diagram of the mc9s12h256 device.
mc9s12h256 device user guide v01.13 21 figure 1-1 mc9s12h256 block diagram extal xtal bkgd xirq periodic interrupt cop watchdog clock monitor single-wire background debug module breakpoints pll xfc irq eclk pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 rxd0 txd0 sdi/miso sdo/mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd1 txd1 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 pk3 pk7 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 can1 rxcan1 txcan1 pm4 pm5 pin kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ddra ddrb pta ptb ddre pte ptk ddrk ptp ddrp pts ddrs ptm ddrm ddrh pth pk2 interrupt logic fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 fp23 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 pe7 pe3 pte ddre pe2 fp22 fp21 fp20 vlcd vlcd m0c0m m0c0p pu3 pu4 pu5 pu6 pu7 pu0 pu1 ptu ddru pwm0 m0c1m m0c1p pwm1 motor0 m1c0m m1c0p pwm2 m1c1m m1c1p pwm3 motor1 lcd sci0 can0 ph2 modb moda integration module reset vddpll vsspll cpu12 clock and reset generation module ptk ddrk fp13 pb5 pb3 pb2 pb1 fp5 pix0 pix1 pix2 pix3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 ptt ddrt fp24 fp25 fp26 fp27 pu2 m2c0m m2c0p pv3 pv4 pv5 pv6 pv7 pv0 pv1 ptv ddrv pwm4 m2c1m m2c1p pwm5 motor2 m3c0m m3c0p pwm6 m3c1m m3c1p pwm7 motor3 pv2 m4c0m m4c0p pw3 pw4 pw5 pw6 pw7 pw0 pw1 ptw ddrw pwm8 m4c1m m4c1p pwm9 motor4 m5c0m m5c0p pwm10 m5c1m m5c1p pwm11 motor5 pw2 an02 an06 an00 an07 an01 an03 an04 an05 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 vrh vrl an10 an14 an08 an15 an09 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa analog to digital converter ptad vrh vrl vdda vssa kwj2 kwj0 kwj1 kwj3 pj3 pj0 pj1 ddrj ptj pj2 256k bytes flash eeprom 4k bytes eeprom 12k bytes ram multiplexed address/data bus ppage data15 motor0 and motor1 supply vddm1 vssm1 motor2 and motor3 supply vddm2 vssm2 motor4 and motor5 supply vddm3 vssm3 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 multiplexed wide bus multiplexed narrow bus ecs/romone xaddr14 xaddr15 xaddr16 xaddr17 noacc/xclks lstrb/ t a glo r/ w vddr vdd1 vss1,vss2 voltage regulator input capture and output compare timer sda scl pm0 pm1 iic vddx1,2 vssx1,2 vsspll pll 2.5v i/o driver 5v a/d converter 5v & vddpll vdd1 vss1,2 internal logic 2.5v vdda vssa vddr vreg input 5v supply pins driver note: not all functionality shown in this block diagram is available in all packages! pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 voltage regulator reference (atd) (pwm)
mc9s12h256 device user guide v01.13 22 1.5 device memory map table 1-1 and figure 1-2 show the device memory map of the mc9s12h256. table 1-1 device memory map address module size (bytes) $0000 C $0017 core (ports a, b, e, modes, inits, test) 24 $0018 C $0019 reserved 2 $001a C $001b device id register (partid) 2 $001c C $001f core (memsiz, irq, hprio) 4 $0020 C $0027 reserved 8 $0028 C $002f core (background debug mode) 8 $0030 C $0033 core (ppage, port k) 4 $0034 C $003f clock and reset generator (pll, rti, cop) 12 $0040 C $006f standard timer module 16-bit 8 channels (tim) 48 $0070 C $007f reserved 16 $0080 C $00af analog to digital converter 10-bit 16 channels (atd) 48 $00b0 C $00bf reserved 8 $00c0 C $00c7 inter integrated circuit (iic) 8 $00c8 C $00cf serial communications interface 0 (sci0) 8 $00d0 C $00d7 serial communications interface 1 (sci1) 8 $00d8 C $00df serial peripheral interface (spi) 8 $00e0 C $00ff pulse width modulator 8-bit 6 channels (pwm) 32 $0100 C $010f flash control registers 16 $0110 C $011b eeprom control registers 12 $011c C $011f reserved 4 $0120 C $0137 liquid crystal display driver 32x4 (lcd) 24 $0140 C $017f motorola scalable controller area network 0 (mscan0) 64 $0180 C $01bf motorola scalable controller area network 1 (mscan1) 64 $01c0 C $01ff motor control module (mc) 64 $0200 C $027f port integration module (pim) 128 $0280 C $03ff reserved 384 $0000 C $0fff eeprom array 4096 $1000 C $3fff ram array 12288 $4000 C $7fff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at start 16384 $8000 C $bfff flash eeprom page window 16384 $c000 C $ffff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at end and 256 bytes of vector space at $ff80 C $ffff 16384
mc9s12h256 device user guide v01.13 23 figure 1-2 mc9s12h256 memory map 1.6 part id assignments the part id is located in two 8-bit registers partidh and partidl at addresses $001a,$001b, respectively. the read-only value is a unique part id for each revision of the chip. table 1-2 shows the assigned part id numbers. table 1-2 assigned part id numbers device mask set number part id 1 notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision mc9s12h256 0k78x $1000 $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $ff00 ext normal single chip expanded* special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $1000 $3fff $0000 $0fff 4k bytes eeprom mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 16k boundary 12k bytes ram alignable to top ($1000 C $3fff) or bottom ($0000 C $2fff) initially overlapped by register space * assuming that a 0 was driven onto port k7 during reset to normal expanded mode
mc9s12h256 device user guide v01.13 24 the device memory sizes are located in two 8-bit registers memsiz0 and memsiz1 (addresses $001c and $001d after reset). table 1-3 shows the read-only values of these registers. refer to section module mapping and control (mmc) of hcs12 core user guide for further details. table 1-3 memory size registers register name value memsiz0 $25 memsiz1 $81
mc9s12h256 device user guide v01.13 25 section 2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. it is built from the signal description sections of the block user guides of the individual ip blocks on the device. 2.1 device pinout the mc9s12h256 is available in a 112-pin and 144-pin quad flat pack (lqfp). most pins perform two or more functions, as described in the signal descriptions. figure 2-1 and figure 2-2 show the pin assignments. note: in expanded narrow modes the lower byte data is multiplexed with higher byte data through pins 64-71 on the 112-pin lqfp or through pins 111-118 on the 144-pin lqfp version.
mc9s12h256 device user guide v01.13 26 figure 2-1 pin assignments in 112-pin lqfp for mc9s12h256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 mc9s12h-family 112 lqfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/ ecs/romone/fp23 pe7/noacc/xclks/fp22 pe3/ lstrb/ taglo/fp21 pe2/r/ w/fp20 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vdda vrh vrl vssa pe0/ xirq pe4/eclk pe6/ipipe1/modb m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddr vddx2 vssx2 modc/ taghi/ bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 moda/ipip0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss/ps7 irq/pe1
mc9s12h256 device user guide v01.13 27 figure 2-2 pin assignments in 144-pin lqfp for mc9s12h256 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 kwh0/ph0 kwh1/ph1 kwh2/ph2 kwh3/ph3 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 kwh4/ph4 kwh5/ph5 kwh6/ph6 kwh7/ph7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 pwm2/pp2 pwm3/pp3 pwm4/pp4 pwm5/pp5 rxd0/ps0 txd0/ps1 rxd1/ps2 txd1/ps3 vss2 vddr vddx2 vssx2 modc/ taghi/bkgd reset vddpll xfc vsspll extal xtal test sda/pm0 scl/pm1 rxcan0/pm2 txcan0/pm3 rxcan1pm4 txcan1/pm5 moda/ipipe0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss/ps7 irq/pe1 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vdda vrh vrl vssa pe0/ xirq pe4/eclk pe6/ipipe1/modb pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 pj3/kwj3 pj2/kwj2 pj1/kwj1 pj0/kwj0 vssx1 vddx1 pk7/ ecs/romone/fp23 pe7/noacc/xclks/fp22 pe3/ lstrb/ t a glo/fp21 pe2/r/ w/fp20 pl7/fp31 pl6/fp30 pl5/fp29 pl4/fp28 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 mc9s12h-family 144 lqfp pins shown in bold are not available in the 112 lqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
mc9s12h256 device user guide v01.13 28 2.2 signal properties summary table 2-1 summarizes all pin functions. note: bold entries determine pins not available on 112-pin lqfp. table 2-1 signal properties pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by description extal vddpll oscillator pins xtal vddpll reset vddx2 external reset pin test vddx2 test input xfc vddpll pll loop filter bkgd t a ghi modc vddx2 background debug, tag high, mode pin pad[7:0] an[7:0] vdda port ad inputs, analog inputs (atd) pad[15:8] an[15:8] vdda port ad inputs, analog inputs (atd) pa[7:0] fp[15:8] addr[15:8]/ data[15:8] vddx1 port a i/o, multiplexed address/data pb[7:0] fp[7:0] addr[7:0]/ data[7:0] vddx1 port b i/o, multiplexed address/data pe7 fp22 xclks noacc vddx1 port e i/o, access, clock select, lcd driver pe6 ipipe1 modb vddx2 port e i/o, pipe status, mode input pe5 ipipe0 moda vddx2 port e i/o, pipe status, mode input pe4 eclk vddx2 port e i/o, bus clock output pe3 fp21 lstrb t a glo vddx1 port e i/o, lcd driver, byte strobe, tag low pe2 fp20 r/ w vddx1 port e i/o, r/ w in expanded modes pe1 irq vddx2 port e input, maskable interrupt pe0 xirq vddx2 port e input, non maskable interrupt ph[7:0] kwh[7:0] vddm port h i/o, interrupts pj[3:0] kwj[3:0] vddx1 port j i/o, interrupts pk7 fp23 ecs romone vddx1 port k i/o, emulation chip select, rom on enable pk[3:0] bp[3:0] xaddr[17:14] vddx1 port k i/o, lcd driver, extended addresses pl[3:0] fp[19:16] vddx1 port l i/o, lcd drivers pl[7:4] fp[31:28] vddx1 port l i/o, lcd drivers pm5 txcan1 vddx2 port m i/o, tx of can1 pm4 rxcan1 vddx2 port m i/o, rx of can1 pm3 txcan0 vddx2 port m i/o, tx of can0 pm2 rxcan0 vddx2 port m i/o, rx of can0 pm1 scl vddx2 port m i/o, scl of iic pm0 sda vddx2 port m i/o, sda of iic pp[5:2] pwm[5:2] vddx2 port p i/o, pwm channels pp[1:0] pwm[1:0] vddx2 port p i/o, pwm channels ps7 ss vddx2 port s i/o, ss of spi ps6 sck vddx2 port s i/o, sck of spi
mc9s12h256 device user guide v01.13 29 2.3 detailed signal descriptions 2.3.1 extal, xtal oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 2.3.2 reset external reset pin an active low bidirectional control signal, it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. ps5 mosi vddx2 port s i/o, mosi of spi ps4 miso vddx2 port s i/o, miso of spi ps3 txd1 vddx2 port s i/o, txd of sci1 ps2 rxd1 vddx2 port s i/o, rxd of sci1 ps1 txd0 vddx2 port s i/o, txd of sci0 ps0 rxd0 vddx2 port s i/o, rxd of sci0 pt[7:4] ioc[7:4] vddx1 port t i/o, timer channels pt[3:0] ioc[3:0] fp[27:24] vddx1 port t i/o, timer channels, lcd driver pu[3:0] m0c0m m0c0p m0c1m m0c1p vddm port u i/o, motor0 of mc pu[7:4] m1c0m m1c0p m1c1m m1c1p vddm port u i/o, motor1 of mc pv[3:0] m2c0m m2c0p m2c1m m2c1p vddm port v i/o, motor2 of mc pv[7:4] m3c0m m3c0p m3c1m m3c1p vddm port v i/o, motor3 of mc pw[3:0] m4c0m m4c0p m4c1m m4c1p vddm port w i/o, motor4 of mc pw[7:4] m5c0m m5c0p, m5c1m m5c1p vddm port w i/o, motor5 of mc pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by description
mc9s12h256 device user guide v01.13 30 2.3.3 test test pin this pin is reserved for test. note: the test pin must be tied to vss in all applications. 2.3.4 xfc pll loop filter pin dedicated pin used to create the pll loop filter. 2.3.5 bkgd / taghi / modc background debug, tag high, and mode pin the bkgd/ taghi/modc pin is used as a pseudo-open-drain pin for the background debug communication. in mcu expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. 2.3.6 pad[15:8] / an[15:8] port ad input pins [15:8] pad15-pad8 are general purpose input pins and analog inputs for the analog to digital converter. note: these pins are not available in the 112-pin lqfp version. 2.3.7 pad[7:0] / an[7:0] port ad input pins [7:0] pad7-pad0 are general purpose input pins and analog inputs for the analog to digital converter. 2.3.8 pa[7:0] / fp[15:8] / addr[15:8] / data[15:8] port a i/o pins pa7-pa0 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp15-fp8 of the lcd. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.9 pb[7:0] / fp[7:0] / addr[7:0] / data[7:0] port b i/o pins pb7-pb0 are general purpose input or output pins. hey can be configured as frontplane segment driver outputs fp7-fp0 of the lcd. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.10 pe7 / fp22 / xclks / noacc port e i/o pin 7 pe7 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp22 of the lcd module. the xclks signal selects between an external clock or oscillator configuration during reset.
mc9s12h256 device user guide v01.13 31 the xclks input selects between an external clock or oscillator configuration. the state of this pin is latched at the rising edge of reset. if the input is a logic high the extal pin is configured for an external clock drive. if input is a logic low an oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an oscillator circuit on extal and xtal. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or free cycle. this signal will assert when the cpu is not using the bus. 2.3.11 pe6 / modb / ipipe1 port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe1. this pin is an input with a pull-down device which is only active when reset is low. 2.3.12 pe5 / moda / ipipe0 port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the instruction queue tracking signal ipipe0. this pin is an input with a pull-down device which is only active when reset is low. 2.3.13 pe4 / eclk port e i/o pin 4 pe4 is a general purpose input or output pin. it can be configured to drive the internal bus clock eclk. eclk can be used as a timing reference. 2.3.14 pe3 / fp21 / lstrb / taglo port e i/o pin 3 pe3 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp21 of the lcd module. in mcu expanded modes of operation, lstrb is used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, taglo is used to tag the low half of the instruction word being read into the instruction queue. 2.3.15 pe2 / fp20 / r/ w port e i/o pin 2 pe2 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp20 of the lcd module. in mcu expanded modes of operations, this pin performs the read/write output signal for the external bus. it indicates the direction of data on the external bus. 2.3.16 pe1 / irq port e input pin 1 pe1 is a general purpose input pin and also the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode.
mc9s12h256 device user guide v01.13 32 2.3.17 pe0 / xirq port e input pin 0 pe0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.18 ph[7:0] / kwh[7:0] port h i/o pins [7:0] ph7-ph0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode. note: these pins are not available in the 112-pin lqfp version. 2.3.19 pj[3:0] / kwj[3:0] port j i/o pins [3:0] pj3-pj0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode.and are shared with the interrupt function. note: these pins are not available in the 112-pin lqfp version. 2.3.20 pk7 / fp23 / ecs / romone port k i/o pin 7 pk7 is a general purpose input or output pin. it can be configured as frontplane segment driver output fp23 of the lcd module. during mcu expanded modes of operation, this pin is used as the emulation chip select signal ( ecs). during reset of the mcu to normal expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map (romone). at the rising edge of reset, the state of this pin is latched to the romon bit. 2.3.21 pk[3:0] / bp[3:0] / xaddr[17:14] port k i/o pins [3:0] pk3-pk0 are general purpose input or output pins. they can be configured as backplane segment driver outputs bp3-bp0 of the lcd module. in mcu expanded modes of operation, these pins provide the expanded address xaddr[17:14] for the external bus. 2.3.22 pl[7:4] / fp[31:28] port l i/o pins [7:4] pl7-pl4 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp31-fp28 of the lcd module. note: these pins are not available in the 112-pin lqfp version. 2.3.23 pl[3:0] / fp[19:16] port l i/o pins [3:0] pl3-pl0 are general purpose input or output pins. they can be configured as frontplane segment driver outputs fp19-fp16 of the lcd module.
mc9s12h256 device user guide v01.13 33 2.3.24 pm5 / txcan1 port m i/o pin 5 pm5 is a general purpose input or output pin. it can be configured as the transmit pin txcan1 of the motorola scalable controller area network controller 1 (can1) 2.3.25 pm4 / rxcan1 port m i/o pin 4 pm4 is a general purpose input or output pin. it can be configured as the receive pin rxcan1 of the motorola scalable controller area network controller 1 (can1) 2.3.26 pm3 / txcan0 port m i/o pin 3 pm3 is a general purpose input or output pin. it can be configured as the transmit pin txcan0 of the motorola scalable controller area network controller 0 (can0) 2.3.27 pm2 / rxcan0 port m i/o pin 2 pm2 is a general purpose input or output pin. it can be configured as the receive pin rxcan0 of the motorola scalable controller area network controller 0 (can0) 2.3.28 pm1 / scl port m i/o pin 1 pm1 is a general purpose input or output pin. it can be configured as the serial clock pin scl of the inter-ic bus interface (iic). note: this pin is not available in the 112-pin lqfp version. 2.3.29 pm0 / sda port m i/o pin 0 pm0 is a general purpose input or output pin. it can be configured as the serial data pin sda of the inter-ic bus interface (iic). note: this pin is not available in the 112-pin lqfp version. 2.3.30 pp[5:2] / pwm[5:2] port p i/o pins [5:2] pp5-pp2 are general purpose input or output pins. they can be configured as pulse width modulator (pwm) channel outputs pwm5-pwm2. note: these pins are not available in the 112-pin lqfp version. 2.3.31 pp[1:0] / pwm[1:0] port p i/o pins [1:0] pp1-pp0 are general purpose input or output pins. they can be configured as pulse width modulator (pwm) channel outputs pwm1-pwm0.
mc9s12h256 device user guide v01.13 34 2.3.32 ps7 / ss port s i/o pin 7 ps7 is a general purpose input or output pin. it can be configured as slave select pin ss of the serial peripheral interface (spi). 2.3.33 ps6 / sck port s i/o pin 6 ps6 is a general purpose input or output pin. it can be configured as serial clock pin sck of the serial peripheral interface (spi). 2.3.34 ps5 / mosi port s i/o pin 5 ps5 is a general purpose input or output pin. it can be configured as the master output (during master mode) or slave input (during slave mode) pin mosi of the serial peripheral interface (spi). 2.3.35 ps4 / miso port s i/o pin 4 ps4 is a general purpose input or output pin. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso for the serial peripheral interface (spi). 2.3.36 ps3 / txd1 port s i/o pin 3 ps3 is a general purpose input or output pin. it can be configured as transmit pin txd1 of the serial communication interface 1 (sci1). note: this pin is not available in the 112-pin lqfp version. 2.3.37 ps2 / rxd1 port s i/o pin 2 ps2 is a general purpose input or output pin. it can be configured as receive pin rxd1 of the serial communication interface 1 (sci1). note: this pin is not available in the 112-pin lqfp version. 2.3.38 ps1 / txd0 port s i/o pin 1 ps1 is a general purpose input or output pin. it can be configured as transmit pin txd0 of the serial communication interface 0 (sci0). 2.3.39 ps0 / rxd0 port s i/o pin 0 ps0 is a general purpose input or output pin. it can be configured as receive pin rxd0 of the serial communication interface 0 (sci0).
mc9s12h256 device user guide v01.13 35 2.3.40 pt[7:4] / ioc[7:4] port t i/o pins [7:4] pt7-pt4 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc7-ioc4 of the timer (tim). 2.3.41 pt[3:0] / ioc[3:0] / fp[27:24] port t i/o pins [3:0] pt3-pt0 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc3-ioc0 of the timer (tim). they can be configured as frontplane segment driver outputs fp27-fp24 of the lcd module. 2.3.42 pu[7:4] / m1c0m, m1c0p, m1c1m, m1c1p port u i/o pins [7:4] pu7-pu4 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive current flow through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state. 2.3.43 pu[3:0] / m0c0m, m0c0p, m0c1m, m0c1p port u i/o pins [3:0] pu3-pu0 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive current flow through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state. 2.3.44 pv[7:4] / m3c0m, m3c0p, m3c1m, m3c1p port v i/o pins [7:4] pv7-pv4 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive current flow through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state. 2.3.45 pv[3:0] / m2c0m, m2c0p, m2c1m, m2c1p port v i/o pins [3:0] pv3-pv0 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive current flow through coil 0 when m2c0p is driven to a logic high state. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state.
mc9s12h256 device user guide v01.13 36 2.3.46 pw[7:4] / m5c0m, m5c0p, m5c1m, m5c1p port w i/o pins [7:4] pw7-pw4 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive current flow through coil 0 when m5c0p is driven to a logic high state. pwm output on m5c1m results in a positive current flow through coil 1 when m5c1p is driven to a logic high state. 2.3.47 pw[3:0] / m4c0m, m4c0p, m4c1m, m4c1p port w i/o pins [3:0] pw3-pw0 are general purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive current flow through coil 0 when m4c0p is driven to a logic high state. pwm output on m4c1m results in a positive current flow through coil 1 when m4c1p is driven to a logic high state. 2.4 power supply pins mc9s12h256 power and ground pins are described below. note: all vss pins must be connected together in the application ( 21.2 recommended pcb layout ). because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded ( table 21-1 ). 2.4.1 vddr external power pin vddr is the power supply pin for the internal voltage regulator. 2.4.2 vddx1, vddx2, vssx1, vssx2 external power and ground pins vddx1, vddx2, vssx1 and vssx2 are the power supply and ground pins for input/output drivers.vddx1 and vddx2 as well as vssx1 and vssx2 are not internally connected. 2.4.3 vdd1, vss1, vss2 core power pins vdd1, vss1 and vss2 are the core power and ground pins and related to the voltage regulator output. these pins serve as connection points for filter capacitors. vss1 and vss2 are internally connected. note: no load allowed except for bypass capacitors.
mc9s12h256 device user guide v01.13 37 2.4.4 vdda, vssa power supply pins for atd and vreg vdda, vssa are the power supply and ground pins for the voltage regulator and the analog to digital converter. 2.4.5 vddm1, vddm2, vddm3 power supply pins for motor 0 to 5 vddm1, vddm2 and vddm3 are the supply pins for the output drivers of motor 0 to 5. vddm1, vddm2 and vddm3 are internally connected. 2.4.6 vssm1, vssm2, vssm3 ground pins for motor 0 to 5 vssm1, vssm2 and vssm3 are the ground pins for the output drivers of motor 0 to 5. vssm1, vssm2 and vssm3 are internally connected. 2.4.7 vlcd power supply reference pin for lcd driver vlcd is the voltage reference pin for the lcd driver. adjusting the voltage on this pin will change the display contrast. 2.4.8 vrh, vrl atd reference voltage input pins vrh and vrl are the voltage reference pins for the analog to digital converter. 2.4.9 vddpll, vsspll power supply pins for pll vddpll and vsspll are the pll supply pins and serve as connection points for external loop filter components. note: no load allowed except for bypass capacitors.
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mc9s12h256 device user guide v01.13 39 section 3 system clock description 3.1 overview the clock and reset generator provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block user guide for details on clock generation. figure 3-1 clock connections crg bus clock core clock extal xtal oscillator clock s12_core iic ram sci0, sci1 pwm atd eeprom flash tim mc spi can0, can1 pim lcd
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mc9s12h256 device user guide v01.13 41 section 4 modes of operation 4.1 overview eight possible modes determine the operating configuration of the mc9s12h256. each mode has an associated default memory map and external bus configuration. three low power modes exist for the device. 4.2 modes of operation the operating mode out of reset is determined by the states of the modc, modb, and moda pins during reset ( table 4-1 ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. there are two basic types of operating modes: 1. normal modes: some registers and bits are protected against accidental changes. 2. special modes: allow greater access to protected control registers and bits for special purposes such as testing. a system development and debug feature, background debug mode (bdm), is available in all modes. in special single-chip mode, bdm is active immediately after reset. some aspects of port e are not mode dependent. bit 1 of port e is a general purpose input or the irq interrupt input. irq can be enabled by bits in the cpus condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. bit 0 of port e is a general purpose input or the xirq interrupt input. xirq can be enabled by bits in the cpus condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. the estr bit in the ebictl register is set to one by reset in any user mode. this assures that the reset vector can be fetched table 4-1 mode selection modc modb moda mode description 000 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 0 0 1 emulation expanded narrow, bdm allowed 0 1 0 special test (expanded wide) ( motorola use only ), bdm allowed 0 1 1 emulation expanded wide, bdm allowed 1 0 0 normal single chip, bdm allowed 1 0 1 normal expanded narrow, bdm allowed 110 peripheral ( motorola use only ); bdm allowed but bus operations would cause bus con?icts (must not be used) 1 1 1 normal expanded wide, bdm allowed
mc9s12h256 device user guide v01.13 42 even if it is located in an external slow memory device. the pe6/modb/ipipe1 and pe5/moda/ipipe0 pins act as high-impedance mode select inputs during reset. the following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. 4.2.1 normal operating modes these modes provide three operating configurations. background debug is available in all three modes, but must first be enabled for some operations by means of a bdm background command, then activated. 4.2.1.1 normal single-chip mode there is no external expansion bus in this mode. all pins of ports a, b and e are configured as general purpose i/o pins port e bits 1 and 0 are available as general purpose input only pins with internal pull-ups enabled. all other pins of port e are bidirectional i/o pins that are initially configured as high-impedance inputs with internal pull-ups enabled. ports a and b are configured as high-impedance inputs with their internal pull-ups disabled. the pins associated with port e bits 6, 5, 3, and 2 cannot be configured for their alternate functions ipipe1, ipipe0, lstrb, and r/ w while the mcu is in single chip modes. in single chip modes, the associated control bits pipoe, lstre, and rdwe are reset to zero. writing the opposite state into them in single chip mode does not change the operation of the associated port e pins. in normal single chip mode, the mode register is writable one time. this allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. port e, bit 4 can be configured for a free-running e clock output by clearing neclk=0. typically the only use for an e clock output while the mcu is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.1.2 normal expanded wide mode in expanded wide modes, ports a and b are configured as a 16-bit multiplexed address and data bus and port e bit 4 is configured as the e clock output signal. these signals allow external memory and peripheral devices to be interfaced to the mcu. port e pins other than pe4/eclk are configured as general purpose i/o pins (initially high-impedance inputs with internal pull-up resistors enabled). control bits pipoe, neclk, lstre, and rdwe in the pear register can be used to configure port e pins to act as bus control outputs instead of general purpose i/o pins. it is possible to enable the pipe status signals on port e bits 6 and 5 by setting the pipoe bit in pear, but it would be unusual to do so in this mode. development systems where pipe status signals are monitored would typically use the special variation of this mode. the port e bit 2 pin can be reconfigured as the r/ w bus control signal by writing 1 to the rdwe bit in pear. if the expanded system includes external devices that can be written, such as ram, the rdwe bit
mc9s12h256 device user guide v01.13 43 would need to be set before any attempt to write to an external location. if there are no writable resources in the external system, pe2 can be left as a general purpose i/o pin. the port e bit 3 pin can be reconfigured as the lstrb bus control signal by writing 1 to the lstre bit in pear. the default condition of this pin is a general purpose input because the lstrb function is not needed in all expanded wide applications. the port e bit 4 pin is initially configured as eclk output with stretch. the e clock output function depends upon the settings of the neclk bit in the pear register, the ivis bit in the mode register and the estr bit in the ebictl register. the e clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 4.2.1.3 normal expanded narrow mode this mode is used for lower cost production systems that use 8-bit wide external eproms or rams. such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. ports a and b are configured as a 16-bit address bus and port a is multiplexed with data. internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. since the pear register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. the pe3/ lstrb pin is always a general purpose i/o pin in normal expanded narrow mode. although it is possible to write the lstre bit in pear to 1 in this mode, the state of lstre is overridden and port e bit 3 cannot be reconfigured as the lstrb output. it is possible to enable the pipe status signals on port e bits 6 and 5 by setting the pipoe bit in pear, but it would be unusual to do so in this mode. lstrb would also be needed to fully understand system activity. development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. the pe4/eclk pin is initially configured as eclk output with stretch. the e clock output function depends upon the settings of the neclk bit in the pear register, the ivis bit in the mode register and the estr bit in the ebictl register. in normal expanded narrow mode, the e clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. the pe2/r/w pin is initially configured as a general purpose input with a pull-up but this pin can be reconfigured as the r/ w bus control signal by writing 1 to the rdwe bit in pear. if the expanded narrow system includes external devices that can be written such as ram, the rdwe bit would need to be set before any attempt to write to an external location. if there are no writable resources in the external system, pe2 can be left as a general purpose i/o pin. 4.2.1.4 internal visibility internal visibility is available when the mcu is operating in expanded wide modes or special narrow mode. it is not available in single-chip, peripheral or normal expanded narrow modes. internal visibility is enabled by setting the ivis bit in the mode register.
mc9s12h256 device user guide v01.13 44 if an internal access is made while e, r/ w, and lstrb are configured as bus control outputs and internal visibility is off (ivis=0), e will remain low for the cycle, r/ w will remain high, and address, data and the lstrb pins will remain at their previous state. when internal visibility is enabled (ivis=1), certain internal cycles will be blocked from going external. during cycles when the bdm is selected, r/ w will remain high, data will maintain its previous state, and address and lstrb pins will be updated with the internal value. during cpu no access cycles when the bdm is not driving, r/ w will remain high, and address, data and the lstrb pins will remain at their previous state. 4.2.1.5 emulation expanded wide mode in expanded wide modes, ports a and b are configured as a 16-bit multiplexed address and data bus and port e provides bus control and status signals. these signals allow external memory and peripheral devices to be interfaced to the mcu. these signals can also be used by a logic analyzer to monitor the progress of application programs. the bus control related pins in port e (pe7/noacc, pe6/modb/ipipe1, pe5/moda/ipipe0, pe4/eclk, pe3/ lstrb/ taglo, and pe2/r/ w) are all configured to serve their bus control output functions rather than general purpose i/o. notice that writes to the bus control enable bits in the pear register in special mode are restricted. 4.2.1.6 emulation expanded narrow mode expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. accesses to internal resources that have been mapped external (i.e. porta, portb, ddra, ddrb, porte, ddre, pear, pucr, rdriv) will be accessed with a 16-bit data bus on ports a and b. accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using port a as an 8-bit data bus. internal operations continue to use full 16-bit data paths. they are only visible externally as 16-bit information if ivis=1. ports a and b are configured as multiplexed address and data output ports. during external accesses, address a15, data d15 and d7 are associated with pa7, address a0 is associated with pb0 and data d8 and d0 are associated with pa0. during internal visible accesses and accesses to internal resources that have been mapped external, address a15 and data d15 is associated with pa7 and address a0 and data d0 is associated with pb0. the bus control related pins in port e (pe7/noacc, pe6/modb/ipipe1, pe5/moda/ipipe0, pe4/eclk, pe3/ lstrb/ taglo, and pe2/r/ w) are all configured to serve their bus control output functions rather than general purpose i/o. notice that writes to the bus control enable bits in the pear register in special mode are restricted. 4.2.2 special operating modes there are two special operating modes that correspond to normal operating modes. these operating modes are commonly used in factory testing and system development.
mc9s12h256 device user guide v01.13 45 4.2.2.1 special single-chip mode when the mcu is reset in this mode, the background debug mode is enabled and active. the mcu does not fetch the reset vector and execute application code as it would in other modes. instead the active background mode is in control of cpu execution and bdm firmware is waiting for additional serial commands through the bkgd pin. when a serial command instructs the mcu to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the mcu was reset. there is no external expansion bus after reset in this mode. ports a and b are initially simple bidirectional i/o pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to the mode select bits in the mode register (which is allowed in special modes) can change this after reset. all of the port e pins (except pe4/eclk) are initially configured as general purpose high-impedance inputs with pull-ups enabled. pe4/eclk is configured as the e clock output in this mode. the pins associated with port e bits 6, 5, 3, and 2 cannot be configured for their alternate functions ipipe1, ipipe0, lstrb, and r/ w while the mcu is in single chip modes. in single chip modes, the associated control bits pipoe, lstre and rdwe are reset to zero. writing the opposite value into these bits in single chip mode does not change the operation of the associated port e pins. port e, bit 4 can be configured for a free-running e clock output by clearing neclk=0. typically the only use for an e clock output while the mcu is in single chip modes would be to get a constant speed clock for use in the external application system. 4.2.2.2 special test mode (motorola use only) in expanded wide modes, ports a and b are configured as a 16-bit multiplexed address and data bus and port e provides bus control and status signals. in special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. 4.2.3 test operating mode (motorola use only) there is a test operating mode in which an external master, such as an i.c. tester, can control the on-chip peripherals. 4.2.3.1 peripheral mode this mode is intended for motorola factory testing of the mcu. in this mode, the cpu is inactive and an external (tester) bus master drives address, data and bus control signals in through ports a, b and e. in effect, the whole mcu acts as if it was a peripheral under control of an external cpu. this allows faster testing of on-chip memory and peripherals than previous testing methods. since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the mcu into a different mode. background debugging should not be used while the mcu is in special peripheral mode as internal bus conflicts between bdm and the external master can cause improper operation of both functions.
mc9s12h256 device user guide v01.13 46 4.3 security the device will make available a security feature preventing the unauthorized read and write of the memory contents. this feature allows: ? protection of the contents of flash, ? protection of the contents of eeprom, ? operation in single-chip mode, ? operation from external memory with internal flash and eeprom disabled. the user must be reminded that part of the security must lie with the users code. an extreme example would be users code that dumps the contents of the internal program. this code would defeat the purpose of security. at the same time the user may also wish to put a back door in the users program. an example of this is the user downloads a key through the sci which allows access to a programming routine that updates parameters stored in eeprom. 4.3.1 securing the microcontroller once the user has programmed the flash and eeprom (if desired), the part can be secured by programming the security bits located in the flash module. these non-volatile bits will keep the part secured through resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check the flash block user guide for more details on the security configuration. 4.3.2 operation of the secured microcontroller 4.3.2.1 normal single chip mode this will be the most common usage of the secured part. everything will appear the same as if the part was not secured with the exception of bdm operation. the bdm operation will be blocked. 4.3.2.2 executing from external memory the user may wish to execute from external space with a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash and eeprom will be disabled. bdm operations will be blocked. 4.3.3 unsecuring the microcontroller in order to unsecure the microcontroller, the internal flash and eeprom must be erased. this can be done through an external program in expanded mode. once the user has erased the flash and eeprom, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flash and eeprom. once this program
mc9s12h256 device user guide v01.13 47 completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expanded mode (by writing the mode bits through the bdm) and jumping to an external program (again through bdm commands). note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 low power modes consult the respective block user guide for information on the module behavior in stop, pseudo stop, and wait mode.
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mc9s12h256 device user guide v01.13 49 section 5 resets and interrupts 5.1 overview consult the exception processing section of the hcs12 core user guide for information on resets and interrupts. 5.2 vectors 5.2.1 vector table table 5-1 lists interrupt sources and vectors in default order of priority. table 5-1 reset and interrupt vector table vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff external or power on reset none none - $fffc, $fffd clock monitor fail reset none copctl (cme, fcme) - $fffa, $fffb cop failure reset none cop rate select - $fff8, $fff9 unimplemented instruction trap none none - $fff6, $fff7 swi none none - $fff4, $fff5 xirq x-bit none - $fff2, $fff3 irq i-bit intcr (irqen) $f2 $fff0, $fff1 real time interrupt i-bit rtictl (rtie) $f0 $ffee, $ffef timer channel 0 i-bit tie (c0i) $ee $ffec, $ffed timer channel 1 i-bit tie (c1i) $ec $ffea, $ffeb timer channel 2 i-bit tie (c2i) $ea $ffe8, $ffe9 timer channel 3 i-bit tie (c3i) $e8 $ffe6, $ffe7 timer channel 4 i-bit tie (c4i) $e6 $ffe4, $ffe5 timer channel 5 i-bit tie (c5i) $e4 $ffe2, $ffe3 timer channel 6 i-bit tie (c6i) $e2 $ffe0, $ffe1 timer channel 7 i-bit tie (c7i) $e0 $ffde, $ffdf timer over?ow i-bit tscr2 (toi) $de $ffdc, $ffdd pulse accumulator a over?ow i-bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i-bit pactl (pai) $da $ffd8, $ffd9 spi i-bit sp0cr1 (spie) $d8 $ffd6, $ffd7 sci0 i-bit sc0cr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 sci1 i-bit sc1cr2 (tie, tcie, rie, ilie) $d4 $ffd2, $ffd3 atd0 i-bit atdctl2 (ascie) $d2 $ffd0, $ffd1 reserved $ffce, $ffcf port j i-bit ptjif (ptjie) $ce $ffcc, $ffcd port h i-bit pthif (pthie) $cc $ffca, $ffcb reserved
mc9s12h256 device user guide v01.13 50 5.3 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block user guides for register reset states. 5.3.1 i/o pins refer to the hcs12 core user guides for mode dependent pin configuration of port a, b, e and k out of reset. refer to the pim block user guide for reset configurations of all peripheral module ports. note: for devices assembled in 112-pin lqfp packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. refer to table 2-1 for affected pins. $ffc8, $ffc9 reserved $ffc6, $ffc7 crg pll lock i-bit crgint (lockie) $c6 $ffc4, $ffc5 crg self clock mode i-bit crgint (scmie) $c4 $ffc2, $ffc3 reserved $ffc0, $ffc1 iic bus i-bit ibcr (ibie) $c0 $ffbe, $ffbf reserved $ffbc, $ffbd reserved $ffba, $ffbb eeprom i-bit eectl (ccie, cbeie) $ba $ffb8, $ffb9 flash i-bit fctl (ccie, cbeie) $b8 $ffb6, $ffb7 can0 wake-up i-bit can0rier (wupie) $b6 $ffb4, $ffb5 can0 errors i-bit can0rier (cscie, ovrie) $b4 $ffb2, $ffb3 can0 receive i-bit can0rier (rxfie) $b2 $ffb0, $ffb1 can0 transmit i-bit can0tier (txeie[2:0]) $b0 $ffae, $ffaf can1 wake-up i-bit can0rier (wupie) $ae $ffac, $ffad can1 errors i-bit can1rier (cscie, ovrie) $ac $ffaa, $ffab can1 receive i-bit can1rier (rxfie) $aa $ffa8, $ffa9 can1 transmit i-bit can1tier (txeie[2:0]) $a8 $ff98 to $ffa7 reserved $ff96, $ff97 motor control timer over?ow i-bit mcctl1 (mcocie) $96 $ff9e to $ff95 reserved $ff8c, $ff8d pwm emergency shutdown i-bit pwmsdn(pwmie) $8c $ff80 to $ff8b reserved table 5-1 reset and interrupt vector table vector address interrupt source ccr mask local enable hprio value to elevate
mc9s12h256 device user guide v01.13 51 5.3.2 memory refer to table 1-1 for locations of the memories depending on the operating mode after reset the ram array is not automatically initialized out of reset.
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mc9s12h256 device user guide v01.13 53 section 6 hcs12 core block description consult the hcs12 core user guide for information about the hcs12 core modules, i.e. central processing unit (cpu), interrupt module (int), module mapping control module (mmc), multiplexed external bus interface (mebi), breakpoint module (bkp) and background debug mode module (bdm). section 7 clock and reset generator (crg) block description consult the crg block user guide for information about the clock and reset generator module. 7.1 device-specific information 7.1.1 xclks the xclks input signal is active high (see 2.3.10 pe7 / fp22 / xclks / noacc port e i/o pin 7 ). section 8 timer (tim) block description consult the tim_16b8c block user guide for information about the timer module. section 9 analog to digital converter (atd) block description consult the atd_10b16c block user guide for information about the analog to digital converter module. section 10 inter-ic bus (iic) block description consult the iic block user guide for information about the inter-ic bus module. section 11 serial communications interface (sci) block description
mc9s12h256 device user guide v01.13 54 there are two serial communications interfaces (sci0 and sci1) implemented on the mc9s12h256 device. consult the sci block user guide for information about each serial communications interface module. section 12 serial peripheral interface (spi) block description consult the spi block user guide for information about the serial peripheral interface module. section 13 pulse width modulator (pwm) block description consult the pwm_8b6c block user guide for information about the pulse width modulator module. section 14 flash eeprom 256k block description consult the fts256k block user guide for information about the flash module. section 15 eeprom 4k block description consult the eets4k block user guide for information about the eeprom module. section 16 ram block description the ram module does not contain any control registers. thus no block user guide is available. this module supports single-cycle misaligned word accesses without wait states. section 17 liquid crystal display driver (lcd) block description consult the lcd_32f4b block user guide for information about the liquid crystal display driver module. section 18 mscan block description
mc9s12h256 device user guide v01.13 55 there are two mscan modules (can0 and can1) implemented on the mc9s12h256 device. consult the mscan block user guide for information on each mscan. section 19 pwm motor control (mc) block description consult the mc_10b12c block user guide for information about the pwm motor control module. section 20 port integration module (pim) block description consult the pim_9h256 block user guide for information about the port integration module. section 21 voltage regulator (vreg) block description consult the vreg block user guide for information about the dual output linear voltage regulator. 21.1 device-specific information 21.1.1 vregen there is no vregen pin implemented on this device. 21.1.2 modes of operation 21.1.2.1 run mode vreg enters run mode whenever the cpu is neither in stop nor in pseudo stop mode. both regulating loops operate in run mode with full performance. 21.1.2.2 standby mode vreg enters standby mode when the cpu operates either in stop or in pseudo stop mode. the supply of the core logic as well as the oscillators are derived from two voltage clamps. standby mode minimizes quiescent current drawn by the voltage regulator block. 21.1.2.3 shutdown mode vreg shutdown mode is not available on mc9s12h family devices.
mc9s12h256 device user guide v01.13 56 21.2 recommended pcb layout figure 21-1 lqfp112 recommended pcb layout c9 c4 c6 c8 c2 c1 c10 c11 q1 c13 c12 r1 vssx1 vddx1 vddr/ vddm2 vssm2 vdd1 vss1 vddpll vsspll vdda vssa c3 c7 vddm1 vssm1 vddx2 c5 vddm3 vssm3 c14
mc9s12h256 device user guide v01.13 57 figure 21-2 lqfp144 recommended pcb layout c8 vssx1 vddx1 c6 vddm2 vssm2 c7 vddm1 vssm1 c5 vddm3 vssm3 c9 c4 c10 c11 q1 c13 c12 r1 vddr/ vddpll vsspll c3 vddx2 c2 c1 vdd1 vss1 vdda vssa c14
mc9s12h256 device user guide v01.13 58 the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: ? every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible to the corresponding pins(c1 C c9). ? central point of the ground star should be the vss1 pin. ? use low ohmic low inductance connections between vss1, vss2, vssa, vssx1,2 and vssm1,2,3. ? vsspll must be directly connected to vss1. ? keep traces of vsspll, extal and xtal as short as possible and occupied board area for c10, c11, c14 and q1 as small as possible. ? do not place other signals or supplies underneath area occupied by c10, c11, c14 and q1 and the connection area to the mcu. ? central power input should be fed in at the vdda/vssa pins. table 21-1 recommended components component purpose type value c1 vdd1 ?lter cap ceramic x7r 100 .. 220nf c2 vdda ?lter cap x7r/tantalum >=100nf c3 vddx2 ?lter cap x7r/tantalum >=100nf c4 vddr ?lter cap x7r/tantalum >=100nf c5 vddm3 ?lter cap x7r/tantalum >=100nf c6 vddm2 ?lter cap x7r/tantalum >=100nf c7 vddm1 ?lter cap x7r/tantalum >=100nf c8 vddx1 ?lter cap x7r/tantalum >=100nf c9 vddpll ?lter cap ceramic x7r 100nf .. 220nf c10 osc load cap see crg block user guide c11 osc load cap c12 pll loop ?lter cap c13 pll loop ?lter cap c14 dc cutoff cap r1 pll loop ?lter res q1 quartz/resonator
mc9s12h256 device user guide v01.13 59 appendix a electrical characteristics a.1 general note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values cannot be guaranteed by motorola and are subject to change without notice. this supplement contains the most accurate electrical information for the mc9s12h256 microcontroller available at the time of publication. the information should be considered preliminary and is subject to change. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. note: this classification is shown in the column labeled c in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the mc9s12h256 utilizes several pins to supply power to the i/o ports, a/d converter, oscillator and pll as well as the digital core. the vdda, vssa pair supplies the a/d converter and the resistor ladder of the internal voltage regulator.
mc9s12h256 device user guide v01.13 60 the vddx1/vssx1 and vddx2/vssx2 pairs supply the i/o pins except ph, pu, pv and pw. vddr supplies the internal voltage regulator. vddm1/vssm1, vddm2/vssm2 and vddm3/vssm3 pairs supply the ports ph, pu, pv and pw. vdd1, vss1 and vss2 are the supply pins for the digital logic, vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdda, vddx1, vddx2, vddm as well as vssa, vssx1, vssx2 and vssm are connected by anti-parallel diodes for esd protection. note: in the following context vdd5 is used for either vdda, vddm, vddr and vddx1/2; vss5 is used for either vssa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the currents flowing into the vdda, vddx1/2, vddm and vddr pins. vdd is used for vdd1 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vddpll. a.1.3 pins there are four groups of functional pins. a.1.3.1 5v i/o pins those i/o pins have a nominal level of 5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this group is made up by the vrh and vrl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only.
mc9s12h256 device user guide v01.13 61 a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in external power supply going out of regulation. ensure external vdd5 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ).
mc9s12h256 device user guide v01.13 62 a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device table a-1 absolute maximum ratings 1 notes : 1. beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 C0.3 6.0 v 2 digital logic supply voltage 2 2. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd C0.3 3.0 v 3 pll supply voltage 2 v ddpll C0.3 3.0 v 4 voltage difference vddx1 to vddx2 to vddm and vdda d vddx C0.3 0.3 v 5 voltage difference vssx to vssr and vssa d vssx C0.3 0.3 v 6 digital i/o input voltage v in C0.3 6.0 v 7 analog reference v rh, v rl C0.3 6.0 v 8 xfc, extal, xtal inputs v ilv C0.3 3.0 v 9 test input v test C0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins except pu, pv and pw 3 3. all digital i/o pins are internally clamped to v ssx1/2 and v ddx1/2 , v ssm and v ddm or v ssa and v dda . i d C25 +25 ma 11 instantaneous maximum current single pin limit for port pu, pv and pw 4 4. ports pu, pv, pw are internally clamped to v ssm and v ddm . i d C55 +55 ma 12 instantaneous maximum current single pin limit for xfc, extal, xtal 5 5. those pins are internally clamped to v sspll and v ddpll . i dl C25 +25 ma 13 instantaneous maximum current single pin limit for test 6 6. this pin is clamped low to v sspll , but not clamped high. this pin must be tied low in applications. i dt C0.25 0 ma 14 storage temperature range t stg C 65 155 c
mc9s12h256 device user guide v01.13 63 specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note: please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation table a-2 esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 w storage capacitance c 100 pf number of pulse per pin positive negative C C 3 3 machine series resistance r1 0 w storage capacitance c 200 pf number of pulse per pin positive negative C C 3 3 latch-up minimum input voltage limit C2.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 C v 2 c machine model (mm) v mm 200 C v 3 c charge device model (cdm) v cdm 500 C v 4c latch-up current at t a = 125 c positive negative i lat +100 C100 Cma 5c latch-up current at t a = 27 c positive negative i lat +200 C200 Cma
mc9s12h256 device user guide v01.13 64 calculations refer to section a.1.8 power dissipation and thermal characteristics . a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j )in c can be obtained from: table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 4.5 5 5.25 v digital logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage 2 v ddpll 2.35 2.5 2.75 v voltage difference vddx to vddr and vdda d vddx C0.1 0 0.1 v voltage difference vssx to vssr and vssa d vssx C0.1 0 0.1 v oscillator f osc 0.5 C 16 mhz bus frequency f bus 0.5 C 25 mhz mc9s12h256 c operating junction temperature range t j C40 C 100 c operating ambient temperature range 2 2. please refer to section a.1.8 power dissipation and thermal characteristics for more details about the rela- tion between ambient temperature t a and device junction temperature t j . t a C40 27 85 c mc9s12h256 v operating junction temperature range t j C40 C 120 c operating ambient temperature range 2 t a C40 27 105 c mc9s12h256 m operating junction temperature range t j C40 C 140 c operating ambient temperature range 2 t a C40 27 125 c t j t a p d q ja () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] =
mc9s12h256 device user guide v01.13 65 the total power dissipation can be calculated from: p io is the sum of all output currents on i/o ports associated with vddx1,2 and vddm1,2,3. a.1.9 i/o characteristics this section describes the characteristics of all 5v i/o pins. all parameters are not always applicable, e.g. not all pins feature pull up/down resistances. table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1t thermal resistance lqfp112, single sided pcb 2 2. pc board according to eia/jedec standard 51-2 q ja CC54 o c/w 2t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 q ja CC41 o c/w 3 t thermal resistance lqfp 144, single sided pcb q ja CC45 o c/w 4t thermal resistance lqfp 144, double sided pcb with 2 internal planes q ja CC37 o c/w q ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = p int i ddr v ddr i dda v dda + = p io r dson i ? i io i 2 =
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mc9s12h256 device user guide v01.13 67 table a-6 5v i/o characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 C v dd5 + 0.3 v 2 p input low voltage v il v ss5 C 0.3 C 0.35*v dd5 v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high impedance input mode) 1 v in = v dd5 or v ss5 i in C2.5 C 2.5 m a 5p output high voltage (pins in output mode, except pu, pv and pw) partial drive i oh = C1.0ma full drive i oh = C10ma v oh v dd5 C 0.8 CCv 6p output low voltage (pins in output mode except pu, pv and pw) partial drive i ol = +1.0ma full drive i ol = +10ma v ol C C 0.8 v 7p output high voltage (pins pu, pv and pw in output mode) i oh = C20ma v oh v dd5 C 0.32 v dd5 C 0.2 Cv 8p output low voltage (pins pu, pv and pw in output mode) i ol = +20ma v ol C .2 0.32 v 9p output rise time (pins pu, pv and pw in output mode with slew control enabled) v dd5 =5v, r load =1k w , 10% to 90% of v oh t r 75 100 120 ns 10 p output fall time (pins pu, pv and pw in output mode with slew control enabled) v dd5 =5v, r load =1k w , 10% to 90% of v oh t f 75 100 120 ns 11 p internal pull up device current, tested at v il max. i pul C C C130 m a 12 p internal pull up device current, tested at v ih min. i puh C10 C C m a 13 p internal pull down device current, tested at v ih min. i pdh C C 130 m a 14 p internal pull down device current, tested at v il max. i pdl 10 C C m a 15 d input capacitance c in 6Cpf 16 t injection current 2 single pin limit total device limit. sum of all injected currents i ics i icp C2.5 C25 C 2.5 25 ma 17 p port h, j interrupt input pulse ?ltered 3 t pulse 3 m s
mc9s12h256 device user guide v01.13 68 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25mhz bus frequency using a 4mhz oscillator in colpitts mode. production testing is performed using a square wave signal at the extal input. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be 18 p port h, j interrupt input pulse passed 3 t pulse 10 m s notes : 1. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. 2. refer to section a.1.4 current injection , for more details 3. parameter only applies in stop or pseudo stop mode. table a-6 5v i/o characteristics conditions are shown in table a-4 unless otherwise noted
mc9s12h256 device user guide v01.13 69 given. a very good estimate is to take the single chip currents and add the currents due to the external loads. table a-7 supply current characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p run supply currents single chip, internal regulator enabled i dd5 65 ma 2p p wait supply current all modules enabled, pll on only rti enabled 1 i ddw 40 5 ma 3 c p c c c c p pseudo stop current (rti and cop enabled) 1, 2 C40 c 27 c 70 c 85 c 105 c 125 c 140 c notes : 1. pll off 2. at those low power dissipation levels t j = t a can be assumed i ddps tbd 600 tbd tbd tbd tbd 1000 750 5000 m a 4 c c c c c c c pseudo stop current (rti and cop disabled) 1, 2 C40 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps tbd 350 tbd tbd tbd tbd 700 m a 5 c p c c c c p stop current 2 C40 c 27 c 70 c 85 c 105 c 125 c 140 c i dds tbd 30 tbd 200 tbd tbd 500 100 5000 m a
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mc9s12h256 device user guide v01.13 71 a.2 atd characteristics this section describes the characteristics of the analog to digital converter. a.2.1 atd operating characteristics the table a-8 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. a.2.2 factors influencing accuracy three factors C source resistance, source capacitance and current injection C have an influence on the accuracy of the atd. a.2.2.1 source resistance: due to the input pin leakage current as specified in table a-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or table a-8 atd operating characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.50v v rh Cv rl 4.50 5.00 5.25 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles m s 6d stop recovery time (v dda =5.0 volts) t sr 20 m s 7 p reference supply current i ref 0.375 ma
mc9s12h256 device user guide v01.13 72 operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. a.2.2.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 3 1024 * (c ins C c inn ). a.2.2.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than specified as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err =k*r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table a-9 atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s CC1k w 2t total input capacitance non sampling sampling c inn c ins 10 22 pf 3 c disruptive analog input current i na C2.5 2.5 ma 4 c coupling ratio positive current injection k p 10 C4 a/a 5 c coupling ratio negative current injection k n 10 C2 a/a
mc9s12h256 device user guide v01.13 73 a.2.3 atd accuracy table a-10 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. for the following definitions see also figure a-1 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: table a-10 atd conversion performance conditions are shown in table a-4 unless otherwise noted v ref = v rh C v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl C1 1 counts 3 p 10-bit integral nonlinearity inl C2.5 1.5 2.5 counts 4p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae C3 2.0 3 counts 5 p 8-bit resolution lsb 20 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.0 0.5 1.0 counts 8p 8-bit absolute error 1 ae C1.5 1.0 1.5 counts dnl i () v i v i1 C C 1lsb ------------------------ 1 C = inl n () dnl i () i1 = n ? v n v 0 C 1lsb ------------------- - n C ==
mc9s12h256 device user guide v01.13 74 figure a-1 atd accuracy definitions note: figure a-1 shows only definitions, for specification values refer to table a-10 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 45 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb v iC1 v i dnl
mc9s12h256 device user guide v01.13 75 a.3 nvm, flash and eeprom note: unless otherwise noted the abbreviation nvm (non volatile memory) is used for both flash and eeprom. a.3.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table a-11 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.3.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.3.1.2 burst programming this applies only to the flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: burst programming is more than 2 times faster than single word programming. t swpgm 9 1 f nvmop --------------------- 25 1 f bus ---------- + = t bwpgm 4 1 f nvmop --------------------- 9 1 f bus ---------- + = t brpgm t swpgm 31 t bwpgm + =
mc9s12h256 device user guide v01.13 76 a.3.1.3 sector erase erasing a 512 byte flash sector or a 4 byte eeprom sector takes: the setup time can be ignored for this operation. a.3.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.3.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. table a-11 nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 32 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections a.3.1.1 - a.3.1.4 for guidance. m s 5d flash burst programming consecutive word 4 4. urst programming operations are not applicable to eeprom t bwpgm 20.4 2 31 3 m s 6d flash burst programming time for 32 words 4 t brpgm 678.4 2 1035.5 3 m s 7 p sector erase time t era 20 5 5. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 26.7 3 ms 8 p mass erase time t mass 100 5 133 3 ms t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ?
mc9s12h256 device user guide v01.13 77 the failure rates for data retention and program/erase cycling are specified at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. note: all values shown in table a-12 are target values and subject to further extensive characterization table a-12 nvm reliability characteristics note: flash cycling performance is 10 cycles at -40?c to +125?c. data retention is specified for 15 years. note: eeprom cycling performance is 10k cycles at -40?c to 125?c. data retention is specified for 5 years on words after cycling 10k times. however if only 10 cycles are executed on a word the data retention is specified for 15 years. conditions are shown in table a-4 unless otherwise noted num c rating cycles data retention lifetime unit 1 c flash/eeprom (-40?c to +125?c) 10 15 years 2 c eeprom (-40?c to +125?c) 10,000 5 years
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mc9s12h256 device user guide v01.13 79 a.4 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). a.4.1 startup table a-13 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block user guide. a.4.1.1 por the release level v porr and the assert level v pora are derived from the vdd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.4.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.4.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. table a-13 startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr 2.07 v 2 t por assert level v pora 0.97 v 3 d reset input pulse width, minimum input time pw rstl 2 t osc 4 d startup from reset n rst 192 196 n osc 5 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 6 d wait recovery startup time t wrs 14 t cyc
mc9s12h256 device user guide v01.13 80 a.4.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. a.4.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. a.4.2 oscillator the device features an internal colpitts oscillator. by asserting the xclks input during reset this oscillator can be bypassed allowing the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa. table a-14 oscillator characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c crystal oscillator range f osc 0.5 16 mhz 2 p startup current i osc 100 m a 3 d oscillator start-up time from por or stop n uposc 4100 cyc osc 4 c oscillator start-up time t uposc 8 1 notes : 1. f osc = 4mhz, c = 22pf. 100 2 2. maximum value is for extreme cases using high q, low frequency crystals ms 5 d clock quality check time-out t cqout 0.45 2.5 s 6 p clock monitor failure assert frequency f cmfa 50 100 200 khz 7p external square wave input frequency 3 f ext 0.5 32 mhz 8 d external square wave pulse width low t extl 15 ns 9 d external square wave pulse width high t exth 15 ns 10 d external square wave rise time t extr 1ns 11 d external square wave fall time t extf 1ns 12 d input capacitance extal pin c in 9pf 13 d input capacitance xtal pin c in 13 pf 14 c dc operating bias in colpitts con?guration on extal pin v dcbias 1.1 v
mc9s12h256 device user guide v01.13 81 a.4.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.4.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. figure a-2 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table a-15 . the vco gain at the desired vco output frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. 3. xclks =1 during reset f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k f 1 2 d f cmp c s r c p vddpll k v k 1 e f 1 f vco C () k 1 1v ----------------------- = k f i ch k v =
mc9s12h256 device user guide v01.13 82 the loop bandwidth f c should be chosen to fulfill the gardners stability criteria by at least a factor of 10, typical values are 50. z = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above inputs the resistance can be calculated as: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: the stabilization delays shown in table a-15 are dependant on pll operational settings and external component selection (e.g. crystal, xfc filter). a.4.3.2 jitter information the basic functionality of the pll is shown in figure a-2 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-3 . f c 2 z f ref pz 1 z 2 + + ? ?? ------------------------------------------ 1 50 ------ f c f ref 450 -------------- z 0.9 = ( ) ; < ? < n f vco f ref ------------- 2 synr 1 + () == r 2 p nf c k f ---------------------------- - = c s 2 z 2 p f c r --------------------- - 0.516 f c r -------------- - z 0.9 = () ; ? = c s 20 c p c s 10
mc9s12h256 device user guide v01.13 83 figure a-3 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: figure a-4 maximum bus clock jitter approximation 2 3 nC1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom --------------------- C 1 t min n () nt nom -------------------- - C , ? ? ?? = jn () j 1 n -------- j 2 + = 1 5 10 20 n j(n)
mc9s12h256 device user guide v01.13 84 this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. table a-15 pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 32 mhz 3d lock detector transition from acquisition to tracking mode |d trk | 34 % 1 notes : 1. % deviation from target frequency 4 d lock detection |d lock | 0 1.5 % 1 5 d un-lock detection |d unl | 0.5 2.5 % 1 6d lock detector transition from tracking to acquisition mode |d unt | 68 % 1 7c pllon total stabilization delay (auto mode) 2 2. f ref = 4mhz, f bus = 16mhz equivalent f vco = 32mhz: refdv = #$03, synr = #$0f, cs = 4.7nf, cp = 470pf, rs = 10k w . t stab 0.5 ms 8d pllon acquisition mode stabilization delay 2 t acq 0.3 ms 9d pllon tracking mode stabilization delay 2 t al 0.2 ms 10 d fitting parameter vco loop gain k 1 C120 mhz/v 11 d fitting parameter vco loop frequency f 1 75 mhz 12 d charge pump current acquisition mode | i ch | 38.5 m a 13 d charge pump current tracking mode | i ch | 3.5 m a 14 c jitter ?t parameter 1 2 j 1 1.1 % 15 c jitter ?t parameter 2 2 j 2 0.13 %
mc9s12h256 device user guide v01.13 85 a.5 mscan table a-16 mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wake-up dominant pulse ?ltered t wup 2 m s 2 p mscan wake-up dominant pulse pass t wup 5 m s
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mc9s12h256 device user guide v01.13 87 a.6 spi a.6.1 master mode figure a-5 and figure a-6 illustrate the master mode timing. timing values are shown in table a-17 . figure a-5 spi master timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 10 4 4 2 9 (cpol = 0) (cpol = 1) 3 11 12 1. if configured as output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
mc9s12h256 device user guide v01.13 88 figure a-6 spi master timing (cpha =1) table a-17 spi master mode timing characteristics 1 notes : 1. the numbers 7, 8 in the column labeled num are missing. this has been done on purpose to be consistent between the master and the slave timing shown in table a-18 . conditions are shown in table a-4 unless otherwise noted, c load = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1p sck period t sck = 1./f op t sck 4 2048 t bus 2 d enable lead time t lead 1 / 2 t sck 3 d enable lag time t lag 1 / 2 t sck 4 d clock (sck) high or low time t wsck t bus - 30 1024 t bus ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 0ns 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 11 12 10 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 11 3 1. if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
mc9s12h256 device user guide v01.13 89 a.6.2 slave mode figure a-7 and figure a-8 illustrate the slave mode timing. timing values are shown in table a-18 . figure a-7 spi slave timing (cpha = 0) figure a-8 spi slave timing (cpha =1) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 10 4 4 2 7 (cpol = 0) (cpol = 1) 3 12 slave 12 11 10 11 8 sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 11 12 10 (cpol = 0) (cpol = 1) ss (input) 2 12 11 3 slave 7 8
mc9s12h256 device user guide v01.13 90 table a-18 spi slave mode timing characteristics conditions are shown in table a-4 unless otherwise noted, cload = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1p sck period t sck = 1./f op t sck 4 2048 t bus 2 d enable lead time t lead 1 t cyc 3 d enable lag time t lag 1 t cyc 4 d clock (sck) high or low time t wsck t cyc - 30 ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 25 ns 7 d slave access time t a 1 t cyc 8 d slave miso disable time t dis 1 t cyc 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns
mc9s12h256 device user guide v01.13 91 a.7 lcd_32f4b table a.7-19 lcd_32f4b driver electrical characteristics characteristic symbol min. typ. max. unit lcd supply voltage vlcd -0.25 - vddx + 0.25 v lcd output impedance(bp[3:0],fp[31:0]) for outputs to charge to higher voltage level or to gnd 1 notes : 1. outputs measured one at a time, low impedance voltage source connected to the vlcd pin. z bp/fp - - 5.0 kohm lcd output current (bp[3:0],fp[31:0]) for outputs to discharge to lower voltage level except gnd 2 2. outputs measured one at a time, low impedance voltage source connected to the vlcd pin. i bp/fp 50 - - ua
mc9s12h256 device user guide v01.13 92
mc9s12h256 device user guide v01.13 93 a.8 external bus timing a timing diagram of the external multiplexed-bus is illustrated in figure a-9 with the actual timing values shown on table table a-20 . all major bus signals are included in the diagram. while both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. a.8.1 general muxed bus timing the expanded bus timings are highly dependent on the load conditions. the timing parameters shown assume a balanced load across all outputs.
mc9s12h256 device user guide v01.13 94 figure a-9 general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 ecs 21 20 22 23 non-multiplexed 17 19 lstrb 29 no a cc 32 ipipo0 ipipo1, pe6,5 35 18 27 28 30 33 36 31 34 r/ w 24 26 25 addresses pe4 pa, pb pa, pb pk5:0 pk7 pe2 pe3 pe7
mc9s12h256 device user guide v01.13 95 table a-20 expanded bus timing characteristics conditions are shown in table a-4 unless otherwise noted, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 16.0 mhz 2 p cycle time t cyc 62.5 ns 3 d pulse width, e low pw el 30 ns 4d pulse width, e high 1 pw eh 30 ns 5 d address delay time t ad 8ns 6d address valid time to e rise (pw el Ct ad )t av 22 ns 7 d muxed address hold time t mah 2ns 8 d address hold to data valid t ahds 7ns 9 d data hold to address t dha 2ns 10 d read data setup time t dsr 24 ns 11 d read data hold time t dhr 0ns 12 d write data delay time t ddw 7ns 13 d write data hold time t dhw 2ns 14 d write data setup time 1 (pw eh Ct ddw ) t dsw 23 ns 15 d address access time 1 (t cyc Ct ad Ct dsr ) t acca 30 ns 16 d e high access time 1 (pw eh Ct dsr ) t acce 6ns 17 d non-multiplexed address delay time t nad 6ns 18 d non-muxed address valid to e rise (pw el Ct nad )t nav 26 ns 19 d non-multiplexed address hold time t nah 2ns 20 d chip select delay time t csd 6 + t cyc /4 ns 21 d chip select access time 1 (t cyc Ct csd Ct dsr ) t accs t cyc /4 C 2 ns 22 d chip select hold time t csh 2ns 23 d chip select negated time t csn 8ns 24 d read/write delay time t rwd 7ns 25 d read/write valid time to e rise (pw el Ct rwd )t rwv 25 ns 26 d read/write hold time t rwh 2ns 27 d low strobe delay time t lsd 7ns 28 d low strobe valid time to e rise (pw el Ct lsd )t lsv 25 ns 29 d low strobe hold time t lsh 2ns 30 d noacc strobe delay time t nod 7ns 31 d noacc valid time to e rise (pw el Ct nod )t nov 25 ns
mc9s12h256 device user guide v01.13 96 32 d noacc hold time t noh 2ns 33 d ipipo[1:0] delay time t p0d 27ns 34 d ipipo[1:0] valid time to e rise (pw el Ct p0d )t p0v 22 ns 35 d ipipo[1:0] delay time 1 (pw eh Ct p1v ) t p1d 225ns 36 d ipipo[1:0] valid time to e fall t p1v 22 ns notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. table a-20 expanded bus timing characteristics conditions are shown in table a-4 unless otherwise noted, c load = 50pf num c rating symbol min typ max unit
mc9s12h256 device user guide v01.13 97 appendix b package information b.1 general this section provides the physical dimensions of the mc9s12h256 packages.
mc9s12h256 device user guide v01.13 98 b.2 112-pin lqfp package figure b-1 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 q q q q 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 q 2 q 0.050 seating plane gage plane 1 q q view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0
mc9s12h256 device user guide v01.13 99 b.3 144-pin lqfp package figure b-2 144-pin lqfp mechanical dimensions (case no. 918-03) n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 q view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m t l-m q dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 q 0 q 07 q 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35. case 918-03 issue c 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 q 0.25 view ab n 0.20 t l-m m l n 2 q t t 144x x x=l, m or n
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mc9s12h256 device user guide v01.13 101 user guide end sheet
mc9s12h256 device user guide v01.13 102 final page of 102 pages

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