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sharc ? processor adsp-21371 high performan c e 32 -bit/40- bit fl oating point pr oce ssor optimized for high performan c e audio processing single- i nstru c tion, multiple-da t a (simd) compu t a t ional on-chip memory1m bit of on-chip sram and a dedi cated cod e compatibl e with all other m e m b ers of the sha r c fa m il y the ad sp- 21371 is ava i labl e with a 266 mh z core i n stru ction rate with unique aud iocentric peripheral s such as the di gi- tal applications interface, serial ports, precision clock ge n e rators, and more. for comple te ordering information , 24 11 32 sd r a m c o nt ro l l e r 3 7 as y n chr o no us me m o r y in t e r f a c e c o n t r o l p i n s ad d re s s da t a co nt ro l e x te rna l p o rt fl a g s 4- 1 5 sp i p o r t ( 2 ) ti m e r s ( 2 ) ua r t ( 1 ) d p i i i r o u t n g u n t d i g i ta l p e r i p he r al i nt e rf a ce gp i o f l a gs / ir q /t im e x p 4 s e ri al p o r t s ( 8 ) in p u t d a t a p o r t / pd a p d g n t u o r i a i u n i t di g i t a l ap p li ca ti o ns i n t e rf a ce io d ( 3 2 ) a d dr da t a io a ( 2 4 ) 4b l o c k s o f o n- chi p m e m o ry 1m b i t r a m , 4 m b i t r o m pm d a t a b u s d m da t a bu s 32 p m ad dr e s s b us d m ad dr e s s b us 64 px r e g i s t e r pr o c e ss i n g e l em en t (p e y ) pr oc e s s i n g el em e n t (p e x ) ti m e r s in s t r u c t io n ca c he 32 48 - b i t da g 1 8 4 32 c o r e pr o c e ssor pr o g r a m se q u e n c er d m a c on t r ol l e r ( 3 0 c h a n n el s) me mo ry - t o - m e m o r y dm a ( 2 ) s io p r e g is t e r ( m e m o r y m a p p e d ) c o n t ro l , s t at u s , & da t a b uf f e rs j t ag te s t & e m u la ti o n dag 2 8 4 32 i / o pr o c esso r da i p i n s dp i p i ns 64 32 14 20 pr e c i s i o n c l o c k g e ne rat o r s ( 4 ) tw o w i r e in t e r f a c e 32 64 pw m s/ pd i f ( r x / t x) summar y architecture 4m bi t of on-ch ip mask-programmable rom see ordering guide on page 48 . figure 1. funct i on al bl oc k dia g ra m sharc and the s h a r c logo are registere d trademarks of ana lo g devices, i n c . rev. 0 in fo rmatio n furn ish e d by an alo g d e v i ces is beli ev ed t o be ac curate and reli able. ho wever, no r es p on si bil i ty is assumed b y analo g dev i ces for i t s use, n o r fo r any in frin gement s of pat e nt s or ot her ri ght s of t h i r d p a rt ies t h at m a y resul t from i t s use. speci f ic a t ion s subject t o ch ange wit h out no t i ce . n o l i ce n s e is gr a n te d by im p l ic a t io n or otherwise un der any pat en t or p a t en t ri g h ts of analog devices. tr ademarks an d regist ere d t r ademarks are t h e p r o p er ty of th e i r respect i v e co mpan ies. o ne tec hnology way, p. o. bo x 9106 , n o rwood , ma 02 062 -910 6 u. s. a. tel : 7 81. 329 .4 700 ? 2007 an a l og devices, inc. all rights reserved. www .analo g . com fax: 7 81. 326 .31 1 3
adsp-21371
ke y f e a t u r e s p r oc essor c o re at 26 6 mhz (3 .75 ns) core instruction ra te, the adsp- 21371 performs 1.596 gflops/53 3 mma cs 1m bi t on-chip, sram for simulta n e ous a c cess by the core processor and dm a 4m bi t on-chip, mask-programmable rom dual data address generato rs (dags ) wi th mo dul o and bit- reverse addressing zero -ov erhead lo op ing with sing le-c y c le l oop setu p, p r ov id- ing e fficient program sequencing sin g le in s t ruction multiple data (sim d) architecture pro v ide s : two computation a l processing ele m ents concurrent execution code compatibility with othe r shar c family m e mbers at the assembly le vel parallel ism in buses and com p utational units a llows: sing le cycle execut i o ns (with or without si md) of a mul- tipl y operation, an alu oper ation, a dual memory read or write, and an instruct i o n fetch transfers betwee n m e m o ry and core at a sustained 4.25g byte s/second bandwidth at 266 mhz core instruc- tion rate inp u t/o u tput f e atur es dma control l er supports: 32 d m a channels for transfers between adsp-2 1371 inter- nal memory and a variety of periph e r a l s 32-bit dma transf ers at peripheral clock spe ed, in parallel wi th full- speed processor execution 32-bit wide ex ternal port provide s gl ueless con n ection to both synch r on ous (sdr am ) and asyn chronous memory dev i ces programm a b le w a i t state op tions: 2 to 31 sdclk cycles delay-line dm a engine m a i n tains circular buffe r s in exter- nal memory with tap/offset base d reads sdram accesses at 133 mhz and asy n chronou s accesses at 44.4 mhz 4 memory select lines a llows multiple extern a l memory dev i ces digital au dio interface (dai) incl udes eight s erial ports, four precision clock generators, an input data port, an s/pdif transceiver, and a signal routing unit digital peripheral interface (dpi) includes, tw o timers, one uart, and tw o spi ports, and a 2-wire interface port ou tputs of pc gs a a n d b can be ro uted thro ugh dai pins ou tputs o f pc g's c and d can be drive n on to da i as well as dpi pins eight dual data line serial ports that operate at up to 50 mbps on each data line each has a clock, fram e sync, and two dat a l i ne s t h at c a n be co nfi g ur ed as either a rece iver or transm itter pair tdm support for telecommunications interfaces incl uding 128 t d m channel su pport for newer telephony i n terfaces such as h.10 0/h.1 10 up to 16 td m s t rea m support, each with 12 8 channels per frame com p anding selection on a per channel basis in tdm mode in put data port, configurable as eight channels of serial d ata or seven channels of serial da t a and up to a 2 0 -bit wide parallel data channel sign al routin g un it provides confi g ura b le and flexible con- nections be tween the various peripherals and the da i/dpi co mp onen ts 2 mu xed flag/ irq lines 1 mu xed flag/ irq / ms pin 1 mux e d flag/t im e r expired line / m s pin s/pd if- c om patible d igital audio receiver/transm i tt e r sup- ports eiaj cp-34 0 (cp-1 201), iec-95 8, aes/ebu s t a n d ards left-justified, i 2 s or righ t- justified serial data in put with 16-, 18-, 2 0- or 24-bit word wid t hs (transmitte r) pul s e-width modu lation prov ides: 16 pwm out p uts configured as four groups of four outputs s u pp or t s ce nt er -a l i gn ed or edge-aligned pwm wavefo rms rom based s e curity features include: jtag access to memory permitted with a 6 4 -bi t key protected m e m o ry regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of softw a re and hardware multi- plier/divide r ratios newly introduced running reset feature that allows a reset of the processor core and peripherals, but without reset- ting the pll and sdram controller, or performin g a boot du al voltage: 3.3 v i/o, 1.2 v core available in 20 8-lead mqfp pack age (see or dering guide on page 48 ) r e v . 0 | p a ge 2 of 48 | j une 2007
adsp-21371
t a ble of contents
s u m m a r y ... ..... ..... ..... ..... ..... ..... ..... ..... ...... ..... ..... ..... 1
k e y f e a t u r e s p r o c e s s o r c o r e ... ..... ..... ...... ..... ..... ..... 2
i n p u t / o u t p u t f e a t u r e s ... ..... ..... ..... ..... ...... ..... ..... ..... 2
g e n e r a l d e s c r i p t i o n .... ..... ..... ..... ..... ..... ...... ..... ..... ..... 4
adsp-2137 1 family core architecture . . ...... ..... ..... ..... 4
adsp-2137 1 memory .... ..... ..... ..... ..... ...... ..... ..... ..... 5
e x t e r n a l m e m o r y ..... ..... ..... ..... ..... ..... ...... ..... ..... ..... 5
adsp-2137 1 input/output features . ..... ...... ..... ..... ..... 7
s y s t e m d e s i g n .... ..... ..... ..... ..... ..... ..... ...... ..... ..... ... 1 0
d e v e l o p m e n t t o o l s .. ..... ..... ..... ..... ..... ...... ..... ..... ... 1 0
a d d i t i o n a l i n f o r m a t i o n .. ..... ..... ..... ..... ...... ..... ..... ... 1 1
p i n f u n c t i o n d e s c r i p t i o n s . ..... ..... ..... ..... ...... ..... ..... ... 1 2
d a t a m o d e s .. ..... ..... ..... ..... ..... ..... ..... ...... ..... ..... ... 1 4
b o o t m o d e s .. ..... ..... ..... ..... ..... ..... ..... ...... ..... ..... ... 1 4
c o r e i n s t r u c t i o n r a t e t o c l k i n r a t i o m o d e s ..... ..... ... 1 4
adsp-2137 1 specifications ..... ..... ..... ..... ...... ..... ..... ... 1 5
o p e r a t i n g c o n d i t i o n s .... ..... ..... ..... ..... ...... ..... ..... ... 1 5
e l e c t r i c a l c h a r a c t e r i s t i c s . ..... ..... ..... ..... ...... ..... ..... ... 1 5
a b s o l u t e m a x i m u m r a t i n g s . ..... ..... ..... ...... ..... ..... ... 1 6
m a x i m u m p o w e r d i s s i p a t i o n .... ..... ..... ...... ..... ..... ... 1 6
p a c k a g e i n f o r m a t i o n ..... ..... ..... ..... ..... ...... ..... ..... ... 1 6
e s d s e n s i t i v i t y ... ..... ..... ..... ..... ..... ..... ...... ..... ..... ... 1 6
t i m i n g s p e c i f i c a t i o n s .... ..... ..... ..... ..... ...... ..... ..... ... 1 7
o u t p u t d r i v e c u r r e n t s ... ..... ..... ..... ..... ...... ..... ..... ... 4 4
t e s t c o n d i t i o n s .. ..... ..... ..... ..... ..... ..... ...... ..... ..... ... 4 4
c a p a c i t i v e l o a d i n g ... ..... ..... ..... ..... ..... ...... ..... ..... ... 4 4
t h e r m a l c h a r a c t e r i s t i c s . ..... ..... ..... ..... ...... ..... ..... ... 4 5
208-lead mqfp pinout ..... ..... ..... ..... ..... ...... ..... ..... ... 4 6
o u t l i n e d i m e n s i o n s .... ..... ..... ..... ..... ..... ...... ..... ..... ... 4 8
o r d e r i n g g u i d e ..... ..... ..... ..... ..... ..... ..... ...... ..... ..... ... 4 8
revision hist or y 6/07r e vision pra to rev. 0 change to tab le, adsp-21371 internal memory space . ..... 6
change to clkout/ resetout / run rst i n , p i n l i s t ... 1 2
change s in v a lues, m e m o r y r e a d b u s m a s t e r . ..... ..... ... 2 7
change s in v a lues, m e m o r y w r i t e b u s m a s t e r ..... ..... ... 2 8
change s, s / p d i f t r a n s m i t t e r .. ..... ..... ..... ...... ..... ..... ... 3 6
add diagrams fo r c a p a c i t i v e l o a d i n g . ..... ...... ..... ..... ... 4 4
r e v . 0 | p a ge 3 of 48 | j une 2007
adsp-21371
general description
the adsp-21371 sh arc proc essor is a member of the sim d sharc f a mily of dsps that feat ure analog devices' super har- vard arc h itecture. the adsp-21371 is source code compatible with the adsp-2126x, adsp-2136x , and adsp-2116x dsps as well as with first generation adsp-2106x sharc processors in sisd (single-instruction, sing le-data) mode. the adsp -21371 is a 32-bit/40-bit floating point pr ocessors o ptimized fo r high performa nce a u tomoti ve audio appli c a t i o ns wi th i t s large on- ch ip sram a n d ma sk- p ro gra mma b l e rom, m u lti p le i n terna l buses t o eli m i n ate i/o bottlenec ks , and an in nova tive di gita l applica t ion s in terface (dai). as sh ow n in th e f u ncti on al b l ock dia g r a m on page 1 , t h e adsp-2137 1 uses two computationa l units to deliver a signif i- ca nt perfo r ma nce i n crea se over the previ o us sharc processors on a ran g e of d s p algorith ms. fab r i c ate d i n a st ate - of- the -art, high speed, cmos proc ess, th e adsp-21 371 processor achieves an instruc t ion cycle time of 3.75 ns at 266 mhz. with its simd computational ha rdware, the adsp-21371 can perf orm 1.596 g f lo ps running at 266 mh z. ta ble 1 shows perf ormance benchm arks for the adsp-21371 . table 1. adsp-21371 benchmarks (at 26 6 mhz) b e nc hm ark algor i th m 10 2 4 p o i n t c o m p le x ff t (r a d ix 4 , w i th r ever sa l)
f i r f i lt er (per t ap ) 1
iir f i lt er (per biquad) 1
m a trix multiply (p ipelined)
[3 3] [3 1]
[4 4] [4 1]
divide (y/)
i n v e rse s q uar e root
speed (a t 2 66 mhz) 34 . 5 s 1. 8 8 ns 7. 5 ns 16 . 9 1 ns 30 . 0 7 ns 1 3.1 ns 2 0 .4 ns 1 assum e s two fil e s in multichanne l simd mode the adsp-21371 continues sharc s industry-leading stan- d a r d s of in te gr at io n f or dsps, comb in ing a hi gh perform a n c e 32-bi t dsp core wit h integrat ed, on-chi p syst em features. the block diagram of the adsp-2 1371 on page 1 illustrates the following archite c tura l feat ure s : ? t w o processing elements, each of w h ich compri ses an alu, multiplier, shifter, and data register file ? d at a ad dr ess gen e r a t o r s (dag1, da g2) ? p ro gram sequencer with instruction cache ? p m and dm b u ses capa ble of s u pporting four 32-bi t da ta transfers b e tw een me mory and the core at ev ery core pro- cessor cycle ? t w o progra mmab le interva l timers wit h external eve n t counter capabilities ? o n - c h i p s r a m ( 1 m b i t ) ? o n - c h i p m a s k - p r o g r ammable rom (4m bit) ? jtag test access port the block diagram of the adsp-21371 on page 1 also illustrates the following archite c tural feature s: ? d ma controller ? di g ita l applica t ion s int e rfa c e th at i n clud es four pre c ision clock generators ( p cg) , an s/pdif-compatible dig i tal audio receiv er/transmi tte r, a n input data port (idp), eigh t serial po rts, eight serial i n te rfa c es, a 20-b i t pa ra llel input port (pda p), an d a flexib le sign al routin g uni t (dai sru ) . ? d igi t al peri ph eral i n terf ace t h a t in cludes t w o t i m e rs, on e u a rt, t w o seri al per i ph era l in t e r faces (spi) , a 2- w i r e interface (twi), and a flex ible signal r o uting unit (dpi sru) . ads p -213 71 f a mily c o r e a r chite c tu r e the adsp-21371 is code compatible at the assembly level with the adsp-21 375, adsp-2136x, adsp-2126x, adsp-21160, and adsp-21161, and with the fi rst generation adsp-2106x sharc processors. the adsp -21371 shares architectural fea- tures with the adsp-2126x, adsp-21 36x, and adsp-2116x simd sharc pr ocessors, a s detai l ed i n th e follow i ng sectio ns. simd computationa l engine the adsp-21371 contains two c o mputational p r ocessing ele- men t s th at o p er at e as a si ngle- i n s tr ucti on , mult i p le-d at a (simd) e n gine. the processi ng elements are referred t o as pex an d pey a n d ea ch con tai ns an alu , m u ltipli er, shi f ter, a n d reg- ist e r file. pex is always activ e , and pey may be e n abled by sett ing the p e y e n mode bi t in the mo de1 regi ster. when th is mo de i s ena b led, th e sam e i n stru ct ion i s exe c uted i n b o t h pro- cessing ele m ents, b ut each proc essi ng ele m ent operates on di ffere nt d a t a . t h is a r ch it ecture is effici en t at e x ecut ing m a t h in ten s iv e dsp algorith ms . ent e ring simd mode also h a s a n effect on th e w a y data is trans- ferr ed between memory an d the processi ng ele m ents. when in simd mode, tw ice th e da ta b a ndw i dth i s re qui r e d to susta i n computational operation in the pr ocessing element s. because of this requirement , ent e ring simd mode also doubles the band- wi dth bet w ee n memory and the processing elements. when using the da gs t o transfer data in simd mode, t w o data values are transferred w i th each access of memory or the regist er fi le. ind e p e ndent, p a r a llel computati on units within each processing element is a set of comput ati o nal unit s. th e com p ut at io na l uni t s con s ist of an ar it hm eti c / l ogi c uni t (alu), multiplier, and shifter. th ese units p e r form all opera- tions in a single cycl e. the thre e units wi thin each proce ssing element are arranged in paralle l, ma xi mi zi ng c o mputa t i o n a l throughp ut. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode , the p a rallel alu and multiplier operations occur in bo th pr ocessin g ele- r e v . 0 | p a ge 4 of 48 | j une 2007
adsp-21371
me nts. t h e s e com p uta tio n un it s sup p ort ieee 32-bit single - pr eci s i o n floa ti ng- p oi n t , 40- b i t extend ed pr eci s i o n f l oati ng- po in t, a n d 32- b i t fi xed- poi n t d a ta for m a t s. data r e gi st e r f i l e a general-purpose d a ta register file i s con tai ne d in ea ch pro - cessing element. the regis t er fi les transfer da ta b etwe en t h e computation units and the data buses, and store inte rmediate re sults. these 1 0 -port, 32-regist er (16 pri m a ry, 16 seco nd ar y) register fil e s, combined with the adsp-2136x enhanc ed har- vard architecture, allo w unco nstr a i ne d d a ta flow betw een com p uta t ion un its a n d in terna l me mory. t h e regi sters in pex are referre d to as r 0 - r 15 an d i n pey a s s0- s 15. single- c y c le f e tch of instruc tion a n d f ou r o p er a n ds the adsp-21371 features an enhanc ed harvard architecture in wh ich t h e d a ta me mo ry (dm) bu s transfers data and the pro- gra m memo ry ( p m) b u s tr an sfer s both instructions and data (see figure 1 on page 1 ). with the adsp- 21371s sep a rate pro- gra m an d d a t a memo ry b u ses an d o n - c hi p i n st ruct i o n cach e, the processor can sim u ltaneously fetch four operand s (two over each da ta b u s) a n d on e in struction (from the ca che ) , a ll in a sin - gle cyc l e. in s t r u c t ion c a c h e the adsp-21371 includes an on-c hip instructio n cache that enable s three - bus operat io n fo r fe tchi ng a n i n st ructi o n a n d four d a t a va l u e s . th e c a ch e is s e l e ct i v eonly the instructions w h ose fetches conflict with p m bus data accesses are cached. this cache allows full speed executio n o f cor e , looped operation s such as digital f i lter multiply -accumulates, and fft butterfly processing. d a ta addres s gener a tors w i th z e ro - o v e rh ead hardw a re circular buffer sup p or t the adsp-21371s two data addr ess generators ( d ags) are used f o r ind i rect ad dressing an d i m plementing circular data buffers in hardware. circular buffers allow efficient progr a m- mi ng o f dela y li ne s a n d o the r d a ta str u ctur es re qui r ed i n d i git a l sign al proce ssin g , an d are comm only used i n d i gi tal fil t ers an d fourier transforms. the two dags of th e adsp-21371 contain sufficient registers to all o w the cr eation of up to 3 2 circular buff- ers (16 primary register se ts, 16 secondary). the dags automatically handle ad dress poin ter wrapa r oun d , red u ce ove r - h e ad , in crease perf orm a n c e, an d si mpli fy i m plem ent a t i on . circular buffers can start a n d end at any m e mory locat i on. f l exi b le instru c tion s e t the 48-bit instruction word acco mmodates a v a riety of p a rallel ope r a t ion s, for con c ise progra mm in g. for exam ple, the adsp-2137 1 can conditionally exec ute a mul t iply, an add, and a subtrac t in both processing el e m ents w h i l e branchi n g and fetch- ing up to four 32-bit values from memoryall in a single in struction. ads p -213 71 m emor y the adsp-21371 adds the following architectural features to the simd sharc family core. on- c hip me mor y the adsp-21371 contains 1 megabit of internal ram and f o ur m e gab i ts of in tern al m a sk -program ma ble rom. each block ca n b e conf igured for di fferent co mb in ati o n s of co de a nd da ta stor- a g e ( s ee ta ble 2 o n pa ge 6 ). e a ch memo ry blo c k suppo rts si ngle-c ycle, in depend ent a ccesses b y th e core pr ocessor an d i/ o processor. the adsp-21371 memory architecture, in combina- tion with its separate on-chip buse s, allo w tw o data transfers fr om th e core and one f r om the i/ o p r ocessor, in a single cycle. the adsp-21371s sram can be co nfigured as a maximum of 32k words of 32-bit data, 6 4k wo rds of 16-bit da ta, 21.3k words of 48-bit instructions (or 40-bit da t a ) , o r c o m b i n a t i o n s o f d i f f e r - ent word siz e s up to 1 mega bi t. all of the memory can b e acces sed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit float- in g-poin t storage form at is supporte d th at e f fect ively d o ub les th e amount of da ta th at ma y be stor ed on -chip. con v ersion be twee n th e 32-bi t floati ng- p oint a n d 16- b it floa ting-point for- ma t s is p e r f orm e d i n a si ngle in st ruct io n. w h i l e ea ch me mo ry b l ock can st ore com b in at i o ns o f cod e an d d a t a , accesses ar e most e f fi cient when one block st ores data using t h e d m b us for tran sfers, an d t h e oth e r block stor e s in st ruct io ns a n d da ta usin g the pm bus for transfers. using the dm bus and pm buse s, wit h one b u s dedica ted to a memory block, assures single-c ycle execut ion wi th t w o data transfers. in this ca se, the instruc t ion must be ava i la ble in th e cache. ex ternal memor y the external port on the ad sp-21371 sharc provides a high pe rfo r ma nc e, gl ue l e s s in t e r f ac e t o a wid e variety of in dustry - stan da rd memo ry d e vi ces. the 32- bit w i d e bus m a y be used to interface to synchronous and/ or asy n ch ro no us me mo ry de vices through the use of its separate intern al memor y co ntrollers: the first is an sdram con t roller f o r co nn ec tion of ind u stry-stan - da r d sy nch r o n ous dr am de vices a n d dimms (dua l i n li ne m emo ry m o d u le), wh ile t h e seco n d is a n a s yn chro no us me mo ry con t roller intend ed to in terf ace to a vari ety of memo ry d e vi ces. f o ur me mo ry sele ct pin s ena b le up to four sepa ra te devi ce s to coexist, supporting any de sire d com b in at ion of syn c hron ous and async h ro nous device types. non sdram extern al memo ry address space is shown in ta ble 3 . ex terna l memor y ex ecution in the adsp-21371, the program sequencer can execute code d i rectly f r om exter n al memory bank 0 (sram, sdram). this allow s a reducti o n in in terna l me mo ry siz e, th ereby reduci ng the di e area. wi th e x te rnal e x ec ution , pro g rams run at slower speeds since 48-bit instructions are fetched in parts from a 32- bi t externa l bus coupled w i th the inherent lat e ncy of fetch i ng in struction s from sd ram. fetch i ng i n st ructi o ns from externa l memory generally takes 1.5 pe ripheral cloc k cycles p e r in struction . r e v . 0 | p a ge 5 of 48 | j une 2007
adsp-21371
table 2. adsp-21371 internal memory space iop regist e r s 0x0000 0000C0x00 03 f fff l o ng w o r d ( 64 bit s ) ex t ended p r ecisi on norm al or instruc t ion w o rd (48 bi ts) n ormal w o rd (32 bits) s hor t w o r d (16 bit s ) bl ock 0 rom 0x00 04 000 0C 0x00 04 7ff f bl ock 0 rom 0x0 008 00 00 C0x0 008 a a a 9 bl ock 0 rom 0 x 000 8 0 00 0C0 x00 08 f fff bl ock 0 rom 0x0 010 00 00 C0x0 011 ff ff reser v ed 0x00 04 800 0C 0x00 04 bfff r e se r ved 0x0 008 aa a a C 0x00 08 fff f re ser v ed 0 x 000 9 0 00 0C0 x00 09 7 fff r e se r ved 0x0 012 00 00 C0x0 012 ff ff bl ock 0 ram 0x00 04 c00 0C 0x00 04 cff f bl ock 0 ra m 0x0 009 00 00 C0x0 009 15 54 bl ock 0 ram 0 x 000 9 8 00 0C0 x00 09 9 fff bl ock 0 ra m 0x0 013 00 00 C0x0 013 3f ff reser v ed 0x00 04 d00 0 C 0 x00 0 4 fff f r e se r ved 0x0 009 15 55 C0x0 009 ff ff re ser v ed 0 x 000 9 a 00 0C 0x00 09 fff f r e se r ved 0x0 013 40 00 C0x0 013 ff ff bl ock 1 rom 0x00 05 000 0C 0x00 05 7ff f bl ock 1 rom 0x0 00 a 0 000 C0 x0 00 a a a a 9 bl ock 1 rom 0 x 000 a 000 0C 0x00 0a fff f bl ock 1 rom 0x0 014 00 00 C0x0 015 ff ff reser v ed 0x00 05 800 0C 0x00 05 bfff r e se r ved 0x0 0 0 a a a a a C 0x0 00a ff ff re ser v ed 0 x 000 b 00 00 C0x0 00 b 7ff f r e se r ved 0x0 016 00 00 C0x0 016 ff ff bl ock 1 ram 0x00 05 c00 0C 0x00 05 cff f bl ock 1 ra m 0x0 00b 000 0C 0x00 0b 1 554 bl ock 1 ram 0 x 000 b 80 00 C0x0 00 b 9ff f bl ock 1 ra m 0x0 017 00 00 C0x0 017 3f ff reser v ed 0x00 05 d00 0 C 0 x00 0 5 fff f r e se r ved 0x0 00b 155 5C 0x000 b ff ff re ser v ed 0 x 000 b a 000 C0 x000 b ff ff r e se r ved 0x0 017 40 00 C0x0 017 ff ff bl ock 2 ram 0x00 06 000 0C 0x00 06 0ff f bl ock 2 ra m 0x0 00c 00 00 C0x0 00c 15 54 bl ock 2 ram 0x 00 0c 00 0 0C 0x 00 0c 1 f f f bl ock 2 ra m 0x0 018 00 00 C0x0 01b 3ff f reser v ed 0x00 06 100 0C 0x00 06 fff f r e se r ved 0x0 00c 15 55 C0x0 00d ff ff re ser v ed 0x0 0 0 c 20 00 C 0 x0 0 0 d ff f f r e se r ved 0x0 018 40 00 C0x0 01b fff f bl ock 3 ram 0x00 07 000 0C 0x00 07 0ff f bl ock 3 ra m 0x0 00e 00 00 C0x0 00 e 1 554 bl ock 3 ram 0 x 000 e 000 0C 0x00 0e 1ff f bl ock 3 ra m 0x0 01c 00 00 C0x0 01c 3f ff reser v ed 0x00 07 100 0C 0x00 07 fff f r e se r ved 0x0 00e 15 55 C0x0 00 f ff ff re ser v ed 0 x 000 e 200 0C 0x00 0f f fff r e se r ved 0x0 01c 40 00 C0x0 01f fff f r e v . 0 | p a ge 6 of 48 | j une 2007
adsp-21371
sdr a m co ntroller th e sdra m co n t r o lle r p r ov ide s an i n t e rf a c e to up to f o ur sep a - ra te b a n k s o f i n d u str y -sta nd ar d sdr am de vices o r dimms. full y compliant with the sd ram stan da rd , ea ch ba nk can h a s its o w n me mo ry sele ct lin e (ms0 Cms3 ), an d ca n be con f i g ured to contain between 16m byte s and 128m bytes of memory. sdra m e x ternal memory address space is shown in ta ble 4 . the controller maintains all of th e ba nk s as a cont iguous address space so that the processo r se es this as a single address space, e ven i f different siz e device s are used i n t h e different ba nk s. a set of pr ogramm able timin g par a me ters is a vai lab l e to confi g - ur e t h e sdr a m b a n k s t o s u ppo rt slower memory devices. the me mo ry ba nk s can be co nfigured as 16 bits wide or as 32 bits wi de. th e sdr am con tr o lle r a d d r ess, da ta , clo c k , an d co mm an d pin s can drive loads up to 30 p f . fo r large r memory syste m s, the sdram contr o ller external buffer timing should be sele cted an d exte rn al b u fferin g should be prov ided so th at th e load on the sdram controller pins does not exceed 30 pf. table 3. externa l memor y for non sdram addresses ban k si ze i n w o rds a dd r e s s r a nge bank 0 1 4m 0 x 00 20 000 0 C 0x00 ff ffff bank 1 1 6m 0 x 04 00 000 0 C 0x04 ff ffff bank 2 1 6m 0 x 08 00 000 0 C 0x08 ff ffff bank 3 1 6m 0 x 0c 00 0 0 0 0 C 0x0c ff f fff table 4. extern al mem o ry for sd ra m ad dres ses ban k si ze i n w o rds a dd r e s s r a nge bank 0 6 2m 0 x 00 20 000 0 C 0x03 ff ffff bank 1 6 4m 0 x 04 00 000 0 C 0x07 ff ffff bank 2 6 4m 0 x 08 00 000 0 C 0x0bf f f fff bank 3 6 4m 0 x 0c 00 0 0 0 0 C 0x0f ff f fff n ot e th at t h e ex tern al m e mor y b a n k ad dresses sho w n ar e for normal word accesses. if 48-bit in str u ct ion s a re place d in an y such ba nk (wit h tw o i n structi o ns pack ed i n to th re e 32-bi t loca - tions), t h en care must be ta ke n to ma p da ta b u ffe r s i n th e same ba nk . for exa m ple , if 2k in struct ions are placed starti ng at the bank 0 base address ( 0x0020 0000 ), then the data buffers can be placed starti ng a t an ad dress th at is offset by 3k words (0 x0020 0c00) . asy n ch ro no us con t ro ller the as ynchronous memory contro ller provides a configurable interface for up to four sepa rate banks of memory or i/o de vices. ea ch ba nk can b e in de pend en tly pr o g ra mm ed wit h di f- fer e nt tim in g par a met e rs , ena bli ng co nn ecti on to a wid e va r iety of memory devices including sr a m, rom, fla s h, an d eprom, as w ell as i/ o dev i ces th at int erfa c e wi th st an da rd mem o ry con- trol lines. bank 0 occupies a 14. 7m word window and banks 1, 2, and 3 occupy a 16m word window in the processors address space b u t, if not fully popula ted, th ese wi ndow s are not made contiguous by the memory contro ller logic. the banks can also be conf igured as 8-bit or 16-bit wide buses for ease of interfac- i n g to a ra nge of memo ri es a n d i/o devi ces ta ilore d ei the r to h i gh perfor mance or to low cost and power. the asy n chron o us memory con t r o ller is c a pable of a m a ximum throughp ut of 176 mbps using a 44 mhz external bus speed. other features include 8 to 3 2-b it and 16 to 32 -bit packing and unp a cking, booting fr om bank select 1, an d suppo rt fo r dela y line dma. ads p -213 71 input/ output f ea t ur es the adsp-21371 i/o proces sor prov ides 32 channels of dma, a s w e ll as an ext e nsi v e set of pe ripherals. these include a 20 le ad di git a l appli c ati o n s in terface, w h ich con t rol s : ? ei g ht seri al po rt s ? s /pd i f recei ver/tra nsm i tt er ? f our pr ecisi o n clock gene ra to rs ? i nput dat a po rt /par alle l da ta a c qui s iti o n po rt the adsp-21371 processor also c o ntains a 14 lead digital peripher al interface, whic h co ntrols: ? t wo gene ra l-p u r p o s e t im e rs ? t wo serial peripheral in ter fac es ? o n e u n i v e r s a l a s y n c h r o n o u s receiver/transmitter (uart ) ? a n i 2 c ? -compa tib le 2-wi re interface dma contro ller the adsp-21371s on-c hip dma c o ntroller allows data trans- fers without pro cesso r interventio n . t h e dma con t r o ller operates i n dependently and i n vi sibly to the processor c o re, allowing d m a ope r ations to oc cur w h i le the core i s simulta- neously executing i t s program in struc t ions. d m a transfers can occ ur between the adsp-21371s inte rnal memory and its serial ports , t h e spi-compati b le (serial peripheral interface) por t s, the idp (i np ut da ta p o rt), th e pa rallel da ta a c qui s iti o n por t (pdap) or t h e u a rt . t h i rt y - t wo ch an nels of dma a re avai la ble on t h e adsp-21371, 1 6 via the serial po rts, eight via the inp ut data port, t w o for the uar t , tw o for t h e spi i n te rfa c e , two for th e external por t , an d two for memory -to-memory tran sfers. pro - grams can be downloaded to the adsp-21371 using dma transfers. other dma featur es in clude interrupt generatio n upon com pletion of dma transfers, and dma chain i n g for a u to ma ti c li nk e d d m a tr an sfe rs. de la y l i ne d m a the adsp-21371 processor provides delay line dma function- ality. this allows p r ocessor read s an d w r i t es t o ex te r na l de l ay li ne b u ffers (a nd hen ce to exte r n a l memo ry ) w i th li m i ted co re in tera ct ion. r e v . 0 | p a ge 7 of 48 | j une 2007
adsp-21371
digita l a p plic ations inter f ac e (d ai) th e d i git a l appli c ati o n s in terface (dai) prov id es the abi l ity to conne c t various periph erals to any of th e dsp dai pi ns (dai_p20C1). p r o g ra ms m ak e th e s e co nn ec ti on s using the sig n al routing unit (s ru), shown in fi gure 1 . th e sru i s a m a trix rout in g un it (or g r oup of m u ltiplexers) tha t enables the per i pherals provided by th e d a i t o be i n t e rcon - ne ct ed un de r so ftwa r e con tr o l. t h is allows easy use of the dai associated peri pherals for a much wi der vari ety of appli c ati o ns by usin g a larger set of algorith ms t h an is possib le wi th n o n c on- figurable signal paths. the dai also includes ei ght se ri al p o rt s, fo ur p r e c i s io n clo c k gen era to r s (pcg ), a n d an in put da ta p o rt (id p ). t h e id p p r o - vides a n additi onal i n put pat h to th e adsp- 21371 core, con f igurab le as ei th er eight channels of i 2 s serial data, or a sin- gle 20-bi t wi de sy nch r o n ous pa ra llel da ta a c quisit io n po rt . ea ch da ta ch an nel h a s i ts o w n d m a cha n n el th at i s ind epen d e n t from the adsp-21371 s serial ports. se ri a l p o r t s the adsp-21371 features eight sy nchronous serial ports that provi d e an i n expensive int e rface to a wi de varie t y of di gital and m i x e d - si gn al pe ri ph er al d e vi ce s s u ch a s a n a l og d e vi ce s ad183x family of audio codecs , adcs, and dacs. the serial ports are m a d e up of t w o d a ta li nes, a clock, an d fra m e syn c . t h e da ta li ne s ca n b e pro g r a m m e d to eit h er tr an sm it o r r ecei ve a n d each da ta li ne h a s a ded i ca ted dma cha n n el. serial ports are enab led via ei gh t pr ogrammable pins and simul- taneous receiv e or transmit pins th at support up t o 16 transmi t or 16 r eceiv e chan n els of a u di o d a ta wh en a ll fo ur sport s ar e enabled, or four full duplex tdm streams of 128 c h annels per fr ame. t h e serial po rts operate at a ma xim u m d a ta ra te o f 50 mb ps. serial port d a ta can be automa ti cally transfe r red to and from on -ch i p me mo r y vi a d edi cate d dma ch an ne ls. ea ch o f the serial p o rts can work in co nj unct ion with another serial po rt to pr ovide tdm suppor t . one sport provides two transmit sig- na ls wh ile th e othe r spor t prov ides the two receiv e signals. th e fram e syn c an d clock are sh ared . serial ports op er ate in five mod e s: ? s ta nda rd dsp ser i a l mo de ? m u l t i c h a n n e l ( t d m ) mode with support for packed i 2 s mo d e ? i 2 s mode ? p a c k e d i 2 s mode ? l eft-justified sample pair mode left-justified sample pair mo de is a mode whe r e i n each frame sync cycle two samples of data are transmitte d/ rece ived o ne sample on the high segment of t h e frame sync, the ot her on the l o w s e gme n t o f t h e fr am e s ync. pr ogra ms h a ve co nt rol o v er v a r- ious attributes of this mode. each of the serial p o rts supports the le f t -jus tifie d sample pair an d i 2 s pr ot oco l s ( i 2 s i s an i n d u stry -sta nd ard i n te rfa c e com - mo nly used b y a u di o co decs, adcs, a n d dacs such as the analog devices ad183x family), with two data pins, allowing fo ur left-justified sample pair or i 2 s channels (using two ste r e o d e vices) per serial po rt, with a maximum of up to 32 i 2 s chan- n e ls. t h e serial po rts permit li ttle- endian or b i g- endian transmission formats an d word le ngths selectable from 3 bits to 32 bit s. for the left-justifi ed sa mple pa ir and i 2 s modes, data- word lengths are selectable betw een 8 bits and 32 bits. serial ports offer selectable synchron iz ati o n an d tra n sm it m o d es a s well as op tion al -law or a-law c o mpanding selection on a p e r channel basis. se rial port cloc k s an d fr am e syncs can be i n t e r- nally or externally ge nerated. the serial ports also contain fr ame sync error det e ction logi c where the serial ports de tect fram e syncs that arriv e early (for example frame syncs that arrive whi le the transmi ssion/ r e c ep- tion of the previous word is occu rring). all the se rial ports also share o n e ded i cated erro r interrupt. s/p d if- c ompatible digital audio r e c e iv er/t r a nsmitt er the s/ pdif recei v er/t ransmit t er has no separate dma chan- ne ls. it re ceive s aud i o d a t a i n serial forma t and conv erts i t i n to a bi pha s e encoded si gna l . th e seria l da ta i n put to th e receiver/transmitter ca n be formatted as left justif ied, i 2 s or righ t just ified wi th w o rd w i d t hs of 16, 1 8, 20, or 24 bits. t h e seri al da ta , clock , an d fra m e sy nc i n p u ts t o th e s/pd if receiver/transmitter ar e routed th rough the sign al routing un it (sru). they can co me fr om a va riety of sourc e s such as the sports, external pins, the pr ec ision clock gen e rato rs (pcgs), an d a r e con tr o lle d by th e sru co nt ro l r egist er s. d i gi ta l p e ri phe r al int e r f ac e (d pi) the digital peripheral interfac e provides con n ections to two serial peripher al in terf ace por t s (spi), one univer sal asynchr o - n o us receiver-transmitter (uart) , 12 flags, a 2-wire interface (t wi), and two general-pur p ose timers. ser i al p e riph er al ( c ompatible ) int e r f ac e the adsp-21371 sharc processor co ntains two serial periph- eral inte rface ports (spis). the spi is an indust ry-st a ndard synchronous serial link, enab ling the adsp-21371 spi-compat- ib le port t o comm uni c ate w i t h othe r spi compat ibl e dev i ces. th e spi co nsi s ts of tw o da ta pi ns, one d e vi ce select pi n, a n d on e cloc k pin. it is a full-duplex synchronous serial interface, sup- por t ing both master and slave modes. the spi p o rt can ope r ate in a multimast e r env i ronme n t b y i n te rfa c i n g w i th up t o four othe r spi- com p ati b le d evi ce s, eit h er acti ng a s a m a ste r or slave device. the adsp-21 371 spi-comp atible peripheral implemen- t a t i on also f e a t ures pro g ram m a b le b a ud ra t e an d clo c k ph ase and p o larities. the adsp-21371 spi- compatibl e port uses open d rai n dri v er s to suppor t a m u lt im aster configura t ion a n d to a v o i d da ta co ntenti on. r e v . 0 | p a ge 8 of 48 | j une 2007
adsp-21371
ua r t p o r t the adsp-21371 p r ocessor provid es a full-duplex universal asyn chr o no us recei v er /t ra nsmi tter (u art) port, w h i c h is fully compatible with pc-sta nd ar d u art s. th e ua rt po r t pr ov id e s a si mpli fi ed u a rt in te rf ace to o t her peripher als o r hosts, supporting full-duplex, dma-suppo rted , asy n chro nous transfers of se rial data. the ua rt also has multiprocessor com- munica tion capab i li ty using 9-bi t ad dress detection . th is allo ws it to be used in multidrop networks th rough the rs-485 data interface stan dard. t h e uart port also includes support for 5 to 8 d a t a bi ts, 1 or 2 stop bi ts, a n d none, even, or odd parity. the ua rt port supports two modes of operation: ? pio (programmed i/o) C the proc e ssor sends or re ceive s da ta b y w r i tin g or read in g i/o-mapp ed uart registers. t h e da ta i s d o uble- b uffered o n b o th tr an smi t a n d recei v e. ? d ma (d irect memory ac cess) C the dma con t roller trans- fers b o th tran smi t an d r e c e i v e da ta . th is r e duces the number and frequency of interr upt s requi r e d to transfer d a ta to an d f r om memo ry. t h e u a rt ha s two dedi ca ted d m a ch a nn e l s , on e fo r tr an s m i t a nd o ne for r e ce i v e. th e s e dma ch annels h a ve lowe r default priority tha n mos t dma channels because of their re lativ e ly low se rv ice rate s. t h e uart port's baud rate, ser i al data fo rmat, error cod e gen - erati o n an d st atus, a n d in terrupt s are program m a b le: ? s uppo rtin g bit rates r a n g in g fro m ( f pc l k / 1,048,576) to
(f pc l k /16) bits per second.
? s upporti n g data forma t s from 7 to 12 bi ts per fra m e . ? b o t h t ran smi t an d r e c e i v e oper at io ns ca n be co n f i g ur ed to generate mask ab le interrupt s to the processor. in co nj uncti o n wi th t h e gen er a l- purpo s e ti mer funct i o n s, a u to - b a ud detectio n i s suppor t ed . ti m e r s the adsp-21371 has a total of thre e timers: a core timer that can gene ra te p er i o d ic sof t war e i n te rr up ts a n d t wo gene ra l p u r- pose timers tha t can genera te periodic interrupts and be in depe nd ent l y set to o p er at e in one of t h ree modes: ? pulse waveform generatio n mode ? pulse width count/capture mode ? e xt ernal e v ent watchdog mode the core timer can be configur ed t o use fla g 3 as a t i me r ex pir ed si gna l , an d ea ch gen er a l-pur pose tim e r h a s on e bidirec- tion al pin an d four regi sters that implement its mode of o p er at i o n: a 6-b i t con f igur at i o n regi ster, a 32-bi t count re giste r , a 32-bit period register, and a 32- bi t pulse wi dt h regist er. a sin- gle co ntr o l an d sta tus r egist er e n a b les or dis a ble s both gen e ral- p u rp o s e ti me rs i n d e p e n d en tly . 2- w i re int e r f ac e p or t ( t wi) th e tw i is a bid i r e c t i o n a l 2-wir e , serial bus used to mov e 8-bit da ta whi l e ma inta ini n g compli ance wi th th e i 2 c bus proto c ol. the twi mast er i n corporat es t h e f ol l ow i n g fe at ur es : ? 7 - b i t ad dr essi ng ? simultaneous maste r and slave operation on multip le
device syste m s with sup por t fo r multi ma ster da ta
arbi trat ion
? di g ital filteri n g and t i med ev ent processi ng ? 100 kbp s and 400 kbps data rates ? low interrupt rate pu lse - w id t h mo dula t ion the pwm module is a f le x ible , programmable, pwm waveform generator that can be progr a mm ed t o ge nerat e the re qui r ed switchin g patterns f o r various appl i c ati o ns relate d to motor and engi ne con t r o l or a u di o pow e r con t r o l. the pwm genera tor ca n generate either cent er-ali gne d or edge-aligned pwm wave- forms. in addition, it can gene ra te co mplemen t a r y sign als o n two outputs in pa ir ed mo de or in depend ent si gn als in non - pair ed mode (applic able to a single group of four pwm wa veform s). t h e e n t i r e p w m m o d u l e h a s f o u r g r o u p s o f f o u r p w m o u t p u t s each. therefore , thi s module gene ra tes 16 pwm output s in total. e a ch pwm gr oup pr oduces two pair s of pw m sign als o n th e four pwm output s. the pwm generator i s capab le of operat ing i n tw o dist inct mo des wh ile gen e ra ti ng center- a li gned pwm w a vefor m s: si n g le upda te m o de o r do uble upd a t e mo d e. in sing le upda te m o d e th e dut y cycle values are programmab le only once per pwm period. this result s in p w m pat t erns th at are symmetrica l a b out th e m i d- poi n t o f th e pwm per i o d . in do ub le upda te mo d e, a se c- on d upd a ti ng o f the pwm regist ers is i m plemented at the mid- point of the pwm period . in t h is mod e , i t is possi ble to pr od uce asy m met r i c al pw m pa tte rn s th at prod uce lower ha rm oni c d i s- tortion i n th ree-ph ase pwm inverters. rom base d s e curit y the adsp-21371 has a rom securi ty feature that provides hard ware suppo rt for securing user s o f t w a r e c o d e b y p r e v e n t i n g un auth or iz ed rea d i n g f r om th e internal code when enabled. when using thi s feature, t h e pr o c esso r do es not b o o t - l oa d a n y external code, executi n g exclus ive l y from int e rnal sra m /rom. addi tionally, the processor i s no t freely accessi ble vi a the jtag port. instead, a unique 64-bit ke y, which must be scanne d in through the jtag or test access port will be assigne d to each cus t om er . th e d e vi ce w i l l i g no re a w ro n g k e y. em ul at i on f e a - t u res an d ex tern al boo t mod e s ar e o n ly ava i la ble a ft e r t h e co rr ect k ey i s scan ne d. r e v . 0 | p a ge 9 of 48 | j une 2007
adsp-21371
s y stem design th e followi ng section s prov id e a n introduction to s y ste m desi gn options and p o we r supply issues. program bo oting the internal memory of th e adsp-21371 boots at system power-up from an 8- b i t ep ro m v i a t h e ex te rn a l port , a n sp i master, or an spi slave. booting is d e t e rm in e d b y t h e b oo t c on- figuratio n (bootcf g1C0) pins (see ta ble 7 o n pa ge 14 ). selectio n of th e bo ot sour ce is co nt rol l e d vi a th e sp i as ei t h e r a master or slave device , or it can i m medi at ely b e gin executing fr om rom. t h e new l y i n tro d uced runni n g re set feature a llow s a user to perform a re set of the proce ssor cor e and peripher als, but with- out re setti ng th e pll a n d sdram cont r oller, or perf o rming a bo ot. t h e f u nctionality of th e clkout/reset out /ru n - rstin pin has now be en e x te nded t o also act as t h e i n put for in iti a ti ng a runn in g rese t. for more in forma t i o n , see th e adsp-2 13 6x sh arc p r oce ssor hardware reference fo r the adsp-2136 7/8/9 process o rs. po we r s u p p l i e s the adsp-213 71 has separate p o we r supply connections for the in terna l (v dd int ), an d ext e rn al ( v dde xt ) power supplies. the internal s u ppli es must meet the 1.2 v requirement . the exte rnal supply must me et the 3.3 v requirement . all external supply pi ns m u st be co nn ected to the same power supply. t a rget boa r d jt a g em ula t or connec t or analog devices dsp t ools prod uct line of jtag emulators uses the ie ee 1149.1 jtag test acce ss port of the adsp-21371 pro- cessor to mo ni to r an d con t r o l th e ta rget b o a rd pro c esso r duri ng emulation. analog dev i ces dsp tools product line of jtag emulators p r ovides emulation at full p r ocessor spe e d, allowing inspection and mo dification of me mo ry, regis t ers, an d proce s - sor stacks. the processor's jtag i nt e rfa c e en s u re s t ha t th e emulator will not affect targe t sys t em loading or timing. f o r co mplete in formation on an alo g de v i ces sh a r c d s p to o l s pro d uct lin e of jt ag em ulat or ope r a tio n , see th e appr o- p r i a te em u lat o r ha rd wa re u s er ' s g u id e. dev e lop m ent t o ols the adsp-21371 is supported with a complete set of crossc ore ? soft ware a n d ha rd wa re d eve lopm en t tools, including analog dev i ces emulators and v i sualdsp++ ? devel- opment environment . the same em ulat or ha rd wa re tha t supports other sh arc proce ssors also fully emulates the adsp-2137 1. the vi sualdsp++ project management env i ronme n t le ts pro- gra m m er s dev elop an d de bug an a p pli c ati o n . th is env i r o n m e n t i n clud es an easy to use a ssemb ler (w hi ch is b a sed on an alge- brai c s y n t ax), an archi v er (li b raria n / l ibra ry bui l der), a lin k e r , a loader, a cycle-accura te i n st ruct ion-l evel simulator, a c/c++ co mpi l er, an d a c/ c+ + run t i m e li b rar y t h at i n clud es dsp a n d m a t h em at i c al f u nct i o n s. a k e y point for th ese tools is c/ c++ code effici ency. the compi ler ha s b een dev e lope d for effici ent tran slat ion of c/c++ cod e to dsp as semb ly. t h e sharc h a s archi tect u ra l fe atures th at impr ove the effici ency of compi led c/c++ code. t h e vi suald s p++ d ebugger ha s a n u mb er of im porta n t fe a- tures. da ta v i sua liza t i o n is enha nced by a plotti ng pack age t h at offe rs a sign ifica n t lev e l of flexib ili t y. t h i s graphi cal represen ta- ti on of user data enables t h e p r og ra mm er to q u i c kly det e rm in e the performance of an algorithm. as algorithms grow in com- plexity , th is capa bi lity can hav e in cre a sin g sign ifi c a n ce on the de sign er s de velo pmen t sch edule , in cr ea sin g pro d uct i vi ty . sta- ti stica l profilin g en ab les the pr ogrammer to nonintrusively poll th e processor as it is runn in g the progra m. t h i s feat ure, un ique to visualdsp++, enable s the so ftware d e veloper to passively ga th e r i m por t an t c ode e xe c ut io n m e tr ics w i th out i n t e rrupt i n g the real- t ime characterist ics of t h e program. essentially, the de velo per can i d e n ti fy bo tt lene cks in so ft war e quick l y a n d effi- ciently. by using the profiler , th e progr a m m er can f o cus on th ose areas i n th e program th at i m pa ct pe rforma nce a n d tak e corrective ac tion. deb u gging both c / c++ and ass emb ly prog ra ms w i th the visualdsp++ d e bugger, pr ogrammer s can : ? vi ew m i x ed c / c++ and asse mb ly co de (i nte r lea ved so urce an d obj ect i n form at ion) ? i ns ert breakpoi nt s ? s et co nd it io na l br eak p oi nt s o n re gister s, m em o r y ,
an d s t a ck s
? perform linear or statis tical profiling of progr a m executio n ? f i ll, dum p, a nd grap hi cally plot the co ntents of m e mor y ? perform source lev e l debugging ? c reate custom deb u gger wi nd ow s th e visua l dsp+ + idde lets pr ogra mm ers defi ne a n d ma na ge dsp software de velopme n t. its di alog boxes and property pages let pr ogr a m m ers co nfigur e an d ma na ge all of the sha rc dev el- opm e nt tools, inc l ud ing the co lo r sy nt ax hi gh li gh ti ng i n th e vi sualdsp++ ed itor. th is capa bili ty perm it s program m ers to: ? c on tr ol h ow th e de v e lopme n t to ols pro c e s s in puts a n d generate output s ? m a i n t a i n a on e- t o - o n e c o rr es po nd en ce wi t h t h e to ol s
co mm an d li ne sw itch es
t h e vi suald s p++ ke rn el (vdk ) i n corporat es sched u lin g an d resour ce ma na gem e nt tai l ored sp eci f ically to address the mem- o r y an d t i mi ng co nst r a i n ts o f d s p pro g r a m m i n g. t h ese ca pab i l i t i es e n ab l e en gin e er s t o de v e l op co de mo re e ffe ct iv e l y, eli m i n a t ing the nee d to sta r t from th e very begi nning, whe n d e velopi ng n e w a ppli cati o n code. t h e vdk fea t ur es in clude th re ad s, cri tica l an d uns c h ed u le d regions, semaphores, ev ent s, an d d evi ce flags. t h e v dk a l so supports pr iority-bas ed, pre- emptiv e, cooperat ive , and t i me-s lic e d scheduling approaches. i n ad di tion , the v dk w a s de sign ed t o be scalab le. if the a pplicat ion does not use a speci f ic feat ure, the suppor t co de fo r that feature is e x cluded from the target syst em. r e v . 0 | p a ge 10 of 48 | j une 2007
adsp-21371
because th e vd k i s a libr ar y , a de velo per can de ci de wh eth e r to use it or not. the v d k i s integrate d i n to th e visua ldsp++ de velopment environment, but ca n also be used vi a st a n d a r d co mm an d li ne tools. w h en th e vd k is us ed, the developme n t environment assists the dev e lop e r w ith ma ny er ro r -p r on e ta sks and assists in managing system re sources, a u toma ting th e gen- eratio n of various vdk based objects, and v i sualizing the sy st em st at e, w h en deb u ggi n g an a ppli c at i on th a t uses th e vdk. visualdsp++ component softwa re engineering (vcse) is analog devices technology f o r creating, using, and reusing soft ware compone n ts (i ndepen d e nt m o dules of substa ntia l fun c t i o n a l it y) to qui c kly an d r e li a b ly assemb le soft w a r e a ppli c a- tions. do wn load comp onen ts from th e web and dr op th em in to th e applica tion. p u blish com p on en t archi ves from wi thi n visualdsp++. vcse supports co m p on en t im pl em e nt at i on in c/c + + or assembly language. use t h e expert linker to vi sua lly manip ulate the place m ent of co de a nd da ta on the emb e dd ed system. vi ew m e m o ry utili z a - ti on in a c o lor- co ded gra p hi cal fo rm , e asi ly mo ve cod e an d da ta to di fferent areas of th e proces sor or external memory w i th the drag of th e m o use , exam in e run ti me sta c k an d hea p usag e. t h e expert li nker is fully compatib le wi th t h e exi sting linker de fi - ni tion fi le (l df), a llow i ng the deve lope r to move betw een the graphi cal an d t extual en vi ronm en ts. in a d diti on to the softw a re and h a rdw a re developme n t t o ols ava i la ble from an alog dev i ces, th ird pa rt ies provid e a w i de r a n g e o f tools supp orting the sharc p r ocessor fam i ly . hard - war e to ols includ e sharc proce ssor pc plug-in cards. third party softw a re tools in clud e dsp li brarie s, re al-t ime opera t in g sys t ems, and block diagram design tools. d e signing an emulat or- c ompatib l e dsp board ( t a rget ) t h e analog devices family of em ul at or s ar e to ol s t ha t ev e r y dsp developer nee d s to test an d debug hard ware and software sys t ems. analog devices has supp lied an ieee 1149.1 j t ag te st access port (tap ) on each jt ag dsp . n o ni ntr u si ve in - circuit emulation is assured by the use of the processors jta g interfaceth e emulat or doe s not a f fe ct targe t system loading or timing. the emulat or uses the tap to access t h e i n te rnal fea- tures of the proce ssor, al lowing the deve loper to load code , set breakpoints, observe variables, observe memo ry, a n d exa m i n e re giste r s. the p r ocessor must be ha lted to se nd da ta a n d co m - ma nd s, but on ce an operat ion h a s be en com p le ted by t h e emulator, the d s p system is set r u nn in g at full spee d wi th n o impact on system timing. to use these e m ulators, the targ e t board m u st i n clud e a h e ad er th at connects th e dsp s jtag port to the emula t or. fo r det ai l s on tar g et b o ar d d e si gn issues i n clud in g mech an ica l la yout, si ngle pro cesso r co nnecti o ns, si gna l b u fferi ng, si gn a l ter- mi na tio n , an d em ulat or pod lo gic, see t h e e e -6 8: an al og devices jtag emulation techn ical refe re nce on the a n a l og d e vi ce s web s ite ( ww w . an alog.co m ) use site search on ee-68. this do cume nt is upda ted r egular l y to kee p pace w i th improvements to emulator support. ev a l u a t i o n k i t analog devices off e r s a r a n g e o f ez-kit lite ? e valua tion pl at- forms to use as a cost e f fect ive meth od to learn more about developing or prototyping appl ica t ion s wit h an alog dev i ces processors, platforms, and softwa re tools. each ez-kit lite in clude s an e valua tion board a l on g wi th a n ev aluat i on sui t e of th e visua ldsp++ ? d e velopm ent an d d e buggi ng en vi ro nm en t with t h e c/c++ compiler, asse mble r , an d li nk er. also i n clud ed are sa mple a pplicat ion programs, power supply, and a us b cab l e. all ev alua tion v e rs ions of the softw a re tools a r e limite d for use only wi th t h e ez-kit lite product. the u s b controlle r on th e ez- k it lite b o a r d connects th e board to t h e u s b port of t h e use r s pc, enabli ng the visualdsp++ evaluation suite to emulate t h e on- b oard proce s- sor in -c irc u it . th is p e r m i t s th e custo m e r t o dow n lo ad , e xe c ut e, and debug programs for the ez-kit lite system. it also allows i n - c ir cuit pr ogra mm in g of th e on -board flash device to st ore user-specific boot code, enabling th e bo ar d to r u n a s a sta n d a l- one unit w i th out bei n g connected to the pc. w i th a full version of vis u aldsp ++ installe d (sold separately), engineers can dev e lop software fo r th e ez-k it li te or a n y cus- tom defi ned sy stem . conn ecti ng one o f an a l o g devi ces jtag emulators to the ez -k it lit e b oa rd en ab les hi gh sp eed , non - in trusiv e emula ti o n . a d d i t i o n al in f o rm a t io n this data sheet provides a ge neral overview of the adsp-21371 archi t ect u re a n d functi on ali t y . for det a ile d in form ati o n on th e adsp-2137x family core arc h itectu re and instruction set, refer to th e adsp-2 13 6x sha r c p r o c e sso r pro g ram m i n g refe re nce . r e v . 0 | p a ge 11 of 48 | j une 2007
adsp-21371
pin function descriptions the fol lowing symbols appear in the type column of ta ble 5 : a = asynchronous, i = input, o = output , s = synchronous, (a/d) = acti ve dri v e, (o/d ) = open drain, and t = t h ree- stat e, (p d) = pull- dow n resistor, (pu) = pull-up resistor. table 5. pin l i st na m e t y pe sta t e during an d a f t e r re s e t d es crip tio n addr 23 C 0 o/t (pu ) p u ll ed hi gh/ dri v e n lo w e x ter n al a ddres s . t h e adsp -21 371 outputs addr esses f o r ex t e rnal memor y and periph- er als on the s e pins . da t a 31C0 i/o (p u) p u lled high/ pulle d hig h ex t e rna l d a ta. t h e d a ta pins can be mul t iplex e d t o suppor t the ex t e rnal memor y in t e r f ace d a t a ( i / o ) , t h e p d a p ( i ) , f l ag s ( i / o ) a n d p w m (o) . af t e r re s e t , a l l da t a p i n s a re i n e m i f m o d e a n d f l ag ( 0 - 3 ) p i n s w i l l b e i n f l ag s m o d e ( d e f a u l t ) . w hen c onfigur e d in the id p_ pd ap _c tl r eg ist er , id p ch annel 0 scans t h e d a t a 31C8 pins f o r parallel input data. da i _ p 20C1 i/o with pr o g rammable p u 1 pu l l e d h i g h / pulle d hig h dig ital a p plic a t ions in t e r f a c e p ins . t h e s e pi ns pr o v id e the ph y s i c al i n t e r f ace to the d a i sru . t h e d a i s r u c o nf igu r ati o n r eg i ste r s de fine the c o mbina t io n o f on- c hi p au di oc en tri c peripheral inputs o r outputs connec t ed t o the pi n and to t h e p i n s ou tpu t ena b l e . the configura tion r e gist ers o f these perip h erals then det e rm ines the exac t beha vior of the pin. an y input or output signal pr esen t in th e d ai s ru ma y be r o ut ed to an y of the s e pins . t h e d a i sru pr o vid es the c o nnec ti on f r om the se rial por ts , th e s/pdif module , input da ta p o r ts (2 ), and the pr ec i s i o n clo c k gener a t o r s (4 ) , t o the d a i _ p2 0C 1 pi ns . p u llu ps c a n be d i sable d via the d a i_pi n_pull up r e g i ster . dpi _p 14C1 i/o with pr o g rammable p u 1 pu l l e d h i g h / pulle d hig h dig i tal p e rip h er al i n t e r f a c e . t h ese pi ns pr o v id e the ph y s ical in te r f ac e t o the dpi sru . t h e dpi sru c o nfiguratio n r e gist ers d e fine th e c o mbin a tion of on- c hip p e ripheral inputs or outputs c o nnec t ed to the pin a n d t o the p i n s output enable . t h e c o nfigur ation r e gisters of the s e peri pher als the n det ermi n es the ex ac t beh a v i or of the pin. an y inp u t or output sig n al pr esen t in the dpi sru ma y be r o u t e d t o an y of these pi ns . t h e dpi s ru pr o vi d es the conn ec ti on f r om the time rs ( 2 ) , s p is (2 ), u a r t (1 ), flag s (1 2), and g e ne ral- pu r p o s e i/ o ( 9 ) to th e d p i_ p14C 1 p i ns . p u ll-ups can be di sabled vi a the dpi _ pi n_ pull up r e gister . ac k i ( p u ) m e m o r y ac k n o w l e d g e. ex tern al devic e s can deass e r t a c k (lo w ) t o add wait stat es t o an ex t ernal me mor y ac c ess . a c k is used b y i /o de vic es , me mo r y c o n t r o lle rs , o r o t he r periph- erals t o hold of f c o mple tion of an ex t e rnal memor y ac cess . rd o/t (pu ) p u ll ed hi gh/ dri v e n h i gh e x ter n al p o r t re ad ena ble . rd i s as ser t e d wh en ever the ad sp - 213 71 r e ads a wor d f r om ex t e rnal memor y . rd has a 22.5 k in tern al p u ll-up resist o r . wr o/t (pu ) p u ll ed hi gh/ dri v e n h i gh e x ter n al p or t w r i t e en able . wr is asser t ed whe n the ad sp - 2 1371 wri t es a w o r d t o ex t e rnal memor y . wr has a 22.5 k in tern al pull-up r e sist o r . sd r a s o/t (pu ) p u ll ed hi gh/ dri v e n h i gh sdr a m ro w a ddr ess str o be . c o nnec t t o sdram s r a s p i n. i n c o njunc t io n with o t her sdr am comman d pins , d e fines the opera tion f o r the sdr a m to per f o r m. sd c a s o/t (pu ) p u ll ed hi gh/ dri v e n h i gh sdr a m c o lumn a ddress s e lec t . c o nnec t t o sd r a m's cas pin. i n c o nj unc t io n w i th o t her sdr am comman d pins , d e fines the opera tion f o r the sdr a m to per f o r m. sd we o/t (pu ) p u ll ed hi gh/ dri v e n h i gh sdr a m w r i t e en abl e . co n n e c t to s d r a m s w e o r w b u f f e r p i n . sd cke o/t ( p u ) p u ll ed hi gh/ dri v e n h i gh sdr a m clock e n able . c o nnec t to sdr a m s ck e pin. e nab les and disables the clk signal . f o r d e tai ls , se e the da ta sheet suppli ed wi th the s d ram d e vi ce . sd a10 o/t ( p u ) p u ll ed hi gh/ dri v e n lo w sdr a m a10 p i n. enables ap pli c a t ions t o r e fr e s h an sd r a m in paralle l wi th a non- sdr am a c cesses . this p i n replaces the dsp s a10 p i n o nly d u r i ng sdr a m acc e sses . sd clk o /t h i gh-z /dri ving sdr a m c l ock . ms 0C 1 o/t (pu ) p u ll ed hi gh/ dri v e n h i gh memor y s e lec t lines 0 C 1. t h ese lines ar e asser ted (low) a s chip sel e c ts f o r the corr e- spo n ding ban k s of ex t e rnal memor y . t h e ms 3- 0 lines ar e dec o ded memor y addr ess lines th a t ch ange at the same time as the other ad dr ess lines . when no ex tern al memor y ac cess i s occur r i n g th e ms 3- 0 lines ar e inac tiv e ; they ar e ac tiv e how e v e r wh en a c o n d itional memor y ac cess i n str u c t ion is ex ecut e d , whether or not the c o nd iti o n i s tr ue . th e m s 1 p i n c a n b e u s e d i n e p o r t / f l a s h b o o t m o d e . f o r m o re i n fo r m at i o n , s e e t h e adsp -2136x sharc p r oc essor har d w a r e ref erenc e for the adsp -21367/8/ 9 p ro c esso r s . r e v . 0 | p a ge 12 of 48 | j une 2007
adsp-21371
table 5. pin l i st (continued ) na m e t y pe sta t e during an d a f t e r re s e t d es crip tio n fla g [0 ]/i r q 0 i/o h igh-z / high-z fla g 0/in t e r r upt request0. fla g [1 ]/i r q 1 i/o h igh-z / high-z fla g 1/in t e r r upt request1. fla g [2 ]/i r q 2 / ms2 i/o with pr o g rammable p u (f or ms mo de ) h i gh-z /high-z fl a g 2 / in t e r r u p t re qu es t/m e mo r y sele c t 2 . fla g [3 ]/ti me xp/ m s3 i/o with pr o g rammable p u (f or ms mo de ) h i gh-z /high-z fl a g 3 / t i m er ex p i r e d/m e m o r y sele c t 3. tdi i (pu) t e st da ta in put ( j t a g). pro v i d e s s e r i a l d a t a fo r t h e b o u n d a r y s c a n lo g i c. t d i h a s a 22 .5 k in tern al pull-up r e sist o r . tdo o /t t e st da ta o u tput ( jt a g). s e r i a l s c a n o u t p u t o f t h e b o u n d a r y s c a n p a t h . tms i (pu) t e st mo de s el ec t ( j t a g) . u s ed t o c o n t rol the t e st sta t e mac hin e . tms has a 22.5 k in tern al pull-up r e sist o r . tc k i te s t c l o c k ( j t a g ) . p r o v ides a c l o c k f o r jt a g b o undar y scan . t c k must be asser t ed (pul s e d lo w ) af t e r pow e r-up or h e ld lo w f o r pr o p er op eratio n of the ad sp -2 13 71. trst i ( p u) t e st re set ( j t a g) . r e sets the test stat e mach ine . trst must be asser ted (pulsed lo w ) af t e r pow e r - u p or h e ld low f o r pr oper operati o n of the ad sp -213 71. trs t has a 22. 5 k int e rnal pull-up r e sist or . em u o/t (pu ) e m u l at i o n st at u s . m u s t b e c o n n e c t e d to t h e a d s p - 2 1 3 7 1 a n a l o g d e v i ce s d s p t o o l s produ c t li ne of jt a g emu l ators tar g et boar d c o nnec t or only . e m u has a 22.5 k in t e rnal pull-up r e sist or . cl k_ cfg 1C0 i c o r e to clkin ratio c o n t r o l . t h ese pins set th e star t up clock fr eq uenc y . see table 8 fo r a d e s c riptio n of the cloc k c o nfigur ation mo des . not e that the opera ting fr eq uenc y can be ch ange d b y pr og ramming the pll mul t iplie r an d divider in the p m c tl reg i st er at an y time af ter the c o r e comes out of r e set. boo t _cf g 1C0 i boot c o n f ig ur a t ion se l e c t . t h ese pins sele c t the boot mod e f o r the pr oce s sor . t h e b o o t cfg pins must be v a lid bef o r e r e set is ass e r t ed . see ta b l e 7 fo r a d e s c r i p t i o n o f t h e bo ot mo des . rese t i proc e sso r rese t. r e s e t s t h e a d s p - 2 1 3 7 1 to a k n ow n s t a t e. u p o n d e a s s e r t i o n , t h e r e i s a 4 096 clki n c y c l e la ten c y f o r the pll t o l o ck . a f ter this time , the cor e begins pr ogram ex ecution fr om the har d war e r e set v e c t or add r ess . the res e t input must b e asser t ed (lo w ) a t p owe r - u p . xt al o cr y s t a l o s c i l l ato r t e r m i n al. u s e d i n co n j u n c t i o n w i t h c l k i n t o d r i v e a n e x te r n a l c r y s t a l. cl kin i lo c a l c l o c k i n . us e d i n co n j u n c t i o n w i t h x t a l . c l k i n i s t h e a d s p - 2 1 3 7 1 c l o c k i n p u t . i t config ur es the ads p -21371 to use either its i n te r n a l c l o c k g e n e ra tor or a n e x te r n a l c l o c k sour ce . c o n nec ting the necessar y c o mpon ents t o clki n an d x t al enables the int e rnal c l ock genera t o r . c o n nec ting th e ex tern al cl ock t o c l kin whi le lea v ing x t al unconnec t ed configur es the adsp -213 71 to use th e ex terna l c l ock s o ur c e such as an ex t e r n al clock oscil l at or . clkin ma y not be halt ed , change d , or ope r at ed belo w the speci f ie d f r equ e nc y . cl k out/ rese t out / runr stin i/o ( pu) cloc k out/reset o u t/ run n i n g r es et i n . the func tio n ality can be switched betwee n the pll output clock and reset out by setting bi t 12 of th e pmctreg register. the default is res e t out. th is pin also h as a third func tion as runrstin . the f u nc tio n al ity o f w h ic h is enabled b y setting bit 0 of the r u nrst ctl r e g i ster . f o r m ore i n f or m atio n, se e th e adsp - 2 1 36x sharc p r o c es s o r ha rdw a re refe r enc e for the adsp -21367/8/9 p ro c esso r s . 1 pull-up ca n be e n abl e d / dis a bl ed , val ue of pull -up cannot b e program med. r e v . 0 | p a ge 13 of 48 | j une 2007
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data mo des the upper 32 data pins of the external memory in ter fac e are muxed (usi ng b i ts i n th e sysctl regist er) to support t h e e x te r- na l memory interface dat a (input /output), th e pdap (input on ly ), a n d the fla g s (i nput/ o utput) . ta ble 6 pro v i d es t h e pin setting s. table 6. function of data pins d a t a pin mode d a t a 31C16 d a t a 15C8 d a t a7C0 00 0 e pd a t a3 2C 0 00 1 f la gs /pw m 1 5 C 0 1 epd a t a1 5C 0 01 0 f la gs /pw m 1 5 C 0 1 fl a gs1 5C 8 e p d a t a 7C 0 01 1 f la gs /pw m 1 5 C 0 1 fl a gs1 5C 0 10 0 pd ap ( d a t a + c t rl ) e pd a t a7 C0 10 1 pd ap ( d a t a + c t rl ) f la g s 7 C 0 1 1 0 r eser v e d 111 t hr e e -stat e all pins 1 t h e s e signals can be fl ags or pwm or a mix of both. howeve r , they can be selected only in groups of four. their function is de t e r mi ne d by th e co ntro l s ignal s f l ags/pwm_s e l. for more information , se e the adsp-2 136x sharc pr ocesso r hardw a r e refe rence for t h e adsp- 213 67/8/9 proc essors . boot modes table 7. boot mo de se le ction bo o t cfg1C0 b ooting mode 00 sp i s l av e boot 01 sp i m a ste r b oot 10 ep rom/fl as h boot c o r e instruc t ion r a t e t o clkin r a ti o modes for details on processor timing, see t i m i ng spe c i f icat ions an d fi gur e 3 on page 17 . table 8. core i n struction rate/ clkin ratio s e lec t ion clk cf g1C0 c ore t o clk i n r a ti o 00 6: 1 01 32 : 1 10 16 : 1 r e v . 0 | p a ge 14 of 48 | j une 2007
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adsp-21371 specifications o p er a t in g c o n d it i o ns pa r a m e t e r 1 descr i ption m in max u nit v dd i n t v dd ext v ih 2 v il 2 v ih_ c lk in 3 v il_ c l k i n 3 t ju n c t i o n i n ter nal ( c ore) sup p ly v o lta g e e x t e rnal (i/ o ) s u pply v o l t age h i gh l e v e l i n put v o lt age @ v ddex t = max l o w l e v e l in p ut v o lt a g e @ v ddex t = min h i gh l e v e l i n put v o lt age @ v ddex t = max l o w l e v e l in p ut v o lt a g e @ v ddex t = min junc tio n t e mp er a tur e 208 -l ead mqfp @ t am b i e n t 0 c t o +7 0 c 1 .14 3 .1 3 2 .0 C0.5 1 .7 4 C0.5 0 1 .26 3 .47 v dde x t + 0 . 5 +0.8 v dde x t + 0 . 5 +1.10 115 v v v v v v c 1 specifi catio n s subject to ch ange w i th o u t n o t i c e. 2 applies to input and bi direct ional pins: ad23C0, dat a 31 C0 , f l ag3 C0 , da i_px, dpi_px, spids , bootc f gx , clk cfgx , clk o ut ( run rstin ), re s e t , tc k, tms , td i, tr st . 3 applies to input pin clkin. elec trical char ac t e ristics pa r a m e t e r 1 description t e st c o n d itions min t ypical m a x u nit v oh 2 v ol 2 i ih 4, 5 i il 4 i il pu 5 i oz h 6, 7 i oz l 6 i oz l p u 7 i dd -in t yp 8, 9 c in 10 , 11 h ig h l e v e l ou tput v o ltage low le ve l o u t p u t v o l t a g e hi g h l e v e l i n p u t c u r r e n t low le ve l i n p u t cu r r e n t l o w l ev el i nput c u rren t p u ll-up thr e e - stat e l eak age c u r r en t thr e e - stat e l eak age c u r r en t thr e e -stat e l eak age c u r r en t p u l l -up sup p ly c u r r en t (i nterna l) i n put capac i tan c e @ v dd ex t = min, i oh = C1.0 ma 3 @ v dd ex t = min, i ol = 1.0 ma 3 @ v dd ex t = max , v in = v dd e x t max @ v dd ex t = max , v in = 0 v @ v dd ex t = max , v in = 0 v @ v dd ex t = max , v in = v dd e x t max @ v dd ex t = max, v in = 0 v @ v dd ex t = max, v in = 0 v t cc l k = 3.75 ns , v dd int = 1. 2 v , 2 5 c f in = 1 mh z, t ca se = 25c, v in = 1.2 v 2. 4 6 0 0 0. 4 1 0 1 0 2 00 1 0 1 0 20 0 4 .7 v v a a a a a a m a pf 1 spec ifica t ions s u bjec t to c h a n ge wit h out notice . 2 applies to o u tput and bidirection al pi n s : a d dr23-0, data31-0, rd , w r , flag3C0, dai_px, dpi_px, emu , td o, c l kou t , s d ras , sdcas , sdwe , sdcke, sda10, a n d sd clk0 . 3 se e o u tput drive curren t s on page 44 for typical drive current capabil it i e s. 4 applies to input pins: bootcfg x, clkcfgx, tck, res e t , clki n. 5 applies to input pins with 22.5 k internal pull-ups : trst , tms, td i. 6 applies to three-statable pins: flag 3C0. 7 applies to three-statable pins with 22.5 k pull-ups: dai_px, dpi _px, emu . 8 t ypi cal intern a l current dat a reflec ts nominal operat ing conditions. 9 see engineer-to -engineer no te estimating po wer dissip ation for adsp-2137x shar c proce ss o r s (e e-3 19) fo r furt he r info rma tio n . 10 applies to all signal pins. 11 gua ra ntee d, but not tes ted . r e v . 0 | p a ge 15 of 48 | j une 2007
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p ackage inf o rmatio n the informati o n pre sent e d i n figure 2 prov ide s det a ils a b out the package branding for th e adsp-21371 processor. for a complete listing of pr oduct availability, se e ordering guide on page 48 . v vvv vv . x n . n tp p z - c c s ad s p - 213 7x a y yw w co un t r y _o f _o rig i n figur e 2 . typi ca l pa cka g e br and table 9. pack age brand information br and k e y t t emper a t ur e r a n g e pp p a c k a g e t y p e z r o hs c o mpli ant p a r t ccc s e e o r de r i n g g u i d e v vvv vv . x a s s e m b l y l o t c o d e n. n s ilic on rev i sion yyww d a t e c o d e f ield de scription maximum p o w e r dissipa tion see engineer-to-engineer note estimating powe r dissipation for adsp-2137x sharc proc esso rs ( ee-319) for detailed th erma l an d po wer i n fo rm ati o n rega rd in g ma xi mum po wer di s- sipation. f o r inf o rmation o n pack age thermal specifications, see t h erm a l ch aracte ri stics on pa ge 45 . a b s o lute maximum r a tings stresses greater than t h ose li sted i n ta ble 1 0 ma y ca use perma - ne nt d a m a ge to t h e d evi ce. these are stress ratings only; fun c tion al operation of th e device at th ese o r any other co nd i- ti ons gre a te r th an th ose i n dica ted in t h e operati o nal se ctions of th is s p e c ifica tion is n o t i m pli ed. exposure to absolute maximum r a ti ng co nd iti o ns fo r ex te nd ed per i o d s ma y a f fect dev i ce relia b il ity . t a ble 1 0 . abs o lute ma xi mu m r a ti ngs p a r a me te r r ati n g i n ternal ( c or e) sup ply v oltage ( v ddi nt ) C 0 . 3 v t o + 1 . 5 v ex ternal (i/o) su p p ly v o lt age ( v dde x t ) C 0 . 3 v t o + 4 . 6 v i n put v o ltag e C0.5 v t o v dd e x t +0.5 v out p ut v o l t age s wing C0.5 v to v dd e x t +0.5 v l oad capacitanc e 2 00 pf st or age t e mper a t ur e r ange C 6 5 c to +150 c junc tion t e mper a t ur e under bias 12 5 c esd s e nsitivit y
esd ( el ec t r o sta t ic dischar g e) sensitiv e de vic e . char ged devices and cir c u i t bo ar ds can dis c har g e wit h out d e tec tion. although this produ c t f e atur es pa te nt ed or pr oprietar y cir c uitr y , damage ma y oc cur on devi c e s subjec ted t o high ener gy es d . t he r e f or e , prop er esd p r e cautions s houl d be ta ke t o a v oi d per f or manc e deg r ada t ion or l o ss of func tio nalit y . r e v . 0 | p a ge 16 of 48 | j une 2007
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figure 3 shows core to clkin ratios of 6 : 1 , 16:1, and 32:1 with external oscillato r or cr ys tal. not e th at more rat i os are pos sible an d ca n b e set th r o ugh softw a r e usi n g th e pow er ma na geme nt t i ming specific a t ions the adsp-21371s internal clock ( a multiple of clkin) pro- vides the clock signal for timi ng in tern al memo ry, pr ocessor co re, an d serial ports. during re set, progra m th e rati o b etw een t h e pr ocessor s i n t e rn al clo c k f r equency an d ext e rn al (clk in) clock frequency w i th th e clkc fg1C 0 pi ns (see ta ble 8 o n page 14 ). to de t e rmi n e sw it ch in g fre que n c ie s fo r t h e se ri al ports, d i vi de down the i n t ern al clock, usi n g t h e progra mm abl e d i vider co ntro l of each po rt (divx fo r the serial p o rts). the adsp-213 71s intern al clock swi t ches at higher frequencies than the system input clock (clk in). to gene ra te th e internal cl o c k, t h e pr oce s s or us es a n i n te rn al p h a s e- l ock e d l o op (p l l ) . th is pll- ba sed clo c ki ng m i n i m i ze s the skew betw een the s y s- tem c l oc k (c lkin ) si gna l an d th e processors internal clock. core clock frequency ca n be ca lculate d a s : cc lk = 1 t ccl k = f inp u t (pllm/plld) 2 + C 0 1 in d i v [ 8 ] l oop fi l te r vc o 1 , 2 ,4 ,8 n p l l d [ 7 ..6 ] di v e n[ 9 ] 0 1 1 pl l b p[ 1 5 ] am p 1 - 64 m p l l m [ 5 ..0 ] c l k _ c f g [ 1 . . 0 ] 00 = 6 01 = 32 10 = 16 11 = 6 de l ay 40 9 6 cl ki n cl ko ut e n[ 1 2 ] buf f 2 0 1 ccl k 10 0m h z 26 6m h z pc l k (i o p ) cl k o ut or co r e r s t rs t o u t cl k i n 3 . 125 m h z 66 . 7 m h z re s e t xt a l @ b oot , c l k c f g[ ] - > p l l m [ ] 160 m h z < v c o _o u t < 800 m h z 2 , 2 . 5 , 3, 3. 5, 4 s d r a t io[ 2 0 ..1 8 ] pl l b yp a s s; r e s e r v e d mu l t i p l i e r bl o ck con t rol register (pmctl) . fo r mor e info rmatio n, see the adsp- 21 36 x sharc pro c es sor prog ram m ing referen c e . to to sd c l k fig u re 3. core clock an d sys t em cl oc k re la t i o n s h ip to clk i n note tha t in the user a pplicat ion, t h e pll multi p li er value should be selecte d in such a wa y that t h e v co frequency falls in between 160 mhz and 800 mhz. the vco f r equency is calcu- lated as follows: where: f vc o = vco f r equency . pllm = multiplier v a lue programmed.
plld = di vi der va lue progr a m m ed.
f inp u t = i n put frequency to th e pll.
f inp u t = c lkin whe n th e input di vider is disa bled.
f inp u t = c lkin/2 when t h e i n put divi der is e n abled.
c c l k f g [ 1 . . 0 ] r e v . 0 | p a ge17 of48 | j une2007
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n o te th e defi ni tio n s of va ri ous clock periods shown in ta ble 1 2 which ar e a fun ction of clkin an d the appro priate ratio c o n- trol sh own i n ta ble 1 1 . table 11. adsp-21371 clkou t and ccl k clock gene r a tio n o p eration ti m i n g requir emen ts cl kin cc l k des c r i pt ion i n put clock c o r e c l o c k c alcula tion 1 / t ck 1 / t cc lk table 12. clock periods ti m i n g requir emen ts des c r i pt ion 1 t ck clkin clock p e riod t cc l k (p r oc e ssor) c or e clock p e riod t pclk (p eriphe ral) clock p e riod = 2 t cc l k t sc l k serial p o r t clock p e r i od = (t pclk ) sr t sd cl k sdram cloc k p e riod = (t cc l k ) sdr t sp ic l k spi clock p e r i od = (t pcllk ) spi r 1 where: sr = serial port-to-co re clock rat i o (wide range , det e rmined by sport c l kdi v bits in divx register) spir = spi-to-core clock ra tio (wide ra nge, de termine d by spibaud regis ter setting) sd r=sd ram - to-c ore c l oc k ra tio (v a l ue s de termine d by bits 2 0 -18 of the pmc tl regist e r) use t h e exact timing informatio n give n. do not a ttempt to de ri ve p a r a m e te rs f r o m th e ad di tion o r subtraction of o t h e rs. w h ile ad dition or subtractio n wo uld y i e l d m ean in gful r esult s for an indi vidual devi ce , the va lues gi ven in thi s data sheet re flect statist i cal variat ions and worst cases. consequently, it is not meaningful to a d d paramete rs to derive longer t i mes. see figure 36 on page 44 un der t est co nd it io ns fo r vo lta g e r efer - ence levels. switching characteris t ics specify how the proce ssor change s its signals. ci rcui try external to t h e proce ssor must be des i gned for co mpa t i b ili t y w i t h t h e s e sign al ch ar act e ri st ics. sw it ch in g ch ar- acte ristics describe what the processor will do in a give n circumstanc e . use switching c h arac teristics to e n sure that any timing requi r e m ent of a de vice connected to th e processor (such a s memo ry) is sa tisfi e d. tim ing requ irem ents apply to signals that ar e contro lled b y ci r- cuitry externa l to th e proce ssor, such as the da ta input for a read o p er ati o n. t i m i ng requi remen ts guaran tee t h at the processor o p er at es cor rectly w i t h ot her d e vi ces. r e v . 0 | p a ge 18 of 48 | j une 2007
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po we r - u p s e q u e n c i n g the ti mi ng requirement s for pr ocessor startup are given in ta ble 1 3 . table 13. power u p sequen cin g timin g requi rements (p rocess or st artu p) p a r a m e t e r min ma x u ni t timi ng re qu ire m en t s t rs t v dd re se t low b e f o re v dd i n t /v dd ex t on t ivddevdd v ddint o n b e fo re v dd ex t t cl k v dd 1 cl kin v alid a f t e r v dd i n t /v ddex t va l i d t cl k r s t clki n v a lid b e f o r e re se t deasser t ed t pllr st pl l c o ntr o l s e t u p bef o r e res e t deasser t ed s w i t ch ing char ac teristic t c o re rs t c or e reset deasser t ed af t e r rese t deasser t ed 0 C5 0 0 10 2 20 3 40 96 t ck + 2 t cc l k 4, 5 2 0 0 2 0 0 n s ms m s s s 1 va lid v ddint /v dd e x t as sume s th at t he supplie s a r e ful l y ra mped to th eir 1.2 a n d 3.3 vo lt rails. vo lta g e ra mp r a te s can var y from microseconds to h undre ds of mill iseconds depending on th e de sign of th e powe r supply subsyste m. 2 as sum es a st abl e clk i n signa l , af ter mee ting w o rst - ca se s tart u p t i m i n g o f crys ta l o s c i ll a to r s. r efe r to your cry s ta l o s c i l l a to r manufacture r's da ta shee t f o r s t art u p t i m e . assum e a 25 ms maximum oscillat o r start up tim e if using the xtal pin and internal oscill ator circuit in conju nction w i t h an ext ernal cryst a l. 3 bas e d on c l ki n cycl es . 4 applies after the power-up sequence is complete . subsequ e nt re se ts requi r e a minimum of four cl kin cycl e s for reset to be held low in order to prop erly initialize and propaga te de fa ult s t a tes a t all i/o pins. 5 th e 4 09 6 cy c l e co u n t de pe n ds o n t srs t specificatio n in ta ble 1 5 . if s etup time is not m et, one a d d i t i ona l c lkin c y cl e may be added t o the core reset time, resu l t ing in 4097 cycl e s maximum. cl kin r e set t rst v d d rs t o ut v dd e x t v dd int t p llr s t t clkrst t cl kvd d t i v ddev d d cl k _ cf g 1 - 0 t co rer s t fi gu re 4. po we r-u p seque n ci ng r e v . 0 | p a ge 19 of 48 | j une 2007
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clo c k input table 14. clock input 266 mhz unit p a r a me te r min m ax timi ng re qu ire m en t s t ck clki n p eriod 22 .5 1 32 0 2 ns t ckl cl ki n w idth l o w 1 0 1 18 0 2 ns t ckh cl ki n w idth h ig h 10 1 18 0 2 ns t ckr f cl ki n rise/f all (0 .4 v t o 2 .0 v ) 6 n s t cc l k 3 c c l k p eriod 3. 75 1 10 ns 1 applies o n ly f o r clk cfg 1C0 = 00 a n d def a ul t values for pll cont rol b i t s in pmc tl. 2 applies o n ly f o r clk cfg 1C0 = 01 a n d def a ul t values for pll cont rol b i t s in pmc tl. 3 any changes to pll control bits in the p mctl regis ter must me et core clock t iming specification t cc l k . clki n t ck t ck h t ckl fig u re 5. clock in put clo c k signals the adsp-21371 can use an external clock or a crystal. see the clki n pi n descri ptio n i n ta ble 5 . the programmer can confi g - ure the adsp-21371 to use its in ternal clock g e nerator by co nn ect i ng t h e n e ce ss a r y com p on en t s to c l k i n an d x ta l . fi gur e 6 shows the component connec ti ons used for a crysta l o p er at i n g i n f u nda men t a l m ode. n ot e th at t h e clo c k r a t e i s achieved using a 16.67 mhz c r ysta l and a pll multiplier ratio 16:1 ( c clk:cl kin achieves a clock speed of 266 m h z). to a c hi e v e t h e ful l core cl o c k r a t e , programs need to confi gure the multiplie r bits in the pmctl re gister. c1 22 p f y1 r1 1m ? * xt a l cl ki n c2 22 p f 16 . 6 7 m h z r2 47 ? * a d s p - 2 13 7x r2 s ho ul d be cho s e n to l i m i t c ry s t al d r i ve p ow er . r ef er t o c r ys t a l ma nu f a c t ur e r s sp e c if ic a t io n s *t yp i c a l v a l u es figur e 6 . 26 6 mh z opera t io n (funda me ntal mode crystal ) r e v . 0 | p a ge 20 of 48 | j une 2007
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re s e t table 15. r eset p a r a me te r timi ng re qu ire m en t s t wrst 1 re se t pu l s e w i d t h lo w t sr st re se t s e t u p b e fo re c l k i n low m i n 4 t ck 8 ma x u n i t ns n s 1 applie s af t e r th e powe r-up se que n ce is comp l e te. at po wer-up, the processors internal ph ase-locke d l oop requires no more t h an 1 00 ms while reset is lo w, a s s u m i ng st abl e v dd and c lki n (no t incl uding st art - up time o f ext e rna l c l o c k o s cil l a t o r) . cl k i n re s e t t ru nw rs t t run s r st fig u re 7. reset r u nning r e set th e follow i n g t i m i n g spe c ifica tion a pplies to clk o ut / r e set o ut/ r un r s tin pin w h e n it i s conf igur ed as runrstin . table 16. r u nning reset p a r a me te r timi ng re qu ire m en t s t wrunrst running rese t pu l s e wi d t h lo w t sr unr s t running rese t setup b e f o r e clki n h i gh m i n 4 t ck 8 ma x u n i t ns n s clkin runrstin t w r un r st t s ru n r st figure 8. running reset r e v . 0 | p a ge 21 of 48 | j une 2007
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in te rr up ts th e fol l ow ing t i m i n g spe c ifica tion a pplies to th e flag 0, fl ag 1, an d fla g2 pi ns wh en the y a r e confi g ured as irq0 , irq1 , and irq2 in terrupts as w e ll as th e da i_p20-1 an d dpi_p14-1 pins when they ar e con f igur ed a s in te r rupt s . table 17. interrupts p a r a m e t e r min ma x u ni t timi ng re qu ire m en t t ipw ir qx p u lse w i dth 2 t pc l k +2 n s da i _ p 2 0 - 1 dp i _ p 1 4 - 1 fl ag 2 - 0 (i r q 2 - 0) t ip w f i g u r e 9 . inte rr up ts co r e t i me r th e fol l ow ing t i m i n g spe c ifica tion a pplies to flag3 wh en it is configured as the core ti me r (ctimer ) . table 18. core timer p a r a m e t e r m in m a x un it s w i t ch ing char ac teristic t wc tim ct i m e r p u l s e w i d t h 4 t pcl k C 1 n s fl ag 3 (c t i m e r ) t wc t i m fi gure 10. cor e ti mer ti m e r p w m _ o u t cy c l e ti m i n g th e fol l ow ing t i m i n g spe c ifica tion a pplies to t i m er0 a n d ti me r1 in pw m_out (pulse -wi d t h mo d u lati on ) mo de . ti mer signals are routed t o the d pi_p 14C1 pins through the dpi sru. therefore, t h e t i mi ng speci f icat io ns prov ided b e low are valid at the dpi_p14C1 pins. table 19. t i m er pwm_ou t t i ming pa r a m e t e r m i n m a x u n i t s w i t ch ing char ac teristic t pwmo t i mer p u lse w i dth output 2 t pc lk C 2 2 (2 31 C 1 ) t pcl k ns dp i _ p 1 4 - 1 (t i m e r 1 - 0) t pw m o figure 11. t imer pwm_out timing r e v . 0 | p a ge 22 of 48 | j une 2007
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t i mer wd th _cap t i min g th e follow i n g t i m i n g spe c ifica t ion a pplies to ti mer0, an d timer1, and i n wdth_cap (pul se width count and capture) mode. ti me r si gna ls are route d to th e dpi_p14C1 pins th rough the sru. the r efore, the timing specifi c ati o n provi d ed below i s valid at the dpi_p14C1 pins. ta ble 20. t i m er wi dt h ca pt ure ti mi n g pa r a m e t e r m i n m a x u n i t timi ng re qu ire m en t t pwi t ime r p u lse w idth 2 t pc l k 2 (2 31 C 1 ) t pcl k ns dp i _ p 1 4 - 1 (t i m e r 1 - 0 ) t pwi figu r e 1 2. t i mer wi dth capt ur e t i mi ng p i n to pi n di r e c t r o uti n g ( d ai an d dpi ) fo r di re ct pin co nn ecti on s o n ly (for example dai_pb01_i to dai_pb02_o ) . table 21. dai pin to pin routing p a r a m e t e r min ma x u ni t timi ng re qu ire m en t t dpio delay d a i/dpi p i n i n put v a lid t o d a i output v a lid 1 .5 10 ns da i _ p n
dp i _p n
da i _ p m
dp i _ p m
t dp i o fi g u re 13 . d ai pi n t o pi n d i re ct r o ut i n g r e v . 0 | p a ge 23 of 48 | j une 2007
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precis ion cl ock gener a tor (di r ec t pin routing) this timing is only valid when t h e sru is confi g ured such t h at the preci s ion clock gen erat o r (pcg) tak es it s in put s di rect ly fr om the dai pins (via pin buffers) and sends its outputs directly to the dai p i ns. f o r th e o the r ca ses, where the pcgs table 22. precision clock generator (direct pin routing) inputs a n d outputs are not direct ly ro uted t o / f r o m dai p i ns ( v ia pi n b u ffers) th ere i s no ti mi ng d a ta ava i la ble. all tim i n g pa ram - et er s an d sw it ch in g ch ara c t e ri st i c s ap ply t o ext e rn al da i pi ns (dai_p01 C dai_p20). p a r a m e t e r m in max u ni t timi ng re qu ire m en t s t pc g i w i nput clock p e r i od t str i g p c g t r igg e r s e tup b e f o r e f a lling edge of p c g i n put clock t htr i g p c g t r i g g e r h o l d af te r f a l l i n g ed g e o f p c g i n p u t clock s w i t ch ing char ac teristics t dpc g io p c g ou tput clock and f r ame sync a c tiv e edg e delay a f t e r p c g i nput clock t dt r i g c l k p c g ou tput clock delay a f ter p c g t r ig ger t dt r i g f s pc g f r ame s y nc dela y a f ter pc g t r igg er t pc g o w 1 output clock p e riod 24 4. 5 3 2 .5 2 .5 + ((2.5) t pc g i w ) 2 . 5 + ((2.5 + d C p h ) t pcg i w ) 2 t pc g i w C 1 10 1 0 + (( 2. 5 ) t pcg i w ) 1 0 + (( 2.5 + d C ph) t pc g i w ) ns n s n s ns n s n s n s d = fs xd iv , ph = fs xphas e . f o r m o r e inf o r m ation, see the ads p -2 1 3 6 x sh arc p r oc essor h a r d war e re f er enc e f o r the ad sp -2 13 68 p r oc e ssor , p r e c i sion cloc k g e nera tors cha pter . 1 normal m o de of operation. da i _ p n
dp i_ p n
p c g _ t r ig x_i
da i _ p m
dp i_ p m
pc g _ ex t x _ i
(c lki n )
da i _ p y
dp i_ p y
p c g _ cl kx_o
da i _ p z
dp i_ p z
pc g _ f s x _o
t st r i g t htri g t dpc g i o t dt r i g f s t pcg i w t pcg o w t dt r i g cl k t dpc g i o fi gu re 14 . p re ci si on clo c k ge ner a tor (di r ec t pi n r o uti n g) r e v . 0 | p a ge 24 of 48 | j une 2007
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fl a g s th e tim i n g specifica t ion s provid ed b e low apply t o th e flag3C0 and dp i _ p14 C 1 p i ns, and the data31-0 pins. see ta ble 5 o n page 12 for mo re infor m ation on flag use. table 23. flags p a r a m e t e r m in m a x unit timi ng re qu ire m en t t fipw d pi _ p 1 4- 1, d a t a 31 - 0 , f la g 3C 0 in p u lse w i d t h 2 t pcl k + 3 ns s w i t ch ing char ac teristic t fo pw d pi _ p 1 4- 1, d a t a 31 - 0 , f la g 3C 0 ou t p u lse w i d t h 2 t pcl k - 2 n s dp i _ p 1 4 - 1 (f l a g 3 - 0 in ) ( dat a3 1 - 0) dp i _ p 1 4 - 1 ( fla g 3 - 0 ou t ) (d a t a 3 1 - 0) t fi p w t fo p w f i gure 1 5 . fl a gs r e v . 0 | p a ge 25 of 48 | j une 2007
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sdr am int e r f ac e t i ming (133 mhz sdc l k ) table 24. sd ram interface timing 1 p a r a me te r min m a x uni t timi ng re qu ire m en t s t ss d a t da t a s e t u p b e fo re s d c l k t hs d a t da t a h o l d af t e r s d c l k s w i t ch ing char ac teristic s t sd cl k sdc l k p eriod t sd cl kh s d cl k w i d t h h i g h t sc cl kl sdclk w i dth l o w t dc a d c o mmand , add r , da ta d e la y af t e r s d c l k 2 t hc ad c o mmand , add r , da ta hold a f t er sd clk 2 t ds d a t da ta disable a f t er s d cl k t en sd a t da ta enable a f t er s d cl k 0 .5 8 2 .2 7. 5 3 3 1. 3 1 . 6 5. 3 5 . 3 n s n s n s n s ns n s n s ns ns 1 fo r f ccl k = 133 mhz (s dcl k r a tio = 1:2).
2 c o mmand pins incl ude: s d c a s , sdras , sdwe , ms x , s d a1 0, and sd ck e.
t hc ad t h cad t ds d at t dc ad t ssd a t t dc ad t en sd a t t hs da t t s d cl kl t s d cl kh t sd c l k sd c l k da t a ( i n) da t a ( o u t ) cm n d a ddr (ou t ) fi gure 16 . s dr am interfa ce tim i n g fo r 13 3 mhz sdclk r e v . 0 | p a ge 26 of 48 | j une 2007
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me mor y r e ad bu s ma ste r use t h ese specifications for asyn ch rono us i n terf aci n g to memo- ri es. not e tha t ti mi ng for a c k, da ta , rd , wr , and st robe ti mi ng pa ra meter s on ly a pply to a s yn chr o no us acc e ss m o d e . table 25. memory read bus mast er p a r a me te r m i n m a x u ni t timi ng re qu ire m en t s t da d a d dr ess , s e lec t s dela y to da ta v a lid 1, 2 t dr l d rd l o w to d a t a v a l i d 1 t sd s data setu p t o rd hi g h t hdr h data hold f r om rd hi g h 3, 4 t d aak ac k d e l a y f r o m ad d r e s s, s e l e c t s 2, 5 t ds ak ac k d e l a y f r o m r d low 4 s w i t ch ing char ac teristics t dr ha a d dr ess selec t s hold a f ter rd h ig h t da r l a d dr ess selec t s to rd low 2 t rw rd p u lse w i dth t rw r rd h i g h to w r , r d , l o w 2 . 2 0 rhc + 0. 38 t sdc l k C3 . 3 w C 1.4 h i + t sd cl k C0 . 8 w+t sdc l k C5 . 1 2 w C 3 t sdc l k C1 0 . 1 + w w C 7. 0 n s n s n s n s n s n s ns n s n s n s w = (number of w ait sta t es specified in a m ic tlx r e g i st er) t sdc l k .
hi = rhc + ic (rhc = ( n umber of read hold c y cles spec ifi ed in amic tlx r egi ster ) x t sd c l k
ic = (number of id le c y cles sp e cifi e d in amic tlx r e g i ster ) x t sd c l k ).
h = (number of hold c y cles specified in amic tlx regist er) x t sdc l k .
1 dat a delay/se t up: s y st em m u st mee t t dad , t dr l d , o r t sds .
2 th e f a lli ng e dge of m s x, is re fe re nc e d .
3 not e that timing for ac k, data, rd , wr , and strobe timing paramete rs on l y a pply t o as ynchro n ous ac ce ss mo de .
4 da ta h o ld : u se r m u s t m e et t hdrh in as ynch r o n o u s ac ce ss mo d e. se e test co n d itions on page 44 f o r the ca lcula t ion of hold time s give n c a pa cit i ve and d c loa d s .
5 ac k delay/set up: use r must meet t daak , or t dsak , for de asse rtion of ack (low ) . for asynchron ou s asser t ion of ack (high) use r must mee t t d aak or t ds ak .
ad dre s s ms x rd data ack wr t da rl t rw t da d t daak t hdrh t rw r t drl d t drha t ds a k t sd s fi gure 17 . m em or y re adbus mast er r e v . 0 | p a ge 27 of 48 | j une 2007
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me mor y w r ite bus master use t h ese spe c ifica t ions for asy n ch rono us i n terf aci n g to memo- ri es. not e tha t ti mi ng for a c k, da ta , rd , wr , and st robe timing paramete rs only apply to asynch ronous a c ce ss mode . table 26. memory write b u s ma st er p a r a m e t e r m in max u nit timi ng re qu ire m en t s t d aak ac k d e l a y f r o m ad d r es s, s e l e c t s 1, 2 t ds ak a c k dela y fr om wr lo w 1, 3 s w i t ch ing char ac teristics t da w h a d d r ess , selec t s t o wr deasser t ed 2 t da w l a d d r ess , selec t s t o wr lo w 2 t ww wr p u lse w i d t h t ddwh dat a s e tup b e f o r e wr hi g h t dwha a d d r ess hold af t e r wr deasser t ed t dwhd da ta hold a f t e r wr deasser t ed t da t r w h da ta disable a f te r w r dea s se r t ed 4 t ww r wr hi g h t o w r , rd lo w t ddwr da ta disable bef o r e rd lo w t wde wr l o w to da ta enabled t sdc l k C3 . 6 + w t sdc l k C2 . 7 w C 1.3 t sdc l k C3 . 0 + w h + 0.15 h + 0.02 t sdc l k C1 . 3 7 + h t sdc l k C1 . 5 + h 2 t sd cl k C 5 . 1 t sdc l k C 4 . 1 t sd cl k C 1 0 . 1 + w w C 7. 1 t sd cl k +4 . 9 + h n s n s n s n s ns n s ns ns n s n s n s n s w = (number of w ait sta t es specified in amic tlx r e g i st er) t s sd cl k
h = (number o f hold c y cles specified in amic tlx regist er) x t sdc l k
1 ac k delay/se t up: syste m must meet t d aak , or t ds a k , for dea s s e rt ion of ac k (low). for a s ync hron ous a s s e rt ion of ac k ( h igh) user mus t m eet t d aak or t ds a k .
2 th e f a lli ng e dge of m s x is re fere nce d .
3 n o te that timing for ac k, d ata, rd , wr , and strobe timing paramete rs on l y appl ies t o as ync hro n o u s ac c ess m o d e.
4 se e test co n d itions on page 44 fo r ca lc ul at ion of ho ld t i mes gi ve n c apac i t i ve a n d dc l o ad s.
add re s s ms x wr dat a ack rd t daw l t ww t daak t ww r t wd e t ddw r t dw h a t da w h t dsa k t dd w h t dw h d t dat rw h figur e 1 8 . m em o r y wr ite bu s maste r r e v . 0 | p a ge 28 of 48 | j une 2007
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se ri a l p o r t s t o d e t e rm in e w h et h e r com m un ica t io n i s possi ble b e tw e e n t w o s e r i a l p o r t s i g n a l s ( s c l k , f s , d a t a c h a n n e l a , d a t a c h a n n e l b ) de vices a t clock speed n, th e fol l ow ing spe c ifica tions m u st be are routed to the d a i_p20C1 pins using the sru. therefore, the co nfi r m e d : 1) f r am e sync delay an d fra m e syn c setup an d h o ld, t i m i n g spe c if ica t io ns pr ov id ed b e lo w a re v a li d at t h e 2) da ta d e la y a n d da ta setup a n d hold , an d 3) sclk w i dth. dai _ p20C1 pins. table 27. serial portsexternal clock p a r a me te r min m ax uni t timi ng re qu ire m en t s t sf se 1 f s s e t u p b e fo re s c l k (ex t ernally g e ner a ted fs in e i ther t r ansmit or rec eiv e mode) 2 . 5 ns t hfs e 1 f s h o l d af t e r s c l k (ex t ernally g e ner a ted fs in e i ther t r ansmit or rec eiv e mode) 2 . 5 ns t sd re 1 r e cei v e d a t a s e t u p b e fo re r e ce i v e s c l k 2 . 5 n s t hdr e 1 r e cei v e d a t a h o l d af t e r s c l k 2 . 5 n s t sc l k w sc l k w i dt h 1 0 n s t sc l k sc l k p e r i od 2 0 ns s w i t ch ing char ac teristics t dfs e 2 fs delay a f ter sclk (i n t ernally gener a ted f s in either t r ansmi t or rec e iv e mode) 1 0 . 5 ns t ho fse 2 f s h o l d af t e r s c l k (i n t ernally gener a ted f s in either t r ansmi t or rec e iv e mode) 2 ns t dd te 2 t r ansmit data delay a f ter t r ans m it scl k 11 ns t hd te 2 t r ansmit d ata hold a f t e r t r ansmit s c lk 2 ns 1 referenced t o sample e d ge. 2 referenced t o drive e d ge. table 28. serial portsinter n al clock p a r a me te r min m a x uni t timi ng re qu ire m en t s t sf si 1 fs s e tup b e f or e scl k (ex t e r na lly gener a t ed fs in either t r ansm it or rec e iv e mode) t hfs i 1 fs hold a f t er sclk (ex t e r na lly gener a t ed fs in either t r ansm it or rec e iv e mode) t sd ri 1 rec eiv e d a ta setup bef o r e sc lk t hdr i 1 r e ceiv e dat a hold af t e r sc lk s w i t ch ing char ac teristics t dfs i 2 fs d e la y af t er s c lk (i n t ernally gene r a t ed fs in t r ansmit mode) t ho fsi 2 f s h o l d af te r s c l k ( i n t e r n a l l y g e n e rat e d fs i n t r a n s m it m o d e ) t dfs i r 2 fs d e la y af t er s c lk (i n t ernally gene r a t ed fs in rec e iv e mode) t ho fsir 2 f s h o l d af te r s c l k ( i n t e r n a l l y g e n e rat e d fs i n r e ce i v e m o d e ) t dd ti 2 t r ansmit da ta dela y af t e r sclk t hd ti 2 t r a n s m i t d a t a h o l d af t e r s c l k t sc kl iw t r ansm it or rec e iv e sc lk w i dth 7 2 . 5 7 2 . 5 C 1 . 0 C 1 . 0 C 1 . 0 0 . 5 t sc lk C 2 4 1 0 . 7 3.6 0 .5 t scl k + 2 ns ns n s n s ns n s n s n s n s n s n s 1 ref erenc ed t o the sa mple e d ge. 2 referenced t o drive e d ge. r e v . 0 | p a ge 29 of 48 | j une 2007
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table 29. serial portsenable a n d three-state pa r a m e t e r m i n m a x u n i t s w i t ch ing char ac teristics t dd ten 1 data enable from ex t e rnal t r ansmit sclk 2 n s t dd t t e 1 data di sable from e x ter n al t r ansm i t s c l k 1 0 ns t dd tin 1 data enable from i n ternal t r ansmit sclk C1 ns 1 ref e ren c ed t o driv e e d ge. table 30. serial portsexternal late frame sync pa r a m e t e r m i n m a x u n i t s w i t ch ing char ac teristics t dd tlfs e 1 da t a d e l a y f r o m l a te e x te r n a l t r a n s m it f s o r e x te r n al r e ce i v e f s with mce = 1, mfd = 0 1 0 n s t dd tenfs 1 data enable f or mce = 1, mfd = 0 0 .5 ns 1 th e t dd t l f s e a n d t ddten fs parame ters apply to l e ft-just i fi e d sa mple pa ir a s we ll as dsp se rial mod e , a n d mc e = 1, mfd = 0 . r e v . 0 | p a ge 30 of 48 | j une 2007
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d at a r e ce iv e in t e rna l cl o ck dat a r e ce i v e e x t e rnal cl o ck
dr iv e e dg e s am p l e e dg e d r i v e e d ge s a m p l e e d ge
da i _ p 2 0 - 1
( s cl k)
d a i _p 20 - 1
(f s )
d a i _p 20 - 1 ( dat a chann e l a / b) da i _ p 2 0 - 1
( s cl k)
da i_ p 2 0 - 1
(f s )
d a i _p 20 - 1 d a i _p 20 - 1 ( dat a chan ne l a/b) (dat a c h anne l a/ b) no t e : e it h e r t h e ris i ng e d g e o r f al l i n g e dg e o f s cl k ( e x t e r nal ) o r s cl k ( in t e rnal ) can be us e d as t he a ct iv e s am p l i ng e dg e . t sdri t hdri t sf si t hf si t df si r t ho f s i r t scl k i w t sdre t hd re t sf se t hf s e t df s e t sc l k w t ho f s e t ddt i dr iv e e dg e s a m p l e e dg e d r i v e e d ge s a m p l e e d ge dat a t r ans m i t i nt e rn al cl o ck t sf si t hf si da t a t ran s m it e x t e rna l cl o ck t df si t ho f s i t scl k i w t hdt i t ddt e t sfse t hf se t df s e t hof s e t sc l k w t hdt e da i _ p 2 0 - 1 ( s cl k) d a i _p 20 - 1 (f s ) d a i _p 20 - 1 (dat a chann e l a / b) d a i _p 20 - 1 ( s cl k) d a i _p 20 - 1 (f s ) no t e : e it he r t he r i s i ng e dg e o r f al l i ng e d g e o f s cl k ( e x t e rn al ) o r s c l k (int e rnal ) can be us e d as t he ac t i v e s am p l i ng e dg e . dr i v e e dg e dri v e e dg e sc l k dai _ p 2 0 - 1 sc l k ( ex t ) t dd t t e t dd t e n d a i _p 20 - 1 ( dat a chan ne l a/b) dr i v e e d g e da i _ p 2 0 - 1 sc l k ( i n t ) t ddt in d a i _p 20 - 1 ( dat a chan ne l a/b) fi gure 19. s e r ia l po rt s r e v . 0 | p a ge 31 of 48 | j une 2007
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da i _ p 2 0 - 1 ( s cl k) da i _ p 2 0 - 1 (f s ) dai _p 20 - 1
( dat a channe l a/ b)
dai _p 20 - 1
( s cl k)
da i _ p 2 0 - 1
(f s)
da i _ p 2 0 - 1
( dat a channe l a/ b)
ex t e rnal re ce i v e f s w i t h m c e = 1 , m f d = 0 dri v e sa m p l e d r i v e dri v e sa m p l e d r i v e l at e e x t e rnal t ra ns m i t f s 1s t b i t 2nd b i t 1st bi t 2nd bi t t hfse/ i t sfs e / i t ddt e/ i t dd t e n f s t d d t lfse t hdt e / i t sfse / i t ddt e / i t dd t e nf s t ddt l f s e t hdt e/ i t hf se / i no te : s e r i a l p o r t s ign a l s ( s c lk , f s , da t a chann e l a/ b) a r e ro ut e d t o t h e d a i _p 20 - 1p i n s u s i ng t he s ru. t he t i m i ng s p e ci f i cat i o n s p ro v i d e d he re a re v al i d a t t he dai _p 2 0 - 1p i n s . t he chara ct e ri z e d ac s p o rt t i m i n g s a re ap p l i c abl e w he n i nt e rna l cl o ck s and f ram e s a re l o o p e d b ack f r o m t he p i n, no t ro ut e d di rect l y t hro ug h s au. fig u re 20. ext e rnal late frame sync 1 1 th is fig u re ref l e ct s ch ange s mad e t o s u pport l e ft-justified sample pair mode. r e v . 0 | p a ge 32 of 48 | j une 2007
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input data p o r t (idp ) the t i ming requirement s for the idp are gi ven i n ta ble 3 1 . id p signals (sclk , fs, and sdata) are rout ed t o the da i_p20C1 pin s usin g t h e sr u. t h erefore , the t i m i n g spe c ifica t ions pro- v i de d b e l o w ar e va l i d a t t h e da i_ p 20C 1 pi ns . tab l e 31. inp u t data p o rt (idp) p a r a m e t e r m in m a x un it timi ng re qu ire m en t s t sis f s 1 f s s e t u p b e fo re s c l k r i s i ng e d g e 3 . 8 n s t sih f s 1 f s h o l d af t e r s c l k r i s i n g e d g e 2 . 5 n s t sis d 1 s d at a s e t u p b e f o re s c l k r i s i n g e d g e 2 . 5 n s t sih d 1 sda t a hold a f t e r sclk r i sing edge 2.5 n s t idpclk w cl oc k w i dth 9 ns t idpclk cl oc k p e riod 24 ns 1 dat a, sc lk, fs can come from any of the da i pi n s . s c lk and fs can also come via pcg or sport s . pcg's input can be either clkin or an y o f th e da i pin s . sa m p l e e d g e da i _ p 2 0 - 1 ( s cl k) da i _ p 2 0 - 1 (fs ) t si sf s t si h f s t i p dcl k d a i _p 20 - 1 ( s dat a) t i p dcl kw t sis d t si hd figure 21. i dp master timing r e v . 0 | p a ge 33 of 48 | j une 2007
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p a r allel d ata a c qu isitio n p o r t (p d a p ) the ti mi ng requirement s for t h e p d a p ar e prov i de d i n ta ble 3 2 . pd ap is the parall el mode operation of channel 0 of the idp. for de tai l s on th e opera t ion of the pdap, se e the pdap ch apte r of the ads p -21368 s h arc processor hardware table 32. parallel data acquisition port (pdap) reference . not e tha t th e most si gni f icant 16 bi ts of exte rnal pda p data ca n be provi d ed t h rough the da ta31C 16 pins. the rema in in g four bi ts can on ly be sourced through dai_p4C1. the timing below is vali d at the data31C16 p i ns. p a r a me te r min m a x uni t timi ng re qu ire m en t s t sp cl ke n 1 p d a p _ cl k en setu p bef o r e pd ap _c lk s a mple e d g e t hpcl ken 1 pd ap _c lke n hold a f ter pd ap _c lk s a mple edg e t pds d 1 pd ap _d a t s e tu p b e f o re s c l k pd ap_ c l k s a mple edg e t pdhd 1 pd ap _d a t hold af t e r sc lk p d ap _ c l k s a mple edg e t pdclk w cloc k w i dth t pdclk cloc k p e riod s w i t ch ing char ac teristics t pdhldd d e lay of p d ap st r obe a f ter last pd ap_ c l k capt ur e edg e f o r a w o r d t pds t rb p d a p s t ro b e pu l s e w i d t h 2. 5 2 . 5 3 . 8 5 2 . 5 7 24 2 t pc l k + 3 2 t pc l k C 1 n s n s ns n s ns ns n s ns 1 s o u r c e pin s of d a ta ar e d a ta 3 1 C 1 2 or d a i pin s. s o urce pins for sc lk and f s are: 1) dai pins, 2) clkin t h rough pc g, or 3) dai p ins t h rough pc g. da i _ p 2 0 - 1 ( p da p _ c l k) da i _ p 2 0 - 1 ( p da p _ cl ke n ) dat a da i _ p 2 0 - 1 ( p dap _ s t r o b e) sa mp le ed g e t pd sd t pdh d t sp c l ke n t hp c l ke n t pdc l kw t pd strb t pd hl dd t pdc l k figure 22. p dap timing r e v . 0 | p a ge 34 of 48 | j une 2007
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p u lse- w i dth modulation gener a tor s (pw m ) t h e follo wi ng ti mi ng speci fica t io ns a pply w h en th e data31- 16 pi ns a r e co nfi g ured a s pwm. t ab l e 33. puls e-w idt h m o du lati on (pwm ) ti mi ng p a r a m e t e r m in m a x un it s w i t ch ing char ac teristics t pwmw pwm output p u lse w i dth t pwmp pwm output p e riod t pc lk C 2. 5 2 t pcl k C 2 . 5 ( 2 16 C 2 ) t pcl k C 2 . 5 ( 2 16 C 1 ) t pcl k C 2 . 5 n s n s pw m ou t p u t s t pw m w t pw m p figure 23. p wm timing r e v . 0 | p a ge 35 of 48 | j une 2007
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s/p d if t r ansmitt e r seria l dat a input to th e s/pdif transmi tte r can be forma tted as left j u stifie d, i 2 s, or righ t just ifie d wi th word widths of 16-, 18-, 20-, or 24-bits. the f o llowing se ct ions prov id e tim i n g for th e transmi tter. s/ p d i f t r a n smit t e r -s e ria l i n p u t w a vef o rms fi gur e 24 shows the right-justified mo de . lrclk is h i gh f o r th e left channel and low for the rig h t channel. d a ta is valid on the r i si ng edge o f sclk. t h e msb i s dela yed 12- b i t clo ck peri od s (in 20-b i t output mode) or 16-bi t clock pe ri ods (i n 16-b i t output dai _ p2 0 -1
lrc l k
dai _p 20- 1
scl k
dai _p 20- 1
sd a t a
mode) from a n lrc lk tra n si tion, so th at w h en th ere are 64 sclk per i ods per lrclk period, the lsb of t h e data will be righ t-justifi ed to th e ne xt l rclk t r a n si tion. l e f t ch anne l r i g ht chann e l m s b - 1 m sb - 2 l sb + 2 l sb + 1 l sb m sb m sb - 1 m sb - 2 l s b + 2 l sb + 1 l sb ls b ms b figure 24. r ight-ju s tified mode fi gur e 25 s h ows th e de fa ult i 2 s- just i f ie d mo de . lrclk is lo w fo r the left channel and hi for the r i gh t ch a nnel. data is vali d o n the rising edge of sclk. the msb is left-justified to an lrclk transiti on but w i th a si ngle scl k period dela y. dai _p 20- 1
lrc l k
dai _p 20- 1
scl k
dai _p 20- 1
sd a t a
ms b - 1 m s b - 2 l s b + 2 l s b + 1 l s b l e f t c hannel m s b m s b- 1 m s b- 2 l s b + 2 l s b+ 1 l s b ms b ms b ri g ht chan ne l figure 25. i 2 s-justified mode fi gur e 26 s h ows th e left- j usti fied mo de . lrclk is hi gh fo r t h e left channel and l o f o r the right channel. d a ta is valid on the ri sing edge of sclk . the msb is le f t -justifie d to an lrclk transiti on wi th no msb delay. dai _ p 20- 1
lrc l k
dai _ p 20- 1
scl k
dai _ p 20- 1
sd a t a
l e f t chan ne l ri g ht ch a nne l ms b - 1 ms b - 2 ls b + 2 l s b + 1 ls b ms b m s b - 1 ms b - 2 ls b + 2 l s b + 1 l s b ms b ms b + 1 ms b figure 26. l eft-justified mode r e v . 0 | p a ge 36 of 48 | j une 2007
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s / pdif t r an s m i t ter input d a t a t i m i ng th e ti mi ng requirement s for the s/pdif transmi tter a r e gi ven in ta ble 3 4 . input signals (sclk, fs, sdata) are routed to t h e dai_p20C 1 pi ns using the sru. there f ore, t h e t i ming specifica- tions p r ovided below ar e va lid at the dai_p20C1 pins. table 34. s/pdif transmitter in put d a ta timin g p a r a m e t e r m in m a x un it timi ng re qu ire m en t s t sis f s 1 f s s e t u p b e fo re s c l k r i s i ng e d g e 3 n s t sih f s 1 f s h o l d af t e r s c l k r i s i n g e d g e 3 n s t sis d 1 s d at a s e t u p b e f o re s c l k r i s i n g e d g e 3 n s t sih d 1 sda t a hold a f t e r sclk r i sing edge 3 n s t sit x c l kw t r ansmit cl oc k w i dth 9 ns t sit x c l k t r ansmit cl oc k p e riod 20 ns t sis c l k w cl oc k w i dth 3 6 n s t sis c l k cl oc k p e riod 80 ns 1 dat a, sc lk, fs can come from any of the da i pi ns . sc lk and f s c a n als o come via pc g or sport s . pcg s input c a n be either clk i n o r a ny of t h e dai pins. dai_ p 20- 1 (s c l k ) dai_ p 20- 1 (f s) sa m p l e e d g e t sis d t si s f s t si s c l k w dai_ p 20 - 1 (s da t a ) dai_ p 20- 1 (tx c lk ) t si h d t sih f s t s i t x cl kw t si t x cl k t si sc l k fig u re 2 7 . s / p dif tra n smi tter input tim i ng o v ers a mpli n g c l o c k ( t xc l k ) s w it chi n g c h ar a c t e risti c s th e s/ pdif transmitte r ha s an ov er sa mplin g clo c k. th is tx clk input is divi ded down to gene ra te th e bi pha se clock . table 35. over sampli ng clock (txclk) swit chin g charac teris t ic s p a r a m e t e r min ma x u ni t t x clk f r equenc y f o r t x clk = 3 8 4 fs 73 .8 mh z t x clk f r equenc y f o r t x clk = 2 5 6 fs 49 .2 mh z fr a m e r a t e 19 2.0 k h z r e v . 0 | p a ge 37 of 48 | j une 2007
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s/p d if r e c e iv er the fol lowing se ction describes timing as i t re late s to t h e s/pdif receiver. in t e r n a l d i g i t a l p l l mo d e in th e internal digit a l pha se-lock e d loop mode th e internal pll (digital p ll) generates the 512 fs clo c k. table 36. s/pdif receiver inte rn al di git al pll m o de ti mi ng p a r a meter m i n max u ni t s w i t ch ing char ac teristics t dfs i lr cl k d e l a y af t e r sc l k t ho fsi lr cl k hold af t e r s c lk t dd ti t r ansmit data delay a f ter scl k t hd ti t r a n s m i t d a t a h o l d af te r s c l k t sc l k iw 1 t r ansm i t sc l k w i dt h C 2 C 2 3 8. 5 5 5 n s ns n s n s n s 1 s c l k f r eq u e nc y is 6 4 fs whe r e f s = th e fr e q u e n c y of l r c l k. dai _p 2 0 - 1 ( s cl k) dai _p 2 0 - 1 (f s ) dai _p 2 0 - 1
( data channe l a/ b)
dr i v e e dg e s a m p l e e d g e t sc l k iw t dfs i t dd t i t ho f s i t hd t i figure 2 8 . s /p dif r e cei ve r in te rna l digi ta l pll mo de t i m i n g r e v . 0 | p a ge 38 of 48 | j une 2007
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sp i inter f ac emaster the adsp-21371 contains two spi ports. both primary and sec- o nda ry ar e avai la ble t h r ough dpi o n ly . the t i mi ng pr ovid ed i n ta ble 3 7 an d ta ble 3 8 appli e s to both. table 37. spi interface protoc ol ma ster swit chin g and timin g speci f i cat ions pa r a m e t e r m i n m a x u n i t timi ng re qu ire m en t s t ss pidm data i n put v a lid t o spi c l k e d ge (data i n put setup t i me) 8 .2 ns t hs pidm s p i c l k l a s t s a mp l i n g e d g e t o d a t a i n p u t n o t v a l i d 2 n s s w i t ch ing char ac teristics t sp ic l k m serial clock c y cle 8 t pc lk C 2 n s t sp ic h m serial clock h i gh p eriod 4 t pc lk C 2 n s t sp ic l m serial clock l o w p e r i od 4 t pc lk C 2 n s t dds pidm sp icl k edg e t o data out v a lid (data out d e lay t i me) 2 .5 t hds p idm sp icl k edg e t o data out n o t v a lid ( d at a out hol d t i me) 2 ns t sd sc im fla g 3C0in ( s pi devic e selec t ) l o w t o f i rst spiclk edge 4 t pc lk C 2 n s t hds m last sp ic lk edg e to fl a g 3 C 0i n h i gh 4 t pc lk C 2 n s t sp itd m sequential t r ansf er dela y 4 t pc lk C 1 n s fl ag 3 - 0 (o u t p u t ) spi c l k (c p = 0 ) (o u t p u t ) spi c l k (c p = 1 ) (o u t p u t ) c p has e = 1 mo s i (o u t p u t ) mi s o ( i np ut ) c p has e = 0 mo s i (o u t p u t ) mi s o ( i np ut ) ls b va l i d ms b va l i d t ss pi d m t hs p i dm t hd spi d m ls b ms b t h spi dm t dd s p i d m t spi c h m t spi cl m t spi c l m t s p i cl km t spi ch m t hds m t spi t d m t hds p i dm ls b va l i d ls b ms b ms b va l i d t hspi d m t dds p i dm t ss pi d m t sd s c im t sspi dm figure 29. s pi master timing r e v . 0 | p a ge 39 of 48 | j une 2007
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sp i inter f ac eslav e table 38. spi interface protocol slav e swi tchin g an d ti mi ng spec ificat ion s pa r a m e t e r m i n m a x u n i t timi ng re qu ire m en t s t sp ic l k s serial clock c y cle t sp ic h s serial clock h i gh p eriod t sp ic l s serial clock l o w p e r i od t sd sc o sp id s asser t ion to f i rst spi c l k ed ge cp ha se = 0 cp ha se = 1 t hds last sp ic lk edg e to sp id s not a sser t ed , cphase = 0 t ss pids data i n put v a lid t o spi c l k edg e (data i n put s e t - up t i me) t hs pids sp icl k l a st sampling edg e t o data i n put n o t v a lid t sd ppw sp id s d e asser t ion p u lse w i dth ( c phase=0) s w i t ch ing char ac teristics t ds oe sp id s a s s e r t i o n t o d a t a o u t ac t i v e t ds dhi sp id s d e asser t ion to data h i g h i m pedance t dds pids sp icl k edg e t o data out v a lid (data out d e lay t i me) t hds p i d s sp icl k edg e t o data out n o t v a lid ( d at a ou t hold t i me) t ds ov sp id s asser t ion to da ta out v alid ( c phas e = 0) 4 t pc lk C 2 2 t pc lk C 2 2 t pc lk C 2 2 t pc lk 2 t pc lk 2 t pc lk 2 2 2 t pc lk 0 0 2 t pc lk 6 . 8 6.8 9 .5 5 t pc l k n s n s n s ns ns ns ns ns n s n s ns ns ns sp i d s ( i np ut ) sp i c l k (cp = 0 ) ( i np ut ) sp i c l k (cp = 1 ) ( i np ut ) mis o mo s i ( i np ut ) (out p u t ) cphas e = 1 mis o (out p u t ) mo s i ( i np ut ) cp has e = 0 t hs pi ds t dd spi d s t dsd h i ls b ms b ms b v a l i d t dso e t d d spi ds t hds pi ds t sspi d s t sdsc o t spi c h s t sp i c l s t sp ic l s t spi c l k s t hd s t sp i chs t ssp i d s t hspi d s t dsd h i ls b v a l i d msb ms b v a l id t dd spi d s t ssp i d s ls b v a l i d ls b t sd ppw t dso v t hds pi ds figure 30. spi slave t i ming r e v . 0 | p a ge 40 of 48 | j une 2007
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univ ersal asynchronous r e c e iv er- t r a nsm i tter ti on of i n te rnal u a rt interr upt s and th e externa l da ta ( u a r t ) p o r t r ec eiv e and t r ans m it t i ming operations. these latencies are ne gli g ib le at t h e data transmi s- sion rates for the uart. fi gur e 31 describes ua rt port re ceiv e an d t r a nsmi t o p erat i o n s . th e ma xi mum baud ra te is pclk/16 where p c lk = 1/t pc lk . as shown in fi gure 31 t h ere i s s o me lat e ncy bet w een the genera- table 39. u a r t port pa r a m e t e r m i n m a x u n i t timi ng re qu ire m en t t rx d 1 i nc o ming da ta p u lse w i dth 95 ns s w i t ch ing char ac teristic t rx d 1 i nc o ming da ta p u lse w i dth 95 ns 1 u a r t s ignal s r x d and t x d are ro uted t h rough dpi p14-1 pins using the sru. dp i _ p 1 4 - 1 [r x d ] da t a ( 5 - 8) in t e rna l u a r t r ec ei v e int e rru p t uart r e ce iv e bit s e t by dat a s t o p ; cl e a re d by f if o re ad st o p re c e iv e dpi_ p 1 4 - 1 [tx d ] da t a ( 5 - 8) st o p ( 1 - 2) i nt e rn al uar t t ra ns m i t in t e rru p t u art t r ans mit bit s e t by p ro g ram ; cl e a re d b y w rit e t o t rans mi t st a r t tr an s m i t figur e 3 1 . ua rt po rtr ec ei ve a n d tra n sm it ti mi ng r e v . 0 | p a ge 41 of 48 | j une 2007
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t w i c o ntr o ller t i ming ta ble 4 0 a nd figure 32 pro v id e ti mi ng in form at i o n for t h e tw i interface. input signals (scl , sda ) a r e routed to the dpi_p14C1 pins usi n g the sru. therefore , the timing specifica- t i ons p r ov i d e d b e l ow ar e va l i d a t t h e dp i_ p 14C 1 pi ns . table 40. charac teris t ic s of the sda and scl b u s lines for f/s - mode twi bus devic e s 1 p a r a me te r min standar d mode m ax min f a st mo de m a x u n it f sc l s c l clock f r equenc y 0 10 0 0 40 0 kh z t hds t a hold t i me (repeated) star t c o nd it ion. a f t e r this p e r i od , the f i rst clock p u lse is gener a t ed . 4. 0 0. 6 s t lo w l o w p e r iod of the sc l c l ock 4. 7 1. 3 s t hi gh h ig h p er i od o f the s c l clock 4. 0 0. 6 s t su st a setup t i m e f o r a repea t ed star t c o ndition 4 . 7 0. 6 s t hdd a t data hold t i me f o r t w i-bus devic e s 0 0 s t su d a t d a ta setup t im e 25 0 10 0 n s t su st o setup t im e f o r st op c o ndition 4. 0 0. 6 s t buf bus f r ee t im e be t w e en a s t op an d s t a r t c o ndition 4. 7 1. 3 s t sp p u lse w i dth of spikes sup pr e ssed by the i nput f i lter n/a n/a 0 50 n s 1 all value s refe rred to v ihm i n a n d v ilm a x le ve ls . fo r m o r e in for m a ti on , s e e el ec tr ical characteristics o n page 15. dp i _ p 1 4 - 1 sd a dp i _ p 1 4 - 1 sc l t lo w t hi g h t hd s t a t hd d a t t s uda t t su st o s t su s t a sr t sp t hds t a p s t bu f fig u re 32. fast and st andard mode timing on the twi bus r e v . 0 | p a ge 42 of 48 | j une 2007
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jt a g t e st a c c e ss p o r t a n d em u lation table 41. jt ag test access port and em ulation pa r a m e t e r timi ng re qu ire m en t s t tc k tc k pe r i o d t st ap tdi, tms setup b e f o r e t c k h i gh t ht ap tdi, tms hold af t e r t c k h i gh t ss y s 1 s y st em i n puts setup bef or e t c k h i gh t hs y s 1 s y st em i n puts hold a f ter t c k high t trst w trst p u lse w i dth s w i t ch ing char ac teristics t dt d o tdo dela y from t c k l o w t ds y s 2 s y st em outputs dela y a f ter t c k l o w m i n t ck 5 6 7 18 4 t ck m a x 7 t ck / 2 + 7 u n i t ns ns n s ns ns ns ns n s 1 s y st em input s = ad 15 C0 , c l kc f g 1C 0, re s e t , bootcf g1C0, dai_px, and f l ag3C0. 2 system outputs = dai_px, ad15C0, r d , wr , flag3 C0 , cl kou t , e m u , a n d al e. tc k tm s td i td o sy s t e m in p u t s sy s t em ou t p u t s t st ap t tc k t htap t dtdo t ssys t h sys t dsys fi gure 33 . i ee e 11 49.1 j t ag tes t ac ce ss p o r t r e v . 0 | p a ge 43 of 48 | j une 2007
) 10 th e ac si gna l specifica t ion s (t imi n g pa ra me ters) a ppear in table 15 on page 21 through tabl e 41 on p a ge 43 . these i n clude out p ut di sabl e time, output enabl e time, and ca pacit i ve loa d ing. the ti mi ng speci f i c ati o ns for the shar c apply for the v o lt age re f ere nce le vels in fi gur e 35 . fi gur e 34 sh ow s t y pi cal i-v ch ar act e ri stics for the output driv - ers of the ads p -21371. the curves repres ent the current drive capab i li ty of th e out p ut drive r s as a fun ction of o utput vo ltage. s o u u r r r c c e e ( ( v ) ) n t m a d d e x t adsp-21371
outpu t driv e c u rr en ts 40 30 20 3. 47v , - 4 5 c 3.3v, 2 5 c ca p a c i t i ve lo a d i n g output dela y s an d h o lds a r e ba sed on standard capac i tiv e loads: 30 pf on all pins ( s ee fi gure 35 ). figure 39 sh ow s grap hi cally how output dela ys a n d holds va ry wi th l o a d capa cita nce. the graphs of figure 37 , fi gure 38 , an d figure 39 m a y no t be li near outside the ranges shown for typical output de lay vs. load ca pa cita nce and typica l output rise time (20% to 80 %, v = mi n) vs. lo ad capa ci ta nce. 12 r s s e e a a n f t m ( ( n s ) i i d l l r i i s s e e a a n d f l l t m n s v oh 3 .3v, 2 5 c 3 . 1 1 v , 1 2 5c 3.1 1 v , 125 c v ol 3. 4 7v, - 45 c y = 0 . 046 7x + 1 .632 3 ri s fa l l e y = 0. 045 x + 1.5 2 4 10 0 - 10 8 - 20 6 - 30 4 - 40 0 0. 5 1 .0 1 . 5 2 .0 2 . 5 3 .0 3 . 5 sw ee p ( v dd e x t ) v ol t a ge (v ) 2 fi gur e 34 . adsp- 213 71 typ i c a l dr iv e at j u nct i on tem p er a ture t e st c o nditi o ns ti mi ng i s me asured o n sign als w h en the y cross the 1.5 v level a s de scr i bed in figur e 36 . a ll d ela ys (in na no seco nd s) ar e me a- sured b e twe e n t h e point th at th e first si gna l rea c hes 1.5 v a n d the poi n t t h at the s econd si gna l re ache s 1.5 v . 0 0 50 10 0 15 0 20 0 2 50 l o ad c ap a ci t an ce ( p f ) fi gure 37. typic a l out p ut ris e / f al l tim e (2 0% to 8 0 %, v dde xt = ma x) 12 ri s e y = 0.04 9x + 1 . 5 1 0 5 fa l l y = 0 . 0 482 x + 1.4 604 10 8 50 ? 6 to ou t p u t 1.5 v pi n 4 30 p f 2 0 0 5 0 1 00 1 50 2 0 0 250 fig u r e 3 5 . equ iv al en t d e vic e lo adi n g for ac mea s u r em en ts (in c l u d e s al l fi xtures ) l o ad capac it a n c e ( p f ) fi gure 38. typic a l out p ut ris e / f al l tim e (2 0% to 8 0 %, v ddex t = min) j une 2007 in p u t
or 1.5 v
1 . 5v ou t p u t fi gure 36 . v ol ta ge r e fer e nc e le ve ls for a c mea s urem en ts r e v . 0 | p a ge 44 of 48 |
ta ble 4 2 ai rf lo w measur em ent s com p ly with jede c standards jesd51- 2 a n d jesd5 1 -6 a n d the j u ncti on- t o- b o ar d m e a s ure- m e n t c o m p l i e s w i t h j e s d 5 1 - 8 . t e s t b o a r d d e s i g n c o m p l i e s w i t h jedec standards jesd51-7 (mqf p). the j u nction -to-case measurement complies with mi l- std-883. all measurements use a 2s2p jedec test board. the adsp-21371 p r ocessor is rate d for perf ormance over the temperature range specifi e d i n opera t in g cond iti o n s on page 15 . o o o u u t t p d d e l l a y r h ( n s ) t herma l char ac t e ristics to de termi n e the junct i on te mperat ure of th e dev i ce w h ile on th e applica t ion pc b, use: where: t j = j u nc tion temperatur e c t case = ca se t e mp er a t ur e ( c) measured at the top center of the package jt = j u ncti on -t o- top ( o f pa cka g e) ch aract eriza tion pa ram eter is the typi cal val u e from ta ble 4 2 . p d = power dissipation value s of ja are provi d ed for pack age compa r i son an d pc b d e si gn consi d er atio ns. ja can be used for a first o r der appr oxi- ma tio n of t j by t h e e q ua ti on : where: t a = a m b i ent temperature c value s of jc are provi d ed for package compari son and pc b d e si gn consi d er at io ns w h en an ext e rna l hea t si n k i s requi r ed. adsp-21371 values of jb are provi d ed for package comparison and p c b de sign considerati o ns. note tha t th e the r mal ch aracte ri stics v a l- 10 0 2 0 0 5 0 100 15 0 y = 0 . 048 8x - 1 . 5923 ues provided in ta ble 4 2 a r e mo de led v a lues. 8 table 42. thermal characteristics for 208-le ad mqfp 6 4 2 0 -2 -4 p a r a me te r c on di ti on t y p i c a l u n i t ja air f lo w = 0 m/s 3 0.82 c/w jm a air f lo w = 1 m/s 2 7.53 c/w jm a air f lo w = 2 m/s 2 6.22 c/w jc 1 4 . 0 4 c/w jt air f lo w = 0 m/s 2 .0 c/w jm t air f lo w = 1 m/s 2 .65 c/w jm t air f lo w = 2 m/s 3 .12 c/w l o ad ca p ac i t a nc e ( p f ) figur e 3 9 . t y p ic al out p ut de la y or hol d vs. lo ad capa ci ta nc e (at am bient tem p erat ure) t j = t case + ( jt p d ) t j = t a + ( ja p d ) r e v . 0 | p a ge 45 of 48 | j une 2007
adsp-21371
208-lead mqfp pinout table 43. 208 -lead mqfp pin assignment (numerically by lead number) p i n no . s ignal p in no . s ign al p in no . s ignal p in no . s ignal 1 v dd i n i t 53 v dd 10 5 v dd 15 7 v dd 2 d a t a 2 8 5 4 g nd 10 6 g nd 15 8 v dd 3 d a t a 2 7 5 5 v dde x t 10 7 v dd e x t 15 9 g nd 4 g nd 56 a d d r 0 1 0 8 sdca s 16 0 v dd 5 v dd e x t 57 a dd r 2 1 0 9 sdra s 16 1 v dd 6 d a t a 26 58 a dd r1 11 0 sdc ke 16 2 v dd 7 d a t a 2 5 5 9 a dd r4 11 1 s dw e 16 3 t d i 8 d a t a 2 4 6 0 a d d r 3 1 1 2 w r 16 4 t rst 9 d a t a 2 3 6 1 a dd r5 11 3 s d a1 0 16 5 t c k 1 0 gnd 6 2 g nd 11 4 g nd 16 6 g nd 11 v dd i n t 63 v dd 11 5 v dd e x t 16 7 v dd 1 2 d a t a 22 64 g n d 1 1 6 sdc l k 1 6 8 tms 1 3 d a t a 21 65 v dde x t 11 7 g nd 16 9 c lk_ c fg 0 1 4 d a t a 20 66 a dd r 6 11 8 v dd 17 0 b oo t c fg 0 15 v dd e x t 67 a d d r 7 1 1 9 rd 1 71 cl k _c f g 1 1 6 gn d 68 a dd r8 12 0 a c k 17 2 e mu 17 d a t a 1 9 6 9 ad dr 9 1 21 f l a g3 1 73 bo o t c f g1 1 8 d a t a 18 70 a dd r 1 0 12 2 f la g 2 17 4 t do 19 v dd i n t 7 1 gn d 1 23 f l a g1 1 75 d a i 4 20 g n d 7 2 v dd 12 4 f la g 0 17 6 d a i2 21 d a t a 1 7 7 3 gn d 1 25 d a i 20 1 77 d a i 3 22 v dd i n t 74 v dde x t 12 6 g nd 17 8 d a i 1 2 3 gn d 7 5 a dd r1 1 1 2 7 v dd 17 9 v dd e x t 24 v dd i n t 76 a d d r 1 2 12 8 g nd 18 0 g nd 2 5 gn d 7 7 a dd r1 3 1 2 9 v dd e x t 18 1 v dd 26 d a t a 1 6 7 8 gn d 1 30 d a i 19 1 82 gnd 2 7 d a t a 15 79 v dd 13 1 d a i 1 8 18 3 d p i 14 2 8 d a t a 14 80 nc 13 2 d a i 1 7 18 4 d p i 13 2 9 d a t a 13 81 nc 13 3 d a i 1 6 18 5 d p i 12 30 d a t a 1 2 8 2 gn d 1 34 d a i 15 1 86 dpi 1 1 31 v dd e x t 8 3 cl kin 1 35 d ai 1 4 1 87 dpi 1 0 32 g n d 8 4 x t a l 1 36 d a i 13 1 88 dpi 9 33 v dd i n t 85 v dde x t 13 7 d a i 1 2 18 9 d p i 8 34 g n d 8 6 gn d 1 38 v dd 19 0 d p i 7 3 5 d a t a 11 87 v dd 13 9 v dd e x t 19 1 v dd e x t 3 6 d a t a 10 88 a d d r 1 4 14 0 g nd 19 2 g nd 37 d a t a 9 8 9 gn d 1 41 v dd 19 3 v dd 38 d a t a 8 9 0 v dde x t 14 2 g nd 19 4 g nd 39 d a t a 7 9 1 a d dr 15 1 43 d a i 11 1 95 dpi 6 40 d a t a 6 9 2 a d dr 16 1 44 d a i 10 1 96 dpi 5 41 v dd e x t 93 a dd r 1 7 14 5 d a i8 19 7 d p i4 4 2 gn d 9 4 a dd r1 8 1 4 6 d a i9 19 8 d p i3 43 v dd i n t 95 g n d 14 7 d a i6 19 9 d p i1 44 d a t a 4 9 6 v dde x t 14 8 d a i7 20 0 d p i2 r e v . 0 | p a ge 46 of 48 | j une 2007
adsp-21371
table 43. 208 -lead mqfp pin assignment (num eric a lly by lea d nu mb er) (c on ti n u e d ) p i n no . s ignal p in no . s i g n al p in no . s ignal p in no . s ignal 45 d a t a5 9 7 ad d r 1 9 1 49 d ai 5 2 0 1 c l k out/ ~rese t out/ ~runrsti n 46 d a t a 2 9 8 a d dr 20 1 50 v dd e x t 20 2 r e se t 47 d a t a 3 9 9 a d dr 21 1 51 g n d 2 03 v dd e x t 4 8 d a t a 0 100 a dd r 2 3 15 2 v dd 20 4 g nd 4 9 d a t a 1 101 a d d r 2 2 15 3 g nd 20 5 d a t a 3 0 50 v dd e x t 102 ms1 15 4 v dd 20 6 d a t a 31 5 1 gnd 103 ms0 15 5 g nd 20 7 d a t a 2 9 52 v dd i n t 104 v dd 15 6 v dd 20 8 v dd r e v . 0 | p a ge 47 of 48 | j une 2007
rev. 0 | page 48 of 48 | june 2007 adsp-21371 ? 2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06176-0-6/07(0) outline dimensions the adsp-21371 is available in a 208-lead pb-free mqfp package. ordering guide figure 40. 208-lea d mqfp (s-208-2) model temperature range 1 1 referenced temperature is ambient temperature. on-chip sram rom operating voltage package description package option adsp-21371ksz-2b 2 2 z = rohs compliant part 0 c to +70 c 1m bit 4m bit 1.2 int v/3.3 ext v 208-lead mqfp s-208-2 adsp-21371ksz-2a 2,3 3 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. for a complete list, visit our website at www.analog.com/sharc 0 c to +70 c 1m bit 4m bit 1.2 int v/3.3 ext v 208-lead mqfp s-208-2 0.20 0.09 3.60 3.40 3.20 0.50 0.25 0.08 max (lead coplanarity) view a rotated 90 ccw 1 208 157 156 105 104 53 52 top view (pins down) 0.50 bsc 28.00 sq bsc 0.27 0.17 (lead pitch) (lead width) seating plane 4.10 max 0.75 0.60 0.45 notes: 1. the actual position of each lead is within 0.08 from its ideal position when measured in the lateral direction. 2. center dimensions are typical unless otherwise noted. 3. dimensions are in millimeters and comply with jedec standard ms-029, fa-1. 30.60 sq bsc view a pin 1 indicator

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