differential clock buffer/driver cy2sstv8575 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07458 rev. ** revised october 30, 2002 tv8575 features ? operating frequency: 60 mhz to 170 mhz supports 266-mhz ddr sdram 5 differential outputs from 1 differential input spread spectrum compatible low jitter (cycle-to-cycle): < 75 very low skew: < 100 ps power management control input high-impedance outputs when input clock < 20 mhz 2.5v operation 32-pin tqfp jedec ms-026 c description the cy2sstv8575 is a high-performance, low-skew, low jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. the cy2sstv8575 generates five differential pair clock outputs from one differential pair clock input. in addition, the cy2sstv8575 features differential feedback clock outputs and inputs. this allows the cy2sstv8575 to be used as a zero-delay buffer. when used as a zero-delay buffer in nested clock trees, the cy2sstv8575 locks onto the input reference and translates with near zero delay to low-skew outputs. block diagram pin configuration 16 2 1 12 11 15 27 28 30 31 18 19 test and powerdown logic pll 5 6 21 22 fbi n fbin # clk clk# avdd 23 8 oe y0 y0# y1 y1# y2 y2# y3 y3# y4 y4# fbout fbout# tqfp-32 jedec ms-026 c y2# y2 vss vddq y1 y1# vss avss y0# y0 vddq ck ck# avdd vddq vddq vddq vss y4# y4 y3# y3 vddq vss vss oe fbin vddq fbout# vss fbin# fbout cy2sstv8575 12345678 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25
cy2sstv8575 document #: 38-07458 rev. ** page 2 of 8 pin description pin name i/o type description 5,6 clk, clk# i lv differential input differential clock input 21 fbin# i differential input feedback clock input . connect to fbout# for accessing the pll. 22 fbin i feedback clock input . connect to fbout for accessing the pll. 2,12,15,27,30 y(0:4) o differential outputs clock + outputs 1,11,16,28,31 y(0:4)# o clock ? outputs 18 fbout o differential outputs feedback clock output . connect to fbin for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. 19 fbout# o feedback clock output . connect to fbin# for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. 23 oe i output enable inpu t. when oe is set high, all q and q# outputs are enabled and switch at the same frequency as clk. when set low, all q and q# outputs are disabled (hi-z) and the pll is powered down. 3,4,7,13,20,26, 29 vddq 2.5v nominal 2.5v power supply for output clock buffers 8avdd2.5v nominal 2.5v power supply for pll . when avdd is at gnd, pll is bypassed and clk is buffered directly to the device outputs. during disable (oe = 0), the pll is powered down. 10,14,17,24,25, 32 vss 0.0v ground common ground 9 avss 0.0v analog ground analog ground table 1. function table inputs outputs pll avdd oe clk clk# y y# fbout fbout# gnd h l h l h l h bypassed/off gnd h h l h l h l bypassed/off xllhzz zz off xlhlzz zz off 2.5v h l h l h l h on 2.5v h h l h l h l on 2.5v h < 20 mhz < 20 mhz hi-z hi-z hi-z hi-z off
cy2sstv8575 document #: 38-07458 rev. ** page 3 of 8 power management functions output enable/disable control of the cy2sstv8575 allows the user to implement power management schemes into the de- sign. outputs are three-stated/disabled when oe is asserted low, see table 1 . the enabling and disabling of outputs is done in such a manner to eliminate the possibility of the partial ? runt ? clocks. zero delay buffer when used as a zero delay buffer the cy2sstv8575 will likely be in a nested clock tree application. for these applications the cy2sstv8575 offers a differential clock input pair as a pll reference. the cy2sstv8575 can lock onto the refer- ence and translate with near zero delay to low-skew outputs. for normal operation, the external feedback input, fbin, is connected to the feedback output, fbout. by connecting the feedback output to the feedback input the propagation delay through the device is eliminated. the pll works to align the output edge with tine input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when avdd is strapped low, the pll is turned off and by- passed for test purposes. figure 1. clock structure 1 [1] note: 1. output load capacitance for 2 ddr-sdram loads: 5 pf < cl < 8 pf. pll fbin fbin# 120 ohm 120 ohm clk clk# ddr - sdram 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr _sdram represents a capacitive load ddr - sdram fbout# fbout yx yx#
cy2sstv8575 document #: 38-07458 rev. ** page 4 of 8 figure 2. clock structure 2 [2] figure 3. differential signal using direct termination resistor governing agencies the following agencies provide specifications that apply to the cy2sstv8575. the agency name and relevant specification is listed below; agency name specification jedec ms - 026-c note: 2. output load capacitance for 4 ddr-sdram loads: 10 pf < cl < 16 pf. ddr-sdram pll fbin fbin# 120 ohm 120 ohm clk clk# ddr-sdram stack ddr-sdram stack 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr-sdram represents a capacitive load fbout# fbout ddr-sdram ddr-sdram ddr-sdram yx# yx 60 ohm receiver vcp vtr r t = 120 ohm vdd out out# vdd 60 ohm 14 pf 14 pf vdd/2 vdd/2
cy2sstv8575 document #: 38-07458 rev. ** page 5 of 8 absolute maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any volt- age higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd (v ddq voltage) unused inputs must always be tied to an appropriate logic volt- age level (either v ss or v ddq ) . notes: 3. unused inputs must be held high or low to prevent them from floating. 4. all outputs switching loaded with 16pf in 60 ? environment. see figure 3 . parameter description conditions min. max. unit v dd supply voltage non functional ? 0.3 3.5 vdc v dd operating voltage functional 2.38 2.63 vdc v in input voltage relative to vss ? 0.3 2.63 vdc v out output voltage relative to vss ? 0.3 2.63 vdc t s temperature, storage non functional ? 65 150 c t a temperature, operating ambient functional 0 +85 c ? jc dissipation, junction to case functional ? 18 c/w ? ja dissipation, junction to ambient functional ? 48 c/w esd h esd protection (human body model) ? 2k volts fit failure in time manufacturing test ? 10 ppm dc parameters (av dd = v ddo = 2.5 5%, temperature = 0 c to +85 c) parameter description conditions min. typ. max. unit v il input voltage, low [3] oe ?? 0.75 v v ih input voltage, high [3] 1.75 ?? v v ol output voltage, low v ddq = 2.375v, i ol = 12 ma ?? 0.6 v v oh output voltage, high v ddq = 2.375v, i oh = ? 12 ma 1.7 ?? v i ol output low current v ddq = 2.375v, v out = 1.2v 26 35 ? ma i oh output high current v ddq = 2.375v, v out = 1v 28 ? 32 ? ma i ddq dynamic supply current [4] all v ddq , fo = 170 mhz ? 235 300 ma. i pds power down current oe = 0 or clk/clk# < 20 mhz ?? 100 a. c in input pin capacitance ?? 4pf
cy2sstv8575 document #: 38-07458 rev. ** page 6 of 8 notes: 5. parameters are guaranteed by design and characterization. not 100% tested in production. 6. pll is capable of meeting the specified parameters while supporting ssc synthesizers with modulation frequency between 30 khz and 50 khz with a down spread of ? 0.5%. 7. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle = t wh /t c , where the cycle time (t c ) decreases as the frequency goes up. 8. refers to transition of non-inverting output. 9. all differential input and output terminals are terminated with 120 ? /16 pf as shown in figure 2 . ac input parameters (av dd = vddq = 2.5 5%, t a = 0 c to +85 c) parameter description conditions min. typ. max. unit f in input frequency 1.25 60 ? 170 mhz d tyc input duty cycle av dd , v dd = 2.5v0.2v 40 ? 60 % ac output parameters (avdd= vddq = 2.5 5%, temperature = 0 c to +85 c) [5,6] parameter description conditions min. typ. max. unit f or output frequency range av dd , v dd = 2.5v0.2v 60 ? 170 mhz t lock maximum pll lock time av dd , v dd = 2.5v0.2v ?? 100 s d tyc duty cycle [7] 60 mhz to 100 mhz 49.5 50 50.5 % 101 mhz to 170 mhz 49 ? 51 % t r rise time 20% to 80% of v od 1 ? 2v/ns t f fall time 20% to 80% of v od 1 ? 2v/ns t skew any output to any output skew [9] all outputs equally loaded ?? 100 ps t plh propagation delay (low to high) clk to y 1.5 3.5 6 ns t phl propagation delay (high to low) clk to y 1.5 3.5 6 ns t odis output disable time [8] all outputs ? 3 ? ns t oenb output enable time [8] all outputs ? 3 ? ns t jit(cc) cycle to cycle jitter all outputs @ 66 mhz ? 100 ?? 100 ps t phase phase error ? 150 ? 150 ps t jit(phase) phase error jitter all outputs @ 66 mhz ? 50 ? 50 ps
cy2sstv8575 document #: 38-07458 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimension all product and company names mentioned in this document may be the trademarks of their respective owners. ordering information part number package type product flow CY2SSTV8575AC 32-pin tqfp commercial, 0 to 85 c CY2SSTV8575ACt 32-pin tqfp -tape & reel commercial, 0 to 85 c 32-lead thin plastic quad flatpack 7 x 7 x 1.0 mm a32 51-85063-*b
cy2sstv8575 document #: 38-07458 rev. ** page 8 of 8 document history page document title: cy2sstv8575 differential clock buffer/driver document #: 38-07458 rev. ecn no. issue date orig. of change description of change ** 120711 10/31/02 rgl new data sheet
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