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description the M35080FP is a bitmap pattern display control ic can display on the screen. display frequency can operate in 3.3mhz to 20mhz, and is equipped with the analog rgb output (512 colors / 260k colors) and the digital rgb output (512 colors) function. moreover, 2 pages (horizontal 128 dot ? vertical 96 dots/page) display can be simultaneously performed on 1 screen.it uses a silicon gate cmos process and it housed in a 24-pin shrink sop package. features pixel composition ............ eight kinds (can be chosen from the following) ........................ horizontal 128 dots ? verical 96 dots ? 2 pages ........................ horizontal 192 dots ? verical 64 dots ? 2 pages ........................ horizontal 256 dots ? verical 48 dots ? 2 pages ........................ horizontal 384 dots ? verical 32 dots ? 2 pages ........................ horizontal 32 dots ? verical 384 dots ? 2 pages ........................ horizontal 48 dots ? verical 256 dots ? 2 pages ........................ horizontal 64 dots ? verical 192 dots ? 2 pages ........................ horizontal 96 dots ? verical 128 dots ? 2 pages rgb output .................................................................................... analog rgb output ...................................... rout, gout,bout number of colors displayed ........................................................ double-screen display (3 bits each of rgb) : 512 colors one-screen display (6 bits each of rgb) : 260 k colors digital rgb output .......................... r0 to r2, g0 to g2, b0 to b2, number of colors displayed ........................................................ one and double-screen display (3 bits each of rgb) : 512 colors bit map ram ....................................................... 1000h to 3affh .............................. 128 ? 96 ? 9 plans (r, g, b every 3 bit) ? 2 .................................................................. 221184 bit (27 kbyte) display input frequency range ....................................................... ................................... external input f osc = 3.3 mhz to 20 mhz horizontal synchronous input frequency .......................................................... h.sync = 10 khz to 20 khz output ports (combination port output) ........................................ ................. 4 ports (switches with r0, r1, r2 and blnk output) dac ................................................................. 6 bits ? 3 (r, g, b) operating voltage .................................................... 2.7 v to 3.3 v application liquid crystal display, plasma display, multi-scan monitor outline 24p2q-a pin configuration (top view) mitsubishi microcomputers M35080FP screen character and pattern display controllers rev.1.0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 lp nc v dd2 rout/g2 gout/g1 bout/g0 iref/b2 vg2/b1 vg1/b0 bin v ss1 v ss2 ac cs sck sin tck v dd1 p0/blnk p1/r2 M35080FP 11 12 p2/r1 p3/r0 14 13 vert hor
mitsubishi microcomputers M35080FP screen character and pattern display controllers 2 symbol lp v ss2 __ ac __ cs sck sin tck v dd1 p0/blnk p1/r2 p2/r1 p3/r0 hor vert v ss1 bin vg1/b0 vg2/b1 iref/b2 bout/g0 gout/g1 rout/g2 v dd2 nc input/ output output input input input input input output output output output input input output output output output output output pin name test output earthing pin auto-clear input chip select input serial clock input serial data input external clock power pin port p0 output blnk port p1 output r2 port p2 output r1 port p3 output r0 horizontal synchro- nous signal input vertical synchro- nous signal input earthing pin test pin reference voltage output 1 b0 reference voltage output 1 b1 reference voltage output 2 b2 analog b signal output g0 analog g signal output g1 analog r signal output g2 power pin nc pin description function test pin. open this pin. connect to gnd. when l , this pin resets the internal ic circuit. hysteresis input. built-in pull-up resistor. this is the pin for chip select input. set l level at serial data transmission. hysteresis input. __ at cs pin is l level, sda pin serial data is taken in when scl rises. hysteresis input. built-in pull-up resistor. this is the pin for serial input of display control register and display ram data. also, this pin output acknowledge signal. hysteresis input. nch open-drain output. this is the pin for external clock input. digital power supply. connect to +3v with the power pin. this is a general purpose port output at analog rgb output. outputs port output or blnk signal. outputs blnk signal at digital rgb output. this is the output port output at analog rgb output. outputs r2 signal at digital rgb output. this is the output port output at analog rgb output. outputs r1 signal at digital rgb output. this is the output port output at analog rgb output. outputs r0 signal at digital rgb output. input horizontal synchronous signal. (hysteresis input.) input vertical synchronous signal. (hysteresis input.) connect to gnd. test pin. connect to gnd. use reference voltage output 1 of dac for analog rgb output at analog rgb output. connect to capacitor. output b0 signal at digital rgb output. use reference voltage output 2 of dac for analog rgb output at analog rgb output. connect to capacitor. output b1 signal at digital rgb output. the pin connects resistors which convert voltage current at analog rgb output. output b2 signal at digital rgb output. output analog b signal at analog rgb output(current output). connect to load resistance. output g0 signal at digital rgb output. output analog g signal at analog rgb output(current output). connect to load resistance. output g1 signal at digital rgb output. output analog r signal at analog rgb output(current output). connect to load resistance. output g2 signal at digital rgb output. digital power supply. connect to +3v with the power pin. nc pin. open.
mitsubishi microcomputers M35080FP screen character and pattern display controllers 3 block diagram 7 6 8 23 4 sck sin v dd1 v dd2 3 input control circuit data control circuit display control register read-out control circuit display control circuit shift register display position detection circuit synchronous signal switching circuit h counter polality switching circuit output control circuit port output control circuit address control circuit timing generator ac 15 v ss1 2 v ss2 cs bit map ram (page a) bit map ram (page b) tck 13 hor 14 9 vert p0/blnk 10 p1/r2 11 p2/r1 12 p3/r0 22 rout/g2 21 gout/g1 20 bout/g0 5 16 bin 1 lp 19 18 (dac) 17 iref /b2 vg2 /b1 vg1 /b0
mitsubishi microcomputers M35080FP screen character and pattern display controllers 4 memory constitution address 0000 16 to 0007 16 are assigned to the display ram, ad- dress 1000 16 to 3aff 16 are assigned to bitmap ram. the internal circuit is reset and all display control registers (address 0000 16 to 0007 16 ) are set to "0" when the ac pin level is "l". and then, bit map ram is not erased and be undefinited. this memory has 2- page composition (an address is page a and page b community) fig.1 memory constitution (display control register) daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 pageonb pageona ym2 ym1 ym0 blank1 blank0 allon dspon width2 width1 width0 vsize1 vsize0 vp9 vp8 vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 hp9 hp8 hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 anadig2 anadig1 anadig0 syncck test polv polh mode2 mode1 mode0 dacon sblank3 sblank2 sblank1 sblank0 ptd3 ptd2 ptd1 ptd0 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address of the memory for page a, and the memory for page b. registers pageona and pageonb perform page control at the time of writing in data. for detail, refer to "data input example". memory constitution is shown in figure 1 to 10. note : address 0000 16 and 0004 16 to 0007 16 are page a and b common registers. the writing of data is made regardless of registers pageona and pageonb. as for addresses 0001 16 to 0003 16 , register of page a and page b exists for every page (common to an address.) when write data in the memory for page a, and write data in the memory for page b, set it as register pageona = 1 at register pageonb = 1. when both of pageona and pageonb are set to 1 , data can be simultaneously written in both the memory for page a, and the memory for page b. address 0xxx 16 other than addresses 0000 16 to 0007 16 are write-protected.
mitsubishi microcomputers M35080FP screen character and pattern display controllers 5 daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 1000 16 1001 16 1002 16 1003 16 1004 16 1005 16 1006 16 1007 16 1008 16 1009 16 100a 16 1206 16 1207 16 1208 16 12f9 16 12fa 16 12fb 16 12fc 16 12fd 16 12fe 16 12ff 16 1300 16 13ff 16 address fig.2 memory constitution (bit map ram (r0)) dot composition (daf to da0) at 128 dots ? 96 dots bit map ram (r0) data unused area dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 33 to 48 of line 1 dot 49 to 64 of line 1 dot 65 to 80 of line 1 dot 81 to 96 of line 1 dot 97 to 112 of line 1 dot 113 to 128 of line 1 dot 1 to 16 of line 2 dot 17 to 32 of line 2 dot 33 to 48 of line 2 dot 81 to 96 of line 95 dot 97 to 112 of line 95 dot 113 to 128 of line 95 dot 1 to 16 of line 96 dot 17 to 32 of line 96 dot 33 to 48 of line 96 dot 49 to 64 of line 96 dot 65 to 80 of line 96 dot 81 to 96 of line 96 dot 97 to 112 of line 96 notes : bit map ram (addresses 1000 16 to 3aff 16 ) has 2-page composition of the memory for page a, and the memory for page b. when write data in the memory for page a, and write data in the memory for page b, set it as register pageona = 1 at register pageonb = 1. when both of pageona and pageonb are set to 1 , data can be simultaneously written in both the memory for page a, and the memory for page b.
mitsubishi microcomputers M35080FP screen character and pattern display controllers 6 daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 1400 16 1401 16 16fe 16 16ff 16 1700 16 17ff 16 address daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 1800 16 1801 16 1afe 16 1aff 16 1b00 16 1fff 16 address bit map ram (r1) data unused area unused area bit map ram (r2) data fig.3 memory constitution (bit map ram (r1)) fig.4 memory constitution (bit map ram (r2)) dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96 dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96
mitsubishi microcomputers M35080FP screen character and pattern display controllers 7 daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 2000 16 2001 16 22fe 16 22ff 16 2300 16 23ff 16 address fig.5 memory constitution (bit map ram (g0)) bit map ram (g0) data unused area daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 2400 16 2401 16 26fe 16 26ff 16 2700 16 27ff 16 address fig.6 memory constitution (bit map ram (g1)) bit map ram (g1) data unused area daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 2800 16 2801 16 2afe 16 2aff 16 2b00 16 2fff 16 address fig.7 memory constitution (bit map ram (g2)) bit map ram (g2) data unused area dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96 dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96 dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96
mitsubishi microcomputers M35080FP screen character and pattern display controllers 8 daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 3000 16 3001 16 32fe 16 32ff 16 3300 16 33ff 16 fig.8 memory constitution (bit map ram (b0)) bit map ram (b0) data unused area daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 3400 16 3401 16 36fe 16 36ff 16 3700 16 37ff 16 address fig.9 memory constitution (bit map ram (b1)) bit map ram (b1) data unused area daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 3800 16 3801 16 3afe 16 3aff 16 3b00 16 3fff 16 address fig.10 memory constitution (bit map ram (b2)) bit map ram (b2) data unused area address dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96 dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96 dot composition (daf to da0) at 128 dots ? 96 dots dot 1 to 16 of line 1 dot 17 to 32 of line 1 dot 81 to 96 of line 96 dot 97 to 112 of line 96
mitsubishi microcomputers M35080FP screen character and pattern display controllers 9 000 16 001 16 002 16 003 16 004 16 005 16 006 16 007 16 008 16 009 16 00a 16 00b 16 00c 16 00d 16 00e 16 00f 16 010 16 011 16 012 16 013 16 014 16 015 16 016 16 017 16 018 16 019 16 01a 16 01b 16 01c 16 01d 16 01e 16 01f 16 020 16 021 16 022 16 023 16 024 16 025 16 026 16 027 16 028 16 029 16 02a 16 02b 16 02c 16 02d 16 02e 16 02f 16 2d0 16 2d1 16 2d2 16 2d3 16 2d4 16 2d5 16 2d6 16 2d7 16 2d8 16 2d9 16 2da 16 2db 16 2dc 16 2dd 16 2de 16 2df 16 2e0 16 2e2 e6 2e2 16 2e3 16 2e4 16 2e5 16 2e6 16 2e7 16 2e8 16 2e9 16 2ea 16 2eb 16 2ec 16 2ed 16 2ee 16 2ef 16 2f0 16 2f1 16 2f2 16 2f3 16 2f4 16 2f5 16 2f6 16 2f7 16 2f8 16 2f9 16 2fa 16 2fb 16 2fc 16 2fd 16 2fe 16 2ff 16 1 2 3 4 5 6 91 92 93 94 95 96 * the numerical value in a thick frame corresponds to lower 10-bits of bit map ram (r0 to r2, g0 to g2, b0 to b2) address. (n ram character number : 0 to 7) dot composition in 1 address (16 bits) is msb....................lsb 1 to 16 17 to 32 33 to 48 49 to 64 65 to 80 81 to 96 97 to 112 113 to 128 lines dots 000 16 001 16 002 16 003 16 004 16 005 16 006 16 007 16 008 16 009 16 00a 16 00b 16 00c 16 00d 16 00e 16 00f 16 010 16 011 16 012 16 013 16 014 16 015 16 016 16 017 16 2e8 16 2e9 16 2ea 16 2eb 16 2ec 16 2ed 16 2ee 16 2ef 16 2f0 16 2f1 16 2f2 16 2f3 16 2f4 16 2f5 16 2f6 16 2f7 16 2f8 16 2f9 16 2fa 16 2fb 16 2fc 16 2fd 16 2fe 16 2ff 16 1 2 3 4 5 6 187 188 189 190 191 192 1 to 16 17 to 32 33 to 48 49 to 64 lines dots pixel composition each bit of a bit map display consists of nine bit map ram (r0 to r2, g0 to g2, and b0 to b2.) color setup can be specified out of 512 kinds per dot. the bit map ram address corresponding to dot composition in case pixel composition is 128 dot x 96 dot is shown in fig. 11. and, the bit map ram address corresponding to dot composition in case pixel composition is 64 dot x192 dot is shown in fig. 12. in other pixel composition, the bit map ram is similarly assigned in an order from the dots 1 to 16 of line 1. fig.11 pixel composition (at 128 dots ? 96 dots) * the numerical value in a thick frame corresponds to lower 10-bits of bit map ram (r0 to r2, g0 to g2, b0 to b2) address. (n ram character number : 0 to 7) dot composition in 1 address (16 bits) is msb....................lsb fig.12 pixel composition (at 64 dots ? 192 dots)
mitsubishi microcomputers M35080FP screen character and pattern display controllers 10 writing to the memory(display control registers and bit map ram) for page a is disapproval. writing to the memory(display control registers and bit map ram) for page a is permission. writing to the memory(display control registers and bit map ram) for page b is disapproval. writing to the memory(display control registers and bit map ram) for page b is permission. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. register address 0000 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status memory writing control for page a. memory writing control for page b. pageona pageonb
mitsubishi microcomputers M35080FP screen character and pattern display controllers 11 address 0001 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status set "0" to this bit. can not be used. display off display on set "0" to this bit. can not be used. when set to r < 0, r = 0. same as g output and b output. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set the pixel composition. the blnk signal of the range set up by this register is outputted at the time of blank1, 0 = 0, and 0 (normal) setup. the measure against a character bend (test bit) control of blank signal. (a blank setup in a bit unit is possible). note 2 control of r, g and b output luminosity width0 width1 width2 dspon blank0 blank1 ym0 ym1 ym2 width2 width1 width0 pixel (horizontal ? vertical) 0 0 0 128 ? 96 dots 0 0 1 192 ? 64 dots 0 1 0 256 ? 48 dots 0 1 1 384 ? 32 dots 100 32 ? 384 dots 101 48 ? 256 dots 110 64 ? 192 dots 111 96 ? 128 dots blank1 blank0 blank signal 00 normal(control by register width 0 to 2) 0 1 control by bit map ram(r0) 1 0 control by bit map ram(g0) 1 1 control by bit map ram(b0) r = 2 n r n 2 n ym n 2 n = 0 2 n = 0 notes 1 : this register is consisted of 2 pages (address community) of the register for page a, and the register for page b. writing control to each page is performed by registers pageona and pageonb (address 0000 16 ). 2 : the bit map ram used for blank signal control is not applicable to color setup.
mitsubishi microcomputers M35080FP screen character and pattern display controllers 12 address 0002 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 register da status contents function remarks vp0 vp1 vp2 vp3 vp4 vp5 vp6 vp7 vp8 vp9 vsize0 vsize1 if vs is the vertical display start location, vs = h ? 2 n vp n h: cycle with the horizonal synchronizing pulse setting vertical start location . it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. 9 n = 0 0 1 2 3 4 5 6 7 8 9 a b c d e f notes 1 : this register is consisted of 2 pages (address community) of the register for page a, and the register for page b. wr iting control to each page is performed by registers pageona and pageonb (address 0000 16 ). 2 : set up the horizontal and vertical display start location so that display range may not exceed it. set the character code "1ff 16 " (blank without background) for the display ram of the part which the display range exceeds. setting vertical direction dot size it should be fixed to "0". can not be used. vsize1 0 0 1 1 vsize0 0 1 0 1 vertical direction size 1h/dot 2h/dot 3h/dot 4h/dot h : synchronous of horizontal direction pulse display area note 2 note 2 hs vs hor vert note 2 note 2 monitor display
mitsubishi microcomputers M35080FP screen character and pattern display controllers 13 address 0003 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status hp0 hp1 hp2 hp3 hp4 hp5 hp6 hp7 hp8 hp9 it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. it should be fixed to "0". can not be used. if hs is the horizontal display start location, hs = t ? 2 n hp n t: display clock setting horizontal start location 9 n = 0 display area note 2 note 2 hs vs hor vert note 2 note 2 monitor display notes 1 : this register is consisted of 2 pages (address community) of the register for page a, and the register for page b. wr iting control to each page is performed by registers pageona and pageonb (address 0000 16 ). 2 : set up the horizontal and vertical display start location so that display range may not exceed it. set the character code "1ff 16 " (blank without background) for the display ram of the part which the display range exceeds.
mitsubishi microcomputers M35080FP screen character and pattern display controllers 14 address 0004 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status set "0" to this bit. can not be used. hor pin is negative polarity hor pin is positive polarity vert pin is negative polarity vert pin is positive polarity set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. it synchronizes with a display ck rising and is port output (at the time of digital output setup). it synchronizes with a display ck falling and is port output (at the time of analog output setup). port p1 to p3 output (at the time of analog rgb output setup "l" fixation) r0 to r2 output (at the time of digital rgb output setup "h" fixation) set "0" to this bit. can not be used. set "0" to this bit. can not be used. mode0 mode1 polh polv test sblank0 sblank1 ptc13 polarity of hor pin polarity of vert pin test bit blnk signal output timing control (blnk signal). effective at the time of sblank1, 2 = 1, and 1 (blnk output) setup. p0/blnk pin output control. sblank2 : address 0007 16 p1 to p3 output control mode1 0 0 1 1 display mode priority is given to page a priority is given to page b 260 k colors display the average of page a and page b mode0 0 1 0 1 sblank1 0 0 1 1 p0/blnk pin output port p0 output can not be used can not be used blnk output sblank2 0 1 0 1
mitsubishi microcomputers M35080FP screen character and pattern display controllers 15 address 0005 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used.
mitsubishi microcomputers M35080FP screen character and pattern display controllers 16 address 0006 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. dac off (at the time of digital rgb output setup "l" fixation) digital rgb output mode (g0 to g2, b0 to b2 signal output) dac on (at the time of analog rgb output setup "h" fixation). analog rgb output mode (vg1, vg2, iref, rout, gout, and bout signal output) set "0" to this bit. can not be used. dacon dac on/off, and digital rgb/analog rgb output change
mitsubishi microcomputers M35080FP screen character and pattern display controllers 17 address 0007 16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 a b c d e f register da function contents remarks status "l" fixation at port output, negative polarity at blnk output. "h" fixation at port output, positive polarity at blnk output. "l" fixation at port output. "h" fixation at port output. "l" fixation at port output. "h" fixation at port output. "l" fixation at port output. "h" fixation at port output. refer to sblank1(0004 16 ). set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. set "0" to this bit. can not be used. ptd0 ptd1 ptd2 ptd3 sblank2 data control of p0 pin data control of p1 pin data control of p2 pin data control of p3 pin output control of p0/blnk pin
mitsubishi microcomputers M35080FP screen character and pattern display controllers 18 ? ? ? ? ? ? fig. 13 the example of a display at the time of a 2-page display display form M35080FP can display two pages, page a and page b, simulta- neously, as shown in figure 13. and,1 page of 260k color display can be displayed by piling up two pages completely. page a: register pageona (address 0000 16 ) set up by = "1." page b: register pageonb (address 0000 16 ) set up by = "1." example 1 example 2 page a (128 dots ? 96 dots) page a (128 dots ? 96 dots) page b (128 dots ? 96 dots) monitor display monitor display page b (128 dots ? 96 dots) notes 1: setup of display position, display size, etc. can be freely performed for every page. two pages can be displayed side by side vertically and horizon tally. 2: when the display area of two pages overlaps on the monitoring screen, registers mode0 and mode1 (address 0004 16 ) can perform four displays as follows. (1) priority is given to page a ................... the overlaped part gives priority to page a, and page b is not displayed. (2) priority is given to page b .................. the overlaped part gives priority to page b, and page a is not displayed. (3) 260 k colors display ............................ by overlaping two pages completely, 1 page of 260k color is displayed. rgb output is 6-bit(note 2)each setup. (4) the average of page a and page b ... the overlaped part averages and outputs the rgb output of two pages. notes 1. it becomes 512 color displays at the time of digital rgb output setup. 2. assignment of 6 bits each of rgb is as follows. mode1 0 0 1 1 display mode priority is given to page a priority is given to page b 260 k colors display(note 1) the average of page a and page b mode0 0 1 0 1 display number of pages 2 pages 2 pages 1 page 2 pages msb lsb r r2 page a r1 r0 r2 page b r1 r0 g g2 page a g1 g0 g2 page b g1 g0 b b2 page a b1 b0 b2 page b b1 b0
mitsubishi microcomputers M35080FP screen character and pattern display controllers 19 data input example data of bit map ram and display control registers can be set by the 16-bit serial input function. example of data setting is shown in figure 14. fig. 14 example of data setting da0 da1 daf dae dad dac dab daa da9 da8 da7 da6 da5 da4 da3 da2 address/data remarks 000 0000000000000 0000000000000011 0000000000000000 0000000000000000 0000000000000001 0 vsize1 vsize0 0 0 0 vp9 vp8 vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 000000hp9hp8hp7hp6hp5hp4hp3hp2hp1hp0 0000000000 0 polv polh mode2 mode1 mode0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 sblank 3 sblank 2 sblank 1 sblank 0 ptd3 0001000000000000 bit map ram (page a) (r0,r1,r2,g0,g1,g2,b0,b1,b2) bit map ram (pageb) (r0,r1,r2,g0,g1,g2,b0,b1,b2) 0000000000000000 0000000000000010 0 vsize1 vsize0 0 0 0 vp9 vp8 vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 000000hp9hp8hp7hp6hp5hp4hp3hp2hp1hp0 0001000000000000 0000000000000000 0000000000000011 0000000000010000 address setting address setting page a and b display off page a and b writing setting (note 1) page a and b writing setting page a writing setting page b writing setting display form setting ? dac setting port output setting address setting address setting address setting address setting display on bit map setting vertical display location setting horizontal display location setting page a vertical display location setting horizontal display location setting page b page b bit map setting page a address 0000 16 data 0000 16 data 0001 16 address 0000 16 data 0007 16 data 0006 16 data 0005 16 data 0004 16 data 0003 16 data 0002 16 data 0000 16 address 1000 16 data 1001 16 data 1000 16 data 3aff 16 data 3afe 16 address 0000 16 address 1000 16 address 0000 16 data 0001 16 data 0000 16 data 3aff 16 data 3aff 16 data 1001 16 data 1000 16 data 0003 16 data 0002 16 data 0000 16 notes 1. registers pageona and pageonb perform writing control of data. 2. input the clock with which the cycle was fixed and continued from the tck pin. moreover, input horizontal synchronized signa l into hor pin, and input vertical synchronized signal into vert pin. ............ ............
mitsubishi microcomputers M35080FP screen character and pattern display controllers 20 fig.15 example of the M35080FP peripheral circuit (at analog rgb output setting) fig.16 example of the M35080FP peripheral circuit (at digital rgb output setting) 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 lp v ss2 ac cs sck sin tck v dd1 p0/blnk p1/r2 nc v dd2 rout/g2 gout/g1 bout/g0 iref/b2 vg2/b1 vg1/b0 bin v ss1 +3v +3v r g b + ? + ? ? + M35080FP 11 p2/r1 12 p3/r0 14 13 vert hor blank 100 f 1f 0.01 f 100 f 1f 0.01 f 1 f synchronous signal generator microcomputer external clock horizontal synchronors signal (3v) vertical synchronors signal (3v) mixing video pre-amp 0.1 f 0.1 f 1.2k ? 300 ? output buffer 100 f 1 f 0.01 f 100 f 1 f 0.01 f 1 f synchronous signal generator microcomputer external clock horizontal synchronors signal (3v) vertical synchronors signal (3v) mixing video pre-amp 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 lp v ss2 ac cs sck sin tck v dd1 p0/blnk p1/r2 nc v dd2 rout/g2 gout/g1 bout/g0 iref/b2 vg2/b1 vg1/b0 bin v ss1 +3v +3v r1 g0 b1 + ? + ? ? + M35080FP 11 p2/r1 12 p3/r0 14 13 vert hor blank r2 r0 g2 g1 b0 b2
mitsubishi microcomputers M35080FP screen character and pattern display controllers 21 data input serial data input timing (1) serial data should be input with the lsb first. (2) the address consists of 16 bits. (3) the data consists of 16 bits. __ (4) the 16 bits in the sck after the cs signal has fallen are the address, and for succeeding input data, the address is incremented every 16 bits. therefore, it is not necessary to input the address from the second data. fig.17 serial input timing address(16 bits) data(16 bits) n data(16 bits) n + 1 cs n = 1,2,3 ??? sck sin lsb msb lsb msb lsb msb
mitsubishi microcomputers M35080FP screen character and pattern display controllers 22 timing requirements (v dd = 3 0.30 v, ta = ? 20 to +85 c, unless otherwise noted) serial data input fig.18 serial input timing ns ns s ns ns s parameter limits max. 200 200 2 200 200 10 typ. ? ? ? ? ? ? max. ? ? ? ? ? ? unit remarks refer to fig 18 symbol tw(sck) ___ t su(cs) ___ t h(cs) t su(sin) t h(sin) t word sck width ____ cs setup time ____ cs hold time sin setup time sin hold time 1 word write time t su(cs) t w(sck) t w(sck) t su(sin) t h(sin) t h(cs) t w(cs) 1 s (min.) t word more than 2 s 1 2 12 13 14 15 16 ? 1 1213141516 ? cs sck sin sck cs
mitsubishi microcomputers M35080FP screen character and pattern display controllers 23 parameter supply voltage supply current (at analog output) ? h ? level output voltage ? l ? level output voltage __ pull-up resistance ac external clock input width full scale width nonlinear nature error symbol v dd v i v o p d t opr t stg parameter supply voltage input voltage output voltage power dissipation operating temperature storage temperature conditions with respect to v ss . ta = +25 c ratings ? 0.3 to +4.2 v ss ? 0.3 v i v dd +0.3 v ss v o v dd +70 ? 20 to +85 ? 40 to +125 unit v v v mw c c min. 2.7 0.8 v dd 0 10.0 10.0 typ. 3.00 v dd 0 ? ? max. 3.3 v dd 0.2 v dd 20.0 20.0 unit v v v mhz khz supply voltage "h" level input voltage "l" level input voltage oscillating frequency for display horizontal synchronous signal input frequeney v dd v ih v il f osc h.sync __ __ sin, sck, cs, ac, hor, vert __ __ sin, sck, cs, ac, hor, vert min. 2.70 ? 2.2 ? 10 0.7 v dd ? ? typ. 3.00 15 ? ? ? ? 1.0 ? max. 3.30 25 ? 0.5 100 v dd ? 2.0 unit v ma v v k ? v vp-p lsb test conditions ta = ? 20 to +70 c v dd = 3.00v v dd = 2.70v, i oh = ? 1ma v dd = 2.70v, i ol = 1ma v dd = 3.00v r iref =1.2k ? , r l =300 ? r iref =1.2k ? , r l =300 ? v dd i dd v oh v ol r i v tck v dao n l p0 to p7,r0 to r2 g0 to g2,b0 to b2 p0 to p7,r0 to r2 g0 to g2,b0 to b2 rout,gout,bout rout,gout,bout absolute maximum ratings (v dd = 3.00v, ta = ? 20 to +85 c, unless otherwise noted) recommended operating conditions (v dd = 3.00v, ta = ? 20 to +85 c, unless otherwise noted) electrical characteristics (v dd = 3.00v, ta = 25 c, unless otherwise noted) symbol limits parameter limits symbol
mitsubishi microcomputers M35080FP screen character and pattern display controllers 24 __ fig.19 timing of power supplying to ac pin note for supplying power (1) __ timing of power supplying to ac pin the internal circuit of M35080FP is reset when the level of the __ auto clear input pin ac is ? l ? . this pin in hysteresis input with the pull-up resistor. __ the timing about power supplying of ac pin is shown in figure be- low. after supplying the power (v dd and v ss ) to M35080FP and the supply voltage becomes more than 0.8 v dd , it needs to keep __ v il time; tw of the ac pin for more than 1ms. __ start inputting from microcomputer after ac pin supply voltage becomes more than 0.8 v dd and keeping 200ms wait time. precaution for use notes on noise and latch-up in order to avoid noise and latch-up, connect a bypass capacitor ( 0.1f) directly between the v dd1 pin and v ss1 pin, and the v dd2 pin and v ss2 pin using a heavy wire. notes on the time of external clock input to tck pin input the continuous external clock which cycle is fixed and syn- chronized with horizontal synchronized signal from tck pin. and, input continuous horizontal synchronized signal which cycle is fixed from hor pin. do not stop clock input absolutely during dis- play. (2) timing of power supplying to v dd1 and v dd2 . supply power to v dd1 and v dd2 at the same time. v dd 0.8 v dd 0.2 v dd t w t s voltage [v] supply voltage time t [s] data input disable v ac (ac pin input voltage)
mitsubishi microcomputers M35080FP screen character and pattern display controllers 25 ssop24-p-300-0.80 weight(g) e jedec code 0.2 eiaj package code lead material cu alloy 24p2q-a plastic 24pin 300mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 e e .3 0 0 .18 0 .0 10 .2 5 e .5 7 .4 0 e e e .27 1 .1 0 e .8 1 .35 0 .2 0 .1 10 .3 5 .8 0 .8 7 .6 0 .25 1 e .62 7 e .2 0 .1 2 e .45 0 .25 0 .2 10 .4 5 e .1 8 .8 0 e .1 0 e b 2 e.5 0e e 0 package outline
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rev. rev. no. date 1.0 first edition 0203 M35080FP data sheet (1/1) revision description revision description list

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