View LC78681KE_5775346.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ordering number : en4969 20695th (ot) no. 4969-1/24 overview the LC78681KE and LC78681KE-l are signal processing and servo control cmos lsis for compact disk players, laser disk players, cd-v, cd-i and similar applications. these products provide a rich set of signal processing functions, including demodulation of the efm signal from the optical pickup, de-interleaving, error detection and correction, and digital filter functions that can contribute to end product cost reduction. these lsis also process servo system commands sent from a control microprocessor. they can be directly interfaced to a serial input dac (such as the sanyo lc78835k or lc78855k) that provides built-in dedicated digital filters. functions input signal processing: the LC78681KE takes an hf signal as input, digitizes (slices) that signal at a precise level, converts that signal to an efm signal, and generates a pll clock with an average frequency of 4.3218 mhz by comparing the phases of that signal and a vco output. precise reference clock and necessary internal timing generation using an external 16.9344 mhz crystal oscillator disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock frame synchronization signal detection, protection and interpolation to assure stable data readout efm signal demodulation and conversion to 8-bit symbol data subcode data separation from the efm demodulated signal and output of that data to an external microprocessor subcode q signal output to a microprocessor over the serial interface after performing a crc error check (an lsb first output format can be selected.) demodulated efm signal buffering in internal ram to handle up to ? frames of disk rotational jitter demodulated efm signal reordering in the prescribed order for data unscrambling and de-interleaving error detection, correction, and flag processing (error correction scheme: dual c1 plus dual c2 correction) the LC78681KE sets the c2 flags based on the c1 flags and a c2 check, and then performs signal interpolation or previous value hold depending on the c2 flags. the interpolation circuit uses a quadruple interpolation scheme. the output value is locked at zero when four or more consecutive c2 flags occur. support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input) built-in digital output circuits. arbitrary track counting to support high-speed data access zero cross muting double speed dubbing support supports most d/a converters built-in digital level and peak meter functions support for bilingual applications features 64-pin qfp (miniature, reduced space package) silicon gate cmos process (low power) provision of a demo pin eases the manufacturing processes associated with adjustment steps. low voltage operation (LC78681KE-l) LC78681KE, 78681ke-l sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan digital signal processor for compact disc players cmos lsi any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
package dimensions unit: mm 3159-qfp64e equivalent circuit block diagram no. 4969-2/24 LC78681KE, 78681ke-l sanyo: qfp64e [LC78681KE, 78681ke-l]
pin assignment specifications absolute maximum ratings at ta = 25?, v ss = 0 v no. 4969-3/24 LC78681KE, 78681ke-l parameter symbol conditions ratings unit maximum supply voltage v dd max v ss 0.3 to +7 v maximum input voltage v in max v ss 0.3 to v dd + 0.3 v maximum output voltage v out max v ss 0.3 to v dd + 0.3 v allowable power dissipation pd max 300 mw operating temperature topr 30 to +75 c storage temperature tstg 40 to +125 c top view
allowable operating ranges at ta = 25 c, v ss = 0 v note: * this value differs between the LC78681KE and the LC78681KE-l. the only difference between these products is the minimum value of the supply voltage v dd , as listed in the table below. electrical characteristics at ta = 25 c, v ss = 0 v, v dd = 5 v no. 4969-4/24 LC78681KE, 78681ke-l parameter symbol conditions min typ max unit supply voltage v dd v dd * 5.5 v v ih (1) test1 to 5, ai, fzd, hfl, demo, m/l, res 0.7 v dd v dd v input high level voltage v ih (2) sbck, rwc, coin, cqck, cs 2.2 v dd v v ih (3) efmin 0.6 v dd v dd v v ih (4) tes 0.8 v dd v dd v v il (1) test1 to 5, ai, fzd, hfl, demo, m/l, res v ss 0.3 v dd v input low level voltage v il (2) sbck, rwc, coin, cqck, cs v ss 0.8 v v il (3) efmin v ss 0.4 v dd v v il (4) tes v ss 0.2 v dd v data setup time t setup coin, rwc: figure 1 400 ns data hold time t hold rwc: figure 1 400 ns high level clock pulse width t w h sbck, cqck: figures 1, 2 and 3 400 ns low level clock pulse width t w l sbck, cqck: figures 1, 2 and 3 400 ns data read access time t rac figures 2 and 3 0 400 ns command transfer time t rwc rwc: figure 1 1000 ns subcode q read enable time t sqe figure 2, with no rwc signal 11.2 ms subcode read cycle t sc figure 3 136 s subcode read enable time t se figure 3 400 ns crystal oscillator frequency fx tal xin, xout 16.9344 mhz operating frequency range fop (1) ai 2.0 20 mhz fop (2) efmin: v in 1 vp-p 10 mhz parameter symbol conditions min typ max unit supply current i dd 17 30 ma i ih (1) ai, efmin, fzd, tes, sbck, coin, cqck, res, 5a input high level current hfl, rwc, m/l: v in = v dd i ih (2) test1 to 5, demo, cs: v in = v dd = 5.5 v 25 75 a input low level current i il (1) ai, efmin, fzd, tes, sbck, coin, cqck, res, 5a hfl, rwc, m/l: v in = v ss ao, pdo,efmo, efmo, clv + , clv , focs, fseq, v oh (1) pck, toff, tgl, thld, jp + , jp , emph, eflg, v dd 1v fsx, v/p: i oh = 1 ma output high level voltage v oh (2) dout: i oh = 12 ma v dd 0.5 v laser, sqout, 16m, 4.2m, cont, lrclk, wrq, v oh (3) c2f, daclk, sfsy, lrsy, sbsy, ck2, pw, romout, v dd 1v c2fclk, dfout, test7, wclk: i oh = 0.5 ma ao, pdo, efmo, efmo, clv + , clv , focs, fseq, v ol (1) pck, toff, tgl, thld, jp + , jp , emph, eflg, 1 v fsx, v/p: i ol = 1 ma v ol (2) dout: i ol = 12 ma 0.5 v output low level voltage laser, sqout, 16m, 4.2m, cont, lrclk, wrq, v ol (3) c2f, daclk, sfsy, lrsy, sbsy, ck2, pw, romout, 0.4 v c2fclk, dfout, test7, wclk: i ol = 2 ma v ol (4) fst: i ol = 5 ma 0.75 v output off leakage current i off (1) pdo, fst: v oh = v dd 5a i off (2) pdo, fst: v ol = v ss 5a normal speed playback double speed playback LC78681KE 4.5 v 4.5 v LC78681KE-l 3.0 v 3.3 v
waveform figure 1 command input figure 2 subcode q output figure 3 subcode output no. 4969-5/24 LC78681KE, 78681ke-l
pin functions no. 4969-6/24 LC78681KE, 78681ke-l no. name i/o description 1 test1 i lsi test pin. normally left open. 2ao o 3ai i 4 pdo o 5v ss gnd 6 efmo o 7 efmo o 8 efmin i 9 test2 i lsi test pin. normally left open. 10 clv + o disk motor control output. 11 clv o 12 v/p o outputs a high level during clv rough servo and a low level during phase control. 13 focs o 14 fst o 15 fzd i 16 hfl i 17 tes i 18 pck o pck is the 4.3218 mhz monitor pin. 19 fseq o fseq outputs a high level when the synchronization (positive fs) detected from the efm signal matches the counter synchronization (interpolation fs). (the output is latched for a single frame.) 20 toff o 21 tgl o 22 thld o 23 test3 i lsi test pin. normally left open. 24 v dd +5 v 25 jp + o 26 jp o 27 demo i sound output function for end product adjustment manufacturing steps. 28 test4 i lsi test pin. normally left open. 29 emph o de-emphasis is required when high. 30 nc no connection 31 wclk o signal used for signal output to the d/a converter, latch signal and l/r switching, and sample and hold. 32 test7 o lsi test pin. normally left open. 33 lrclk o signal used for signal output to the d/a converter, latch signal and l/r switching, and sample and hold. 34 nc no connection 35 dfout o 36 daclk o 37 test6 o lsi test pin. normally left open. 38 lrsy o 39 ck2 o 40 romout o cd-rom application output signals 41 c2fclk o 42 c2f o 43 dout o digital output 44 sbsy o subcode block synchronization signal 45 eflg o c1, c2, single and double error correction monitor pin 46 pw o 47 sfsy o 48 sbck i 49 fsx o 7.35 khz synchronization signal output inputs for the la9210 internal vco output. (8.6436 mhz) set up pdo so that the frequency increases when the efm signal and the phase output are positive. supply an hf signal with a 1 to 2 vp-p level to efmin. efmo and efmo output efm signals with opposite phases that passed through an amplitude limiter circuit. these are used for slice level control. focs outputs a high level when the focus servo is off. the lens is lowered by fst, and when focs is high the lens is raised gradually. focs is reset when an fzd input occurs. these are used for focus pull-in. the LC78681KE outputs a kick pulse from jp + and jp in response to a track jump command. a track jump of the specified number of tracks (1, 2, 4, 16, 32, 64, and 128) is performed. the LC78681KE outputs a kick pulse from jp + and jp in response to a track jump command. a track jump of the specified number of tracks (1, 2, 4, 16, 32, 64, and 128) is performed. the LC78681KE outputs a kick pulse from jp + and jp in response to a track jump command. a track jump of the specified number of tracks (1, 2, 4, 16, 32, 64, and 128) is performed. signals used for signal output to the d/a converter, latch signal and l/r switching, and sample and hold. sfsy is the subcode frame synchronization signal. the p, q, r, s, t, u, v and w subcodes can be read out by applying 8 clock cycles to sbck. continued on next page.
continued from preceding page. pin applications 1. hf signal input circuit; pin 8: efmin, pin 7: efmo, pin 6: efmo an efm signal (nrz) with an optimal slice level can be acquired by inputting the hf signal to efmin. 2. pll clock generation circuit; pin 4: pdo, pin 3: ai, pin 2: ao a vco can be constructed by combining the LC78681KE with the sanyo la9210. the pdo pin swings in the positive direction when the vco phase lags. no. 4969-7/24 LC78681KE, 78681ke-l no. name i/o description 50 wrq o 51 rwc i 52 sqout o 53 coin i 54 cqck i 55 res i this pin must be set low briefly after power is first applied. 56 m/l i similar to pins number 50, 51, 52, 53 and 54 described above. 57 laser o output pin controllable by serial data sent from the microprocessor. 58 16m o 16.9344 mhz output pin 59 4.2m o 4.2336 mhz output pin 60 cont o output pin controllable by serial data sent from the microprocessor. 61 test5 i lsi test pin. normally left open. 62 cs i chip select pin. the LC78681KE becomes active when this pin is low. (a pull-down resistor is built-in.) 63 x in i connections for a 16.9344 mhz crystal oscillator 64 x out o wrq goes high when the subcode q data passes the crc check. an external controller can read out data from sqout by monitoring this pin and applying a cqck signal. set m/l to low when data is required lsb first. the control microprocessor can send commands to the LC78681KE by setting rwc high and then sending command data synchronized with cqck.
3. 1/2 vco; pin 18: pck pck is a monitor pin that outputs an average frequency of 4.3218 mhz, which is the vco frequency divided by two. 4. synchronization detection monitor; pin 19: fseq pin 19 goes high when the frame synchronization (a positive polarity synchronization signal) from the efm signal read in by pck and the timing generated by the counter (the interpolation synchronization signal) agree. this pin is a synchronization detection monitor. (it is held high for a single frame.) 5. servo command function; pin 51: rwc, pin 53: coin, pin 54: cqck, pin 62: cs commands are input to the LC78681KE by setting rwc high and sending commands to the coin pin in synchronization with the cqck clock. focus start track jump mute control 1-byte commands disc motor control other control commands track count 2-byte command 1-byte commands 2-byte commands command execution starts on the falling edge of the rwc signal. command noise exclusion this command allows the noise on the cqck clock signal to be excluded. no. 4969-8/24 LC78681KE, 78681ke-l msb lsb command res = low 11101111 command input noise exclusion mode 11101110 reset noise exclusion mode
6. focus servo circuit; pin 13: focs, pin 14: fst, pin 15: fzd, pin 57: laser laser control focus start when a focus start instruction (either focus start #1 or focus start #2) is input as a servo command, first the charge on capacitor c1 is discharged by fst and the objective lens is lowered. next, the capacitor is charged by focs, and the lens is slowly raised. fzd falls when the lens reaches the focus point. when this signal is received, focs is reset and the focus servo turns on. after sending the command, the microprocessor should check the in-focus detection signal (the la9210 drf signal) to confirm focus before proceeding to the next part of the program. if focus is not achieved by the time c1 is fully charged, the microprocessor should issue another focus command and iterate the focus servo operation. note: 1. values in parentheses are for the focus start #2 command. the only difference is in the fst low period. 2. an fzd falling edge will not be accepted during the period that fst is low. 3. after issuing a focus start command, initialization will be performed if rwc is set high. therefore, do not issue the next co mmand during focus start until the focus coil drive s curve has completed. 4. when focus cannot be achieved (i.e., when fzd does not go low) the focs signal will remain in the high state, so the micropro cessor should initialize the system by issuing a nothing command. 5. when the reset pin is set low, the laser pin is set high directly. 6. focus start using the demo coil executes a mode #1 focus start. no. 4969-9/24 LC78681KE, 78681ke-l msb lsb command res = low 00001000 f ocus start #1 10100010 focus start #2 00001010 l aser on 10001010 l aser off 00000000 nothing
7. clv servo circuit; pin 10: clv + , pin 11: clv , pin 12: v/p the clv + pin provides the signal that accelerates the disk in the forward direction and the clv pin provides the signal that decelerates the disk. commands from the control microprocessor select one of four modes; accelerate, decelerate, clv and stop. the table below lists the clv + and clv outputs in each of these modes. note: clv servo control commands can set the toff pin low only in clv mode. that pin will be at the high level at all other times. clv mode in clv mode the LC78681KE detects the disk speed from the hf signal and provides proper linear speed using several different control schemes by switching the dsp internal modes. the pwm period is 7.35 khz. v/p outputs no. 4969-10/24 LC78681KE, 78681ke-l msb lsb command res = low 00000100 disc motor start (accelerate) 00000101 disc motor clv (clv) 00000110 disc motor brake (decelerate) 00000111 disc motor stop (stop) mode clv + clv accelerate high low decelerate low high clv ** stop low low internal mode clv + clv v/p rough servo (velocity too low) high low high rough servo (velocity too high) low high high phase control (pck locked) pwm pwm low
rough servo gain switching for 8 cm disks, the rough servo mode clv control gain can be set about 8.5 db lower than the gain used for 12 cm disks. phase control gain switching the phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator. clv three state output the clv three state output command allows the clv to be controlled by a single pin. no. 4969-11/24 LC78681KE, 78681ke-l msb lsb command res = low 10110001 clv phase comparator divisor: 1/2 10110010 clv phase comparator divisor: 1/4 10110011 clv phase comparator divisor: 1/8 10110000 no clv phase comparator divisor used msb lsb command res = low 10110100 clv t hree state output 10110101 clv two state output (the scheme used by former products) msb lsb command res = low 10101000 disc 8 set 10101001 disc 12 set
internal brake mode issuing the internal brake on (c5h) command sets the LC78681KE to internal brake mode. in this mode, the disk deceleration state can be monitored from the wrq pin when a brake command (06h) is executed. in this mode the disk deceleration state is determined by counting the efm signal in a single frame to determine the density, and when the efm signal count falls under four, the clv pin is dropped to low. at the same time the wrq signal, which functions as a brake completion monitor, goes high when the microprocessor detects a high level on the wrq signal, it issues a stop command to complete the disk stop operation. in internal brake continuous mode, the clv pin high level output braking operation continues even after the wrq brake completion monitor goes high. note that if errors occur in deceleration state determination due to noise in the efm signal, the problem can be rectified by changing the efm signal count from four to eight with the internal brake control command (a3h). in toff output disabled mode the toff pin is held low during internal brake operations. note: 1. if focus is lost during the execution of an internal brake command, the pickup must be refocussed and then the internal brake command can be reissued. 2. since incorrect deceleration state determination is possible depending on the efm signal playback state (e.g., disk defects, access in progress), we recommend using these functions in combination with a microprocessor. 8. track jump circuit; pin 16: hfl, pin 17: tes, pin 20: toff, pin 21: tgl, pin 22: thld, pin 25: jp + , pin 26: jp the LC78681KE supports the two track jump commands listed below. the former track count function uses the tes signal directly as the internal track counter clock. to reduce counting errors resulting from noise on the rising and falling edges of the tes signal, the new track count function prevents noise induced errors by using the combination of the tes and hfl signals, and implements a more reliable track count function. however, dirt and scratches on the disk can result in hfl signal no. 4969-12/24 LC78681KE, 78681ke-l msb lsb command res = low 11000101 i nternal brake on 11000100 i nternal brake off 10100011 i nternal brake cont 11001011 i nternal brake continuous mode 11001010 reset continuous mode 11001101 toff output disabled mode 11001100 reset toff output disabled mode msb lsb command res = low 00100010 new track count (using the tes/hfl combination) 00100011 former track count (directly counts the tes signal)
track jump commands when the LC78681KE receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). the passage of the braking period (period c) completes the specified jump. during the braking period, the LC78681KE detects the beam slip direction from the tes and hfl inputs. toff is used to cut the components in the te signal that aggravate slip. the jump destination track is captured by increasing the servo gain with tgl. in thld period toff output mode the toff signal is held high during the period when thld is high. note: of the modes related to disk motor control, the toff pin only goes low in clv mode, and will be high during start, stop, and brake operations. note that the toff pin can be turned on and off independently by microprocessor issued commands. however, this function is only valid when disk motor control is in clv mode. no. 4969-13/24 LC78681KE, 78681ke-l msb lsb command res = low 10100000 f ormer track jump 10100001 new track jump 00010001 1 t rack jump in #1 00010010 1 t rack jump in #2 00110001 1 track jump in #3 01010010 1 t rack jump in #4 00010000 2 track jump in 00010011 4t rack jump in 00010100 16t rack jump in 00110000 32t rack jump in 00010101 64t rack jump in 00010111 128 track jump in 00011001 1 track jump out #1 00011010 1 t rack jump out #2 00111001 1 t rack jump out #3 01011010 1 track jump out #4 00011000 2 track jump out 00011011 4 track jump out 00011100 16 track jump out 00111000 32 track jump out 00011101 64t rack jump out 00011111 128t rack jump out 00010110 256t rack check 00001111 toff 10001111 ton 10001100 t rack jump brake 00100001 thld period toff output mode 00100000 reset thld period toff output mode
track jump modes the table lists the relationships between acceleration pulse output, deceleration pulse output, and the braking period. note: 1. as indicated in the table, actuator signals are not output during the 256 track check function. this is a mode in which the tes signal is counted in the tracking loop off state. therefore, feed motor forwarding is required. 2. the servo command register is automatically reset after the track jump sequence (a, b, c) completes. 3. if another track jump command is issued during a track jump operation, the content of that new command will be executed start ing immediately. no. 4969-14/24 LC78681KE, 78681ke-l former track jump mode new track jump mode command abcabc 1 track jump in (out) #1 233 s 233 s 60 ms 233 s 233 s 60 ms 1 track jump in (out) #2 0.5-track jump 233 s 60 ms 0.5-track jump a period 60 ms 1 track jump in (out) #3 0.5-track jump 233 s does not occur 0.5-track jump a period does not occur 1 track jump in (out) #4 0.5-track jump 233 s 60 ms, toff = low 0.5-track jump a period 60 ms, toff = low during the c period during the c period 2 track jump in (out) none none none 1-track jump a period does not occur 4 track jump in (out) 2-track jump 466 s 60 ms 2-track jump a period 60 ms 16 track jump in (out) 9-track jump 7-track jump 60 ms 9-track jump a period 60 ms 32 track jump in (out) 18-track jump 14-track jump 60 ms 18-track jump 14-track jump 60 ms 64 track jump in (out) 36-track jump 28-track jump 60 ms 36-track jump 28-track jump 60 ms 128 track jump in (out) 72-track jump 56-track jump 60 ms 72-track jump 56-track jump 60 ms toff goes high after 256 tracks are toff goes high after 256 tracks are 256 track check jumped. the a and b pulses are not 60 ms jumped. the a and b pulses are not 60 ms output. output. track jump brake there are no a and b periods. 60ms there are no a and b periods. 60 ms
jp three state output the jp three state output allows the track jump operation to be controlled from a single pin. track check mode the LC78681KE will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 16 to 254 after issuing either a track count in or a track count out command. note: 1. once the desired track count has been input in binary, the track count operation is started by the fall of rwc. 2. during a track count operation the toff pin goes high and the tracking loop is turned off. therefore, feed motor forwarding i s required. 3. when a track count in/out command is issued the function of the wrq signal switches from the normal mode subcode q standby mo nitor function to a track count monitor function. this signal goes high when the track count is half completed, and goes low when the count finishes. the control microprocessor should monitor this signal for a low level to determine when the track count completes. 4. if a two-byte reset command is not issued, the track count operation will be repeated. that is, to skip over 20,000 tracks, i ssue a track count 200 command once, and then count the wrq signal 100 times. 5. after performing a track count operation, use the brake command to have the pickup lock onto the track. no. 4969-15/24 LC78681KE, 78681ke-l msb lsb command res = low 10110110 jp three state output 10110111 jp two st ate output (former scheme) msb lsb command res = low 11110000 track count in 11111000 t rack count out 11111111 two byte command reset
9. error flag output; pin 45: eflg, pin 49: fsx the fsx signal is generated by dividing the crystal oscillator clock, and is a 7.35 khz frame synchronization signal. the error correction state for each frame is output from eflg. the playback ok/ng state can be easily determined from the extent of the high level that appears here. 10. subcode p, q, and r to w output circuit; pin 46: pw, pin 44: sbsy, pin 47: sfsy, pin 48: sbck pw is the subcode signal output pin, and all the codes p, q, and r to w can be read out by sending eight clocks to the sbck pin within 136 s after the fall of sfsy. the signal that appears on the pw pin changes on the falling edge of sbck. if a clock is not applied to sbck, the p code will be output from pw. sfsy is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (p to w). subcode data p is output on the fall of this signal. sbsy is a signal output for each subcode block. this signal goes high for the s0 and s1 synchronization signals. the fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (eiaj format) 11. subcode q output circuit; pin 50: wrq, pin 51: rwc, pin 52: sqout, pin 54: cqck, pin 56: m/l, pin 62: cs subcode q can be read from the sqout pin by applying a clock to the cqck pin. no. 4969-16/24 LC78681KE, 78681ke-l msb lsb command res = low 00001001 address free 10001001 address 1
of the eight bits in the subcode, the q signal is used for song (track) access and display. the wrq will be high only if the data passed the crc error check and the subcode q format internal address is 1*. the control microprocessor can read out data from sqout in the order shown below by detecting this high level and applying cqck. when cqck is applied the dsp disables register update internally. the microprocessor should give update permission by setting rwc high briefly after reading has completed. wrq will fall to low at this time. since wrq falls to low 11.2 ms after going high, cqck must be applied during the high period. data can be read out in an lsb first format if the m/l pin is set low, and in an msb first format if that pin is set high. note: * that state will be ignored if an address free command is sent. this is provided to handle cdv applications. note: 1. normally, the wrq pin indicates the subcode q standby state. however, it is used for a different monitoring purpose in t rack count mode and internal brake mode. (see the item on track counting and internal braking for details.) 2. the LC78681KE becomes active when the cs pin is low, and data is output from the sqout pin. when the cs pin is high, the sqou t pin goes to the high impedance state. 12. level meter (lvm) data and peak meter (pkm) data readout no. 4969-17/24 LC78681KE, 78681ke-l msb lsb command res = low 00101011 pkm set (lvm reset) 00101100 lvm set( pkm reset) 00101101 pkm mask set 00101110 pkm mask reset
level meter (lvm) the lvm set (2ch) command sets the LC78681KE to lvm mode. lvm data is a 16-bit word in which the msb indicates the l/r polarity and the low order 15 bits are absolute value data. a one in the msb indicates left channel data and a zero indicates right channel data. lvm data is appended after the 80 bits of subq data, and can be read out from the sqout pin by applying 96 clock cycles to the cqck pin. each time lvm data is read out the left/right channel state is inverted. data is held independently for both the left and right channels. in particular, the largest value that occurs between readouts for each channel is held. peak meter (pkm) the pkm set (2bh) command sets the LC78681KE to pkm mode. pkm data is a 16-bit word in which the msb is always zero and the low order 15 bits are absolute value data. this functions detects the maximum value that occurs in the data, whichever channel that value occurs in. pkm data is read out in the same manner as lvm data. however, data is not updated as a result of the readout operation. pkm mode subq data absolute time is computed by holding the absolute time (atime) detected after the maximum value occurred and sending that value. (normal operation uses relative time.) it is possible to set the LC78681KE to ignore values larger than the already recorded value by issuing the pkm mask set command, even in pkm mode. this function is cleared by issuing a pkm mask reset command. (this is used in pk search in a memory track.) 13. mute control circuit an attenuation of 12 db (mute 12 db) or full muting (mute db) can be applied by issuing the appropriate command from the table. since zero cross muting is used, there is no noise associated with this function. zero cross is defined for this function as the top seven bits being all ones or all zeros. 14. bilingual function following a reset or when a stereo (28h) command has been issued, the left and right channel data is output to the left and right channels respectively. when an lch set (29h) command is issued, the left and right channels both output the left channel data. when an rch set (2ah) command is issued, the left and right channels both output the right channel data. 15. de-emphasis on/off; pin 29: emph the preemphasis on/off bit in subcode q control information is output from the emph pin. de-emphasis should be performed when this signal is high. no. 4969-18/24 LC78681KE, 78681ke-l msb lsb command res = low 00000001 mute: 0 db 00000010 mute: 12 db 00000011 mute: db msb lsb command res = low 00101000 sto cont 00101001 lch cont 00101010 rch cont
16. d/a converter interface; pin 31: wclk, pin 33: lrclk, pin 35: dfout, pin 36: daclk data for the d/a converter is output msb first from dfout synchronized with the falling edge of daclk. when the cd-rom xa command described above is issued, data that is neither interpolated nor muted will be output from the dfout and dout pins. (this command is used for cd-rom xa applications.) the cd-rom xa reset command also functions as a pin 60 cont reset, so caution is required. LC78681KE d/a converter interface 17. cd-rom outputs; pin 39: ck2, pin 37: lrsy, pin 40: romout, pin 42: c2f, pin 41: c2fclk data is output msb first from the romout pin in synchronization with the lrsy signal. this data is appropriate for input to a cd-rom lsi, since it is not interpolated, previous value held, or processed by the digital filter circuits. ck2 is a 2.1168 mhz clock, and data is output on the ck2 rising edge. c2f is the flag information for data in 8-bit units. c2fclk is the synchronization signal for that flag. interface between the lc89510 and the LC78681KE or LC78681KE-l no. 4969-19/24 LC78681KE, 78681ke-l msb lsb command res = low 10001000 cd- rom xa 10001011 cont and cd-rom xa reset
18. digital output circuit; pin 43: dout this is an output pin for use with a digital audio interface. data is output in the eiaj format. this signal has been processed by the interpolation and muting circuits. this pin has a built-in driver circuit and can directly drive a transformer. the dout pin can be locked at the low level by issuing a dout off command. the ubit information in the dout data can be locked at zero by issuing a ubit off command. 19. cont pin: pin 60: cont the cont pin goes high when a cont set command is issued. 20. crystal clock oscillator; pin 63: xin, pin 64: xout the clock that is used as the time base is generated by connecting a 16.9344 mhz crystal oscillator between these pins. the osc off command turns off both the vco and crystal oscillators. also, the LC78681KE can be set up to handle double speed playback simply by issuing a command. the table below lists the relationships between the crystal and vco oscillators. recommended crystal clock oscillator component values no. 4969-20/24 LC78681KE, 78681ke-l msb lsb command res = low 01000010 dout on 01000011 dout off 01000000 ubit on 01000001 ubit off msb lsb command res = low 10001110 osc on 10001101 osc off 11000001 double speed mode 11000010 normal mode 01100000 vco 8m 01100001 vco 16m msb lsb command res = low 00001110 cont set low 10001011 cont and cd-rom xa reset manufacturer oscillator cin/cout citizen watch co., ltd. csa-309 6 pf to 10 pf (16.9344 mhz) (cin = cout) vco playback speed mode 8m mode 16m normal speed mode double speed mode normal speed mode double speed mode when reset ai pin external input (8m vco) 8.6436 mhz ai pin external input (17m vco) 17.2872 mhz 17.2872 mhz ai pin external input (la9210) 8.6436 mhz 17.2872 mhz pck monitor output 4.3218 mhz 8.6436 mhz 4.3218 mhz 8.6436 mhz
21. 4.2m and 16m pins; pin 59: 4.2m, pin 58: 16m the 16.9344 mhz external crystal oscillator 16.9344 mhz buffer output signal is output from the 16m pin. that frequency divided by four (a 4.2336 mhz frequency) is output from the 4.2m pin. when the oscillator is turned off both these pins will be fixed at either high or low. these frequencies are not changed by issuing the double speed command. 22. reset circuit; pin 55: res when power is first applied, this pin should be briefly set low and then set high. this will set the muting to db and stop the disk motor. setting the res pin low sets the LC78681KE to the settings enclosed in boxes in the table. 23. adjustment process sound output function; pin 27: demo by setting this pin high, muting can be set to 0 db, the disk motor can be set to clv, and a focus start operation can be performed, even without issuing any commands from the control microprocessor. also, since the laser pin becomes active, if the mechanism and servo systems are complete, an efm signal can be acquired with only this equipment, and an audio signal can be produced without the presence of a microprocessor. no. 4969-21/24 LC78681KE, 78681ke-l constant linear velocity servo start brake clv muting control 0 db 12 db subcode q address conditions address free laser control on (low) (high) cont high osc off track jump mode new track count mode former new former on low off address 1 stop
24. other pins; pin 1: test1, pin 9: test2, pin 23: test3, pin 28: test4, pin 61: test5, pin 37: test6, pin 32: test7 these pins are used for testing the lsi s internal circuits. since the pins test1 to test5 have built-in pull-down resistors, they can be left open in normal operation. circuit block operating descriptions 1. ram address control the LC78681KE incorporates an 8-bit 2 k-word ram on chip. this ram is used as a buffer memory, and has an efm demodulated data jitter handling capacity of 4 frames. the LC78681KE continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the pck side of the clv servo circuit and the frequency divisor. if the 4 frame buffer capacity is exceeded, the LC78681KE forcibly sets the write address to the 0 position. however, since the errors that occur due to this operation cannot be handled with error flag processing, the ic applies muting to the output for a 128 frame period. 2. c1 and c2 error correction the efm demodulated data is written to internal ram to compensate for jitter, and the LC78681KE performs the following processing with a constant timing based on the crystal oscillator clock. first, the LC78681KE performs c1 error checking and correction in the c1 block, determines the c1 flags, and writes the c1 flag register. next, the LC78681KE performs c2 error checking and correction in the c2 block, determines the c2 flags, and writes data to internal ram. note: 1. if the positions of the errors determined by the c2 check agree with the those specified by the c1 flags, the correction is performed and the flags are cleared. however, if the number of c1 flags is 7 or higher, c2 correction may fail. in this case correction is not pe rformed and the c1 flags are taken as the c2 flags without change. error correction is not possible if one error position agrees and the other doe s not. furthermore, if the number of c1 flags is 5 or under, the c1 check result can be seen as unreliable. accordingly, the flags wil l be set in this case. cases where the number of c1 flags is 6 or more are handled in the same way, and the c1 flags are taken as the c2 flags w ithout change. when there is not even one agreement between the error positions, error correction is, of course, impossible. here, if the number of c1 flags was 2 or under, data that was seen as correct after c1 correction is now seen as incorrect data. the flags are set in this case. the other c1 flags are taken as the c2 flags without change. 2. when data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. here, if the number of c1 flags was 2 or under, data that was seen as correct after c1 correction is now seen as incorrect data. the flags are set in thi s case. the other c1 flags are taken as the c2 flags without change. no. 4969-22/24 LC78681KE, 78681ke-l c1 flag error correction and flag processing no errors no correction required flag reset 1 error correction flag reset 2 errors correction flag set 3 errors or more correction not possible flag set position division ratio or processing 4 or less force to 0 3 589 2 589 increase ratio 1 589 0 588 standard ratio +1 587 +2 587 decrease ratio +3 587 +4 or more force to 0 c2 flag error correction and flag processing no errors no correction required flag reset 1 error correction flag reset 2 errors depends on c1 * 1 3 errors or more depends on c1 * 2
differences between the lc78681e and the LC78681KE/LC78681KE-l 1. new functions clv phase comparator divisor function (divisors of 2, 4, and 8) clv three state output jp three state output 2. new commands command input clv servo track jump internal brake mode 3. changed specification the c periods (braking periods) during track jump operations have all been changed from 24 ms to 60 ms. no. 4969-23/24 LC78681KE, 78681ke-l msb lsb command res = low function 11101111 command input noise exclusion mode excludes noise from the cqck signal. 11101110 reset noise exclusion mode (former product scheme) msb lsb command res = low function 11001011 int ernal brake continuous mode 11001010 reset continuous mode (former product scheme) 11001101 toff output disabled mode 11001100 reset toff output disabled mode (former product scheme) msb lsb command res = low function 10110001 clv phase comparator divisor: 1/2 10110010 clv phase comparator divisor: 1/4 10110011 clv phase comparator divisor: 1/8 10110000 no clv phase comparator divisor used (former product scheme) 10110100 clv three state output mode 10110101 reset three state output mode (former product scheme) the former product compared the phase for each 7.35 khz cycle. a new frequency divisor function has been added. clv servo can be controlled from a single pin since a three state output function has been added to the clv + pin (and to the clv pin as well). the LC78681KE remains in continuous brake operation mode even after wrq goes high. toff goes low during internal brake operation. msb lsb command res = low function 10110110 jp three state output 10110111 reset three state output mode (former product scheme) 01010010 1 t rack jump in #4 01011010 1 track jump out #4 00100001 thld period toff output mode 00100000 reset thld period toff output mode (former product scheme) the track jump function can be controlled from a single pin since a three state output function has been added to the jp + pin (and to the jp pin as well). toff is set low during the track jump c period. toff is set high during the track jump thld period.
no. 4969-24/24 LC78681KE, 78681ke-l this catalog provides information as of august, 1998. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer s products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any and all sanyo products described or contained herein fall under strategic products (including services) controlled under the foreign exchange and foreign trade control law of japan, such products must not be exported without obtaining export license from the ministry of international trade and industry in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

▲Up To Search▲

Price & Availability of LC78681KE

	To Download LC78681KE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .