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1 of 20 features ? real - time clock keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years ? 512k x 8 nv sram directly replaces volatile static ram or eeprom ? embedded lithium energy cell maintains calend ar operation and retains ram d ata ? watch f unction is transparent to ram operation ? automatic leap year compensation valid up to 2100 ? over 10 years of data retention in the absence of power ? full 10% o perating range ? lithium energy source is electrically disconnected to retain freshness u ntil power is applied for the first time ? dip module only C standard 32 - pin jedec pinout C upward compa ti ble with the ds1248 ? powercap module board only ? surface mountable p ackage for direct connection to powercap containing battery and crystal ? replaceable battery (powercap) ? pin - for - pin compatible with other densities of ds124xp phantom clocks ? underwriters laborator ies (ul) recognized ( www.maxim - ic.com/qa/info/ul/ ) pin configurations 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 encapsulated package 740- mil flush a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 a18/ rst dq2 gnd 15 16 18 17 dq4 dq3 ds1251 1 rst 2 3 a15 a16 n.c. v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17 a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 x1 gnd v bat x2 powercap module board (uses ds9034pcx + powercap) DS1251P top view ds1251/DS1251P 4096k nv sram with phantom clock 19 - 6 0 79 ; rev 11 /11
ds1251/DS1251P 2 of 20 ordering information part temp range voltage range (v) pin - package ds1251w - 120+ 0c to +70c 3.3 32 edip (0.740a) ds1251w - 120ind+ - 40c to +85c 3.3 32 edip (0.740a) ds1251wp - 120+ 0c to +70c 3.3 34 powercap* ds1251wp - 120ind+ - 40c to +85c 3.3 34 powercap* ds1251y - 70+ 0c to +70c 5.0 32 edip (0.740a) ds1251yp - 70+ 0c to +70c 5 .0 34 powercap* ds1251yp - 70ind+ - 40c to +85c 5.0 34 powercap* + denotes a lead (pb) - free/rohs - compliant package . * ds9034pcx + or ds9034i - pcx+ (powercap) required. must be ordered separately. pin d escription pin name function edip powercap 1 1 rst active - low reset input. this pin has an internal pullup resistor connected to v cc . 1 34 a18 address inputs 2 3 a16 3 32 a14 4 30 a12 5 25 a7 6 24 a6 7 23 a5 8 22 a4 9 21 a3 10 20 a2 11 19 a1 12 18 a0 23 28 a10 25 29 a11 26 27 a9 27 26 a8 28 31 a13 30 33 a17 31 2 a15 13 16 dq0 data in/data out 14 15 dq1 15 14 dq2 17 13 dq3 18 12 dq4 19 11 dq5 20 10 dq6 21 9 dq7
ds1251/DS1251P 3 of 20 pin description (continued) pin name func tion edip powercap 22 8 ce active - low chip - enable input 24 7 oe active - low output - enable input 29 6 we active - low write - enable input 32 5 v cc power - supply input 4 n.c. no connection 16 17 gnd ground description the ds1251 4096k nv sram w ith phantom clock is a fully static nonvolatile ram (organized as 512k words by 8 bits) with a built - in real - time clock. the ds1251y has a self - contained lithium energy source and control circuitry, which constantly monitors v cc for an out - of - tolerance co ndition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real - time clock. the phantom clock provides timekeeping informatio n including hundredths of seconds, seconds, minutes, hours, days, dates, months, and years. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. the phantom clock operates in ei ther 24- hour or 12 - hour format with an am/pm indicator. packages the ds1251 is available in two packages: 32 - pin dip and 34 - pin powercap module. the 32 - pin dip style module integrates the crystal, lithium energy source, and silicon in one package. the 34 - pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the DS1251P after the completion of the surface mount proce ss. mounting the powercap after the surface mount process prevents damage to the crystal and battery because of the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. ram read mode the ds1251 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address specifi ed by the 19 address inputs (a0 C a18) defines which of the 512 k bytes of data is to be accessed. valid data will be available to the eight data - output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times and states are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe , rather than address access. ram write mode the ds1251 is in the write mode whenever the we and ce signals are in the active (low) state after address inputs are stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must
ds1251/DS1251P 4 of 20 be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus has been enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power - fai l point, v pf (point at which write protection occurs), the internal clock registers and sram are blocked from any access. when v cc falls below the battery switch point, v so (battery supply level), device power is switched from the v cc pin to the backup bat tery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and data can be written or read only when v cc is greater than v pf. when v cc falls below the power - fail point, v p f , access to the device is inhibited. if v pf is less than v bat, the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to the backup supply (v bat ) w hen v cc drops below v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all control, data, and address signals must be powered down when v cc is powered down. phantom clock operation communication wit h the phantom clock is established by pattern recognition on a serial bit stream of 64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on dq0. all accesses that occur prior to recognition of the 64 - bit patter n are directed to memory. after recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. data transfer to and from the timekeeping function is accomplished with a ser ial bit stream under control of chip enable, output enable, and write enable. initially, a read cycle to any memory location using the ce and oe control of the phantom clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64 - bit comparison register. next, 64 consecutive write cycles are executed using the ce and we control of the smartwatch. these 64 write cycles are used only to gain acce ss to the phantom clock. therefore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requir ement is to set aside just one address location in ram as a phantom clock scratch pad. when the first write cycle is executed, it is compared to bit 0 of the 64 - bit comparison register. if a match is found, the pointer increments to the next location of th e comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (figure 1). with a correct match for 64 bits, the phantom clock is enable d and data transfer to or
ds1251/DS1251P 5 of 20 from the timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. c ycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock. phantom clock register information the phantom c lock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64 - bit pattern recognition sequence has been completed. when updating the phantom clock registers, each register must be handled in groups of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in figure 2. data contained in the phantom clock register is in binary - coded decimal format (bcd). reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. phantom clock register definition figure 1 note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c. the odds of this pattern being accidentally duplicated and causing inadvertent entry to the phantom clock is le ss than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb.
ds1251/DS1251P 6 of 20 phantom clock register definition figure 2 am/ pm/12/24 mode bit 7 of the hours register is defined as the 12 - hour or 24 - hour mode - select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the 20- hour bit (20 C 23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the rst and oscillator functions. bit 4 controls the rst (pin 1). when the rst bit is set to log ic 1, the rst input pin is ignored. when the rst bit is set to logic 0, a low input on the rst pin will cause the phantom clock to abort data transfer without changing data in the watch registers. bit 5 controls the oscillator. when set to logic 1, the oscillator is off. when set to logic 0, the oscillator turns on and the watch becomes operational. these bits are shipped from the factory set to a logic 1. zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits, which will always read logic 0. when writing these locations, either a logic 1 or 0 is acceptable.
ds1251/DS1251P 7 of 20 battery longevity the ds1251 has a lithium power source that is designed to provide energy for clock activity, and clock and ram da ta retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1251 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at +25 c with the internal clock oscillator running in the absence of v cc power. each ds1251 is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level gre ater than v pf , the lithium energy source is enabled for battery - backup operation. actual life expectancy of the ds1251 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. clock accuracy (dip module) the ds125 1 is guaranteed to keep time accuracy to within 1 minute per month at +25 c. the clock is calibrated at the factory by maxim using special calibration nonvolatile tuning elements. the ds1251 does not require additional calibration and temperature deviations will have a negligible ef fect in most applications. for this reason, methods of field clock calibration are not available and not necessary. clock accuracy (powercap module) the DS1251P and ds9034pcx are each individually tested for accuracy. once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35ppm) at +25 c.
ds1251/DS1251P 8 of 20 absolute maximum ratings voltage range on any pin relative to ground (5v product) . . . . . . . . . . . . . . . . . . . - 0.3v to +6.0v (3.3v product) . . . . . . . . . . . . . . . . . - 0.3v to +4.6v stor age temperature range edip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40c to +85c powercap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55c to +125c lead temperature (soldering, 10 s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260c note: edip is wave or hand - soldered only soldering temperat ure (reflow, powercap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260c this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated i n the operation sections of this specification is n ot implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. operating range range temp range (noncondensing) v cc (v) commercial 0c to +70c 3.3 10% or 5 10% industrial - 40c to +85c 3.3 10% or 5 10% recommended operating conditions (t a = ov er the operating range.) parameter symbol min typ max units notes logic 1 voltage all inputs v cc = 5v 10% v ih 2.2 v cc + 0.3 v 11 v cc = 3.3v 10% 2.0 v cc + 0.3 logic 0 voltage all inputs v cc = 5v 10% v il - 0.3 +0.8 v 11 v cc = 3.3v 10% - 0.3 +0.6
ds1251/DS1251P 9 of 20 dc electrical characteristics (t a = ov er the operating range.) (5v) 0b parameter symbol min typ max units notes input leakage current i il - 1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io - 1.0 +1.0 a output current at 2.4v i oh - 1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5 10 ma standby current ce = v cc - 0.5v i ccs2 3.0 5.0 ma operating current t cyc = 70ns i cc01 85 ma write protection voltage v pf 4.25 4.37 4.50 v 11 battery switchover voltage v so v bat 6b v 11 dc electrical characteristics (t a = ov er the operating range.) (3.3v) 1b parameter symbol min typ max units notes input leakage current i il - 1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io - 1.0 +1.0 a output current at 2.4v i oh - 1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5 7 ma standby current ce = v cc - 0.5v i ccs2 2.0 3.0 ma operating current t cyc = 70ns i cc01 50 ma write protec tion voltage v pf 2.80 2.97 v 11 battery switchover voltage v so v bat or v pf 7b v 11 capacitance (t a = +25 c) 2b parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf
ds1251/DS1251P 10 of 20 memory ac electrical charact eristics (t a = ov er the operating range.) (5v) 3b parameter symbol ds1251y - 70 units 8b notes min 9b max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high - z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 50 ns 3 address setup time t aw 0 ns write recovery time t wr 0 ns output high - z from we t odw 25 ns 5 o utput active from we t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time from we t dh 5 ns 4
ds1251/DS1251P 11 of 20 phantom clock ac electrical characteristics (t a = ov er the operating range.) (5v) 10b parameter symbol min typ max units notes read cycle time t rc 65 ns ce access time t co 55 ns oe access time t oe 55 ns ce to output low - z t coe 5 ns oe to output low - z t oee 5 ns ce to output high - z t od 25 ns 5 oe to output high - z t odo 25 ns 5 read recovery t rr 10 ns write cycle time t wc 65 ns write pulse width t wp 55 ns 3 write recovery t wr 10 ns 10 data setup time t ds 30 ns 4 data hold time t dh 0 ns 4 ce pulse width t cw 60 ns rst pulse width t rst 65 ns power - down/power - up timing (t a = ov er the operating range.) (3.3v) 11b par ameter symbol min typ max units notes ce at v ih before power - down t pd 0 s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t f 300 s v cc slew from v pf(min) to v so t fb 10 s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t r 0 s ce at v ih after power - up t rec 1.5 2.5 ms (t a = +25c) 4b parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots of any amplitude allowed when device is in battery - backup mode.
ds1251/DS1251P 12 of 20 memory ac electrical characteristics (t a = ov er the operating range.) (3. 3v) parameter 12b symbol 13b ds1251w - 120 14b units 15b notes min 16b max read cycle time t rc 120 ns access time t acc 120 ns oe to output valid t oe 60 ns ce to output valid t co 120 ns oe or ce to output active t coe 5 ns 5 output high - z from deselection t od 40 ns 5 output hold from address change t oh 5 ns write cycle time t wc 120 ns write pulse width t wp 90 ns 3 address setup time t aw 0 ns write recovery time t wr 20 ns 10 output high - z from we t odw 40 ns 5 output active from we t oew 5 ns 5 data setup time t ds 50 ns 4 data hold time from we t dh 20 ns 4 phantom clock ac electrical characteristics (t a = ov er the operating range.) (3.3v) parameter symbol min typ max units notes read cycle time t rc 120 ns ce access time t co 100 ns oe access time t oe 100 ns ce to output low - z t coe 5 ns oe to output low - z t oee 5 ns ce to output high - z t od 40 ns 5 oe to output high - z t odo 40 ns 5 read recovery t rr 20 ns write cycle time t wc 120 ns write pulse width t wp 100 ns 3 write recovery t wr 20 ns 10 data setup time t ds 45 ns 4 data hold time t dh 0 ns 4 ce pulse width t cw 105 ns rst pulse width t rst 120 ns
ds1251/DS1251P 13 of 20 power - down/power - up timing (t a = ov er the operating range.) (3.3v) 17b parameter symbol min typ max u nits notes ce at v ih before power - down t pd 0 s v cc slew from v pf(max) to v pf(min) ( ce at v ih ) t f 300 s v cc slew from v pf(max) to v pf(min) ( ce at v ih ) t r 0 s ce at v ih after power - up t rec 1.5 2.5 ms (t a = +25c) 5b parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots of any amplitude allowed when device is in battery - backup mode.
ds1251/DS1251P 14 of 20 memory read cycle (note 1) memory write cycle 1 (notes 2, 6, and 7)
ds1251/DS1251P 15 of 20 memory write cycle 2 (notes 2 and 8) reset for phantom clock read cycle to phantom clock
ds1251/DS1251P 16 of 20 write cycle to phantom clock power - down/power - up condition (5v)
ds1251/DS1251P 17 of 20 power - down/power - up condition (3.3v)
ds1251/DS1251P 18 of 20 ac test conditions output load: 50pf + 1ttl gate input pulse levels: 0 to 3v timing measurement reference le vels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) we is high for a read cycle. 2) oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3) t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4) t dh , t ds are measured from the earlier of ce or we going high. 5) these parameters are sampled with a 50pf load and are not 100% tested. 6) if the ce low transition o ccurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high - impedance state during this period. 7) if the ce high transition occurs prior to or simultaneously with the we high transition, the output buff ers remain in a high - impedance state during this period. 8) if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9) the expected t dr is def ined as cumulative time in the absence of v cc with the clock oscillator running. 10) t wr is a function of the latter occurring edge of we or ce . 11) voltages are referenced to ground. 12) rst (pin 1) has an internal pullup resistor. 13) real - time clock modules can b e successfully processed through conventional wave - soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85c. post - solder cleaning with water - washing techniques is acceptable, provided that ult rasonic vibration is not used. in addition, for the powercap: 1) maxim recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (live - bug). 2) hand soldering and touch - up: do not to uch or apply the soldering iron to leads for more than three seconds. ? to solder, apply flux to the pad, heat the lead frame pad, and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to re move solder.
ds1251/DS1251P 19 of 20 package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regar dless of rohs status. package type package code outline no. land pattern no. 32 edip mdt32+5 21- 0245 34 pwrcp pc2+5 21- 0246
ds1251/DS1251P 20 of 20 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the ri ght to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products max im is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 11/11 u pdate d the features , ordering information , am/pm/12/24 - mode , and absolute maximum ratings , and package information section s 1, 2, 6, 8, 19

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