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AU9380 usb flash disk controller technical reference manual revision 2 .2 ? 1997 - 2002 alcor micro corp. all rights reserved
copyright notice copyright 1997 - 200 2 alcor micro corp. all rights reserved. trademark acknow ledgements the company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers. disclaimer alcor micro corp. reserves the right to change this product without prior notice. alcor micro corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. specifications are subject to change without prior notice. contact information: web site: http://www.alcormicro.com/ taiwan alcor micro corp. 4f - 1 , no 200 k ang ch i e n rd., nei hu , taipei, taiwan , r.o.c. phone: 886 - 2 - 8751 - 1984 fax: 886 - 2 - 2659 - 7723 santa clara office los angeles office 2901 tasman drive, suite 206 9400 seventh st., bldg. a2 santa clara, ca 95054 rancho cucamonga, ca 9173 0 usa usa phone: (408) 845 - 9300 phone: (909) 483 - 9900 fax: (408) 845 - 9086 fax: (909) 944 - 0464
table of contents i table of contents 1.0 introduction -------------------------------------------------------------------------------------- - 1 1.1 description ----------------- ----------------------------------------------------------------- - 1 1.2 features -------------------------------------------------------------------------------------- - 1 2.0 application block diagram ----------------------------------------------------- ------------ -- 3 3.0 pin assignment -------------------------------------------------------------------------------- -- 5 4.0 system architecture and reference design ----------------------------------------- -- . 9 4.1 au9 380 block diagram ----------------- ------------------------------------------------- 9 4.2 sample schematics ------------------------------------------------------------------------ - 10 5.0 electrical characteristics ------------------------------------------------------------------- 13 5.1 recommended operating conditions ------------------------------------------------ - 13 5. 2 general dc characteristics ------------------------------------------------------------ - 13 5. 3 dc electrical characteristic for 3.3 volts operation ---------- --------------------- -- 13 5. 4 crystal oscillator circuit setup for characteristics ------------------------------ 1 4 5. 5 esd test results -------------------------------------------------------------------------- 1 5 5. 6 latch - up test results ------- ------------------------------------------------------------ 16 6.0 mechanical information ---------------------------------------------------------------------- - 19
table of contents i
introduction 1 1.0 introduction 1.1 description the au93 8 0 is a highly integrated single chip usb flash disk controller. it provides the most cost effective bridge between usb enabled pc and nand type flash memory. AU9380 can be used as a removable storage disk in enormous data exchange applicati ons between pc, macintosh, laptop and workstation . it can also be configured as a bootable disk for system repairing . the au93 8 0 can work with 1 to 4 nand type flash memory chip with the combination of any pop ular flash memory type - 8m, 16m, 32m, 64m and 128m . additional features include write protection switch, activity led and pa ssword protected security . the AU9380 integrated 48mhz pll, 3.3v regulator, power on reset circuit and a power switch for flash memory power control. 1.2 features ? ? fully compliant with usb v 1.1 specification a nd usb device class definition for mass s torage , bulk - transport v1.0 ? ? work with default driver from windows me, windows 2000, windows xp, mac os 9.1, and mac os x . windows 98 se is supported by vendor driver from alcor. ? ? multiple fifo implementation for concurrent bus operation ? ? support up to 4 nand flash memory chips with write - protected cap ability ? ? support total f lash memory size up to 256 mb ? ? support mixed different size nand flash ? ? v endor id, product id and strings can be customized by utility software from alcor ? ? can be configured to support dual partitions with dynamic logic disk space allocation. ? ? security function supported with password pr otection ? ? led for bus activity monitoring ? ? runs at 12mhz, built - in 48 mhz pll ? ? built - in 3.3v regulator ? ? built - in power switch and power management circuit to achieve 500ua suspend current required by usb specification. ? ? built - in power on reset circuit ? ? dedicated dma engine to ensure highest throughput in read and write ? ? 48 - pin tqfp package as standard package; 44 - pin lqfp package is also available
introduction 2
application block diagram 3 2.0 application block diagram f ollowing is the applica tion diagram of a typical flash disk product with AU9380 . by connecting the flash disk to a desktop or notebook pc through usb bus , au93 8 0 is implemented as a bus - powered, full speed usb disk, which can be used as a bridge for data transfer between desktop pc and notebook pc.
application block diagram 4
pin assignment 5 3.0 pin assignment the au93 8 0 is packed in 48 - pin lqfp form factor. the figure on the following page shows the signal names for each of the pins on the chip. accompanying the figure is the table that describes each of the pin signals. alcor micro corp. AU9380 48-pin lqfp
pin assignment 6 table 3 - 1. pin descriptions pin# pin name i/o type description 1 vcca pwr 3.3v input for pll 2 gnda pwr ground 3 xtal1 i crystal oscillator input (12mhz) 4 xtal2 o crystal oscillator output (12mhz) 5 vcc2fm o connect to flash memory vcc 6 vcc5v pwr 5v power supply 7 vccio pwr regulator 3.3v output/ io 3.3v input 8 rstnx i hardware reset (active low) 9 usb_dp i/o usb d+ 10 usb_dm i/o usb d - 11 gndio pwr groun d 12 nc 13 gpo1x o general purpose output pin, used as activity led 14 fmxwp i connect to flash memory write protect 15 fmxwr o connect to flash memory write enable 16 fmale o connect to flash memory address latch enable 17 fmcle o connect to flash memory command latch enable 18 fmxchip1 o connect to flash memory chip1 enable 19 fmxchip2 o connect to flash memory chip2 enable 20 fmxrd o connect to flash memory read enable 21 fmrdyxbzy i connect to flash memory ready/busy output 22 gpo5x o general purp ose output pin, used as activity led 23 reserved 24 nc 25 gpo4x o general purpose output pin, used as activity led 26 fmxchip3 o connect to flash memory chip3 enable
pin assignment 7 27 fmxchip4 o connect to flash memory chip4 enable 28 vcck pwr core 3.3v input 29 gndk pwr ground 30 reserved 31 reserve d 32 reserved 33 reserved 34 reserved 35 reserved 36 nc 37 gpo3x o general purpose output pin, used as activity led 38 fmio4 i/o connect to flash memory data io4 39 fmio5 i/o connect to flash memory data io5 40 fmio6 i/o connect to f lash memory data io6 41 fmio7 i/o connect to flash memory data io7 42 fmio0 i/o connect to flash memory data io0 43 fmio1 i/o connect to flash memory data io1 44 fmio2 i/o connect to flash memory data io2 45 fmio3 i/o connect to flash memory data io3 46 gpo0x o general purpose output pin, used as activity led 47 gpo2x o general purpose output pin, used as activity led 48 nc
system architecture and reference design 8
system architecture and reference design 9 4.0 system architecture and reference design 4.1 au93 8 0 block diagram alcor micro - AU9380 flash memory card reader block diagram fm control & fifo usb sie usb upstream port xcvr usb fifo 3.3 v voltage regulator & power off 3.3 v ram processor rom 12 mhz xtal support up to 4 flash memory suspend
system architecture and reference design 10 4.2 sample schematics fmale c8 0.1uf xtal2 gpo5x vcck r1 1.5k u1 AU9380-48pin 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 12 24 36 48 vcca gnda xtal1 xtal2 vcc2fm vcc5v vccio rstnx usb_dp usb_dm gndio gpo1x fmxwp fmxwr fmale fmcle fmxchip1 fmxchip2 fmxrd fmrdxbzy gpo5x reserved gpo4x fmxchip3 fmxchip4 vcck gndk reserved reserved reserved reserved reserved reserved gpo3x fmio4 fmio5 fmio6 fmio7 fmio0 fmio1 fmio2 fmio3 gpo0x gpo2x nc nc nc nc fmxchip2 gnda r4 47k c6 18pf fmrdyxbzy xtal1 r2 39 y1 12mhz gndk r5 1m vcc3.3 xtal2 gndk vcc c11 0.1uf vcc vcc3.3 f3 fb f2 fb f5 fb fmxrd fmxwp xtal1 d6 fmxchip3 disclaimer: this schematic is for reference only. alcor micro corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. specifications are subject to change without notice. f6 fb c5 18pf vcc3.3 fmxchip4 c1 0.1uf vcc3.3 fmxwr vcca a 1 1 tuesday, september 10, 2002 1.0a AU9380 demostartion schematic size document number rev date: sheet of c10 0.1uf fmcle c9 0.1uf vcc3.3 c3 1uf vcck j1 1 2 3 4 5 vcc data- data+ gnd fgnd1 c7 0.1uf r3 39 vcc5v c4 0.1uf vcc3.3 fmxchip1 r6 330 gpo5x c2 10uf vcc5v sw1 2 1 3 fmio[0..7] vcc2fm f4 fb gnda vcc2fm vcca f1 fb
electrical character istics 11 fmio6 vcc2fm a 1 1 tuesday, september 10, 2002 1.0a AU9380 demostartion schematic size document number rev date: sheet of fmcle vcc2fm u3 k9f5608u0a-ycb0 29 30 31 32 41 42 43 44 6 13 36 12 37 7 8 9 16 17 18 19 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd vss vss vcc vcc r/b re ce cle ale we wp fmxchip3 fmio7 fmale fmio1 fmio5 gnd fmcle fmio0 fmrdyxbzy fmio0 vcc2fm vcc2fm fmio3 fmcle fmio7 fmrdyxbzy fmio2 fmio5 fmio1 fmxrd fmale fmxrd fmio3 fmio[0..7] fmale fmio1 fmxchip1 fmxchip2 fmxrd fmxwr vcc2fm fmio6 fmio4 fmio6 fmio3 fmio4 gnd fmxwr u2 k9f5608u0a-ycb0 29 30 31 32 41 42 43 44 6 13 36 12 37 7 8 9 16 17 18 19 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd vss vss vcc vcc r/b re ce cle ale we wp fmio0 vcc2fm fmrdyxbzy fmio2 fmxwr fmio7 jp2 header 10 1 2 3 4 5 6 7 8 9 10 fmio4 fmio5 vcc2fm jp1 header 10 1 2 3 4 5 6 7 8 9 10 fmxchip4 fmio2
electrical character istics 12 5.0 electrical c haracteristics 5.1 recommended operating conditions symbol parameter min typ max units v cc power supply 4.75 5 5.25 v v in input voltage 0 v cc v t opr operating temperature 0 85 o c t stg storage temperature - 40 125 o c 5.2 general dc characteristics symb ol parameter conditions min typ max units i il input low current no pull - up or pull - down - 1 1 ? a i ih input high current no pull - up or pull - down - 1 1 ? a i oz tri - state leakage current - 10 10 ? a c in input capacitance 5 ? f c out output capacitance 5 ? f c bid bi - directional buffer capacitance 5 ? f 5.3 dc electrical characteristics for 3.3 volts operation symbol parameter conditions min typ max units v il input low voltage cmos 0.9 v v ih input hight voltage cmos 2.3 v v ol output low voltage i ol =4ma, 16ma 0.4 v v oh output high voltage i oh =4ma,16ma 2.4 v r i input pull - up/down resistance vil=0 v or vih=v cc 10k/200k k ?
electrical character istics 13 5.4 cry stal oscillator circuit setup for characterization the following setup was used to measure the open loop voltage gain for crystal oscillator circuits. the feedback resistor serves to bias the circuit at its quiescent operating point and the ac coupling c apacitor, cs, is much larger than c1 and c2.
electrical character istics 14 5.5 esd test results test description : esd testing was performed on a zapmaster system using the human - body ? model (hbm) and machine - model (mm), according to mil_std 883 and eiaj ic_121 respectively. ? ? h uman - body - model stress devices by sudden application of a high voltage supplied by a 100 pf capacitor through 1.5 kohm resistance. ? ? machine - model stresses devices by sudden application of a high voltage supplied by a 200 pf capacitor through very low ( 0 ohm) resistance test circuit & condition ? ? zap interval : 1 second ? ? number of zaps : 3 positive and 3 negative at room temperature ? ? critera : i - v curve tracing model model s/s target results hbm vdd, vss, i/c 15 4000v pass mm vdd, vss, i/c 15 200v pass
electrical character istics 15 5.6 latch - up test results test description: latch - up testing was performed at room ambient using an imcs - 4600 system which applies a stepped voltage to one pin per device with all other pins open except vdd and vss which were biased to 5 v olts and ground respectively. testing was started at 5.0 v (positive) or 0 v(negative), and the dut was biased for 0.5 seconds. if neither the put current supply nor the device current supply reached the predefined limit (dut=0 ma , icc=100 ma), then the v oltage was increased by 0.1 volts and the pin was tested again. this procedure was recommended by the jedec jc - 40.2 cmos logic standardization committee. notes: 1. dut: device under test. 2. put: pin under test. vcc dut gnd pin under test m a untested output open circuit untested input tied to v supply trigger source v supply + + icc measurement 1 source test circuit : p ositive input/ output overvoltage /overcurrent
electrical character istics 16 vcc dut gnd pin under test ma untested output open circuit untested input tied to v supply trigger source v supply + + icc measurement test circuit : negative input/ output overvoltage / overcurrent 1 source vcc dut gnd ma untested output open circuit all input tied to v supply v supply + icc measurement supply voltage test latch ? up data model model voltage (v)/ current (ma) s/s results + voltage - 11.0 11.0 5 pass + current - 200 200 5 vdd - vxx 9.0 5 pass
mechanical informati on 17
mechanical informati on 18 6.0 mechanical information body size d1 e1 lead count a1 a2 l1 b c e 7 7 32 0.1 1.4 1 0.35 0.127 0.8 7 7 44 0.1 1.4 1 0.2 0.127 0.5 7 7 48 0.1 1.4 1 0.2 0.127 0.5 10 10 44 0.1 1.4 1 0.3 0.127 0.8 10 10 64 0.1 1.4 1 0.2 0.127 0.5 10 10 80 0.1 1.4 1 0.16 0.127 0.4 12 12 80 0.1 1.4 1 0.2 0.127 0.5 12 12 100 0.1 1.4 1 0.16 0.127 0.4 14 14 64 0.1 1.4 1 0.35 0.127 0.8 14 14 80 0.1 1.4 1 0.3 0.127 0.65 14 14 100 0.1 1.4 1 0.2 0.127 0.5 14 14 120 0.1 1.4 1 0.16 0.127 0.4 14 14 128 0.1 1.4 1 0.16 0. 127 0.4 14 20 100 0.1 1.4 1 0.3 0.127 0.65 14 20 128 0.1 1.4 1 0.2 0.127 0.5 20 20 144 0.1 1.4 1 0.2 0.127 0.5 20 20 160 0.1 1.4 1 0.16 0.127 0.4 24 24 160 0.1 1.4 1 0.2 0.127 0.5 24 24 176 0.1 1.4 1 0.16 0.127 0.4 24 24 216 0.1 1.4 1 0.16 0.127 0.4 28 28 160 0.1 1.4 1 0.3 0.127 0.65 28 28 208 0.1 1.4 1 0.2 0.127 0.5 28 28 256 0.1 1.4 1 0.16 0.127 0.4 a1 stand - off a2 body thickness l1 lead length b lead width c lead thickness e lead pitch

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