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www.latticesemi.com 1 6at6_01.0 ISPPAC-POWR6AT6 in-system programmable power supply monitoring and margining controller april 2006 preliminary data sheet ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information h erein are subject to change without notice. description lattices power manager ii ISPPAC-POWR6AT6 is a general-purpose power-supply monitoring and margin- ing controller, incorporating in-system programmable analog functions implemented in non-volatile e 2 cmos technology. the ISPPAC-POWR6AT6 device provides six independent analog input channels to monitor up to six power supply test points. each of these input chan- nels offers a differential input to support remote ground sensing. the ISPPAC-POWR6AT6 incorporates six dacs for gen- erating a trimming voltage to control the output voltage of a power supply. the trimming voltage can be set to four hardware selectable preset values (voltage pro?es) or can be dynamically loaded in to the dac through the i 2 c bus. additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the digital closed loop control mode. the operating voltage pro?e can be selected using external hardware pins. features power supply margin and trim functions trim and margin up to six power supplies dynamic voltage control through i 2 c four hardware selectable voltage pro?es independent digital closed-loop trim function for each output analog input monitoring six analog monitor inputs differential input architecture for accurate remote ground sensing 10-bit adc for direct voltage measurements 2-wire (i 2 c/smbus compatible) interface readout of the adc dynamic trimming/margining control other features programmable analog circuitry wide supply range, 2.8v to 3.96v in-system programmable through jtag industrial temperature range: -40? to +85? 32-pin qfn package, only 5mm x 5mm, lead- free option application block diagram po w er s u pply margin/trim control 6 analog monitor inp u ts i 2 c interface 6 analog trim o u tp u ts adc ISPPAC-POWR6AT6 3.3 v 2.5 v 1. 8v pol#1 pol#2 pol#3 other board circ u itry trim v o u t trim v o u t trim v o u t trim v o u t trim v o u t trim v o u t cpu i 2 c b u s the on-chip 10-bit a/d converter can both be used to monitor the v mon voltage through the i 2 c bus as well as for implementing digital closed loop mode for maintain- ing the output voltage of all power supplies controlled by the monitoring and trimming section of the isppac- powr6at6 device. the i 2 c bus/smbus interface allows an external micro- controller to measure the voltages connected to the v mon analog monitor inputs and load the dacs for the generation of the trimming voltages of the external dc- dc converters.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 2 figure 1. ISPPAC-POWR6AT6 block diagram adc trim1 trim2 trim3 trim4 trim5 trim6 control logic i 2 c interface scl sda jtag interface osc set point registers decoder ISPPAC-POWR6AT6 vmon1gs cltenb vps0 vps1 vccd vcca cltlock/smba vmon1 vmon2gs vmon2 vmon3gs vmon3 vmon4gs tms tck tdi tdo vccj gnd vmon4 vmon5gs vmon5 vmon6gs vmon6 dac trimcell 1 dac trimcell 2 dac trimcell 3 dac trimcell 4 dac trimcell 5 dac trimcell 6
lattice semiconductor ISPPAC-POWR6AT6 data sheet 3 pin descriptions number name pin type voltage range description 7 vps0 digital input vccd trim select input 0 8 vps1 digital input vccd trim select input 1 6 cltenb digital input vccd enables closed loop trim process (asserted low) 9 cltlock/ smba open drain output 1 0v to 5.5v signals that all trimcells selected for closed- loop trim have reached a trim locked condi- tion. can be con?ured to be compliant with smbus alert protocol. 2 15 vmon1 analog input -0.3v to 5.75v voltage monitor 1 input 14 vmon1gs analog input -0.3v to 0.3v 3 voltage monitor 1 ground sense 17 vmon2 analog input -0.3v to 5.75v voltage monitor 2 input 16 vmon2gs analog input -0.3v to 0.3v 3 voltage monitor 2 ground sense 19 vmon3 analog input -0.3v to 5.75v voltage monitor 3 input 18 vmon3gs analog input -0.3v to 0.3v 3 voltage monitor 3 ground sense 21 vmon4 analog input -0.3v to 5.75v voltage monitor 4 input 20 vmon4gs analog input -0.3v to 0.3v 3 voltage monitor 4 ground sense 23 vmon5 analog input -0.3v to 5.75v voltage monitor 5 input 22 vmon5gs analog input -0.3v to 0.3v 3 voltage monitor 5 ground sense 25 vmon6 analog input -0.3v to 5.75v voltage monitor 6 input 24 vmon6gs analog input -0.3v to 0.3v 3 voltage monitor 6 ground sense 32 gnd ground ground ground 12 vccd 4 power 2.8v to 3.96v core vcc, main power supply 13 vcca 4 power 2.8v to 3.96v analog power supply 2 vccj power 2.25v to 3.6v vcc for jtag logic interface pins 31 trim1 analog output -320mv to +320mv from programmable dac offset trim dac output 1 30 trim2 analog output -320mv to +320mv from programmable dac offset trim dac output 2 29 trim3 analog output -320mv to +320mv from programmable dac offset trim dac output 3 28 trim4 analog output -320mv to +320mv from programmable dac offset trim dac output 4 27 trim5 analog output -320mv to +320mv from programmable dac offset trim dac output 5 26 trim6 analog output -320mv to +320mv from programmable dac offset trim dac output 6
lattice semiconductor ISPPAC-POWR6AT6 data sheet 4 1 tdo digital output jtag test data out 3 tck digital input jtag test clock input 5 tms digital input jtag test mode select; internal pullup 4 tdi digital input jtag test data in; internal pullup 10 scl digital input i 2 c serial clock input 11 sda digital i/o i 2 c serial data, bi-directional pin 1. open-drain outputs require an external pull-up resistor to a supply. 2. normally asserted low, but can be programmed to assert high (open) if desired. 3. the vmonxgs inputs are the ground sense line for each given vmon pin. the vmon input pins along with the vmonxgs ground sense pins implement a differential pair for each voltage monitor to allow remote sense at the load. vmonxgs lines must be connected and are not to exceed -0.3v to +0.3v in reference to the gnd pin. 4. vcca and vccd pins must be connected together on the circuit board. pin descriptions (cont.) number name pin type voltage range description
lattice semiconductor ISPPAC-POWR6AT6 data sheet 5 absolute maximum ratings absolute maximum ratings are shown in the table below. stresses beyond those listed may cause permanent dam- age to the device. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this speci?ation is not implied. recommended operating conditions analog speci?ations analog voltage monitor inputs (v mon ) symbol parameter conditions min. max. units v ccd core supply -0.5 4.5 v v cca analog supply -0.5 4.5 v v ccj jtag logic supply -0.5 6 v v in digital input voltage (all digital i/o pins) -0.5 6 v v mon+ v mon input voltage -0.5 6 v v mongs v mon input voltage ground sense -0.5 6 v t s storage temperature -65 150 o c t a ambient temperature -65 125 o c symbol parameter conditions min. max. units v ccd, v cca core supply voltage at pin 2.8 3.96 v v ccj jtag logic supply voltage at pin 2.25 3.6 v v in input voltage at digital input pins -0.3 5.5 v v mon input voltage at v mon pins -0.3 5.9 v v mongs input voltage at v mongs pins -0.3 0.3 v v out open-drain output voltage cltlock/smba -0.3 5.5 v t aprog ambient temperature during programming -40 85 o c t a ambient temperature power applied -40 85 o c symbol parameter conditions min. typ. max. units i cc 1 supply current 10 ma i ccj supply current 1ma 1. includes currents on v ccd and v cca supplies. symbol parameter conditions min. typ. max. units r in input resistance input mode = attenuated 1 50 65 80 k input mode = unattenuated 10 m c in input capacitance 12 pf 1. true for vmon input voltage from 600mv to 2.048v. values less than 600mv will see higher input impedance values.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 6 margin/trim dac output characteristics adc characteristics adc error budget across entire operating temperature range symbol parameter conditions min typ max units resolution 8(7+sign) bits fsr full scale range +/-320 mv lsb lsb step size 2.5 mv i out output source/sink current -125 125 ? v bpz bipolar zero output voltage (code=80h) offset 1 0.6 v offset 2 0.8 offset 3 1.0 offset 4 1.25 ts trimcell output voltage settling time 1 dac code changed from 80h to ffh or 80h to 00h 2.5 ms single dac code change 256 ? c_load maximum load capacitance 50 pf t updatem update time through i 2 c port 2 260 ? tose total open loop supply voltage error 3 full scale dac corre- sponds to ?% supply voltage variation -0.75 +0.75 % 1. to 1% of set value with 50pf load connected to trim pins. 2. total time required to update a single trimx output value by setting the associated dac through the i 2 c port. 3. this is the total resultant error in the trimmed power supply output voltage referred to any dac code due to the dacs inl, d nl, gain, out- put impedance, offset error and bipolar offset error across the industrial temperature range and the ISPPAC-POWR6AT6 operating v cca and v ccd ranges. symbol parameter conditions min. typ. max. units adc resolution 10 bits vin input range full scale programmable attenuator = 1 0 2.048 v programmable attenuator = 3 0 5.75 1 v t convert conversion complete time time from i 2 c request to complete one conversion cycle 200 2 ? adc step size lsb programmable attenuator = 1 2 mv programmable attenuator = 3 6 mv eattenuator error due to attenuator programmable attenuator = 3 +/- 0.1 % 1. maximum voltage is limited by v monx pin (theoretical maximum is 6.144v). 2. minimum time to wait for valid adc result. applies when not reading the done status bit (via i 2 c) to determine adc. symbol parameter conditions min. typ. max. units tadc error total measurement error at any voltage 1 measurement range 600 mv to 2.048v, vmonxgs > -100mv, attenuator =1 -8 +/-4 8 mv measurement range 600 mv to 2.048v, vmonxgs > -200mv, attenuator =1 +/-6 mv measurement range 0 to 2.048v, vmonxgs > -200mv, attenuator =1 +/-10 mv 1. total error, guaranteed by characterization, includes inl, dnl, gain, offset, and psr specs of the adc.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 7 digital speci?ations over recommended operating conditions i 2 c port characteristics symbol parameter conditions min. typ. max. units i il ,i ih input leakage, no pull-up/pull-down +/-10 ? i pu input pull-up current (tms, tdi) 70 ? v il voltage input, logic low 1 vps[0:1], tdi, tms, cltenb, 3.3v supply 0.8 v vps[0:1], tdi, tms, cltenb, 2.5v supply 0.7 v ih voltage input, logic high 1 vps[0:1], tdi, tms, cltenb, 3.3v supply 2.0 v vps[0:1], tdi, tms, cltenb, 2.5v supply 1.7 v ol cltlock/smba i sink = 20ma 0.8 v 1. cltenb, vps[0:1] referenced to v ccd ; tdo, tdi, tms referenced to v ccj . symbol de?ition 100khz 400khz units min. max. min. max. f i2c i 2 c clock/data rate 100 1 400 1 khz t su;sta after start 4.7 0.6 us t hd;sta after start 4 0.6 us t su;dat data setup 250 100 ns t su;sto stop setup 4 0.6 us t hd;dat data hold; scl= vih_min = 2.1v 0.3 3.45 0.3 0.9 us t low clock low period 4.7 1.3 us t high clock high period 4 0.6 us t f fall time; 2.25v to 0.65v 300 300 ns t r rise time; 0.65v to 2.25v 1000 300 ns t timeout detect clock low timeout 25 35 25 35 ms t por device must be operational after power-on reset 500 500 ms t buf bus free time between stop and start condition 4.7 1.3 us 1. if f i2c is less than 50khz, then the adc done status bit is not guaranteed to be set after a valid conversion request is completed. in this case, waiting for the t convert minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for readout. when f i2c is greater than 50khz, adc conversion complete is ensured by waiting for the done status bit.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 8 timing for jtag operations figure 2. erase (user erase or erase all) timing diagram figure 3. programming timing diagram symbol parameter conditions min. typ. max. units t ispen program enable delay time 10 ? t ispdis program disable delay time 30 ? t hvdis high voltage discharge time, program 30 s t hvdis high voltage discharge time, erase 200 ? t cen falling edge of tck to tdo active 10 ns t cdis falling edge of tck to tdo disable 10 ns t su1 setup time 5 ns t h hold time 10 ns t ckh tck clock pulse width, high 20 ns t ckl tck clock pulse width, low 20 ns f max maximum tck clock frequency 25 mhz t co falling edge of tck to valid output 10 ns t pwv verify pulse width 30 ? t pwp programming pulse width 20 ms vih vil vih vil update-ir run-test/idle (erase) select-dr scan clock to shift-ir state and shift in the discharge instruction, then clock to the run-test/idle state run-test/idle (discharge) specified by the data sheet tms tck state t h t h t h t h t h t h t su1 t su1 t su1 t su1 t su1 t su1 t su2 t ckh t ckh t ckh t ckh t ckh t gkl t gkl tms tck state vih vil vih vi l update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction, which will stop the discharge process update-ir t su1 t su1 t su1 t su1 t su1 t h t h t h t h t h t ckl t pwp t ckh t ckh t ckh t ckh t ckl
lattice semiconductor ISPPAC-POWR6AT6 data sheet 9 figure 4. verify timing diagram figure 5. discharge timing diagram tms tck state vih vil vih vil update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction update-ir t h t h t h t h t h t ckh t ckh t ckh t ckl t pwv t ckh t ckl t su1 t su1 t su1 t su1 t su1 tms tck state vih vil vih vil update-ir run-test/idle (erase or program) select-dr scan clock to shift-ir state and shift in the verify instruction, then clock to the run-test/idle state run-test/idle (verify) specified by the data sheet actual t h t h t h t h t h t h t su1 t ckh t hvdis (actual) t ckh t ckh t ckh t ckl t pwp t pwv t ckh t ckl t pwv t su1 t su1 t su1 t su1 t su1
lattice semiconductor ISPPAC-POWR6AT6 data sheet 10 theory of operation voltage measurement with the on-chip analog to digital converter (adc) the ISPPAC-POWR6AT6 has an on-chip analog to digital converter that can be used for measuring the voltages at the vmon inputs. the adc is also used in closed loop trimming of dc-dc converters. close loop trimming is cov- ered later in this document. figure 6. adc monitoring vmon1 to vmon6 figure 6 shows the adc circuit arrangement within the ISPPAC-POWR6AT6 device. the adc can measure all ana- log input voltages through the multiplexer, adc mux. the programmable attenuator between the adc mux and vmon pins can be con?ured as divided-by-3 or divided-by-1 (no attenuation). the divided-by-3 setting is used to measure voltages from 0v to 6v range and divided-by-1 setting is used to measure the voltages from 0v to 2v range. a microcontroller can place a request for any vmon voltage measurement at any time through the i 2 c bus. upon the receipt of an i 2 c command, the adc will be connected to the i 2 c selected vmon through the adc mux. the adc output is then latched into the i 2 c readout registers. ? / ? ? / ? ? / ? ? / ? v mo n 1 v mo n 2 v mo n 3 v mo n 4 10 adc adc mux pro g rammable attenuator from closed loop trim circ u it to closed loop trim circ u it to i 2 c reado u t register internal v ref- 2.04 8v from i 2 c adc mux address 3 + + + + ? / ? v mo n 5 + ? / ? v mo n 6 +
lattice semiconductor ISPPAC-POWR6AT6 data sheet 11 calculation the algorithm to convert the adc code to the corresponding voltage takes into consideration the attenuation bit value. in other words, if the attenuation bit is set, then adc output logic multiplies the 10-bit adc code by 3 to cal- culate the actual voltage at that vmon input. the following formula can always be used to calculate the actual volt- age from the adc code. voltage at the vmonx pins vmonx = adc code (12 bits 1 , converted to decimal) * 2mv 1 note: adc_value_high (8 bits), adc_value_low (4 bits) read from i 2 c/smbus interface controlling power supply output voltage with the margin/ trim block one of the key features of the ISPPAC-POWR6AT6 is its ability to make adjustments to the power supplies that it may also be monitoring. this is accomplished through the trim and margin block of the device. the trim and mar- gin block can adjust voltages of up to six different power supplies through trimcells as shown in figure 7. the dc- dc blocks in the ?ure represent virtually any type of dc power supply that has a trim or voltage adjustment input. this can be an off-the-shelf unit or custom circuit designed around a switching regulator ic. the interface between the ISPPAC-POWR6AT6 and the dc power supply is represented by a single resistor (r1 to r6) to simplify the diagram. each of these resistors represents a resistor network. other control signals driving the margin/trim block are: vps [1:0] ?control signals from device pins common to all six trimcells, which are used to select the active voltage pro?e for all trimcells together. adc input ?used to determine the trimmed dc-dc converter voltage. cltenb ?used to enable closed loop trimming of all trimcells together. next to each dc-dc converter, four voltages are shown. these voltages correspond to the operating voltage pro?e of the margin/trim block. when the vps[1:0] = 00, representing voltage pro?e 0: (voltage pro?e 0 is recommended to be used for the nor- mal circuit operation) the output voltage of the dc-dc converter controlled by the trim 1 pin of the ISPPAC-POWR6AT6 will be 1v and that trimcell is operating in closed loop trim mode. at the same time, the dc-dc converters controlled by trim 2, trim 3 and trim 6 pins output 1.2v, 1.5v and 3.3v respectively. when the vps[1:0] = 01, representing voltage pro?e 1 being active: the dc-dc output voltage controlled by trim 1, 2, 3, and 6 pins will be 1.05v, 1.26v, 1.57v, and 3.46v. these sup- ply voltages correspond to 5% above their respective normal operating voltage (also called as margin high). similarly, when vps[1:0] = 11, all dc-dc converters are margined low by 5%.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 12 figure 7. ISPPAC-POWR6AT6 trim and margin block there are six trimcells in the ISPPAC-POWR6AT6 device, enabling simultaneous control of up to six individual power supplies. each trimcell can generate up to four trimming voltages to control the output voltage of the dc-dc converter. figure 8. trimcell driving a typical dc-dc converter trimcell #1 (closed loop) trimcell #2 (i 2 c update) trimcell #3 (i 2 c update) trimcell #6 (register 0) dc-dc trim-in v i n 0123 1 v (clt) 1.05 v 0.97 v 0.95 v dc-dc output volta g e controlled by profiles dc-dc dc-dc di g ital closed loop and i 2 c interface control ISPPAC-POWR6AT6 mar g in/trim block trim 1 trim 2 trim 3 trim 6 trim-in trim-in r1* r2* r3* r6* *indicates resistor net w ork (see fig u re 8 ). inp u t from adc m u x read ?10- b it adc code v ps[0:1] clte nb cltlock/smba v i n v i n dc-dc trim-in v i n 1.2 v (i 2 c) 1.26 v 1.16 v 1.14 v 1.5 v (i 2 c) 1.57 v 1.45 v 1.42 v 3.3 v (ee) 3.46 v 3.20 v 3.13 v v out v i n r 3 r 1 r 2 trimcell # n dac dc-dc con v erter trim v out
lattice semiconductor ISPPAC-POWR6AT6 data sheet 13 figure 8 shows the resistor network between the trimcell #n in the ISPPAC-POWR6AT6 and the dc-dc converter. the values of these resistors depend on the type of dc-dc converter used and its operating voltage range. the method to calculate the values of the resistors r1, r2, and r3 are described in a separate application note. voltage pro?e control the margin / trim block of ISPPAC-POWR6AT6 consists of six trimcells. because all six trimcells in the margin / trim block are controlled by a common voltage pro?e control signals, they all operate at the same voltage pro?e. the voltage pro?e control input comes from a pair of device pins: vps0, vps1. trimcell architecture the trimcell block diagram is shown in figure 9. the 8-bit dac at the output provides the trimming voltage required to set the output voltage of a programmable supply. each trimcell can be operated in any one of the four voltage pro?es. in each voltage pro?e the output trimming voltage can be set to a preset value. there are six 8-bit registers in each trimcell that, depending on the operational mode, set the dac value. of these, four dac values (dac register 0 to dac register 3) are stored in the e 2 cmos memory while the remaining register contents are stored in volatile registers. two multiplexers (mode mux and pro?e mux) control the routing of the code to the dac. the pro?e mux can be controlled by common trimcell voltage pro?e control signals. figure 9. ISPPAC-POWR6AT6 output trimcell figure 7 shows four power supply voltages next to each dc-dc converter. when the pro?e mux is set to voltage pro?e 3, the dc supply controlled by trim 1 will be at 0.95v, the dc supply controlled by trim 2 will be at 1.14v, 1.42v for trim 3 and 3.13v for trim 8. when voltage pro?e 0 is selected, trim 1 will set the supply to 1v, trim 2 and trim 3 will be set by the values that have been loaded using i 2 c at 1.2 and 1.5v, and trim 6 will be set to 3.3v. the following table summarizes the voltage pro?e selection and the corresponding dac output trimming voltage. the voltage pro?e selection is common to all six trimcells. dac register 0 (e 2 cmos) closed loop trim register dac register 3 (e 2 cmos) voltage profile 0 mode select (e2cmos) mode mux profile mux dac 00 01 10 11 trimx 2 8 8 8 8 8 8 8 dac register (i 2 c) 8 voltage profile 3 voltage profile 2 voltage profile 1 voltage profile 0 dac register 2 (e 2 cmos) dac register 1 (e 2 cmos) from closed loop trim circuit trimcell architecture common trimcell voltage profile control
lattice semiconductor ISPPAC-POWR6AT6 data sheet 14 table 1. trimcell voltage pro?e and operating modes trimcell operation in voltage pro?es 1, 2 and 3: the output trimming voltage is determined by the code stored in the dac registers 1, 2, and 3 corresponding to the selected voltage pro?e. trimcell operation in voltage pro?e 0: the voltage pro?e 0 has three operating modes. they are dac register 0 select mode, dac register i 2 c select mode and closed loop trim mode. the mode selection is stored in the e 2 cmos con?uration memory. each of the six trimcells can be independently set to different operating modes during voltage pro?e 0 mode of operation. dac register 0 select mode: the contents of dac register 0 are stored in the on-chip e 2 cmos memory. when voltage pro?e 0 is selected, the dac will be loaded with the value stored in dac register 0. dac register i 2 c select mode: this mode is used if the power management arrangement requires an external microcontroller to control the dc-dc converter output voltage. the microcontroller updates the contents of the dac register i 2 c on the ? to set the trimming voltage to a desired value. the dac register i 2 c is a volatile register and is reset to 80h (dac at bipolar zero) upon power-on. the external microcontroller writes the correct dac code in this dac register i 2 c before enabling the programmable power supply. digital closed loop trim mode closed loop trim mode operation can be used when tight control over the dc-dc converter output voltage at a desired value is required. the closed loop trim mechanism operates by comparing the measured output voltage of the dc-dc converter with the internally stored voltage setpoint. the difference between the setpoint and the actual dc-dc converter voltage generates an error voltage. this error voltage adjusts the dc-dc converter output volt- age toward the setpoint. this operation iterates until the setpoint and the dc-dc converter voltage are equal. figure 10 shows the closed loop trim operation of a trimcell. at regular intervals (as determined by the update rate control register) the ISPPAC-POWR6AT6 device initiates the closed loop power supply voltage correction cycle through the following blocks: non-volatile setpoint register stores the desired output voltage on-chip adc is used to measure the voltage of the dc-dc converter three-state comparator is used to compare the measured voltage from the adc with the setpoint regis- ter contents. the output of the three state comparator can be one of the following: ?+1 if the setpoint voltage is greater than the dc-dc converter voltage ?-1 if the setpoint voltage is less than the dc-dc converter voltage ?0 if the setpoint voltage is equal to the dc-dc converter voltage channel polarity control determines the polarity of the error signal closed loop trim register is used to compute and store the dac code corresponding to the error voltage. the contents of the closed loop trim will be incremented or decremented depending on the channel polar- ity and the three-state comparator output. if the three-state comparator output is 0, the closed loop trim reg- ister contents are left unchanged. the dac in the trimcell is used to generate the analog error voltage that adjusts the attached dc-dc con- verter output voltage. vps[1:0] selected voltage pro?e selected mode trimming voltage is controlled by 11 voltage pro?e 3 dac register 3 (e 2 cmos) 10 voltage pro?e 2 dac register 2 (e 2 cmos) 01 voltage pro?e 1 dac register 1 (e 2 cmos) 00 voltage pro?e 0 dac register 0 select dac register 0 (e 2 cmos) dac register i 2 c select dac register (i 2 c) digital closed loop trim closed loop trim register
lattice semiconductor ISPPAC-POWR6AT6 data sheet 15 figure 10. digital closed loop trim operation the closed loop trim cycle interval is programmable and is set by the update rate control register. the following table lists the programmable update interval that can be selected by the update rate register. table 2. output dac update rate in digital closed loop mode closed loop trim control using the cltenb pin there is a one-to-one relationship between the selected trimcell and the corresponding vmon input for the closed loop operation. for example, if trimcell 3 is used to control the power supply in the closed loop trim mode, vmon3 must be used to monitor its output power supply voltage. the cltenb enable pin (active low) simultaneously starts the closed loop trimming process for all isppac- powr6at6 trim outputs so con?ured. behavior of individual trim output pins is de?ed using lattice pac- designer design software and stored in the ISPPAC-POWR6AT6's non-volatile e 2 cmos memory. in addition to a closed-loop trim control option, two other con?uration alternatives are available. the ?st stores a ?ed, or static, value for a given trim output in e 2 cmos memory. the second enables dynamic trim adjustments to be made using an external microcontroller via the ISPPAC-POWR6AT6's i 2 c interface bus. neither of these options is affected by the cltenb pin, however. when the ISPPAC-POWR6AT6's cltenb pin goes low, closed-loop trimming is enabled. when cltenb subse- quently goes high, there is a brief delay after which closed-loop trimming is suspended. the delay is the time required for ISPPAC-POWR6AT6 control logic to complete a trim update cycle. table 2 shows typical times for update cycles based on which of four trim rates is initially chosen in pac-designer. when the trim process is halted, it should also be noted the trim output dacs have constant voltage output levels (corresponding to their last input code setting). this condition can be safely maintained inde?itely, but resuming closed-loop trimming (by tak- ing cltenb low) better insures power supplies remain precisely adjusted under all possible conditions. when re- enabled, closed-loop trimming restarts where it left off. in this sense, the cltenb pin can be thought of as a ?ause control for closed-loop trim. update rate control value update interval 00 432 ? 01 1.06 ms 10 8.74 ms 11 16.9 ms adc three-state digital compare +/-1 setpoi n t (e 2 cmos) e 2 cmos registers (+1/0/-1) cha nn el polarity (e 2 cmos) trimx r* *indicates resistor net w ork (see fig u re 8 ). v mo n x trimi n dc-dc co nv erter v out g n d powr6at6 dac register 3 dac register 2 closed loop trim register dac trimcell update rate co n trol e 2 cmos dac register 1 dac register 0 dac register i 2 c profile 0 mode control (e 2 cmos) profile control
lattice semiconductor ISPPAC-POWR6AT6 data sheet 16 it should also be noted that whenever the vps0 and vps1 pins are not both low, they effectively stop closed-loop trim the same way the cltenb pin does when it goes high. that is, whenever an alternate trim mode (other than vps0=0 and vps1=0) is selected, the trim process is suspended as described above. assuming the cltenb pin is asserted, when both vps0 and vps1 are low again, closed-loop trimming will resume where it left off. it is recommended that the cltenb pin not be activated until after any necessary power supply sequencing is completed to prevent an ?pen loop condition from occurring. otherwise, if control of when closed-loop trimming begins is not critical, the cltenb pin can be tied to ground. this will cause closed-loop trim to begin immediately after the initial power on of the ISPPAC-POWR6AT6 is completed. closed loop trim start-up behavior the contents of the closed loop register, upon power-up, will contain a value 80h (bipolar-zero) value. the dac output voltage will be equal to the programmed offset voltage. usually under this condition, the power supply out- put will be close to its nominal voltage. if the power supply trimming should start after reaching its desired output voltage, the corresponding dac code can be loaded into the closed loop trim register through i 2 c (same address as the dac register i 2 c mode) before activating the cltenb pin. details of the digital to analog converter (dac) each trimcell has an 8-bit bipolar dac to set the trimming voltage (figure 11). the full-scale output voltage of the dac is +/- 320 mv. a code of 80h results in the dac output set at its bi-polar zero value. the voltage output from the dac is added to a programmable offset value and the resultant voltage is then applied to the trim output pin. the offset voltage is typically selected to be approximately equal to the dc-dc converter open circuit trim node voltage. this results in maximizing the dc-dc converter output voltage range. the programmed offset value can be set to 0.6v, 0.8v, 1.0v or 1.25v. this value selection is stored in e 2 cmos memory and cannot be changed dynamically. figure 11. vbpz offset voltage is added to dac output voltage to derive trim pad voltage reset command via jtag or i 2 c issuing a reset instruction via jtag or i 2 c will force all trim outputs selected for digital closed-loop trim control back to their initial output level (code 80h + vbpz). after that, assuming the cltenb is still asserted, digital closed loop dac 7 bits + sign (-320mv to +320mv) vbpz offset (0.6v,0.8v,1.0v,1.25v) e 2 cmos 8 trimx pad from trim registers trimcell x
lattice semiconductor ISPPAC-POWR6AT6 data sheet 17 trim will begin and cltlock/smba will only reassert when the trim process is complete. contents of the i 2 c cltlock_status register (0x00), however are not fully reset to initial conditions until the cltlock/smba pin achieves a reasserted state. caution: issuing a reset command through i 2 c or jtag during the ISPPAC-POWR6AT6 device operation, results in the device aborting all operations and returning to the power-on reset state except for the one condition mentioned above. i 2 c/smbus interface i 2 c and smbus are low-speed serial interface protocols designed to enable communications among a number of devices on a circuit board. the ISPPAC-POWR6AT6 supports a 7-bit addressing of the i 2 c communications proto- col, as well as smbtimeout and smbalert features of the smbus, enabling it to easily integrated into many types of modern power management systems. figure 12 shows a typical i 2 c con?uration, in which one or more isppac- powr6at6s are slaved to a supervisory microcontroller. sda is used to carry data signals, while scl provides a synchronous clock signal. the smbalert line is only present in smbus systems. the 7-bit i 2 c address of the powr6at6 is fully programmable through the jtag port. figure 12. ISPPAC-POWR6AT6 in i 2 c/smbus system in both the i 2 c and smbus protocols, the bus is controlled by a single master device at any given time. this mas- ter device generates the scl clock signal and coordinates all data transfers to and from a number of slave devices. the ISPPAC-POWR6AT6 is con?ured as a slave device, and cannot independently coordinate data transfers. each slave device on a given i 2 c bus is assigned a unique address. the ISPPAC-POWR6AT6 implements the 7-bit addressing portion of the standard. any 7-bit address can be assigned to the ISPPAC-POWR6AT6 device by pro- gramming through jtag. when selecting a device address, one should note that several addresses are reserved by the i 2 c and/or smbus standards, and should not be assigned to ISPPAC-POWR6AT6 devices to assure bus compatibility. table 3 lists these reserved addresses. microprocessor (i 2 c master) ISPPAC-POWR6AT6 (i 2 c slave) sda sda sda scl scl scl scl/smclk (clock) sda/smdat (data) smbalert out5/ smba out5/ smba to other i 2 c devices interrupt v+ ISPPAC-POWR6AT6 (i 2 c slave)
lattice semiconductor ISPPAC-POWR6AT6 data sheet 18 table 3. i 2 c/smbus reserved slave device addresses the ISPPAC-POWR6AT6s i 2 c/smbus interface allows data to be both written to and read from the device. a data write transaction (figure 13) consists of the following operations: 1. start the bus transaction 2. transmit the device address (7 bits) along with a low write bit 3. transmit the address of the register to be written to (8 bits) 4. transmit the data to be written (8 bits) 5. stop the bus transaction to start the transaction, the master device holds the scl line high while pulling sda low. address and data bits are then transferred on each successive scl pulse, in three consecutive byte frames of 9 scl pulses. address and data are transferred on the ?st 8 scl clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. both data and addresses are transferred in a most-signi?ant-bit-?st format. the ?st frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. the second frame contains the register address to which data will be written, and the ?al frame contains the actual data to be writ- ten. note that the sda signal is only allowed to change when the scl is low, as raising sda when scl is high sig- nals the end of the transaction. figure 13. i 2 c write operation reading a data byte from the ISPPAC-POWR6AT6 requires two separate bus transactions (figure 14). the ?st transaction writes the register address from which a data byte is to be read. note that since no data is being written to the device, the transaction is concluded after the second byte frame. the second transaction performs the actual read. the ?st frame contains the 7-bit device address with the r/w bit held high. in the second frame the isppac- powr6at6 asserts data out on the bus in response to the scl signal. note that the acknowledge signal in the second frame is asserted by the master device and not the ISPPAC-POWR6AT6. address r/w bit i 2 c function description smbus function 0000 000 0 general call address general call address 0000 000 1 start byte start byte 0000 001 x cbus address cbus address 0000 010 x reserved reserved 0000 011 x reserved reserved 0000 1xx x hs-mode master code hs-mode master code 0001 000 x na smbus host 0001 100 x na smbus alert response address 0101 000 x na reserved for access.bus 0110 111 x na reserved for access.bus 1100 001 x na smbus device default address 1111 0xx x 10-bit addressing 10-bit addressing 1111 1xx x reserved reserved ack ack ack start 123456789 a6 a5 a4 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 123456789 123456789 d7 d6 d5 d4 d3 d2 d1 d0 stop device address (7 bits) register address (8 bits) write data (8 bits) scl sda r/w note: shaded bits asserted by slave
lattice semiconductor ISPPAC-POWR6AT6 data sheet 19 figure 14. i 2 c read operation the ISPPAC-POWR6AT6 provides 15 registers that can be accessed through its i 2 c interface. these registers pro- vide the user with the ability to monitor and control the devices inputs and outputs, and transfer data to and from the device. table 4 provides a summary of these registers. table 4. i 2 c control registers i 2 c closed-loop trim register figure 15 shows bit assignments for the ISPPAC-POWR6AT6 i 2 c closed-loop trim status register. there are six read only bits (cltlock_status.in[1:6]) that re?ct the present trim status of individual trim output pins. when a closed loop-trim controlled power supply's output reaches the value speci?d by its pro?e 0 con?uration setting, that trim output's cltlock_status bit is set to a ?? the i 2 c closed-loop trim register has one read/write bit (cltlock_status). when ISPPAC-POWR6AT6 is con?ured in pac-designer to operate in smbus alert mode, it is set to a ? by device control logic to send an smbus alert. logic then waits for it to be acknowledged by a host i 2 c processor (when it is addresses the register), completing register address register name read/write description value on por, reset 0x00 cltlock_status r/w closed-loop trim status *bit-6 is rw, all others r only 1100 0000 0x01 adc_value_low r adc d[3:0] and status 0000 1110 0x02 adc_value_high r adc d[11:4] 0000 0000 0x03 adc_mux r/w adc attenuator and mux[3:0] 1110 1000 0x04 ues_byte0 r ues[7:0] eeee eeee 0x05 ues_byte1 r ues[15:8] eeee eeee 0x06 ues_byte2 r ues[23:16] eeee eeee 0x07 ues_byte3 r ues[31:24] eeee eeee 0x08 reset w resets device on write 1111 1111 0x09 trim1_trim r/w trim dac 1 [7:0] 1000 0000 0x0a trim2_trim r/w trim dac 2 [7:0] 1000 0000 0x0b trim3_trim r/w trim dac 3 [7:0] 1000 0000 0x0c trim4_trim r/w trim dac 4 [7:0] 1000 0000 0x0d trim5_trim r/w trim dac 5 [7:0] 1000 0000 0x0e trim6_trim r/w trim dac 6 [7:0] 1000 0000 note: x = unknown, 0 = low, 1 = high, e= e 2 memory setting (ues string) d5 d4 d3 d2 d1 d0 d6 d7 ack ack ack start 123456789 a6 a5 a4 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 123456789 device address (7 bits) register address (8 bits) scl sda r/w stop start 123456789 a6 a5 a4 a3 a2 a1 a0 ack 123456789 device address (7 bits) read data (8 bits) scl sda r/w stop step 1: write register address for read operation step 2: read data from that register note: shaded bits asserted by slave optional
lattice semiconductor ISPPAC-POWR6AT6 data sheet 20 the smbus alert cycle. refer to the cltlock/smba pin and smbus alert sections of this datasheet for more information on how the closed-loop trim status in this i 2 c register is used. figure 15. i 2 c closed loop trim status register it is possible to read the value of the voltage present on any of the vmon inputs by using the ISPPAC-POWR6AT6s adc. three registers provide the i 2 c interface to the adc (figure 16). figure 16. adc interface registers to perform an a/d conversion, one must set the input attenuator and channel selector. two input ranges may be set using the attenuator, 0 - 2.048v and 0 - 6.144v. table 5 shows the input attenuator settings. table 5. adc input attenuator control the input selector may be set to monitor any one of the six vmon inputs or the vcca input. table 6 shows the codes associated with each input selection. table 6. v mon address selection table atten (adc_mux.4) resolution full-scale range 0 2mv 2.048 v 1 6mv 6.144 v select word input channel sel2 (adc_mux.2) sel1 (adc_mux.1) sel0 (adc_mux.0) 0 0 0 vmon1 0 0 1 vmon2 0 1 0 vmon3 0 1 1 vmon4 1 0 0 vmon5 1 0 1 vmon6 x smba in6 in5 in4 in3 in2 in1 b7 b 0 b 6 b 5 b4 b 3 b2 b1 0x00 ?cltlock_status (b6 = read/write; all others read only) d3 d2 d1 d0 1 1 1 done b7 b0 0x01 - adc_value_low (read only) b6 b5 b4 b3 b2 b1 d11 d10 d9 d8 d7 d6 d5 d4 b7 b0 0x02 - adc_value_high (read only) b6 b5 b4 b3 b2 b1 xxx x atten sel2 sel1 sel0 b7 b0 0x03 - adc_mux (read/write) b6 b5 b4 b3 b2 b1
lattice semiconductor ISPPAC-POWR6AT6 data sheet 21 writing a value to the adc_mux register to set the input attenuator and selector will automatically initiate a conver- sion. when the conversion is in process, the done bit (adc_value_low.0) will be reset to 0. when the conver- sion is complete, this bit will be set to 1. when the conversion is complete, the result may be read out of the adc by performing two i 2 c read operations; one for adc_value_low, and one for adc_value_high. it is recom- mended that the i 2 c master load a second conversion command only after the completion of the current conversion command (waiting for the done bit to be set to 1). an alternative would be to wait for a minimum speci?d time (see tconvert value in the speci?ations) and disregard checking the done bit. note that if the i 2 c clock rate falls below 50khz (see f i2c note in speci?ations), the only way to insure a valid adc conversion is to wait the minimum speci?d time (tconvert), as the operation of the done bit at clock rates lower than that cannot be guaranteed. in other words, if the i 2 c clock rate is less than 50khz, the done bit may or may not assert even when a valid conversion result is available. erroneous adc readout results are also possible when- ever the i 2 c clock is less than 50khz and a second adc convert is commanded before a full t convert time period has elapsed. under these conditions, it is still possible to obtain valid results for the second conversion by reading out the adc low and high byte results twice in succession (read adc_value_low, read adc_value_high, then repeating the low and high byte reads). only the second adc readout value is reliably valid, however. to insure every adc conversion result is valid, preferred operation is to clock i 2 c at more than 50khz and verify done bit status or wait for the full t convert time period between subsequent adc convert commands. if an i 2 c request is placed before the current conversion is complete, the done bit will be set to 1 only after the second request is complete. the ues word may also be read through the i 2 c interface, with the register mapping shown in figure 17. figure 17. i 2 c register mapping for ues bits the i 2 c interface also provides the ability to initiate reset operations. the ISPPAC-POWR6AT6 may be reset by issu- ing a write of any value to the i 2 c reset register (figure 18). refer to the reset command via jtag or i 2 c sec- tion of this data sheet for further information. ues7 ues6 ues5 ues4 ues3 ues2 ues1 ues0 b7 b0 0x04 - ues_byte0 (read only) b6 b5 b4 b3 b2 b1 ues15 ues14 ues13 ues12 ues11 ues10 ues9 ues8 b7 b0 0x05 - ues_byte1 (read only) b6 b5 b4 b3 b2 b1 ues23 ues22 ues21 ues20 ues19 ues18 ues17 ues16 b7 b0 0x06 - ues_byte2 (read only) b6 b5 b4 b3 b2 b1 ues31 ues30 ues29 ues28 ues27 ues26 ues25 ues24 b7 b0 0x07 - ues_byte3 (read only) b6 b5 b4 b3 b2 b1
lattice semiconductor ISPPAC-POWR6AT6 data sheet 22 figure 18. i 2 c reset register the ISPPAC-POWR6AT6 also provides the user with the ability to program the trim values over the i 2 c interface, by writing the appropriate binary word to the associated trim register (figure 19). figure 19. i 2 c trim registers monitoring closed loop trim with the cltlock/smba pin the ISPPAC-POWR6AT6 uses a simple algorithm to determine if closed-loop trimming has reached a stable or locked value. in figure 20, the ?w diagram shows whenever the closed-loop trim enable pin (cltenb) is asserted (low) the status of all six trim output pins is tested and updated at periodic intervals (refer to table 2 for typical cycle times). if a trim lock condition exists for a given pin, a lock result is set and processing continues. pins not selected for closed-loop trim are automatically reported to be in the lock condition, but timing is kept constant to preserve a constant update rate regardless of how many trim outputs are really involved. xxxxxxxx b7 b0 0x8 - reset (write only) b6 b5 b4 b3 b2 b1 d7 d6 d5 d4 d3 d2 d1 d0 b7 b0 0x9 - trim1_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0xa - trim2_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0xb - trim3_trim (read/write) b6 b5 b4 b3 b2 b1 b7 b0 0xc - trim4_trim (read/write) b6 b5 b4 b3 b2 b1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 b7 b0 b6 b5 b4 b3 b2 b1 b7 b0 0xe - trim6_trim (read/write) b6 b5 b4 b3 b2 b1 d7 d6 d5 d4 d3 d2 d1 d0 0xd - trim5_trim (read/write)
lattice semiconductor ISPPAC-POWR6AT6 data sheet 23 figure 20. closed-loop trim lock (cltlock/smba) signal processing logic flow diagram the ISPPAC-POWR6AT6 contains trim detection processing circuitry to signal when closed-loop trimming is com- plete for selected trim output pins. this signal is output on the closed-loop control output pin (cltlock/smba) which has a open drain output and is normally asserted low (pull down). when all closed-loop trim output pins reach a completion or trim ?ocked condition, the cltlock/smba output pin pulls low. afterwards, the cltlock/ smba pin also indicates when a trimming fault exists by de-asserting (going high). finally, the cltlock/smba pin can be con?ured to work in conjunction with the smbus alert protocol to signal when trim lock has been achieved or lost (see the section on smbus alert for details). figure 21 shows a simpli?d diagram of how the state of the cltlock/smba output pin is generated. after closed loop trimming is enabled, the cltlock/smba signal processing logic examines the output result from the adc going to each trimcell at the end of each trim update cycle. if it is determined that a trim lock condition exists for that trim output pin, the trim lock signal is asserted. the status of an individual trim output can be read via the i 2 c closed loop trim register (refer to figure 15). trim output pins not selected for closed-loop trim operation will auto- matically indicate a trim locked condition. figure 21. closed-loop trim lock output pin (cltlock/smba) functionality next, an individual lock signal is or'd with an e 2 cmos mask bit speci? to that trim output pin. there are six mask- ing bits, one for each possible trim output pin. when set, masking bits effectively override the lock determination for a particular trim output pin. the default setting for all mask bits is cleared (not set). changes to the device con?u- ration mask bits can be made using pac-designer. start r u ns w hen clte nb pin is asserted. v mon-n adc meas u rement trim locked? determine ?ock stat u s of trim-n yes n o set ?ock?res u lt for trim-n clear ?ock?res u lt for trim-n cltlock/smb a e 2 config u ration mask cltlock/smba trim1-5 same as b elo w 5 5 i 2 c cltlock/smba stat u s: trim1-6 (6- b its); 1 = locked cltlock/smba signal processing logic 6 lock = 1 1 i 2 c/ smb u s control logic 1 0 e 2 config u ration defa u lt = 0 trim6
lattice semiconductor ISPPAC-POWR6AT6 data sheet 24 finally, the individual lock status inputs all meet at a common nand gate. a trim lock condition is generated when all six trim status inputs are high causing the cltlock/smba pin to go low. if the trim lock is lost for any monitored trim output pin, the cltlock/smba pin will de-assert (go open). this could be due to a failed power supply for example, or if the ISPPAC-POWR6AT6 can no longer adjust a controlled supply to speci?ation. interrogation of the i 2 c register determines which trim output pin lost lock. also, the adc can be used to measure individual supplies to further diagnose an underlying fault. there is an alternative path the cltlock/smba signal can take, depending on how the ISPPAC-POWR6AT6 has been con?ured. refer to the i 2 c/smbus control logic box shown in figure 21. when the alternative output path is enabled in pac-designer, the trim lock result is ?st sent to the i 2 c/smbus control logic for processing before going to the cltlock/smba output pin. the purpose of this control logic is to make the cltlock/smba signal work in accordance with the smbus alert protocol. the main difference between the two output path alternatives is that smbus alert stays set (low) until acknowledged by the host i 2 c processor. also, an smbus alert is set (pulled low) when a trim lock condition is achieved, as well as when it is lost. either condition must be acknowledged or the smbus alert condition will not go away. note that on initial device power-on, or after an i 2 c software reset, an smbus alert is blocked (no trim lock). the smbus master must explicitly set the clt_lock_status bit-6 low to begin the smbalert process. smbus smbalert function the ISPPAC-POWR6AT6 provides an smbus smbalert function to request service from the bus master when used as part of an smbus system. when the smbalert signal mode for closed-loop trimming is chosen in pac-designer, the cltlock/smba output pin will go low whenever the trim lock condition status changes. the reason for this is to report both when all outputs are in trim lock and when one or more trim output pins lose trim lock. when a selected (unmasked) closed-loop trim output loses its locked status, servicing the resulting smbus alert and interrogating the i 2 c closed-loop trim register will reveal which trim output pin(s) that are involved. after acknowledgement by the host i 2 c processor, the cltlock/smba pin will be de-asserted until another change in cltlock/smba trim status occurs. after initial device turn-on and power-on reset (por) is complete, the smba bit in the i 2 c register (0x00, bit-6) is set high or ?? the smbalert function of the ISPPAC-POWR6AT6 is effectively suspended until this location has been overwritten with a low or ?? the purpose of this is to prevent output to the cltlock/smba pin before the bus master or host processor is ready to process smbalerts. note that if closed loop trimming is enabled and completes before this action is performed, the initial trim lock indi- cation (as an smbalert) will not occur. if this happens, trim status can still be interrogated, however. reading the i 2 c trim status register to see that all trim bits are high (bit-1 to bit-6) is a valid indication that trim lock has been achieved. otherwise, the cltenb pin must be held high until after the i 2 c smba bit is written low and then enabled afterwards to insure detection of the initial trim lock status with an smbalert. after the smba bit has been set low, any subsequent change in trim lock status will be reported with an smbalert output to the cltlock/smba pin. to process an smbalert, the following steps must be performed to service the alert and resume monitoring for the next change in trim lock status: the typical ?w for an smbalert transaction is as follows (figure 22): 1. i 2 c closed loop trim register smba bit is forced to high by internal ISPPAC-POWR6AT6 control logic when- ever the trim lock status changes 2. ISPPAC-POWR6AT6 closed-loop trim control logic pulls the cltlock/smba pin low 3. master responds to interrupt from smba line 4. master broadcasts a read operation by sending the smbus alert response address (ara, 18h) 5. ISPPAC-POWR6AT6 responds to the ara request by transmitting its device address
lattice semiconductor ISPPAC-POWR6AT6 data sheet 25 6. if transmitted device address matches ISPPAC-POWR6AT6 address, the master completes the cycle by set- ting the i 2 c closed loop trim register smba bit low again. this releases the cltlock/smba pin (it goes high). figure 22. smbalert bus transaction after cltlock/smba has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ISPPAC-POWR6AT6. as part of the service functions, the bus master will typically need to clear whatever condition initiated the smbalert request (power sup- ply malfunction, etc.). for further information on the smbus functionality, the user should consult the smbus stan- dard. software-based design environment designers can con?ure the ISPPAC-POWR6AT6 using pac-designer, an easy to use, microsoft windows compat- ible program. circuit designs are entered graphically and then veri?d, all within the pac-designer environment. full device programming is supported using pc parallel port i/o operations and a download cable connected to the serial programming interface pins of the ISPPAC-POWR6AT6. a library of con?urations is included with basic solu- tions and examples of advanced circuit techniques are available on the lattice web site for downloading. in addi- tion, comprehensive on-line and printed documentation is provided that covers all aspects of pac-designer operation. the pac-designer schematic window, shown in figure 23, provides access to all con?urable isppac- powr6at6 elements via its graphical user interface. all analog input and output pins are represented. static or non-con?urable pins such as power, ground, and the serial digital interface are omitted for clarity. any element in the schematic window can be accessed via mouse operations as well as menu commands. when completed, con- ?urations can be saved, simulated, and downloaded to devices. figure 23. pac-designer ISPPAC-POWR6AT6 design entry screen ack a4 a3 a2 a1 a0 x a5 a6 start 123456789 000110 0 ack 123456789 alert response address (0001 100) slave address (7 bits) scl sda r/w stop smba note: shaded bits asserted by slave slave asserts smba slave releases smba
lattice semiconductor ISPPAC-POWR6AT6 data sheet 26 in-system programming the ISPPAC-POWR6AT6 is an in-system programmable device. this is accomplished by integrating all e 2 con?u- ration memory and sram control logic on-chip. programming is performed through a 4-wire, ieee 1149.1 compli- ant serial jtag interface at normal logic levels. once a device is programmed, all con?uration information is stored on-chip, in non-volatile e 2 cmos memory cells. the speci?s of the ieee 1149.1 serial interface and all isp- pac-powr6at6 instructions are described in the jtag interface section of this data sheet. user electronic signature a user electronic signature (ues) feature is included in the e 2 cmos memory of the ISPPAC-POWR6AT6. this con- sists of 32 bits that can be con?ured by the user to store unique data such as id codes, revision numbers or inven- tory control data. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. electronic security an electronic security ?use (esf) bit is provided in every ISPPAC-POWR6AT6 device to prevent unauthorized readout of the e 2 cmos con?uration bit patterns. once programmed, this cell prevents further access to the func- tional user bits in the device. this cell can only be erased by reprogramming the device, so the original con?ura- tion cannot be examined once programmed. usage of this feature is optional. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. production programming support once a ?al con?uration is determined, an ascii format jedec ?e can be created using the pac-designer soft- ware. devices can then be ordered through the usual supply channels with the users speci? con?uration already preloaded into the devices. by virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and ?xibility in production planning. evaluation fixture the design kit for the isppac-powr1220at8, a larger device that contains all the same functions as the isppac- powr6at6, can be used to evaluate the ISPPAC-POWR6AT6. included in the basic isppac-powr1220at8 design kit is an engineering prototype board that can be connected to the parallel port of a pc using a lattice download cable. it demonstrates proper layout techniques for the isppac-powr1220at8 which also apply to the ISPPAC-POWR6AT6 and can be used in real time to check circuit operation as part of the design process. input and output connections are provided to aid in the evaluation of either device for a given application. (figure 24). figure 24. download from a pc ieee standard 1149.1 interface (jtag) serial port programming interface communication with the ISPPAC-POWR6AT6 is facilitated via an ieee 1149.1 test access port (tap). it is used by the ISPPAC-POWR6AT6 as a serial programming interface. a brief description ispdownload cable (6') 4 other system circuitry isppac-powr 1220at8 device pac-designer software
lattice semiconductor ISPPAC-POWR6AT6 data sheet 27 of the ISPPAC-POWR6AT6 jtag interface follows. for complete details of the reference speci?ation, refer to the publication, standard test access port and boundary-scan architecture, ieee std 1149.1-1990 (which now includes ieee std 1149.1a-1993). overview an ieee 1149.1 test access port (tap) provides the control interface for serially accessing the digital i/o of the isp- pac-powr6at6. the tap controller is a state machine driven with mode and clock inputs. given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. device programming is performed by addressing the con?uration register, shifting data in, and then executing a program con?uration instruction, after which the data is transferred to internal e 2 cmos cells. it is these non-volatile cells that store the con?uration or the ISPPAC-POWR6AT6. a set of instruc- tions are de?ed that access all data registers and perform other internal control operations. for compatibility between compliant devices, two data registers are mandated by the ieee 1149.1 speci?ation. others are func- tionally speci?d, but inclusion is strictly optional. finally, there are provisions for optional data registers de?ed by the manufacturer. the two required registers are the bypass and boundary-scan registers. figure 25 shows how the instruction and various data registers are organized in an ISPPAC-POWR6AT6. figure 25. ISPPAC-POWR6AT6 tap registers tap controller speci?s the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller design. in a given state, the controller responds according to the level on the tms input as shown in figure 26. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becoming valid on the falling edge of tck. there are six steady states within the controller: test-logic-reset, run- test/idle, shift-data-register, pause-data-register, shift-instruction-register and pause-instruction-register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within ?e tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. cfg_address register (5 bits) e 2 cmos non-volatile memory ues register (32 bits) idcode register (32 bits) bypass register (1 bit) instruction register (8 bits) test access port (tap) logic output latch tdi tck tms tdo multiplexer cfg_data register (56 bits)
lattice semiconductor ISPPAC-POWR6AT6 data sheet 28 figure 26. tap states when the correct logic sequence is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction shift is performed, no action will occur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruc- tion shift is performed. the states of the data and instruction register blocks are identical to each other differing only in their entry points. when either block is entered, the ?st action is a capture operation. for the data regis- ters, the capture-dr state is very simple: it captures (parallel loads) data onto the selected serial data path (previ- ously chosen with the appropriate instruction). for the instruction register, the capture-ir state will always load the idcode instruction. it will always enable the id register for readout if no other instruction is loaded prior to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?lind interrogation of any device in a compliant ieee 1149.1 serial chain. from the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by reentering the shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates the test mode (steady state = test). this is when the device is actually programmed, erased or veri?d. all other instructions are executed in the update state. test instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- facturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being speci?ally called out (all ones and all zeroes respec- tively). the ISPPAC-POWR6AT6 contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be con?ured and ver- i?d. table 7 lists the instructions supported by the ISPPAC-POWR6AT6 jtag test access port (tap) controller: test-logic-rst run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 00 00 00 11 00 00 11 11 00 11 00 11 11 11 1 0 note: the value shown adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 29 table 7. ISPPAC-POWR6AT6 tap instruction table bypass is one of the three required jtag instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the isppacpowr6at6. the ieee 1149.1 standard de?es the bit code of this instruction to be all ones (111111). the required sample/ preload instruction dictates the boundary-scan register be connected between tdi and tdo. the isppac- powr6at6 has no boundary scan register, so for compatibility it defaults to the bypass mode whenever this instruction is received. the bit code for this instruction is de?ed by lattice as shown in table 7. the extest (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between tdi and tdo. again, since the ISPPAC-POWR6AT6 has no boundary scan logic, the device is put in the bypass mode to ensure speci?ation compatibility. the bit code of this instruction is de?ed by the 1149.1 standard to be all zeros (000000). the optional idcode (identi?ation code) instruction is incorporated in the ISPPAC-POWR6AT6 and leaves it in its functional mode when executed. it selects the device identi?ation register to be connected between tdi and tdo. the identi?ation register is a 32-bit shift register containing information regarding the ic manufacturer, device type and version code (figure 27). access to the identi?ation register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is de?ed by lattice as shown in table 7. instruction command code comments extest 0000 0000 external test - defaults to bypass bulk_erase 0000 0011 bulk erase device program_security 0000 1001 program security fuse discharge 0001 0100 fast vpp discharge program_enable 0001 0101 enable program mode idcode 0001 0110 read contents of manufacturer id code (32 bits) ues_read 0001 0111 read contents of ues register from e 2 cmos (32 bits) ues_program 0001 1010 program ues bits into e 2 cmos sample 0001 1100 sample/preload - defaults to bypass program_disable 0001 1110 disable program mode reset 0010 0010 resets device (refer to reset command via jtag or i 2 c section of this data sheet) erase_done_bit 0010 0100 erases the done bit only cfg_verify 0010 1000 verify the con?uration data cfg_erase 0010 1001 erase just the con?uration data cfg_address 0010 1011 select the con?uration address register (4 bits) cfg_data_shift 0010 1101 con?uration data shift (56 bits) cfg_program 0010 1110 program con?uration data program_done_bit 0010 1111 programs the done bit bypass 1111 1111 bypass - connect tdo to tdi
lattice semiconductor ISPPAC-POWR6AT6 data sheet 30 figure 27. ISPPAC-POWR6AT6 id code ISPPAC-POWR6AT6 speci? instructions there are 15 unique instructions speci?d by lattice for the ISPPAC-POWR6AT6. these instructions are primarily used to interface to the various user registers and the e 2 cmos non-volatile memory. additional instructions are used to control or monitor other features of the device. a brief description of each unique instruction is provided in detail below, and the bit codes are found in table 7. bulk_erase - this instruction will bulk erase the ISPPAC-POWR6AT6. the action occurs at the second rising edge of tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). program_security - this instruction is used to program the electronic security fuse (esf) bit. programming the esf bit protects proprietary designs from being read out. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). discharge - this instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ISPPAC-POWR6AT6 for a read cycle. program_enable - this instruction enables the programming mode of the ISPPAC-POWR6AT6. idcode - this instruction connects the output of the identi?ation code data shift (idcode) register to tdo (figure 28), to support reading out the identi?ation code. figure 28. idcode register ues_read - this instruction both reads the e 2 cmos bits in the ues register and places the ues register between the tdi and tdo pins (as shown in figure 29), to support programming or reading of the user electronic signature bits. figure 29. ues register ues_prog - this instruction will program the content of the ues register into the ues e 2 cmos memory. the device must already be in programming mode (program_ enable instruction). program_disable - this instruction disables the programming mode of the isppac-powr6a6. the test- logic-reset jtag state can also be used to cancel the programming mode of the isppac-powr6a6. xxxx / 0000 0001 1000 0000 / 0000 0100 001 / 1 msb lsb version (4 bits) e 2 configured part number (16 bits) 0180h = ISPPAC-POWR6AT6 jedec manufacturer identity code for lattice semiconductor (11 bits) constant 1 (1 bit) per 1149.1-1990 tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 27 bit 28 bit 29 bit 30 bit 31 tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 11 bit 12 bit 13 bit 14 bit 15
lattice semiconductor ISPPAC-POWR6AT6 data sheet 31 reset - this command resets the ISPPAC-POWR6AT6 to a condition near that of the power-on reset state (refer to reset command via jtag or i 2 c section of this data sheet for more details and known exceptions). erase_done_bit - this instruction erases the isppac-powr6a6 done bit. cfg_verify - this instruction is used to verify the contents of the selected con?uration array column. this spe- ci? column is preselected by using cfg_address instruction. cfg_erase - this instruction will bulk erase the con?uration array. the action occurs at the second rising edge of tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). cfg_address - this instruction is used to set the address of the con?uration array for subsequent program or read operations. cfg_data_shift - this instruction is used to shift data into the con?uration register prior to programming or reading. cfg_program - this instruction programs the selected con?uration array column. this speci? column is pre- selected by using cfg_address instruction. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). program_done_bit - this instruction programs the isppac-powr6a6 done bit. note: before any of the above programming instructions are executed, the respective e 2 cmos bits need to be erased using the corresponding erase instruction
lattice semiconductor ISPPAC-POWR6AT6 data sheet 32 package diagram 32-pin qfn dimensions in millimeters 3.5 0.20 a c 2x seating plane 2x 0.20 b c pin 1 id 3 n 1 b a 5.00 0.25 2x ca b 0.25 2x cb a a1 a3 a2 l e 0.08 5 c e2 b 0.10 a m c n 1 d2 3 4 4x 32x c pin #1 id fiducial located in this are a 5.00 3 4 5 4.75 4.75 0 0 top view bottom view side view all dimensions are in millimeters. notes: unless otherwise specified 2. 1. 1.00 1.00 0.50 0.05 max. per ansi y14.5m. 0.20 and 0.25 mm from terminal tip. terminal and is measured between dimension b applies to plated feature is optional. exact shape and size of this 0.20 ref e l d2 a3 a2 0.50 bsc 0.40 0.30 0.65 dimensions and tolerances - 0.00 min. symbol a1 a 0.85 0.01 nom. applies to exposed portion of terminals. 2.70 1.25 3.25 2.70 e2 1.25 3.25 12 - - 0.00 b 0.18 0.24 0.30 note: if soldered to the circuit board for thermal considerations, insure the thermal pad is connected electrically to ground. otherwise, the thermal pad should not be connected electrically (must be left "floating"). for important information on the preferred mounting of qfn packages, refer to the following application note at: http://www.amkor.com/products/notes_papers/mlfappnote.pdf.
lattice semiconductor ISPPAC-POWR6AT6 data sheet 33 part number description ordering information conventional packaging lead-free packaging part number package pins ISPPAC-POWR6AT6-01n32i qfn 32 part number package pins ISPPAC-POWR6AT6-01nn32i qfn 32 device number ISPPAC-POWR6AT6 - 01xx32x operating temperature range i = industrial (-40 o c to +85 o c) package n = 32-pin qfn nn = lead-free 32-pin qfn* *contact factory for package availability. performance grade 01 = standard device family
lattice semiconductor ISPPAC-POWR6AT6 data sheet 34 package options 24 23 22 21 20 19 1 8 17 1 2 3 4 5 6 7 8 tdo vccj tck tdi tms cltenb vps1 vps0 vmon6gs vmon5 vmon5gs vmon4 vmon4gs vmon3 vmon3gs vmon2 cltlock/smba scl sda vccd vcca vmon1gs vmon1 vmon2gs gnd trim1 trim2 trim3 trim4 trim5 trim6 vmon6 9 10111213141516 ISPPAC-POWR6AT6 32-pin qfn 32 31 30 29 2 8 27 26 25

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