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copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 30 w digital audio amplifier with integrated adc digital amplifier features ? fully integrated power mosfets ? no heatsink required ? programmable power foldback on thermal warning ? high efficiency ? > 100 db dynamic range ? < 0.1% thd+n @ 1 w ? configurable outputs (10% thd+n) ? 1 x 30 w into 4 , parallel full-bridge ? 2 x 15 w into 8 , full-bridge ? 2 x 7 w into 4 , half-bridge + 1 x 15 w into 8 , full-bridge ? built-in protection with error reporting ? overcurrent/undervoltage/thermal overload shutdown ? thermal warning reporting ? pwm popguard ? for half-bridge mode ? click-free start-up ? programmable channel delay for system noise & radiated emissions management adc features ? stereo, 24-bit, 48 khz conversion ? multi-bit architecture ? 95 db dynamic range (a-wtd) ? -86 db thd+n ? supports 2 vrms input with passive components system features ? asynchronous 2-channel digital serial port ? 32 khz to 96 khz input sample rates ? operation with on-chip oscillator driver or applied sys_clk at 18.432, 24.576 or 27.000 mhz ? integrated sample rate converter (src) ? eliminates clock-jitter effects ? input sample rate independent operation ? simplifies system integration ? spread spectrum pwm modulation ? reduces emi radiated energy ? low quiescent current (features continued on page 2 ) vp amplifier out 1 amplifier out 2 pgnd amplifier out 3 amplifier out 4 stereo analog in pwm modulator output 2 pwm modulator output 1 gate drive gate drive gate drive gate drive multi-bit ? modulator with integrated sample rate converter audio processing parametric eq high-pass bass/treble adaptive 2-ch mixer 2.1 bass mgr linkwitz-riley crossover de-emphasis serial audio clocks & data serial audio data i/o serial audio clocks & data serial audio input port multi-bit ? adc volume crystal driver i/o system clock crystal oscillator driver register /hardware configuration i2c or hardware configuration reset interrupt error protection thermal warning over current thermal feedback under voltage hp detect/mute pwm 2.5 v to 5 v 8 v to 18 v auxiliary serial port serial audio delay interface loudness compensation august '07 ds726pp1 CS4525
2 ds726pp1 CS4525 software mode system features ? digital audio processing ? 5 programmable parametric eq filters ? selectable high-pass filter ? bass/treble tone control ? adaptive loudness compensation ? 2-channel mixer ? 2.1 bass management ? 24 db/octave linkwitz-riley crossover filters ? de-emphasis filter ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit ? right-justified 16-, 18-, 20-, 24-bits ? digital serial connection to additional CS4525 or dacs for subwoofer ? digital interface to external lip-sync delay ? pwm switch rate shif ting eliminates am frequency interference ? digital volume control with soft ramp ? +24 to -103 db in 0.5 db steps ? programmable peak detect and limiter ? 2-channel logic-level pwm output ? programmable channel mapping ? can drive an external pwm amplifier, headphone amplifier, or line-out amplifier ? integrated headphone detection ? flexible power output configurations ? thermal foldback for interruption-free power-stage protection ? supports internal and external power stages ? operation from on-chip oscillator driver or applied systems clock ? supports i2c ? host control interface hardware mode system features ? 2-channel stereo full-bridge power outputs ? analog and digital inputs ? i2s and left-justified serial input formats ? thermal foldback for interruption-free protection of internal power stage ? operation from applied systems clock ? external mute input common applications ? integrated digital tv?s ? flat panel tv monitors ? computer/tv monitors ? mini/micro shelf systems ? digital powered speakers ? portable docking stations ? computer desktop audio general description the CS4525 is a stereo analog or digital input pwm high efficiency class d amplifier audio system with an integrated stereo analog-to-di gital (a/d) converter. the stereo power amplifiers can deliver up to 15 w per channel into 8 speakers from a small space-saving 48-pin qfn package. the pwm amplifier can achieve greater than 85% efficiency. the package is thermally enhanced for optimal heat dissipation which eliminates the need for a heatsink. the power stage outputs can be configured as two full- bridge channels for 2 x 15 w operation, two half-bridge channels and one full-bridge channel for 2 x 7 w + 1 x 15 w operation, or one parallel full-bridge channel for 1 x 30 w operation. the CS4525 integrates on-chip over-current, under-voltage, and over-tempera- ture protection and error reporting as well as a thermal warning indicator and programmable foldback of the output power to allow cooling. the main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (src ) which eases system inte- gration. the src allows for a fixed pwm switching frequency regardless of incoming sample rate as well as optimal clocking fo r the a/d modulators. an on-chip oscillator driver eliminates the need for an external crystal oscillator ci rcuit, reducing overall design cost and conserving circuit board space. the CS4525 automatically uses the on-chi p oscillator driver in the absence of an applied master clock. the CS4525 is available in a 48-pin qfn package in commercial grade (-10 to +70 c). the crd4525-q1 4-layer, 1 oz. copper and crd4525-d1 2-layer, 1 oz. copper customer reference designs are also available. please refer to ?ordering information? on page 97 for complete ordering information.
ds726pp1 3 CS4525 table of contents 1. pin descriptions - software mode .......................................................................................... 8 2. pin descriptions - hardware mode ....................................................................................... 10 2.1 digital i/o pin characteristics ........................................................................................... ............. 12 3. typical connection diagrams ................................................................................................ .13 4. typical system config uration diagrams . ................. ................ ................ ................ ......... 15 5. characteristics and specificatio ns .......... ................. ................ ................ ................ ......... 18 6. applications ............................................................................................................... .................... 26 6.1 software mode ............................................................................................................. .................. 26 6.1.1 system clocking ......................................................................................................... .......... 26 6.1.1.1 sys_clk input clo ck mode .......... ................. ................ ................ ................ ......... 26 6.1.1.2 crystal oscillator mode ............................................................................................ 27 6.1.2 power-up and power-down ................................................................................................. 28 6.1.2.1 recommended power-up sequence ....................................................................... 28 6.1.2.2 recommended po wer-down sequence .................................................................. 28 6.1.3 input source selection .......................... ........................................................................ ........ 29 6.1.4 digital sound processing ................................................................................................ ...... 29 6.1.4.1 pre-scaler ............................................................................................................ ..... 30 6.1.4.2 digital signal processing high-pass f ilter ............................................................... 30 6.1.4.3 channel mixer ......................................................................................................... .30 6.1.4.4 de-emphasis ........................................................................................................... .31 6.1.4.5 tone control .......................................................................................................... ... 31 6.1.4.6 parametric eq ......................................................................................................... .33 6.1.4.7 adaptive loudness comp ensation ........................................................................... 34 6.1.4.8 bass management .................................................................................................... 35 6.1.4.9 volume and muting control ...................................................................................... 36 6.1.4.10 peak signal limiter ................................................................................................. 3 7 6.1.4.11 thermal limiter ...................................................................................................... .39 6.1.4.12 thermal foldback ................................................................................................... 40 6.1.4.13 2-way crossover & sensitivity contro l ................................................................... 41 6.1.5 auxiliary serial output ................................................................................................. ......... 43 6.1.6 serial audio delay & warning input port . ............................................................................. 44 6.1.6.1 serial audio delay interface ..................................................................................... 44 6.1.6.2 external warning input port ..................................................................................... 44 6.1.7 powered pwm outputs ..................................................................................................... ... 45 6.1.7.1 output channel configurations ................................................................................ 45 6.1.7.2 pwm popguard transient control ............................................................................ 45 6.1.8 logic-level pwm outputs ................................................................................................. ... 46 6.1.8.1 recommended pwm_sig power-up sequence for an external pwm amplifier .... 47 6.1.8.2 recommended pwm_sig power-down sequence for an external pwm amplifier 47 6.1.8.3 recommended pwm_sig power-up se quence for headphone & line-out .......... 48 6.1.8.4 recommended pwm_sig power-down sequence for headphone & line-out ..... 48 6.1.8.5 pwm_sig logic-level ou tput configurations ......................................................... 49 6.1.9 pwm modulator configuration ............................................................................................. .50 6.1.9.1 pwm channel delay ................................................................................................ 50 6.1.9.2 pwm am frequency shift ........................................................................................ 51 6.1.10 headphone detection & hard ware mute input ...... ............................................................. 51 6.1.11 interrupt reporting .... ................................................................................................ .......... 53 6.1.12 automatic power stage shut-down ............. ...................................................................... 53 6.2 hardware mode ............................................................................................................. ................ 54 6.2.1 system clocking ......................................................................................................... .......... 54 6.2.2 power-up and power-down ................................................................................................. 54 6.2.2.1 recommended power-up sequence ....................................................................... 54
4 ds726pp1 CS4525 6.2.2.2 recommended power-down sequence .................................................................. 55 6.2.3 input source selection .................................................................................................. ........ 55 6.2.4 pwm channel delay ....................................................................................................... ..... 55 6.2.5 digital signal flow ..................................................................................................... ........... 56 6.2.5.1 high-pass filter ...................................................................................................... .. 56 6.2.5.2 mute control .......................................................................................................... ... 56 6.2.5.3 warning and error reporting .................................................................................... 56 6.2.6 thermal foldback ........................................................................................................ ......... 57 6.2.7 automatic power stage shut-down ..................................................................................... 58 6.3 pwm modulators and sample ra te converters ............................................................................ 58 6.4 output filters ............................................................................................................ ..................... 59 6.4.1 half-bridge output filter ............................................................................................... ........ 59 6.4.2 full-bridge output filter (s tereo or parallel) ........................................................................ 60 6.5 analog inputs ............................................................................................................. .................... 61 6.6 serial audio interfaces ................................................................................................... ................ 62 6.6.1 i2s data format .................................... ..................................................................... ........... 62 6.6.2 left-justified data format .............................................................................................. ...... 62 6.6.3 right-justified data format ............................................................................................. ..... 63 6.7 integrated vd regulator ................................................................................................... ............. 63 6.8 i2c control port description and timing ................................................................................... ..... 64 7. pcb layout considerations .................................................................................................. ... 65 7.1 power supply, grounding ................................................................................................... ........... 65 7.2 qfn thermal pad ........................................................................................................... ............... 65 8. register quick reference ................................................................................................... ..... 66 9. register descriptions ...................................................................................................... .......... 69 9.1 clock configuration (address 01h) ................ ......................................................................... ....... 69 9.1.1 sys_clk output enab le (ensysclk) ...... ................ ................ ................. ................ ............ 69 9.1.2 sys_clk output divi der (divsysclk) ............ ................ ................ ................ ............. ......... 69 9.1.3 clock frequency (clkfreq[1:0]) .......................................................................................... .. 69 9.1.4 hp_detect/mute pin active logic level (hp/ mutepol) ......................................................... 70 9.1.5 hp_detect/mute pin mode (hp/mute) ........ .......................................................................... 70 9.1.6 modulator phase shifting (p haseshift) ................................................................................. 70 9.1.7 am frequency shifting (freqshift) ....................................................................................... 70 9.2 input configuration (address 02h) ......................................................................................... ........ 71 9.2.1 input source selection (adc/sp) ......................................................................................... 71 9.2.2 adc high-pass filter enab le (enanhpf) ............................................................................ 71 9.2.3 serial port sample rate (sprate[1:0]) - r ead only ............................................................ 71 9.2.4 input serial port digital in terface format (dif [2:0]) ............................................................ 71 9.3 aux port configuration (address 03h) ...................................................................................... .... 72 9.3.1 enable aux serial port (enauxport) ........ ............................................................................. 7 2 9.3.2 delay & warning port configuration (dlyportcfg[1:0]) ......................................................... 72 9.3.3 aux/delay serial port digit al interface format (auxi2s/lj) .................................................. 72 9.3.4 aux serial port right channel data select (rchdsel[1:0]) ................................................. 72 9.3.5 aux serial port left channel data select (lchdsel[1:0]) .................................................... 73 9.4 output configuration (address 04h) ....................................................................................... ...... 73 9.4.1 output configuratio n (outputcfg[1:0]) .................................................................................. 7 3 9.4.2 pwm signals output data select (pwmdsel[1 :0]) .............................................................. 73 9.4.3 channel delay settings (outputdly[3:0]) . ............................................................................. 73 9.5 foldback and ramp configuration (address 05h) ......................................................................... 74 9.5.1 select vp level (selectvp) .............................................................................................. .... 74 9.5.2 enable thermal foldback (entherm) ................................................................................... 74 9.5.3 lock foldback adjust (lockadj) .......................................................................................... .74 9.5.4 foldback attack delay (attackdly[1:0]) ... ............................................................................. 75 9.5.5 enable foldback floor (e nfloor) ......................................................................................... .75
ds726pp1 5 CS4525 9.5.6 ramp speed (rmpspd[1:0]) ................................................................................................ 75 9.6 mixer / pre-scale configuration (address 06h) ............................................................................. 75 9.6.1 pre-scale attenuation (prescale[2:0]) .................................................................................. 7 5 9.6.2 right channel mixer (rchmix[1:0]) ...................................................................................... 7 6 9.6.3 left channel mixer (lchmix[1:0]) ........................................................................................ .76 9.7 tone configuration (address 07h) .......................................................................................... ....... 76 9.7.1 de-emphasis control (deemph) .......................................................................................... 76 9.7.2 adaptive loudness compensation control ( loudness) ....................................................... 76 9.7.3 digital signal processing hig h-pass filter (endighp f) ....................................................... 77 9.7.4 treble corner frequency (t rebfc[1:0]) ................................................................................ 77 9.7.5 bass corner frequency (ba ssfc[1:0]) ................................................................................. 77 9.7.6 tone control enable (entonectrl) ....................................................................................... 7 7 9.8 tone control (address 08h) ................................................................................................ ........... 78 9.8.1 treble gain leve l (treb[3:0]) ........................................................................................... ..... 78 9.8.2 bass gain level (bass[3:0]) ............................................................................................. .... 78 9.9 2.1 bass manager/parametric eq control (address 09h) ............................................................. 78 9.9.1 freeze controls (freeze) ................................................................................................ ...... 78 9.9.2 hi-z pwm_sig outputs (hizpsig) ....................................................................................... 79 9.9.3 bass cross-over frequency (bassmgr[2:0]) ........................................................................ 79 9.9.4 enable channel b parametr ic eq (enchbpeq) ...... ................ ................. ................ ............ 79 9.9.5 enable channel a parametr ic eq (enchapeq) ...... ................ ................. ................ ............ 79 9.10 volume and 2-way cross-over configuration (address 55h) ..................................................... 80 9.10.1 soft ramp and zero cross control (szcmode[1:0]) .......... ................................................ 80 9.10.2 enable 50% duty cycle for mute condition (mute50/50) ................................................... 80 9.10.3 auto-mute (automute) ..... .............................................................................................. ..... 80 9.10.4 enable 2-way cro ssover (en2way) ................................................................................... 81 9.10.5 2-way cross-over frequency (2wayfreq[2:0]) ................................................................. 81 9.11 channel a & b: 2-way sensitivity control (address 56h) ............................................................ 81 9.11.1 channel a and chan nel b low-pass sensitivity adjust (lowpass[3:0]) ............................ 81 9.11.2 channel a and channel b high-pass sensitiv ity adjust (highpass[3:0]) ........................... 82 9.12 master volume control (addr ess 57h) ..................................................................................... ... 82 9.12.1 master volume control (mvol[7:0]) .......... .......................................................................... 82 9.13 channel a and b volume control (address 58h & 59h) .............................................................. 83 9.13.1 channel x volume control (chxvol[7:0]) . .......................................................................... 83 9.14 sub channel volume control (address 5ah) .............................................................................. 83 9.14.1 sub channel volume contro l (subvol[7:0]) ....................................................................... 83 9.15 mute/invert co ntrol (address 5bh) ........................................................................................ ...... 84 9.15.1 adc invert signal polarity (invadc) ..... ............................................................................. 84 9.15.2 invert channel pwm signal polarity (invch x) ................................................................... 84 9.15.3 invert sub pwm signal polarity (invsub) ........................................................................... 84 9.15.4 adc channel mute (muteadc) .......................................................................................... 84 9.15.5 independent channel a & b mute (mutechx) .................................................................... 84 9.15.6 sub channel mute (mutesub ) ............................................................................................ 8 5 9.16 limiter configuration 1 (address 5ch) ...... .............................................................................. ..... 85 9.16.1 maximum threshold (max[2:0]) .................... ...................................................................... 8 5 9.16.2 minimum threshold (min[2:0]) ........................................................................................... .85 9.16.3 peak signal limit all channels (limitall) ............................................................................ 86 9.16.4 peak detect and limiter enable (enlimiter) ....................................................................... 86 9.17 limiter configuration 2 (address 5dh) ...... .............................................................................. ..... 87 9.17.1 limiter release rate (rra te[5:0]) ...................................................................................... 87 9.18 limiter configuration 3 (address 5eh) ...... .............................................................................. ..... 87 9.18.1 enable thermal limiter (enthlim) ........... .......................................................................... 87 9.18.2 limiter attack rate (arate[5:0]) ............ ........................................................................... .. 87 9.19 power control (addr ess 5fh) .............................................................................................. ........ 88
6 ds726pp1 CS4525 9.19.1 automatic power stage retry (autoretry) ......................................................................... 88 9.19.2 select vd level (selectvd) ............................................................................................. ... 88 9.19.3 power down adc (pdnadc) ....................... ...................................................................... 88 9.19.4 power down pwm power output x (pdnoutx ) ................................................................. 88 9.19.5 power down (pdnall) .................................................................................................... ..... 89 9.20 interrupt (address 60h) ................................................................................................. .............. 89 9.20.1 src lock state transition interrupt (srclock) ................................................................ 89 9.20.2 adc overflow interrupt (adcovfl) ........... .......................................................................... 90 9.20.3 channel overflow interrupt (chovfl) .................................................................................. 90 9.20.4 amplifier error interrupt bit (amperr) ................................................................................. .90 9.20.5 mask for src state (srclockm) ...................................................................................... 90 9.20.6 mask for adc overflow (adcovflm) .................................................................................. 91 9.20.7 mask for channel x and sub overflow (chovflm) ............................................................. 91 9.20.8 mask for amplifier error (amperrm) ................................................................................... 91 9.21 interrupt status (a ddress 61h) - read only ............................................................................... .. 92 9.21.1 src state transition (srclockst) .................................................................................... 92 9.21.2 adc overflow (adcovflst) ............................................................................................... .92 9.21.3 sub overflow (subovflst) ............................................................................................... .... 92 9.21.4 channel x overflow (chxovflst) ........................................................................................ 9 2 9.21.5 ramp-up cycle complete (rampdone) ............................................................................ 93 9.22 amplifier error status (addre ss 62h) - read only ....................................................................... 93 9.22.1 over-current detected on channel x (overcurrx) ........................................................... 93 9.22.2 external amplifier state (extampst) ...... ............................................................................. 9 3 9.22.3 under voltage / thermal error state (uvte[ 1:0]) .............................................................. 93 9.23 device i.d. and revision (a ddress 63h) - read only .................................................................. 94 9.23.1 device identification (deviceid[4:0]) ... ............................................................................... .94 9.23.2 device revision (revid[2:0]) .............. ............................................................................. ... 94 10. parameter definitions ..................................................................................................... ......... 95 11. references ................................................................................................................ .................... 95 12. package dimensions ........................................................................................................ .......... 96 13. thermal characteristics ................................................................................................... .... 97 13.1 thermal flag ............................................................................................................. ................... 97 14. ordering information ...................................................................................................... ........ 97 15. revision history .......................................................................................................... ................ 98 list of figures figure 1.typical connection diagram - software mode ........................................................................... 13 figure 2.typical connection diagram - hardware mo de .......................................................................... 1 4 figure 3.typical system configuration 1 ....................................................................................... ........... 15 figure 4.typical system configuration 2 ....................................................................................... ........... 15 figure 5.typical system configuration 3 ....................................................................................... ........... 16 figure 6.typical system configuration 4 ....................................................................................... ........... 17 figure 7.serial audio input port timing ....................................................................................... ............. 21 figure 8.aux serial port interface master mode ti ming ......................................................................... .22 figure 9.sys_clk timing from rese t .............. ................. ................ ................ ................ ............. ......... 23 figure 10.pwm_sigx timing ..................................................................................................... .............. 23 figure 11.control port timing - i2c .............. ............................................................................. ................ 24 figure 12.typical sys_clk input clo cking configuration .... ................ ................ ............. ............. ......... 2 6 figure 13.typical crystal oscillator clocking config uration ................................................................... .. 27 figure 14.digital signal flow ................................................................................................. ................... 29 figure 15.de-emphasis filter .................................................................................................. ................. 31 figure 16.bi-quad filter archit ecture ......................................................................................... ............... 33 figure 17.peak signal detection & limiting .................................................................................... .......... 37
ds726pp1 7 CS4525 figure 18.foldback process .................................................................................................... ................. 40 figure 19.popguard connection diagram ......................................................................................... ........ 46 figure 20.2-channel full-bridge pwm output delay .............................................................................. .50 figure 21.3-channel pwm output delay .......................................................................................... ........ 50 figure 22.typical sys_clk input clock ing configuration .... ................ ................ ............. ............. ......... 5 4 figure 23.hardware mode pwm output delay ...................................................................................... ... 55 figure 24.hardware mode digital signal flow ................................................................................... ....... 56 figure 25.foldback process .................................................................................................... ................. 57 figure 26.output filter - half-bridge ......................................................................................... ................ 59 figure 27.output filter - full-bridge ......................................................................................... ................. 60 figure 28.recommended unity gain input filter ................................................................................. ..... 61 figure 29.recommended 2 v rms input filter ........................................................................................... 61 figure 30.i2s serial audio formats ................. ........................................................................... ............... 62 figure 31.left-justified serial audio formats ................................................................................. .......... 62 figure 32.right-justified serial audio formats ................................................................................ ......... 63 figure 33.control port timing, i2c write ...................................................................................... ............. 64 figure 34.control port timing, i2c read ....................................................................................... ............ 64 list of tables table 1. i/o power rails ...................................................................................................... ..................... 12 table 2. bass shelving filter co rner frequencies .............................................................................. ...... 31 table 3. treble shelving filter corner frequencies ............................................................................ ..... 32 table 4. bass management cross-ov er frequencies .............................................................................. 3 5 table 5. 2-way cross-over frequencies ......................................................................................... ......... 41 table 6. auxiliary serial port data output .................................................................................... ............ 43 table 7. nominal switching frequencie s of the auxiliary serial output ................................................... 43 table 8. pwm power output configurations ......... ............................................................................. ...... 45 table 9. typical ramp times for various vp voltage s ........................................................................... .46 table 10. pwm logic-level output configurations ............................................................................... ... 49 table 11. pwm output switching rates and quantizatio n levels ........................................................... 51 table 12. output of pwm_sig outputs ........................................................................................... ......... 52 table 13. sys_clock frequency sele ction .............. ................ ................ ................. ............ ............ .... 54 table 14. input source selectio n .............................................................................................. ................ 55 table 15. serial audio interface format selection ....................... ...................................................... ....... 55 table 16. thermal foldback enable selection ................................................................................... ...... 57 table 17. pwm output switching rates and quantizatio n levels ........................................................... 58 table 18. low-pass filter compo nents - half-bridge ............................................................................ ... 59 table 19. dc-blocking capacitors values - half-bri dge ......................................................................... .. 59 table 20. low-pass filter compo nents - full-bridge ............................................................................ ... 60 table 21. power supply configurat ion and settings ............................................................................. .... 63
8 ds726pp1 CS4525 1. pin descriptions - software mode pin name pin # pin description int 1 interrupt (output ) - indicates an interrupt condition has occurred. scl 2 serial control port clock ( input ) - serial clock for the i2c control port. sda 3 serial control data ( input/output ) - bi-directional data i/o for the i2c control port. lrck 4 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 5 serial clock ( input ) - serial bit clock for the serial audio interface. sdin 6 serial audio data input ( input ) - input for two?s complement serial audio data. hp_detect/ mute 7 headphone detect / mute ( input ) - headphone detection or mute input signal as configured via the i2c control port. rst 8 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. top-down (through package) view 48-pin qfn package 12 7 6 5 4 3 2 1 11 10 9 8 25 30 31 32 33 34 35 36 26 27 28 29 14 13 15 16 17 18 19 20 21 22 23 24 47 48 46 45 44 43 42 41 40 39 38 37 int scl sda lrck sclk sdin hp_detect/mute rst lvd dgnd vd_reg vd vp out1 pgnd pgnd out2 vp vp out3 pgnd pgnd out4 vp va_reg agnd filt+ vq afiltl afiltr ainl ainr ocref pgnd pgnd ramp_cap xti xto sys_clk aux_lrck/ad0 aux_sclk aux_sdout dly_sdin/ex_twr dly_sdout pwm_sig1 pwm_sig2 pgnd pgnd thermal pad
ds726pp1 9 CS4525 lvd 9 vd voltage level indicator ( input ) - identifies the voltage level attached to vd. when applying 5.0 v to vd, lvd must be connected to vd. when applying 2.5 v or 3.3 v to vd, lvd must be dgnd. dgnd 10 digital ground ( input ) - ground for the internal logic and digital i/o. vd_reg 11 core logic power ( output ) - internally generated low voltage power supply for digital logic. vd 12 power ( input ) - positive power supply for the internal regulators and digital i/o. va_reg 13 analog power (output) - internally generated positive power for the analog section and i/o. agnd 14 analog ground ( input ) - ground reference for the internal analog section and i/o. filt+ 15 positive voltage reference ( output ) - positive reference voltage for the internal adc sampling circuits. vq 16 common mode voltage ( output ) - filter connection for inte rnal common mode voltage. afiltl afiltr 17 18 antialias filter connection ( output ) - antialias filter connection for adc inputs. ainl ainr 19 20 analog input ( input ) - the full-scale input level is specifi ed in the adc analog characteristics specification table. ocref 21 over current reference setting ( input ) - sets the reference for over current detection. pgnd 22,23 27,28 33,34 37,38 power ground ( input ) - ground for the individual output power half-bridge devices. ramp_cap 24 output ramp capacitor ( input ) - used by the pwm popguard transient control to suppress the initial pop in half-bridge-configured outputs. vp 25,30, 31,36 high voltage power ( input ) - high voltage power supply for the individual half-bridge devices. out4 out3 out2 out1 26 29 32 35 pwm output ( output ) - amplified pwm power outputs. pwm_sig2 pwm_sig1 39 40 logic level pwm output ( output ) - logic level pwm switching signals. dly_sdout 41 delay serial audio data out ( output ) - output for two?s comple ment serial audio data. dly_sdin/ ex_twr 42 delay serial audio data input ( input ) - input for two?s comple ment serial audio data. external thermal warning ( input ) - input for an external thermal warning signal. configurable via the i2c control port. aux_sdout 43 auxiliary port serial audio data out ( output ) - output for two?s compleme nt auxiliary port serial data. aux_sclk 44 auxiliary port serial clock (output ) - serial clock for the aux iliary port seri al interface. aux_lrck/ ad0 45 auxiliary port left right clock (output ) - determines which channel, left or right, is currently active on the serial audio data line. ad0 (input ) - sets the lsb of the i2c device address. sensed on the release of rst . sys_clk 46 system clock ( input/output ) -clock source for the internal logic, processing, and modulators. this pin should be connected to through a 10k to ground when unused. xto 47 crystal oscillator output (output) - crystal oscillator driver output. xti 48 crystal oscillator input ( input ) - crystal oscillator driver input. thermal pad - thermal pad - thermal relief pad for optimized heat dissipation. see ?qfn thermal pad? on page 65 for more information.
10 ds726pp1 CS4525 2. pin descriptions - hardware mode pin name pin # pin description clk_freq0 clk_freq1 1 2 clock frequency (input) - determines the frequency of the clock expected to be driven into the sys_clk pin. adc/sp 3 adc/serial port (input) - selects between the analog to digital converter and the serial port for audio input. selects the adc when high or the serial port when low. lrck 4 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 5 serial clock ( input ) - serial bit clock for the serial audio interface. sdin 6 serial audio data input ( input ) - input for two?s complement serial audio data. mute 7 mute ( input ) - the pwm outputs will output silence as a 50% duty cycle signal when this pin is driven low. rst 8 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. top-down (through package) view 48-pin qfn package 12 7 6 5 4 3 2 1 11 10 9 8 25 30 31 32 33 34 35 36 26 27 28 29 14 13 15 16 17 18 19 20 21 22 23 24 47 48 46 45 44 43 42 41 40 39 38 37 clk_freq0 clk_freq1 adc/sp lrck sclk sdin mute rst lvd dgnd vd_reg vd vp out1 pgnd pgnd out2 vp vp out3 pgnd pgnd out4 vp va_reg agnd filt+ vq afiltl afiltr ainl ainr ocref pgnd pgnd ramp_cap tsti tsto sys_clk i2s/lj en_tfb erroc erruvte twr tsto tsto pgnd pgnd thermal pad
ds726pp1 11 CS4525 lvd 9 vd voltage level indicator ( input ) - identifies the voltage level attached to vd. when applying 5.0 v to vd, lvd must be connected to vd. when applying 2.5 v or 3.3 v to vd, lvd must be con- nected to dgnd. dgnd 10 digital ground ( input ) - ground for the internal logic and i/o. vd_reg 11 core logic power ( output ) - internally generated low voltage power supply for digital logic. vd 12 digital power ( input ) - positive power supply for the internal regulators and digital i/o. va_reg 13 analog power (output) - internally generated positive power for the analog section and i/o. agnd 14 analog ground ( input ) - ground reference for the internal analog section and i/o. filt+ 15 positive voltage reference ( output ) - positive reference voltage for the internal adc sampling circuits. vq 16 common mode voltage ( output ) - filter connection for inte rnal common mode voltage. afiltl afiltr 17 18 antialias filter connection ( output ) - antialias filter connection for adc inputs. ainl ainr 19 20 analog input ( input ) - the full-scale input level is specifi ed in the adc analog characteristics specification table. ocref 21 over current reference setting ( input ) - sets the reference for over current detection. pgnd 22,23 27,28 33,34 37,38 power ground ( input ) - ground for the individual output power half-bridge devices. ramp_cap 24 output ramp capacitor ( input ) - this pin should be connected directly to vp in hardware mode. vp 25,30, 31,36 high voltage power ( input ) - high voltage power supply for the individual half-bridge devices. out4 out3 out2 out1 26 29 32 35 pwm output ( output ) - amplified pwm power outputs. tsto 39 40 test output (output) - these pins are outputs used for the logic level pwm switching signals available only in software mode. they must be left unconnected for hardware mode operation. twr 41 thermal warning output ( output ) - thermal warning output. erruvte 42 thermal and undervoltage error output ( output ) - error flag for therma l shutdown and under- voltage. erroc 43 overcurrent error output (output) - overcurrent error flag. en_tfb 44 enable thermal feedback (input) - enables the thermal foldback feature when high. i2s/lj 45 i2s/left justified (input) - selects between i2s and left-justified data format for the serial input port. selects i2s when high and lj when low. sys_clk 46 system clock ( input/output ) -clock source for the delta-sigma modulators. tsto 47 test output (output) - this pin is an output used for the cryst al oscillator driver available only in software mode. it must be left unconn ected for normal hardware mode operation. tsti 48 test input ( input ) - this pin is an input used for the crystal oscillator driver available only in soft- ware mode. it must be tied to digital ground for normal hardware mode operation. thermal pad - thermal pad - thermal relief pad for optimized heat dissipation. see ?qfn thermal pad? on page 65 for more information.
12 ds726pp1 CS4525 2.1 digital i/o pin characteristics the logic level for each input is set by its corresponding power supply and should not e xceed the maximum ratings. power supply pin number pin name i/o driver receiver software mode vd 1 int output 2.5 v-5.0 v, open drain 2 scl input - 2.5 v-5.0 v, with hysteresis 3 sda input/output 2.5 v-5.0 v, open drain 2.5 v-5.0 v, with hysteresis 7hp_detect mute input input - - 2.5 v-5.0 v 2.5 v-5.0 v 41 dly_sdout output 2.5 v-5.0 v, cmos - 42 dly_sdin ex_twr input input - - 2.5 v-5.0 v 2.5 v-5.0 v 43 aux_sdout output 2.5 v-5.0 v, cmos - 44 aux_sclk output 2.5 v-5.0 v, cmos - 45 aux_lrck output 2.5 v-5.0 v, cmos - vd_reg 39 pwm_sig2 output 2.5 v, cmos - 40 pwm_sig1 output 2.5 v, cmos - hardware mode vd 1 sel_osc0 input - 2.5 v-5.0 v 2 sel_osc1 input - 2.5 v-5.0 v 3 adc/sp input - 2.5 v-5.0 v 7 mute input - 2.5 v-5.0 v 41 twr output 2.5 v-5.0 v, open drain - 42 erruvte output 2.5 v-5.0 v, open drain - 43 erroc output 2.5 v-5.0 v, open drain - 44 en_tfb input - 2.5 v-5.0 v 45 i2s/lj input - 2.5 v-5.0 v all modes vd 4 lrck input - 2.5 v-5.0 v 5 sclk input - 2.5 v-5.0 v 6 sdin input - 2.5 v-5.0 v 8 rst input - 2.5 v-5.0 v 9 lvd input - 2.5 v-5.0 v 46 sys_clk input/output 2.5 v-5.0 v, cmos 2.5 v-5.0 v vp 26 out4 output 8.0 v-18.0 v power mosfet - 29 out3 output 8.0 v-18.0 v power mosfet - 32 out2 output 8.0 v-18.0 v power mosfet - 35 out1 output 8.0 v-18.0 v power mosfet - table 1. i/o power rails
ds726pp1 13 CS4525 3. typical connec tion diagrams +8 v to +18 v 31 30 25 v p 36 vp vp vp 12 v d 470 f 0.1 f 0.1 f 0.1 f 0.1 f 470 f 35 ramp_cap 0.1 f 10 f +3.3 or +5 v analog audio inputs 43 aux_sdout analog audio switch ainr 20 ainl 19 10 23 22 28 33 34 37 38 27 p g nd p g nd p g nd p g nd p g n d p g nd p g nd p g nd d g nd *note: resistors are required for i2c control port operation. out1 out2 output filter 35 32 out3 out4 output filter 29 26 pwm_sig2 39 40 pwm_sig1 line output - or - headphone output analog monitor output crystal 24.576 mhz xti xto 48 47 mpeg audio processor - or - hdmi receiver sdin 6 lrck 4 sclk 5 46 sys_clk 7 hp_detect/mute lip-synch delay nju26902 +2.5v vd_reg 11 0.1 f 10 f aux_sclk 44 dly_sdout 41 dly_sdin 42 aux_lrck/ad0 45 micro- controller rst 8 int 1 sda 3 scl 2 2 k 22 k 2 k vd * * agnd 14 va_reg 13 afilta 17 afiltb 18 filt+ 15 vq 16 0.1 f 10 f 150 pf 150 pf 10 f 1 f lvd 9 vd or gnd ocref 21 16.2 k note: on release of rst, ad0 is read as input on the aux_lrck line. 22 k ? ? 22 k figure 1. typical connection diagram - software mode CS4525
14 ds726pp1 CS4525 +8 v to +18 v 31 30 25 vp 36 v p v p v p 12 vd 470 f 0.1 f 0.1 f 0.1 f 0.1 f 470 f 35 ramp_cap 0.1 f 10 f +3.3 or +5 v analog audio inputs analog audio switch ainr 20 ainl 19 10 23 22 28 33 34 37 38 27 pgnd pgnd p g nd p g nd p gn d pgn d pgn d pgnd d gnd out1 out2 output filter 35 32 out3 out4 output filter 29 26 analog monitor output audio processor sdin 6 lrck 4 sclk 5 agnd 14 va_reg 13 afilta 17 afiltb 18 filt+ 15 vq 16 0.1 f 10 f 150 pf 150 pf 10 f 1 f lvd 9 vd or gnd ocref 21 16.2 k tsto tsti 47 48 46 sys_clk clock 24.576 mhz clk_freq0 1 clk_freq1 2 7 mute en_tfb 44 twr 41 erruvte 42 i2s/lj 45 micro- controller rst 8 22 k vd 43 erroc adc/sp 3 vd_reg 11 0.1 f 10 f 22 k 22 k tsto 39 40 tsto figure 2. typical connection diagram - hardware mode CS4525
ds726pp1 15 CS4525 4. typical system co nfiguration diagrams main tuner a/v switch pip tuner a/v in 1 a/v in 2 a/v in x audio delay 27 mhz crystal in crystal out 2 x 7 w stereo + 1 x 15 w subwoofer clock out control port mpeg decoder CS4525 pwm_sig1 pwm_sig2 power foldback aux out analog in digital in delay port gate drive gate drive gate drive gate drive sys_clk control port digital out monitor out hp/ line out left speaker right speaker subwoofer figure 3. typical system configuration 1 main tuner a/v switch pip tuner a/v in 1 a/v in 2 a/v in x monitor out audio delay analog out analog in analog out 27 mhz crystal in crystal out CS4525 pwm_sig1 pwm_sig2 gate drive gate drive gate drive gate drive cs4412a pwm in status out subwoofer 2 x 15 w stereo + 1 x 30 w subwoofer power foldback aux out analog in digital in delay port gate drive gate drive gate drive gate drive clock out sys_clk control port control port sound processor var/fixed out left speaker right speaker 22 k figure 4. typical system configuration 2
16 ds726pp1 CS4525 main tuner a/v switch pip tuner a/v in 1 a/v in 2 a/v in x monitor out audio delay analog out analog in analog out 18.432 mhz crystal in crystal out CS4525 pwm_sig1 pwm_sig2 gate drive gate drive gate drive gate drive cs4412a pwm in status out gate drive gate drive gate drive gate drive cs4412a pwm in status out left speaker right speaker subwoofer 2 x 30 w stereo + 1 x 30 w subwoofer power foldback aux out analog in digital in delay port gate drive gate drive gate drive gate drive clock out sys_clk control port control port sound processor var/fixed out 22 k 22 k figure 5. typical system configuration 3
ds726pp1 17 CS4525 main tuner a/v switch pip tuner a/v in 1 a/v in 2 a/v in x audio delay analog in analog out 18.432 mhz crystal in crystal out 2 x 15 w bi-amp stereo with subwoofer output clock out control port sound processor CS4525 pwm_sig1 pwm_sig2 power foldback aux out analog in digital in delay port gate drive gate drive gate drive gate drive sys_clk control port CS4525 pwm_sig1 pwm_sig2 power foldback aux out analog in digital in delay port gate drive gate drive gate drive gate drive sys_clk control port analog out digital out monitor out var/fixed out left woofer left tweeter right woofer right tweeter sub out figure 6. typical system configuration 4
18 ds726pp1 CS4525 5. characteristics and specifications recommended operating conditions agnd = dgnd = pgnd = 0 v; all voltages with respect to ground. notes: 1. for vd = 2.5 v, va_reg and vd_reg must be connected to vd. see section 6.7 on page 63 for details. absolute maximum ratings agnd = dgnd = pgnd = 0 v; all volt ages with respect to ground. warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 2. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 3. the maximum over/under voltage is limited by the input current. parameters symbol min nom max units dc power supply digital and analog core (note 1) vd 2.375 2.5 2.625 v vd 3.135 3.3 3.465 v vd 4.75 5.0 5.25 v amplifier outputs vp 8.0 - 18.0 v temperature ambient temperature commercial t a -10 - +70 c junction temperature t j -10 - +125 c parameters symbol min max units dc power supply power stage outputs switching and under load power stage no output switching digital and analog core vp vp vd -0.3 -0.3 -0.3 19.8 23.0 6.0 v v v inputs input current (note 2) i in -10ma analog input voltage (note 3) v ina agnd - 0.7 va_reg + 0.7 v digital input voltage (note 3) v ind -0.3 vd + 0.4 v temperature ambient operating temperature - power applied commercial t a -20 +85 c storage temperature t stg -65 +150 c
ds726pp1 19 CS4525 analog input characteristics test conditions (unless otherwise specified): agnd = dgn d = pgnd = 0 v; all voltages with respect to ground; t a = 25c; vd = 3.3 v; input signal: 1 khz sine wave th rough the recommended passive input filter shown in fig- ure 28 on page 61 ; capacitor values connected to afilta, afiltb, filt+, vq, vd_reg, and va_reg as shown in figure 1 on page 13 ; sample frequency = 48 khz; 10 hz to 20 khz measurement bandwidth; power outputs in power-down state (pdnout1 = 1, pdnout2 = 1, pdnout3/4 = 1). notes: 4. referred to the typical full-scale voltage 5. for vd = 2.5 v, va_reg and vd_reg must be connected to vd. see section 6.7 on page 63 for details. 6. measured between ainx and agnd. adc digital filter characteristics notes: 7. filter response is clock dependent and scales with the adc sampling frequency (fs). with a 27.000 mhz or 24.576 mhz xt al/sys_clk, fs is equal to the applied clock divi ded by 512. with an 18.432 mhz xtal/sys_clk, fs is equal to the applied clock divided by 384. parameter min typ max unit dynamic range (note 4) a-weighted unweighted 90 87 95 92 - - db db total harmonic distortion + noise -1 db -20 db -60 db - - - -86 -72 -32 -77 - - db db db dc accuracy interchannel gain mismatch - 0.05 - db gain drift - 100 - ppm/c interchannel isolation - 90 - db full-scale input voltage vd = 2.5v (note 5) vd = 3.3v vd = 5.0v 0.786*vd 0.590*vd 0.398*vd 0.827*vd 0.621*vd 0.419*vd 0.868*vd 0.652*vd 0.440*vd vpp vpp vpp input impedance (note 6) 40 - - k parameter min typ max unit passband (frequency response) (note 7) to -0.1 db corner 0 - 0.4948 fs passband ripple -0.09 - 0 db stopband (note 7) 0.6677 - - fs stopband attenuation 48.4 - - db total group delay - 2.7/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db - - 3.7 24.2 - - hz hz phase deviation 20 hz - 10 - deg passband ripple - - 0.17 db filter settling time -10 5 /fs - s
20 ds726pp1 CS4525 pwm power output characteristics test conditions (unless otherwise s pecified): agnd = dgnd = pgnd = 0 v; a ll voltages with respect to ground; t a = 25c; vd = 3.3 v; vp = 18 v; r l = 8 for full-bridge, r l = 4 for half-bridge and parallel full-bridge; outputdly[3:0] = 1111; phaseshift = 1 for half-bridge, phaseshift = 0 for full-bridge and parallel full-bridge; input signal: full-scale 997 hz sine wave through serial audio input port, 48 khz samp le rate; capacitor values connected to afilta, afiltb, filt+, vq, vd_reg, and va_reg as shown in figure 1 on page 13 ; pwm switch rate = 384 khz; 10 hz to 20 khz meas urement bandwidth; perf ormance measurements taken through aes17 fil- ter. parameters symbol conditions min typ max units power output per channel stereo full-bridge half-bridge parallel full-bridge p o thd+n < 10% thd+n < 1% thd+n < 10% thd+n < 1% thd+n < 10% thd+n < 1% - - - - - - 15 12 7 5.5 30 23.5 - - - - - - w w w w w w total harmonic distortion + noise stereo full-bridge half-bridge parallel full-bridge thd+n p o = 1 w p o = 0 dbfs = 11.3 w p o = 1 w p o = 0 dbfs = 5.0 w p o = 1 w p o = 0 dbfs = 22.6 w - - - - - - 0.05 0.10 0.12 0.28 0.1 0.3 - - - - - - % % % % % % dynamic range stereo full-bridge half-bridge parallel full-bridge dyr p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - - - - - 102 99 99 96 102 99 - - - - - - db db db db db db mosfet on resistance r ds(on) i d = 0.5 a, t j =50 c-280-m efficiency h p o = 2 x 15 w, r l = 8 -85-% minimum output pulse width pw min no load - 50 - ns rise time of outx t r resistive load - 20 - ns fall time of outx t f resistive load - 20 - ns pwm output over-current error trigger point i ce t a = 25 c, ocref = 16.2 k t a = 25 c, ocref = 18 k t a = 25 c, ocref = 22 k - - - 2.5 2.1 1.7 - - - a a a junction thermal warning trigger point t tw -105- c junction thermal error trigger point t te -125- c vp under-voltage error falling trigger point v uvfall t a = 25 c-4.74.9v vp under-voltage error rising trigger point v uvrise t a = 25 c - 4.95 5.4 v
ds726pp1 21 CS4525 serial audio input port switching specifications agnd = dgnd = pgnd = 0 v; t a = 25c; vd = 3.3 v; inputs: logic 0 = dgnd; logic 1 = vd. notes: 8. f clk is the frequency of the crystal connected to the xti/xto pins or the input sys_clk signal. 9. n bits is the number of bits per sample of the serial digital input. 10. after powering up the CS4525, rst should be held low until the power supplies and clocks are stable. parameters symbol mi n nominal max units supported input sample rates f si 28.5 39.5 39.5 86.4 32 44.1 48 96 35.2 52.8 52.8 105.6 khz khz khz khz lrck duty cycle 45 - 55 % sclk frequency (note 8) , (note 9) 1/t p f si *2*n bits -f clk /3 hz sclk duty cycle 45 - 55 % lrck setup time before sclk rising edge t s(lk-sk) 40 - - ns sdin setup time before sclk rising edge t s(sd-sk) 25 - - ns sdin hold time after sclk rising edge t h 10 - - ns rst pin low pulse width (note 10) 1- -ms // // // // // // t s(sd-sk) msb msb-1 lrck sclk sdin t r t f t s(lk-sk) t p t h figure 7. serial audio input port timing
22 ds726pp1 CS4525 aux serial audio i/o port switching specifications agnd = dgnd = pgnd = 0 v; t a = 25c; vd = 3.3 v; aux_ sdout & dly_sdout c l = 15 pf; inputs: logic 0 = dgnd; logic 1 = vd; (note 11) . notes: 11. f clk is the frequency of the crystal connected to the xti/xto pins or the input sys_clk signal. t clk =1/f clk . 12. f si is the frequency of the input lrck signal. t si =1/f si 13. may vary during normal operation. 14. f sclki is the frequency of the input sclk signal. t sclki =1/f sclki . parameters symbol min typ max units input source: analog inputs (internal adc) output sample rate clkfreq[1:0] = ?00? clkfreq[1:0] = ?01? clkfreq[1:0] = ?10? f so - - - f clk /384 f clk /512 f clk /512 - - - hz hz hz aux_lrck duty cycle - 50 - % aux_lrck period - 1/f so -s aux_sclk frequency cl kfreq[1:0] = ?00? clkfreq[1:0] = ?01? clkfreq[1:0] = ?10? f sclko - - - 48*f so 64*f so 64*f so - - - hz hz hz aux_sclk duty cycle - 50 - % aux_sclk period - 1/f sclko -s input source: serial audio input port output sample rate f s-in = 32khz, 44.1 khz, 48 khz f s-in =96khz f so - - f si f si /2 - - hz hz aux_lrck duty cycle (note 13) 45 - 55 % aux_lrck period ( note 12 , 13 )t si - t clk t si t si + t clk s aux_sclk frequency f s-in = 32khz, 44.1 khz, 48 khz (note 14) f s-in =96khz - - f sclki f sclki /2 - - hz hz aux_sclk duty cycle 30 - 70 % aux_sclk period f s-in = 32khz, 44.1 khz, 48 khz ( note 13 , 14 )f s-in =96khz t sclki - t clk 2*t sclki - t clk t sclki 2*t sclki t sclki + t clk 2*t sclki + t clk s s input source: analog inputs or serial audio input port aux_lrck rising edge to aux_sclk falling edge t ltsf - - 20 ns aux_sclk rising edge to data output valid t srdv --t clk + 20 ns dly_sdin setup time before aux_sclk rising edge t dis 25 - - ns dly_sdin hold time after aux_sclk rising edge t dih 10 - - ns aux_lrck aux_sclk aux_sdout dly_sdout dly_sdin msb msb msb - 1 msb - 1 lsb lsb t ltsf t srdv t disu t dih fi g ure 8. aux serial port interface master mode timin g
ds726pp1 23 CS4525 xti switching specifications notes: 15. see ?clock frequency (clkfreq[1:0])? on page 69 . sys_clk switching specifications agnd = dgnd = pgnd = 0 v; t a = 25c; vd = 3.3 v; input: logic 0 = dgnd; logic 1 = vd, sys_clk output: c l =20pf. pwm_sigx switching specifications agnd = dgnd = pgnd = 0 v; t a = 25c; vd = 3.3 v; load = 10 pf. parameter symbol min typ max unit external crystal operating frequency clkfreq[1:0] = ?00? (note 15) clkfreq[1:0] = ?01? clkfreq[1:0] = ?10? f clk 18.240 24.330 26.730 18.432 24.576 27.000 18.617 24.822 27.270 mhz mhz mhz xti duty cycle 45 50 55 % parameter symbol min typ max unit external clock operating fr equency clkfreq[1:0] = ?00? (note 15) clkfreq[1:0] = ?01? clkfreq[1:0] = ?10? f clk 18.240 24.330 26.730 18.432 24.576 27.000 18.617 24.822 27.270 mhz mhz mhz rising edge rst to start of sys_clk t sclko - 1024*t sclki - sys_clk period t sclki 37.04 - 54.25 ns sys_clk duty cycle 45 50 55 % sys_clk high time t clkih 16.67 - 29.84 ns sys_clk low time t clkil 16.67 - 29.84 ns parameter symbol min typ max unit rise time of pwm_sigx t r -2.1-ns fall time of pwm_sigx t f -1.4-ns sys_clk ___ rst (output) t sclko figure 9. sys_clk timing from reset pwm_sigx t r t f figure 10. pwm_sigx timing
24 ds726pp1 CS4525 i2c control port switching specifications agnd = dgnd = pgnd = 0 v; t a = 25c; vd = 3.3 v; inputs: logic 0 = dgnd; logic 1 = vd; sda c l =30pf. notes: 16. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 16) t hdd 10 - ns sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 11. control port timing - i2c
ds726pp1 25 CS4525 dc electrical characteristics agnd = dgnd = pgnd = 0 v; all voltages with respect to ground; pwm switch rate = 384 khz; unless otherwise specified. notes: 17. normal operation is defined as rst = hi. 18. power-down mode is defined as rst = low with all input lines held static. 19. the dc current drain represents the allowed current from the vq pin due to typical leakage through the electrolytic de-coupling capacitors. 20. valid with the recommended capacitor valu es on filt+ and vq. incr easing the capacitance will increase the psrr. digital interface specifications agnd = dgnd = pgnd = 0 v; all voltages with respect to ground; unless otherwise specified. notes: 21. digital interface signals in clude all pins sourced from the vd supply as shown in ?digital i/o pin characteristics? on page 12 . parameters min typ max units normal operation (note 17) power supply current vd = 3.3 v - 54 - ma power dissipation vd = 3.3 v - 180 - mw power-down mode (note 18) power supply current vd = 3.3 v - 2.8 - ma vd_reg characteristics nominal voltage 2.25 2.5 2.75 v dc current source - - 3 ma va_reg characteristics nominal voltage 2.25 2.5 2.75 v dc current source - - 1 ma vq characteristics nominal voltage - 0.5*va_reg - v output impedance - 23 - k dc current source/sink (note 19) --10 a filt+ nominal voltage - va_reg - v power supply rejection ratio (note 20) 1 khz 60 hz - - 60 40 - - db db parameters symbol min max units digital interface signal characteristics (note 21) high-level input voltage v ih 0.75*vd_reg - v low-level input voltage v il - 0.20*vd_reg v high-level output voltage i o =2 ma v oh 0.90*vd - v low-level output voltage i o =2 ma v ol -0.2v input leakage current i in -10ua input capacitance - 8 pf pwm_sigx characteristics high-level pwm_sigx output voltage i o =2 ma v ohps 0.90*vd_reg - v low-level pwm_sigx output voltage i o =2 ma v olps -0.2v
26 ds726pp1 CS4525 6. applications 6.1 software mode maximum device flexibility a nd features are available when the CS4525 is us ed in software mode. the avail- able features are described in the following sections. a ll device configuration is achieved via the i2c control port as described in the i2c control port de scription and timing section on page 64 . 6.1.1 system clocking in software mode, the cs 4525 can be clocked by a stable external clock source inpu t on the sys_clk pin or by a clock internally generate d through the use of its internal oscillator driver circuit in conjunction with an external crystal o scillator. the device automa tically selects which of these clocks to use within 10 ms of the release of rst . the internal clock is used to synch ronize the input serial audio signals with the internal clock domain and to clock the internal digital processing, sample-rate co nverter, and pwm modulators. it is also used to de- termine the sample rate of the serial audio input si gnals in order to automatically configure the various internal filter coefficients. to ensure proper operation, the CS4525 must be in formed of the nominal frequency of the supplied sys_clk signal or the attach ed crystal via the clkfreq[1 :0] bits in the clock co nfig register . these bits must be set to the appropriate value before the pdnall bit is cleared to initiate a power-up sequence. see the sys_clk switching specifications and xti switching specifications tables on page 23 for complete input frequency range specifications. warning: the system clock source must never be re moved or stopped while any of the power output stages are powered-up (the pdnall bit and any of the pdnout1, pdnout2, or pd nout3/4 bits are cleared) and connected to a load. doing so may result in permanent damage to the CS4525 and connected trans- ducers. 6.1.1.1 sys_clk input clock mode if an input clock is detected on the sys_clk pin following the release of rst , the device will automatically use the sys_clk input as its clo ck source. the applied sys_clk clock signal must oscillate within the frequency rang es specified in the sys_clk swit ching specifications table on page 23 . in this mode, xti should be connected to ground and xto should be left unconnected. figure 12 below demonstrates a ty pical clocking configurat ion using the sys_clk input. referenced control register location clkfreq[1:0]......................... ?clock frequency (clkfreq[1:0])? on page 69 pdnall ................................. ?power down (pdnall)? on page 89 pdnoutx ............................. ?power down pwm power output x (pdnoutx)? on page 88 sys_clk rst dsp reset_out clock_in clock xti xto figure 12. typical sys_clk in put clocking configuration CS4525
ds726pp1 27 CS4525 6.1.1.2 crystal oscillator mode to use an external crystal in conjunction with the in ternal crystal driver, a 20 pf fundamental mode par- allel resonant crystal must be connected between the xti and xto pi ns. this crystal must oscillate within the frequency ranges specified in the xti switching specifications table on page 23 . nothing other than the crystal and its load capacitors should be conn ected to xti and xto. the sys_clk pin should be connected to ground through a 22 k pull-down resistor to prevent the CS4525 from recognizing system noise on the sys_clk pin as a valid clocking signal. in this mode, the CS4525 will automa tically drive the generat ed internal clock ou t of the sys_clk pin. this can be disabled with the en sysclk bit which will cause the sys_ clk pin to becom e high-impedance. also, the divsysclk bit allows the frequency of the gener ated internal clock to be divided by 2 prior to be- ing driven out of the sys_clk. it should be noted that the internal oscillator dr iver is disabled when the CS4525 is in reset (rst is low). any external devices connected to the sys_clk output will not receiv e a clock signal until the CS4525 is taken out of reset. if an external crystal is connected to the xti/xto pins while an input clock signal is present on the sys_clk pin following the release of rst , then the CS4525 will automati cally use the sys_clk pin for its internal clock. refer to section 6.1.1.1 for a details about th is mode of operation. figure 13 below demonstrates a typical clocking co nfiguration using th e crystal oscillator. referenced control register location ensysclk............................. ?sys_clk output enable (ensysclk)? on page 69 divsysclk............................ ?sys_clk output divider (divsysclk)? on page 69 dsp rst rst reset sys_clk clock_in xti xto figure 13. typical crystal osc illator clocking configuration CS4525
28 ds726pp1 CS4525 6.1.2 power-up and power-down the CS4525 will remain in a completely powered-down state with the control port inaccessible until the rst pin is brought high. once rst is high, the control port will be acce ssible, but all other internal blocks will remain powered-down until they are powered-up via the control port or until hardware mode is en- tered. when an external crystal is pres ent on the xti/xto pins, software mode will be automatically entered 10 ms after the release of rst . if sys_clk is used as an input, so ftware mode is ente red by writing to the control port within 10 ms after the release of rst . if the control port is not written within this time, the device will begin to oper ate in hard ware mode. 6.1.2.1 recommended power-up sequence 1. hold rst low until the power supplies and th e input sys_clk (if used) are stable. 2. bring rst high. the device will remain in a low-pow er state and the control port w ill be accessible. the device will automatically enter software mode after 10 ms if an external crystal is present on the xti/xto pins, at which time the output sys_ clk signal will become active. 3. if sys_clk is used as an input, initiate a control port write to set the pdnall bit in register 5fh within 10 ms following the release of rst . this operation causes the device to enter softw are mode and places it in power-down mode. 4. if the lvd pin is tied low and vd, vd_reg, and va_reg are connected to 2.5 v, clear the selectvd bit in the power ctrl register to indi cate the 2.5 v vd supply level. see section 6.7 on page 63 for de- tails. 5. if vp is connected to a supply voltage less than or equal to 14 v nominal, clear the selectvp bit in the foldback cfg register to indicate the vp supply level. 6. the desired register settings can be loaded while keeping the pdnall bit set. typical initialization set- tings include input configuration, output conf iguration, master volume, and clock frequency. 7. clear the pdnall bit to initiate the power-up sequence. 6.1.2.2 recommended power-down sequence 1. set the mutecha, mutechb, and mutesub bits in th e mute control register to mute the audio output. 2. set the pdnall bit to power-down the device. 3. bring rst low to bring the device?s power consumption to an absolute minimum. 4. remove power. referenced control register location pdnall ................................. ?power down (pdnall)? on page 89 selectvd ............................. ?select vd level (selectvd)? on page 88 selectvp ............................. ?select vp level (selectvp)? on page 74 mutechx ............................. ?independent channel a & b mute (mutechx)? on page 84 mutesub.............................. ?sub channel mute (mutesub)? on page 85 input configuration.............. ?input configuration (address 02h)? on page 71 output configuration ........... ?output configuration (address 04h)? on page 73 master volume .................... ?master volume control (address 57h)? on page 82 clock frequency ................. ?clock frequency (clkfreq[1:0])? on page 69
ds726pp1 29 CS4525 6.1.3 input source selection the CS4525 can accept analog or digital audio in put signals. digital audio input signals are supplied through the serial audio input port as outlined in ?serial audio interfaces? on page 62 . analog audio input signals are supplied through the internal adc as outlined in ?analog inputs? on page 61 . the input source is selected by the adc/sp bit in the input config register. in software mode, the serial audio input port supports i2s, left-justified and ri ght-justified data formats. the serial audio input port digital interface format is co nfigured by the dif[2:0] bits in the input config reg- ister. the CS4525 internal adc includes a dedicated high-pass filter to remove any dc content from the adc output signal prior to the internal adc/serial audio in put port input multiplexor. this high-pass filter can be bypassed by clearing the enanhpf bit. 6.1.4 digital sound processing the CS4525 implements flexible digital sound proc essing operations including bass management cross- over, 2-way speaker crossovers, high- and low-pass sh elving filters, programmabl e parametric eq filters, adaptive loudness compensation, channel mixers, and volume controls. the digital signal flow is shown in figure 14 below. the signal processing blocks are described in detail in the following sections. referenced control register location adc/sp ............................... ?input source selection (adc/sp)? on page 71 dif[2:0] ............................... ?input serial port digital interface format (dif [2:0])? on page 71 enanhpf ............................ ?adc high-pass filter enable (enanhpf)? on page 71 amplifier out 1 amplifier out 2 amplifier out 3 amplifier out 4 pwm modulator output 2 audio processing high-pass bass/treble 2-ch mixer 2.1 bass mgr de-emphasis serial audio input port volume auxiliary serial port serial audio delay interface pwm output config gate drive power stage gate drive power stage gate drive power stage gate drive power stage stereo analog in serial audio clocks & data serial audio data i/o serial audio clocks & data pwm modulator output 1 x-over sensitivity ch. a hpf ch. a lpf ch. b hpf ch. b lpf ch. a hpf ch. a lpf serial audio data in left right ch. b hpf ch. b lpf ch. 1 ch. 2 pre-scaler high-pass filter mixer de-emphasis bass tone ctrl param. eq aux serial data select data to aux port sub parametric eq linkwitz-riley crossover adaptive loudness compensation high- pass adc treble tone ctrl bass manager loudness ch. a ch. b sub temperature sense master vol control limiter sample rate converter pwm modulator sub sample rate converter pwm modulator ch. 2 sample rate converter pwm modulator ch. 1 temperature sense ch. vol control ch. b ch. a ch. a ch. b thermal foldback thermal limiter figure 14. digital signal flow
30 ds726pp1 CS4525 6.1.4.1 pre-scaler applying any gain to a full-scale sig nal in the digital domain will cause t he signal to clip. to prevent this, a pre-scaler block is included prior to the internal di gital signal processing blocks. this allows the input signal to be attenuated before processing to ensure th at any signal boosting, such as gain in a shelving filter, will not cause a channel to clip. the pre-scaler block allows up to -14.0 db of attenu ation in 2.0 db increments and is controlled with the prescale[2:0] bits. 6.1.4.2 digital signal pr ocessing high- pass filter the CS4525 includes a high-pass filter at the beginnin g of the digital signal processing chain to remove any dc content from the input signal prior to the rema ining internal digital signal processing blocks. the high-pass filter operates by continu ously subtracting a measure of the dc offset from the input signal and may be used regardless of the input data source. the digital signal processing high-pass filter can be disabled by clearing the endighpf bit. 6.1.4.3 channel mixer the CS4525 implements independent channel mixers to provide for both mono mixes and channel swaps for the left and right channels. the channel mixers are controlled by the lchmix[1:0] and rchmix[1:0] bits in the mixer config register. to allow stereo operation when a mono mix is conf igured, when the hp_detect/mute pin is configured for headphone detection (the hp/mute bit is set), the operation of the left channel mixer is affected by the active state of the headpho ne detection input signal. in this configuration, when the left channel mixer is configured for a mono mix (lchmix[1:0] = 01 or 10) and the headphone detection input signal becomes active, the left channel mixer will be automatically reconfigured to out put the left chan nel, thereby dis- abling the mono mix. when the hea dphone detection input si gnal becomes inactive, the mixer will be au- tomatically reconfigured to operate as dictated by the lchmix[1:0] bits. it should be noted that the right channel mixer out put is unaffected by the headphone detection input sig- nal and will always operate as di ctated by the rchmix[1:0] bits. referenced control register location prescale[2:0]....................... ?pre-scale attenuation (prescale[2:0])? on page 75 referenced control register location endighpf ........................... ?digital signal processing high-pass filter (endighpf)? on page 77 referenced control register location lchmix[1:0] ......................... ?left channel mixer (lchmix[1:0])? on page 76 rchmix[1:0] ........................ ?right channel mixer (rchmix[1:0])? on page 76 hp/mute .............................. ?hp_detect/mute pin mode (hp/mute)? on page 70
ds726pp1 31 CS4525 6.1.4.4 de-emphasis the CS4525 includes an on-chip digital de-emphasis f ilter optimized for a sample rate of 44.1 khz to ac- commodate audio recordin gs that utilize 50/15 s pre-emphasis equalization as a means of noise reduc- tion. the filter response is shown in figure 15 . the de-emphasis filter is enabled and disabled by the deemph bit in the tone config register. 6.1.4.5 tone control the CS4525 implements configurable bass and treble shelving filters to easily accommodate system tone control requirements. each shelving filter has 4 se lectable corner frequencies, and provides a cut/boost range from -10.5 db to +12.0 db in 1.5 db increments. the tone control is enabled by the entonectrl bit in the tone config register. each tone control is implemented with one of two pres et internal filter sets. one set is optimized for a 32 khz sample rate, and the other is optimized fo r 44.1 khz, 48 khz, and 96 khz sample rates. the CS4525 automatically detects the input sample rate a nd chooses the appropriate filter set to apply. the available corner frequencies are shown in tables 2 and 3 below and are configured with the bassfc[1:0] and trebfc[1:0] bits in the tone config register. note that the corner frequency of each filter set scales linearly with the input sample rate. when the internal adc is used as the serial audio data source, the input sample rate is nominally 48 khz and the corresponding shelving frequency corners are available. referenced control register location deemph .............................. ?de-emphasis control (deemph)? on page 76 input sample rate bass fc 0 ba ss fc 1 bass fc 2 bass fc 3 32 khz 50 hz 100 hz 200 hz 250 hz 44.1khz 48hz 96hz 192hz 240hz 48 khz, 96 khz 52 hz 104 hz 208 hz 260 hz table 2. bass shelving filter corner frequencies t2 = 15 s t1=50 s 0.07218 fs f1 f2 0 db -10 db 0.24059 fs 32 khz, 44.1 khz, 48 khz 96 khz 0.03609 fs 0.12030 fs normalized to fs frequency (hz) gain (db) nominal sample rate figure 15. de-emphasis filter
32 ds726pp1 CS4525 the cut/boost level of the bass and treble shelving f ilters are set by the bass[3:0] and treble[3:0] bits in the tone control register. input sample rate treble fc 0 treble fc 1 treble fc 2 treble fc 3 32 khz 5.0 khz 7.0 khz 10.0 khz 15.0 khz 44.1 khz 4.8 khz 6.7 khz 9.6 khz 14.4 khz 48 khz, 96 khz 5.2 khz 7.3 khz 10.4 khz 15.6 khz table 3. treble shelving filter corner frequencies referenced control register location entonectrl .......................... ?tone control enable (entonectrl)? on page 77 trebfc[1:0] .......................... ?treble corner frequency (trebfc[1:0])? on page 77 bassfc[1:0] ......................... ?bass corner frequency (bassfc[1:0])? on page 77 treble[3:0] ........................... ?treble gain level (treb[3:0])? on page 78 bass[3:0] ............................. ?bass gain level (bass[3:0])? on page 78
ds726pp1 33 CS4525 6.1.4.6 parametric eq the CS4525 implements 5 fully prog rammable parametric eq filters. the filters are implemented in the bi-quad form shown below. this architecture is represented by the equation sh own below where y[n] repr esents the output sample value and x[n] represents the input sample value. equation 1. bi-quad filter equation the coefficients are represented in binary form by 24-b it signed values stored in 3.21 two?s complement format. the 3 msb?s represent the sign bit and the whol e-number portion of the decimal coefficient, and the 21 lsb?s represent the fractional portion of the de cimal coefficient. the coefficient values must be in the range of -4.00000 decimal (80 00 00 hex) to 3.99996 decimal (7f ff ff hex). the binary coefficient values are stored in registers 0ah - 54h. each 24-bit coeffici ent is split into 3 bytes, each of which is mapped to an individua lly accessible register location. see the ?register quick refer- ence? section beginning on page 66 for the specific register lo cations for each coefficient. by default, all b 0 coefficients are set to 1 decimal, and all ot her coefficients are set to 0 decimal. this im- plements a pass-through function. the parametric equalizers be independently enabled and disabled for channels a and b with the en- chapeq and enchbpeq bits locat ed in the eq config register. referenced control register location enchapeq .......................... ?enable channel a parametric eq (enchapeq)? on page 79 enchbpeq .......................... ?enable channel b parametric eq (enchbpeq)? on page 79 b 0 b 1 b 2 a 1 a 2 z -1 z -1 z -1 z -1 x[n] y[n] figure 16. bi-quad filter architecture y[n] = b 0 x[n] + b 1 x[n-1] + b 2 x[n-2] + a 1 y[n-1] + a 2 y[n-2]
34 ds726pp1 CS4525 6.1.4.7 adaptive loudness compensation the CS4525 includes adaptive lo udness compensation to enhance the audibility of program material at low volume levels. the ad aptive loudness compensation feature oper ates by varying the bass and treble boost of the tone control shelving filters as the volume level changes. the level of boost added to the shelving filters is de termined by the average of the effective volume set- tings of channels a and b after the master volume cont rol. as this average volume setting decreases from 0 db, the boost of the bass and treble shelving filt ers is gradually increased until it reaches the maximum boost level of 12.0 db. as the volu me is increased, the boost applie d due to the adaptive loudness com- pensation feature will be gradually re moved until it reaches the level specified by the treble[3:0] and bass[3:0] bits in the tone control register. the adaptive loudness compensation feature is enab led by setting the loudness bit in the tone config register. when the loudness feature is enabled, it i mmediately evaluates the effe ctive average volume and applies bass and treble boost accordingly. when disabled, any treble or bass boost applied due to the loudness feature will be removed. because the adaptive loudness compensation filter op erates by adjusting the boost level of the tone con- trol shelving filters, it is necessary that they be enabled with the entonectrl bit in the tone config register in order for the loudness feature to be operational. if th e tone control filters are disabled, the adaptive loud- ness compensation featur e will not be functional. referenced control register location loudness............................. ?adaptive loudness compensation control (loudness)? on page 76 entonectrl .......................... ?tone control enable (entonectrl)? on page 77 trebfc[1:0] .......................... ?treble corner frequency (trebfc[1:0])? on page 77 bassfc[1:0] ......................... ?bass corner frequency (bassfc[1:0])? on page 77 treble[3:0] ........................... ?treble gain level (treb[3:0])? on page 78 bass[3:0] ............................. ?bass gain level (bass[3:0])? on page 78
ds726pp1 35 CS4525 6.1.4.8 bass management the CS4525 implements a dedicated stereo 24 db/octav e linkwitz-riley crossover with adjustable cross- over frequency to achieve bass management for 2.1 c onfigurations. the filter?s stereo high-pass outputs are used to drive the full-range speakers, and its st ereo low-pass outputs are each attenuated by 6 db and summed to drive the sub channel. the bass management crossover is implemented with one of two preset internal filter sets. one set is op- timized for a 32 khz sample rate, and the other is optimized for 44.1 khz, 48 khz, and 96 khz sample rates. the CS4525 automatically detects the input samp le rate and chooses the appropriate filter set to apply. the available bass management cross-over frequencies are shown in table 4 below and are con- figured with the bassmgr[2:0] bi ts in the eq config register. note that the corner frequency of each filter set scales linearly with the input sample rate. when the internal adc is used as the serial audio data source, the input sample rate is nominally 48 khz and the corresponding shelving frequency corners are available. the bassmgr[2:0] bits also allow the bass manager to be disabled. when disabled, the bass management crossover is bypassed and no signal is presented on the sub channel. to allow full-range headphone operation, when t he hp_detect/mute pin is configured for headphone detection (the hp/mute bit is set), the operation of the bass manager is affected by the active state of the headphone detection input signal. in this configuration, when the bass manager is enabled, (bassmgr[2:0] bits not equal to ?000?) and the headphone detection input signal becomes acti ve, the bass manager will be automatically disabled. when the headphone detect ion input signal becomes inactive, the bass man- ager will be automatically reco nfigured to operate as dictated by the bassmgr[2:0] bits. input sample rate 32 khz 44.1 khz 48 khz, 96 khz bass manager freq 1 80 hz 77 hz 83 hz bass manager freq 2 120 hz 115 hz 125 hz bass manager freq 3 160 hz 153 hz 167 hz bass manager freq 4 200 hz 192 hz 209 hz bass manager freq 5 240 hz 230 hz 250 hz bass manager freq 6 280 hz 268 hz 292 hz bass manager freq 7 320 hz 307 hz 334 hz table 4. bass management cross-over frequencies referenced control register location bassmgr[2:0] ....................... ?bass cross-over frequency (bassmgr[2:0])? on page 79 hp/mute .............................. ?hp_detect/mute pin mode (hp/mute)? on page 70
36 ds726pp1 CS4525 6.1.4.9 volume and muting control the CS4525?s volume control archit ecture provides the ability to cont rol the level of each output channel on both an individual and master basis. individual control allows the volume and mute state of a single channel to be changed independently from the other channels within the device. the CS4525 provi des three individual volu me and muting controls, each permanently assigned to one channel within the device. the three individual volume controls, chavol, chbvol, and subvol, can gain or attenuate channel a, channel b, or the sub channel (respec- tively) from +24 db to -103 db in 0.5 db steps. the three individual mute controls, mutecha, mutechb, and mutesub bits, can mute channel a, chan nel b, or the sub channel (respectively). master control allows the volume of all channels to be changed simult aneously by offsetting each chan- nel?s individual volume setting by an additional +24 db to -103 db in 0.5 db steps. by default, master vol- ume is set to +3db; if the CS4525 is being used to control the application?s ma ster volume, then it is recommended to change this value to a comfortable listening level before enabling the pwm powered out- puts. master volume control is acco mplished via the master vol register. the pwm outputs can be configured to output silenc e as a modulated signal or an non-modulated 50% duty cycle signal during a mute condition. this se lection is achieved via the mute50/50 bit in the volume cfg register. the automute bit in the sa me register dictates whether the device will automatically mute after the recep- tion of 8192 consecutive samples of static 0 or -1. when the automute function is enabled, a single sample of non-static data will cause the automatic mute to be released. the CS4525 implements soft -ramp and zero-crossing detection capab ilities to provide noise-free level transitions. when the zero-crossing function is enab led, all volume and muting changes are made on an output signal zero-crossing. the zero-crossing dete ction function is implemented independently for each channel. when the soft-ramp function is enabled, the vo lume is ramped from its in itial to its final level at a rate of ? db every 4 samples for 32, 44.1, and 48 khz sample rates, and ? db every 8 samples for a 96 khz sampling rate. all volume and muting changes are implemented as dictated by the soft-ramp and zero-cross settings configured by the szcmode[1:0] bi ts in the volume cfg register. referenced control register location chxvol ................................ ?channel a and b volume control (address 58h & 59h)? on page 83 subvol................................. ?sub channel volume control (address 5ah)? on page 83 mutechx ............................. ?independent channel a & b mute (mutechx)? on page 84 mutesub.............................. ?sub channel mute (mutesub)? on page 85 master vol ........................... ?master volume control (address 57h)? on page 82 mute50/50 ........................... ?enable 50% duty cycle for mute condition (mute50/50)? on page 80 automute............................. ?auto-mute (automute)? on page 80 szcmode ............................ ?soft ramp and zero cross control (szcmode[1:0])? on page 80
ds726pp1 37 CS4525 6.1.4.10 peak signal limiter when enabled, the limiter monitors the digital outp ut following the volume co ntrol block, detects when peak levels exceed a selectable maximum threshold level and lowers the volume at a programmable at- tack rate until the signal peaks fall below the maximum threshold. when the signal level falls below a se- lectable minimum threshold, the volume returns to its original level (as determin ed by the individual and master volume control registers) at a programmable release rate. attack and release rates are affected by the soft ramp/zero cross se ttings and sample rate, fs. recommended settings : best limiting performance may be realiz ed with the fastest attack and slowest release setting with soft ramp enabled in the control registers. use the ?minimum? bits to set a threshold slightly below the maximum thres hold to cushion the sound as the limiter attacks and releases. by default, the limiter affects all channels when t he maximum threshold is exceeded on any single chan- nel. this default functionality is designed to keep all output channels at the same volume level while the limiter is in use. this behavior can be disabled by clearing the limitall bit in the limiter cfg 1 register. max[2:0] output (after limiter) input rrate[5:0] arate[5:0] volume limiter min[2:0] attack/release sound cushion attack/release s ound cushion figure 17. peak signa l detection & limiting
38 ds726pp1 CS4525 when the limitall feature is activa ted, attenuation will be applied to all channels when a single channel exceeds the maximum threshold and released when the level of all channels is below the minimum threshold. when the limitall feature is de-activated, li miter attenuation will be applied and released on a per-channel basis and will only a ffect the channel on which the limiter event occurred. the limiter can be enabled by setting the enlimiter bit in the limiter cfg 1 register the limiter can also be used in conjunction with the thermal limiter function to provide thermal error pro- tection to the CS4525. the thermal limit er function is described in thermal limiter on page 39 . referenced control register location enlimiter ............................. ?peak detect and limiter enable (enlimiter)? on page 86 limitall................................. ?peak signal limit all c hannels (limitall)? on page 86 max[2:0] .............................. ?maximum threshold (max[2:0])? on page 85 min[2:0] ............................... ?minimum threshold (min[2:0])? on page 85 arate[5:0] ........................... ?limiter attack rate (arate[5:0])? on page 87 rrate[5:0] ........................... ?limiter release rate (rrate[5:0])? on page 87
ds726pp1 39 CS4525 6.1.4.11 thermal limiter the CS4525 implements a thermal limiter function to provide a quick corrective response to potentially damaging thermal overload conditions. the thermal lim iter feature operates by sensing the presence of a thermal warning condition and, in response, utilizes the peak signal limiter to dy namically limit the signal amplitude prior to the pwm modulator s. this effectively limits the outp ut power capability of the device, thereby allowing the temperature to reduce to acce ptable levels without fu lly interrupting operation. the thermal limiter is enabled by the enthlim bit in the limiter configuration 3 register. when enabled, the thermal limiter will trigge r once when either of the following conditions is met: 1. the junction temperature crosses the thermal warning threshold for the first time after the thermal limiter function is enabled. 2. the junction temperature is greater than the thermal warning threshold at the time the thermal limiter function is enabled. once triggered, the thermal limit er will remain in a triggered stat e until the rst pin is driven low. when in the triggered st ate, the thermal limiter will engage whenever the en thlim bit is set. while en- gaged, the thermal lim iter utilizes the peak signal limiter function to dynamically limit the signal amplitude prior to the pwm modulators via the peak signal limiter ; the characteristics of th is limiting function are de- scribed in section 6.1.4.10 on page 37 . if the thermal limiter is engaged and the peak signal limiter is dis- abled via the enlimiter bit, the peak signal limiter will be automatically e nabled and its minimum and maximum thresholds will be set to -3 db. if the thermal limiter is engage d and the peak si gnal limiter is enabled, an additional -3db will be automatically a pplied to the minimum and maximum thresholds estab- lished in the limiter cfg 1 register. the automatic en abling of the peak signal limiter and the automatic application of additional attenuation to its thresholds is done internal to the cs4245; the values of the en- limiter, min[2:0], and max[2:0] bits in the limiter cfg 1 register are not affected by the engagement of the thermal limiter function. it should be noted that the ther mal limiter can only be triggered once following the release of the rst sig- nal. once it has tr iggered, the thermal limiter?s attenuation will always be implemented while the thermal limiter is enabled. if the thermal lim iter is disabled after it has triggered, the internal enabling of the peak signal limiter and the addi tional -3 db attenuation applied to its minimum an d maximum thresholds will be released. in this state, the peak si gnal limiter?s operation will follow th e enlimiter, min[ 2:0], and max[2:0] bits with no internal modification. if enthlim is set again before the CS4525 has been reset (by toggling the rst pin low and then high), therma l limiting will engage immediately. referenced control register location enthlim.............................. ?enable thermal limiter (enthlim)? on page 87 enlimiter ............................. ?peak detect and limiter enable (enlimiter)? on page 86 max[2:0] .............................. ?maximum threshold (max[2:0])? on page 85 min[2:0] ............................... ?minimum threshold (min[2:0])? on page 85
40 ds726pp1 CS4525 6.1.4.12 thermal foldback the CS4525 implements comprehensive thermal foldba ck features to guard against damaging thermal overload conditions. thermal foldback is si milar to the thermal limiting described on page 39 in that both features attenuate the output signal in response to thermal warnings conditi ons; however, thermal fold- back will attenuate as a function of how long the rmal warning has been acti ve whereas thermal limiter always limits by a constant amount. also, the ther mal foldback feature will dea ctivate once the thermal warning condition ceases while t he thermal limiter will remain active once triggered until the rst pin is driven low. the thermal foldback algorithm begins limiting the volume of the digital audio input to the amplifier stage as the junction temperatures rise above the maximum safe operating range specified by the thermal warn- ing trigger point listed in the pwm power output characteristics table on page 20 . this effectively limits the output power capability of the de vice, thereby allowing t he temperature to reduce to acceptable levels without fully interrupting operation. as the device cool s, the applied attenuation is gradually released until a new thermal equilibrium is reach ed or all applied attenu ation has been released thereby allowing the device to again achieve its full output power capability. attenuation applied due to thermal foldback re duces the audio output level in a linear manner. figure 18 below demonstrates the foldback process. thermal warning threshold t delay 1 2 2 2 2 3 1 foldback attack delay attackdly[1:0] t delay t delay t delay t delay 3 the junction temperature is checked onc e again after the next foldback attack timer ti meout. if it has remained below the thermal warning threshold since t he last check, the device will begin to releas e any attenuation applied as a result of the foldback event. setting the lockadj bit will prevent the device from removing t he applied attenuation when the thermal overload condition has cleared. if the junction temperature crosses the thermal war ning threshold again, the foldback algorithm will once again enter step 1. 1 when the junction temperature crosses the thermal warni ng threshold, the foldback attack delay timer is started. 2 when the foldback attack delay timer reaches t delay seconds, the junction temperatur e is checked. if the junction temperature is above the thermal warning threshold, the output volume level is lower ed by 0.5 db and the foldback attack timer is restarted. the junction temperature is checked af ter each foldback attack timer timeout, and if necessary, the output volume level is lowered accordingly. if the junction temperature is found to be below the therm al warning threshold, the foldba ck attack timer is restarted once again, but the output volume level is not altere d. the foldback algorithm then proceeds to step 3. figure 18. foldback process
ds726pp1 41 CS4525 the attackdly[1:0] bits in the foldback cfg register allow the foldback attack delay timeout period to be adjusted from approximately 0.5 seconds to appr oximately 2.0 seconds. th e maximum attenuation ap- plied by the thermal foldback algorithm can be restrict ed to -30 db by setting the enfloor bit in the same register. the foldback adjustment lock feature causes the atte nuation applied by the foldback algorithm to be main- tained after the foldback condition has subsided. th e applied attenuation will co ntinue to be applied until the master volume or all active channel volume cont rols are lowered below the foldback attenuation level, or until a subsequent foldback condition occurs caus ing the applied attenuation to be lowered further. if the foldback algorithm applies attenuation while this feature is enabled, when the feature is subsequently disabled, the applied attenuation will be gradually released as long as the temperature re mains within the safe operating range. this foldback lock adjustment feature is enabled by the lockadj bit in the foldback cfg register. thermal warnings will only affect the foldback algorithm and cause attenuation to be applied when en- abled by the entherm bit in the foldback cfg register. the CS4525 can be configured to accept an external thermal warning indicator input. when in this con- figuration, an active input signal in dicates that a thermal warning threshold has been exceeded. if thermal foldback is enabled, th e foldback algorithm will re spond as described above making no distinction be- tween an internal or external thermal warning condition. see ?external warning input port? on page 44 for more information. 6.1.4.13 2-way crossover & sensitivity control the CS4525 implements a d edicated stereo 24 db/octave linkwitz- riley crossover filt er with adjustable cross-over frequency and sensitivity contro l to facilitate 2-way speaker c onfigurations. the filter?s high- pass output can be used to drive the tweeter, and its low-pass output is used can be drive the mid- range/woofer. the sensitivity control is included to adjust the level of the high-pass and low-pass outputs to compensate for differences in the tw eeter and mid-range/woofer sensitivity. the two-way crossover is implemented with one of two pr eset internal filter sets . one set is optimized for a 32 khz sample rate, and the other is optimized for 44.1 khz, 48 khz, and 96 khz sample rates. the CS4525 automatically detects the input sample rate a nd chooses the appropriate filter set to apply. the available cross-over frequencies are shown in table 5 below and are configured with the 2wayfreq[2:0] bits in the volume cfg register. note that the corner frequency of each filter set scales linearly with the input sample rate. when the internal adc is used as the serial audio data source, the input sample rate is nominally 48 khz and the corresponding shelving frequency corners are available. referenced control register location entherm ............................. ?enable thermal foldback (entherm)? on page 74 attackdly[1:0] ...................... ?foldback attack delay (attackdly[1:0])? on page 75 enfloor................................ ?enable foldback floor (enfloor)? on page 75 lockadj ............................... ?lock foldback adjust (lockadj)? on page 74 input sample rate 32 khz 44.1 khz 48 khz, 96 khz x-over freq 0 2.0 khz 1.92 khz 2.09 khz x-over freq 1 2.2 khz 2.11 khz 2.30 khz x-over freq 2 2.4 khz 2.30 khz 2.50 khz x-over freq 3 2.6 khz 2.49 khz 2.71 khz x-over freq 4 2.8 khz 2.68 khz 2.92 khz table 5. 2-way cross-over frequencies
42 ds726pp1 CS4525 the sensitivity level of the high- and low-pass output s of the crossovers can be independently adjusted from 0 db to -7.5 db in 0.5 db incr ements. the maximum atte nuation level of -7.5 db will compensate for an approximate 4 db difference in sound pressure level (spl) between the tweeter and the mid- range/woofer drivers. the sensitivity is adjusted us ing the highpass[3:0] and lowpass[3:0] bits in the sensitivity register. note that these bits affect the sensitivity of both channel a and channel b high- and low-pass outputs. the 2-way crossover can be enabled by setting the en2way bit in the volume cfg register. x-over freq 5 3.0 khz 2.88 khz 3.13 khz x-over freq 6 3.2 khz 3.07 khz 3.34 khz x-over freq 7 3.4 khz 3.26 khz 3.55 khz referenced control register location en2way............................... ?enable 2-way crossover (en2way)? on page 81 2wayfreq[2:0]..................... ?2-way cross-over frequency (2wayfreq[2:0])? on page 81 highpass[3:0]...................... ?channel a and channel b high-pass sensitiv ity adjust (highpass[3:0])? on page 82 lowpass[3:0]....................... ?channel a and channel b low-pass sensitivity adjust (lowpass[3:0])? on page 81 input sample rate 32 khz 44.1 khz 48 khz, 96 khz table 5. 2-way cross-over frequencies
ds726pp1 43 CS4525 6.1.5 auxiliary serial output the CS4525 includes a stereo auxiliary serial output which allows an ex ternal device to leverage on its internal signal processing and routin g capabilities. the auxiliary serial ou tput can receive it s data from any of the sources shown in the digital signal flow diagram on page 29 . the supported output data routing configurations are shown in table 6 below. by default, the serial port is configured to output channels a and b on the auxiliary output data le ft and right channe ls respectively. the data output on each channel of aux_sdout is set by the lchdsel[1:0] and rchdsel[1:0] bits in the aux port configuration regist er. the frequencies of aux_lrck and aux_sclk will vary based upon the whether the serial input or analog input is bein g used and the frequency of the system clock for the CS4525; the nominal values for these clocks are listed in table 7 . the characteristics of aux_sclk, aux_lrck, and aux_sdout are described in the aux serial audio i/o port switching specifications table on page 22 . the auxiliary port can be enabled using the enauxport bit. when en abled, the port operates as a master and clocks out data in the form at dictated by the auxi2s/lj bit. when disabled, the aux_lrck, aux_sclk, and aux_sdout pins cont inuously drive a logic ?0?. it s hould be noted that when the CS4525 is configured for analog input, the aux_lrck, aux_sclk, and aux_sdout pins will contin- uously drive a logic ?0? if either the pdnadc bit or pdnall bit is set. lchdsel[1:0] aux left channel data rchdsel[1:0] aux right channel data 00 channel a 00 channel a 01 channel b 01 channel b 10 sub channel 10 sub channel 11 channel b x-over lpf 11 channel b x-over hpf table 6. auxiliary serial port data output signal adc/sp = 0 (digital input mode) adc/sp = 1 (analog input mode) applied system clock from either sys_clk or external crystal 18.432, 24.576, or 27.000mhz 18.432mhz 24.576mhz 27.000mhz frequency of lrck input 32khz, 44.1khz, or 48khz 96khz not applicable nominal frequency of aux_sclk output frequency of sclk input frequency of sclk input / 2 2.304mhz 3.072mhz 3.375mhz nominal frequency of aux_lrck output frequency of lrck input frequency of lrck input / 2 48khz 48khz 52.734khz table 7. nominal switching frequencies of the auxiliary serial output referenced control register location enauxport ........................... ?enable aux serial port (enauxport)? on page 72 lchdsel[1:0]....................... ?aux serial port left channel data select (lchdsel[1:0])? on page 73 rchdsel[1:0] ...................... ?aux serial port right channel data select (rchdsel[1:0])? on page 72 auxi2s/lj............................. ?aux/delay serial port digital in terface format (auxi2s/lj)? on page 72 pdnadc.............................. ?power down adc (pdnadc)? on page 88 pdnall ................................. ?power down (pdnall)? on page 89
44 ds726pp1 CS4525 6.1.6 serial audio dela y & warning input port the CS4525 includes a configurable delay and warning port to allow easy system integration of external lip-sync delay devices or wa rning inputs from external amplifiers. the port can be configured as a serial audio delay interface, an external warning input port , or disabled by the dlyport cfg[1:0] bits in the aux config register. when disabled, the dly_sdout and dly_sdin/ex_twr pins become high-imped- ance. 6.1.6.1 serial audio delay interface video processing and reproduction circuitry in digita l video display devices can often introduce noticeably more delay than is introduced by the device?s audio processing and reproduction circuitry. this can result in a phenomenon known as lip-synch delay - a delay present between the video and audio content being reproduced. to help overcome this problem, the CS4525 delay and warning port can be configured as serial audio delay interface. this interface consis ts of a serial audio input/output por t to facilitate the use of an external serial audio delay device. the port routes the serial data from the selected input source (the adc or the serial input port) out to an external serial audio del ay device, and then back in to the CS4525 internal dig- ital sound processing blocks. the delay serial audio interface signals include dly_sdout and dly_sdin/ex_twr and are clocked from aux_lrck and aux_sclk. the serial data is output on the dly_sdout pin and input on the dly_sdin/ex_twr in the format specif ied by the auxi2s/lj bits in the aux config register. be cause the delay interface uses the auxilia ry port clock signals, the auxiliary se- rial port must be enabled using the enauxport bit in the aux port configuration register to allow the delay interface to operate properly. 6.1.6.2 external warning input port when implementing external pwm power stage devices with thermal warning indicator outputs, it can be useful to provide these warning signals as an input to the internal thermal foldba ck algorithm. this allows the CS4525 to automatically respond to the external devices? thermal warning conditions without com- pletely disrupting the system?s operation. when configured as an external warning input port, the dly_sdin/ex_twr is an active-low thermal warning input to the foldback algorithm and the dly_sdout pin becomes high-impedance. in order for the foldback algorithm to act on the external thermal warning input signal, the thermal foldback algorithm must be enabled by the enthe rm bit in the foldback cfg register. see ?thermal foldback? on page 40 for more information. referenced control register location dlyportcfg........................... ?delay & warning port configuration (dlyportcfg[1:0])? on page 72 referenced control register location auxi2s/lj ............................. ?aux/delay serial port digital interface format (auxi2s/lj)? on page 72 enauxport ........................... ?enable aux serial port (enauxport)? on page 72 referenced control register location entherm ............................. ?enable thermal foldback (entherm)? on page 74
ds726pp1 45 CS4525 6.1.7 powered pwm outputs the CS4525?s 3 internal modulators can be used to generate multiple powered pwm output configura- tions to enable a wide variety of system implementations. the CS4525 also implements pwm popguard to minimize output transients in half-bridge configurations. 6.1.7.1 output channel configurations three pwm power output configurations are supported as shown in table 8 below. the configurations support stereo full-bridge, stereo half-bridge with full-bridge sub, and mono parallel full-bridge output. the configurations are selected by the outputcfg[1:0] bits in the outp ut cfg register and must only be changed when the device is in power-down mode (the pdnall bit is set). any attempt to write the out- putcfg[1:0] bits while the device is powered-up will be ignored. it should be noted that signals on channels 1, 2 and the sub channel are dependent upon the digital sound processing blocks being used. for instance, if the 2-way crossover is enabled, channel 1 and 2 contain the 2-way crossover channel a high- and low-pass outpu ts respectively. for more information, see the digital sound processing section and figure 14 on page 29 . 6.1.7.2 pwm popguard transient control the CS4525 uses popguard technology to minimize t he effects of power-up and power-down output tran- sients commonly produced by half-bridge, single supp ly amplifiers implemente d with external dc-block- ing capacitors connected in series with the audio outputs. pwm popguard operates by linearly ramping the pwm power outputs up to and down from their bias point of vp/2 when a channel is powered up and down re spectively using the pdnoutx or pdnall bits. this outputcfg[1:0] power configuration output signal output pin(s) 00 2 ch. full-bridge channel 1 + channel 1 - channel 2 + channel 2 - out1 out2 out3 out4 01 2 ch. half-bridge + 1 ch. full-bridge channel 1 + channel 2 + sub channel + sub channel - out1 out2 out3 out4 10 1 ch. parallel full-bridge channel 1 + channel 1 - out1, out2 out3, out4 table 8. pwm power output configurations referenced control register location outputcfg[1:0]..................... ?output configuration (outputcfg[1:0])? on page 73 pdnall ................................. ?power down (pdnall)? on page 89
46 ds726pp1 CS4525 gradual voltage ramp minimizes output transients while the dc blocking capacitor is charged and dis- charged. the popguard ha s no effect on the pwm_sig output s nor the auxiliary serial output. pwm popguard is disabled by defau lt; to enable it, the rmpspd[1:0] register must be set to any value other than 11. pwm popguard should only be used for has when the power outputs are configured for stereo half-bridge with full-bridge sub per section 6.1.7.1 . the ramp_cap pin must be connected to the vp supply through a 0.033 f capacitor whenever pwm popguard is enabled, as shown in figure 19 . table 9. typical ramp times for various vp voltages pwm popguard?s output ramp time w ill vary depending on th e voltage applied to vp and the value of the rmpspd[1:0] bits; typical ramp times are listed in table 9 . all output channels are affected by the rm- pspeed[1:0] bits, and pwm popguard is disabled by default. 6.1.8 logic-level pwm outputs the CS4525 has two configurable logic-level pwm outputs, pwm_sig1 and pwm_sig2. these outputs can be used as either digital input to an external pwm amplifier such as the cs4412, or as an analog input to a headphone amplifier or a line-out amplifier. to eliminate power-up pops when used to supply an ex ternal pwm amplifier, the CS4525 implements the same click-free start-up function on the pwm_sig ou tputs as it does for its own powered pwm outputs. this function can only be utilized if the pwm amplifier has an initia l transition delay feature, such as the cs4412a. to eliminate power-up and power-down pops when used to supply an analog output circuit, the pwm_sig outputs support a high-impedance state that is controlled by the hizpsig bit in the vp voltage typical ramp up times rmpspd[1:0] = 00 rmpspd[1:0] = 01 rmpspd[1:0] = 10 rmpspd[1:0] = 11 12 v 2.16 seconds 2.20 seconds 2.20 seconds instant (no ramp) 15 v 1.74 seconds 1.76 seconds 1.78 seconds instant (no ramp) 18 v 1.40 seconds 1.42 seconds 1.44 seconds instant (no ramp) referenced control register location rmpspeed[1:0] ................... ?ramp speed (rmpspd[1:0])? on page 75 pdnall ................................. ?power down (pdnall)? on page 89 pdnoutx ............................. ?power down pwm power output x (pdnoutx)? on page 88 left speaker right speaker subwoofer 0.033 uf +8v to +18v full- bridge filter CS4525 out1 out2 out3 out4 vp r a m p _ c a p half- bridge filter half- bridge filter figure 19. popguard connection diagram
ds726pp1 47 CS4525 eq config register. this bit is active-low and clea red by default. to use the pwm_sig outputs, the hiz- psig bit must be set to enable the pwm_sig output drivers. 6.1.8.1 recommended pwm_sig power-up sequence for an external pwm amplifier 1. engage the reset/power-down feature of the external pwm amplifier. 2. set the pdnall bit in the power ctrl register to stop the pwm modulators if it is not already set. 3. configure the pwm_sig outputs as desired via th e pwmdsel[1:0] bits in the output cfg register. 4. set the hizpsig bit in the eq config register to activate the pwm_sig output drivers. 5. disengage the reset/power-down feature of the extern al pwm amplifier if it has an initial transition delay feature, such as the cs4412a. warning: releasing the external amplifier from reset/power-down before pwm modulators have started will cause a dc output on the speakers unless the exte rnal amplifier has an in itial transition delay fea- ture. 6. clear the pdnall bit in the power ctrl register to start the pwm modulators. 7. disengage the reset/power-down feature of the exte rnal pwm amplifier if it has not been yet disen- gaged. 6.1.8.2 recommended pwm_sig power-down sequence for an external pwm amplifier 1. mute the pwm_sig outputs to a 50% duty-cycle by either setting master volume to 1111 1111h (master mute) or through use of the hp_detect/mute input pin as described in the headphone detection & hardwa re mute input section on page 51 . 2. engage the reset/power-down feature of the external pwm amplifier. 3. set the pdnall bit in the power ctrl register to disable the pwm modulators and set the pwm_sig outputs to a drive a logic ?0?. 4. power down the remainder of the system (if applicable).
48 ds726pp1 CS4525 6.1.8.3 recommended pwm_sig power- up sequence for headphone & line- out 1. set the pdnall bit in the power ctrl register to stop the pwm modulators if it is not already set. 2. configure the pwm_sig outputs as desired via th e pwmdsel[1:0] bits in the output cfg register. 3. clear the pdnall bit in the power ctrl register to start the pwm modulators. 4. wait 500 ms to allow the internal sample rate converters to achieve lock. 5. set the hizpsig bit in the eq config register to activate the pwm_sig outputs. 6.1.8.4 recommended pwm_sig power- down sequence fo r headphone & line-out 1. mute the pwm_sig outputs to a 50% duty-cycle by either setting master volume to 1111 1111h (master mute) or through use of the hp_d etect/mute input pin as described in the headphone detection & hardware mute input section on page 51 . 2. clear the hizpsig bit in the eq config register to put th e pwm_sig output drivers in a high-imped- ance state. 3. power down the remainder of the system (if applicable). referenced control register location pdnall ................................. ?power down (pdnall)? on page 89 hizpsig ............................... ?hi-z pwm_sig outputs (hizpsig)? on page 79 pwmdsel[1:0]..................... ?pwm signals output data select (pwmdsel[1:0])? on page 73 master volume .................... ?master volume control (mvol[7:0])? on page 82
ds726pp1 49 CS4525 6.1.8.5 pwm_sig logic-level output configurations four channel mapping output conf igurations are supported for the pwm_sig output pins as shown in table 10 below. the configurations support stereo, cha nnel 1 with sub, and channel 2 with sub applica- tions. when disabled, the pwm_sig pins will continuously drive a logic ?0? if the hizpsig bit is set and will be held in a high-impedance state if the hizpsig bit is clear. the configurations are selected by the pw- mdsel[1:0] bits in the output cfg register. the pw m_sig2 can be configured to output the sub channel even if the bass manager is not enabled; however, its signal will be muted unless the bass manager is enabled by the bassmgr[2:0] bits. it should be noted that the hizpsig bit must be set to enable the pwm_sig output drivers. to allow stereo headphone operation when the pwm logic-level outputs are mapped in a non-stereo out- put configuration, if the hp_detect/mute pin is configured for headphone detection (the hp/mute bit is set), the pwm logic-level output mapping can be af fected by the active state of the headphone detection input signal. see the headphone detection & hardware mute input section on page 51 for more informa- tion. it should be noted that signal on channels 1, 2, an d the sub channel are dependent upon the digital sound processing blocks being used. for instance, if the 2-way crossover is enabled, channel 1 and 2 contain the 2-way crossover channel a high- and low-pass outpu ts respectively. for more information, see the digital sound processing section and figure 14 on page 29 . pwmdsel[1:0] pwm_sig1 pwm_sig2 00 disabled. disabled. 01 channel 1 channel 2 10 channel 1 sub channel 11 channel 2 sub channel table 10. pwm logic-level output configurations referenced control register location pwmdsel[1:0]..................... ?pwm signals output data select (pwmdsel[1:0])? on page 73 hizpsig ............................... ?hi-z pwm_sig outputs (hizpsig)? on page 79 hp/mute .............................. ?hp_detect/mute pin mode (hp/mute)? on page 70 bassmgr[2:0] ....................... ?bass cross-over frequency (bassmgr[2:0])? on page 79
50 ds726pp1 CS4525 6.1.9 pwm modulator configuration the CS4525 pwm modulators support flexible configur ation options designed to simplify system integra- tion. delays may be inserted between the switching ed ges on adjacent channels to manage noise, and the pwm switching frequency can be easily modified to eliminate interference with am tuners. 6.1.9.1 pwm channel delay the CS4525 includes a pwm output signal delay mech anism. this mechanism a llows the pwm switching edges to be offset between channels as a method of managing switching no ise and reducing radiated emissions. the outputdly[3:0] bits in the output cfg register are used to adjust the channel delay amount from 0 to 15 sys_clk or crystal input clock cycles, whichever is used as th e input clock source. the absolute delay time is calculated by multiply ing the setting of the outputdly[3:0] bi ts by the period of the input clock source. by default, no delay is inserted. when the power outputs are configured for 2-channel full-bridge operation, the out3/out4 signal pair is delayed from the out1/out2 signal pair by the delay amount as shown in figure 20 . when the power outputs are configured for 3-channe l (2-channel half-bridge and 1-channel full-bridge) operation, out2 is delayed from out1 by the de lay amount, and the out3/out4 pair is delayed from out2 by the delay amount as shown in figure 21 . the outputdly[3:0] bits can only be changed when all modulators and associated logic are in the power- down state by setting the pdnall bi t. attempts to write these bits wh ile the pdnall bit is cleared will be ignored. referenced control register location outputdly[3:0] ..................... ?channel delay settings (outputdly[3:0])? on page 73 out1 out2 tch dly out3 out4 figure 20. 2-channel full-bridge pwm output delay out1 out2 tch dly tch dly out3 out4 figure 21. 3-channel pwm output delay
ds726pp1 51 CS4525 6.1.9.2 pwm am frequency shift when using a pwm amplifier in a system containing an am tuner, it is possible that the pwm switch rate conflicts with the desired tuning frequency of the am tu ner. to overcome this effect, the CS4525 includes a pwm switch rate shift feature. the feature adjusts the pwm switching frequency a nd quantization levels to remove interference when the desired tuning frequency of an am tuner is posit ioned near a harmonic of the pwm switching rate. this feature is enabled by setting the freqshift bit in the clock config register. when this feature is en- abled, the output switch rate is lowered and the quantization levels are increased as shown in table 11 below. the nominal pwm switching frequencies and quantization levels are discussed in ?pwm modulators and sample rate converters? on page 58 . 6.1.10 headphone detection & hardware mute input the CS4525 includes a configurable hp_detect/mu te input pin which can be used as a hardware mute input or a headphone detection input. the function of this pin is set by the hp/mute bit in the clock config register. when configured as a mute input pin, all pwm modulators and th e aux_sdout signal will be placed in a mute state when the pin is active. when configured as a headphone detect input pi n and the hp_detect/mute input is active, the pwm_sig1 and pwm_sig2 output pins can output audio from channel 1 and channel 2 respectively re- gardless of the setting of the pwmdsel[1:0] bits. t he out1 - out4 pwm driver outputs will mute by out- putting a non-modulated 50% duty cycle signal. while the headphone detec t input signal is active, the channel mixing, 2-way crossover, and bass management features will a ll be disabled regardless of the settings of the lchmix[1:0], en2way, and bassmgr[2:0] bits, respectively. it shou ld be noted that the right channel?s channel mixing is not af fected by the headphon e detection input signa l and will always output as dictated by the rchmix[1:0] bits. see ?channel mixer? on page 30 , ?2-way crossover & sensitivity control? on page 41 , and ?bass management? on page 35 for more information. when configured as a headphone detect input pin an d the hp_detect/mute input is inactive, the out1 - out4 driver outp uts will output audio accord ing to the channel mixer and bass manager bits? set- tings, and the pwm_sig output pins will mute by outputting a non-m odulated 50% duty cycle. supplied xtal or sys_clk frequency pwm switch rate quantization levels 18.432 mhz 329.143 khz 56 24.576 mhz 341.300 khz 72 27.000 mhz 375 khz 72 table 11. pwm output switching rates and quantization levels referenced control register location freqshift.............................. ?am frequency shifting (freqshift)? on page 70
52 ds726pp1 CS4525 table 12. output of pwm_sig outputs table 12 describes the exact output of the pwm_sig output pins based on the input to the hp_detect/mute pin and t he settings of the hizpsig , hp/mute , bassmgr[2:0], and pwmdsel[1:0] bits. in all configurations, the active logic input level is determined by the hp/mutepol bit. hizpsig setting hp/mute setting hp_detect /mute input bassmgr [2:0] setting pwmdsel [1:0] setting pwm_sig1 output pwm_sig2 output 0 x x x x high impedance high impedance 1 x x x 00 (disabled) driven low driven low 0 (mute mode) not active 000 (disabled) 01 channel 1 channel 2 10 channel 1 mute 11 channel 2 mute 001 through 111 01 channel 1 channel 2 10 channel 1 sub channel 11 channel 2 sub channel active x 01, 10, or 11 mute mute 1 (head- phone mode) not active x 01, 10, or 11 mute mute active 000 (disabled) 01 channel 1* channel 2** 10 channel 1* mute 11 channel 2** mute 001 through 111 01, 10, or 11 channel 1* channel 2** *signals denoted with one asterisk do not have bass manager, 2-way crossover, or channel mix applied. **signals denoted with two asterisks do not have bass manager or 2-way crossover applied. referenced control register location hp/mute .............................. ?hp_detect/mute pin mode (hp/mute)? on page 70 hp/mutepol ......................... ?hp_detect/mute pin active logic level (hp/mutepol)? on page 70 pwmdsel[1:0]..................... ?pwm signals output data select (pwmdsel[1:0])? on page 73 lchmix[1:0] ......................... ?left channel mixer (lchmix[1:0])? on page 76 rchmix[1:0] ........................ ?right channel mixer (rchmix[1:0])? on page 76 en2way............................... ?enable 2-way crossover (en2way)? on page 81 bassmgr[2:0] ....................... ?bass cross-over frequency (bassmgr[2:0])? on page 79 hizpsig ............................... ?hi-z pwm_sig outputs (hizpsig)? on page 79
ds726pp1 53 CS4525 6.1.11 interrupt reporting the CS4525 has comprehensive inte rrupt reporting capabilities. many conditions including src lock, adc overflow, digital data path overflow, an d amplifier errors can cause an interrupt. the int output pin is intended to drive an interrupt input pin on a host microcontroller. the int pin is an open-drain active-low output and requires an external pull-up for proper operation. if an interrupt source is un-masked, its occurrence will cause the interrupt ou tput pin to become active. to enhance flexibility, each inte rrupt source may be masked such that its occurrence does not cause the in- terrupt output pin to become active. this masking function is accomplished by clearing an interrupt?s re- spective mask bit located in the 4 lsb?s of the interrupt register. when a specific interrupt condition oc curs, it?s respective bit located in the 4 msb?s of the interrupt register will be set to indicate that a change has occurred for the associated interrupt type. when the interrupt reg- ister is read, the contents of the 4 msb?s will be cleared. the int sta tus register may th en be read to de- termine the current state of the interrupt source. for specific information regarding in terrupt types and reporting, see th e interrupt, int status and amp er- ror register descriptions. 6.1.12 automatic power stage shut-down to prevent permanent dam age, the CS4525 will automatically shut down its internal pwm power output stages when a thermal error, pwm power output over-c urrent error, or vp under-voltage condition occurs. in the shut-down state, all digita l functions of the devi ce will operate as normal, however the pwm power output pins become high-impedance. the levels of the over-current error, thermal error, and vp under-voltage trigger points are listed in the pwm power output characteristics table on page 20 . automatic shut-down will occur whenever any of these preset thresholds are crossed. once in the shut-down state, ea ch powered pwm outputs will remain as high-impedanc e and will not re- sume normal operation until either the pdnall bit or the pdnoutx bit for the channel in error is set and then cleared. if the autoretry bit is set, the cs 4525 will attempt to auto matically resume power output operation after an over-current error is encountered and before entering the shut-down state. with the autoretry function enabled, the CS4525 will place the pw m power outputs in a high-impe dance state upon the sensing of an over-current condition, wait approximately 85 ms, and then re-engage the power outputs in an attempt to resume normal operation. if another over-current condition is immediately detected, the pwm power outputs will again be placed in a high -impedance state before retrying to resume normal operation a sec- ond time. it will continue this seque nce for a maximum of fi ve attempts. after the fifth unsuccessful at- tempt, the outputs will remain in a high-impedance state until the pdna ll bit is set an d then cleared. referenced control register location interrupt register ................ ?interrupt (address 60h)? on page 89 int status register............... ?interrupt status (address 61h) - read only? on page 92 amp error register ............. ?amplifier error status (address 62h) - read only? on page 93 referenced control register location autoretry ............................ ?automatic power stage retry (autoretry)? on page 88 pdnall ................................. ?power down (pdnall)? on page 89 pdnoutx ............................. ?power down pwm power output x (pdnoutx)? on page 88
54 ds726pp1 CS4525 6.2 hardware mode a limited feature set is available when the CS4525 powers up in hardware mode. the available features are described in the following sections. all device configuration is achieved via hardware control input pins. 6.2.1 system clocking in hardware mode, the CS4525 must be clocked by a stable external clock source input on the sys_clk pin. this input clock is used to synchronize the inpu t serial audio signals with the internal clock domain and to clock the internal digital processing, sample -rate converter, and pwm modulators. it is also used to determine the sample rate of the serial audio inpu t signals in order to automatically configure the vari- ous internal filter coefficients. to ensure proper operation, the CS4525 must be in formed of the nominal frequency of the supplied sys_clk signal via the clkfreq[1:0] hardware contro l pins. these pins must be set to the appropriate level before the rst signal is released to in itiate a power-up sequence. the nominal clock frequencies indicated by the states of the clkfreq[1:0] pins are shown in table 13 below. see the sys_clk switching specifications table on page 23 for complete input frequency range specifications. warning: the sys_clk signal must neve r be removed or stopped while the rst pin is high and any of the power output stages are connected to a load. doing so may result in permanent damage to the CS4525 and connected transducers. figure 22 below demonstrates a typical clocking configuration using the sys_clk input. 6.2.2 power-up and power-down the CS4525 will remain in a completely powered-down state until the rst pin is brought high. 6.2.2.1 recommended power-up sequence 1. hold rst low until the power supplies and the input sys_clk signal are stable. 2. bring rst high. hardware mode will be entere d after approximately 10 ms. clkfreq1 clkfreq0 nominal sys_clk frequency low low 18.432 mhz low high 24.576 mhz high low 27.000 mhz high high reserved table 13. sys_clock frequency selection sys_clk rst dsp reset_out clock_in clock xti xto figure 22. typical sys_clk in put clocking configuration CS4525
ds726pp1 55 CS4525 6.2.2.2 recommended power-down sequence 1. bring mute low to mute the device?s outputs and minimize audible pops. 2. bring rst low to halt the operation of the device. the device?s power consumption will be brought to an absolute minimum. 3. remove power. 6.2.3 input source selection the CS4525 can accept analog or digital audio in put signals. digital audio input signals are supplied through the serial audio input port as outlined in ?serial audio interfaces? on page 62 . analog audio input signals are supplied through the internal adc as outlined in ?analog inputs? on page 61 . the input source is selected by the adc/sp pin as shown in table 14 below and can be changed at any time without caus- ing any audible pops or clicks. in hardware mode, the serial audio input port supports both i2s and left-justified formats. the serial audio interface format is selected by the i2s/lj pin as shown in table 15 below. 6.2.4 pwm channel delay in hardware mode, the CS4525 offsets the pwm swit ching edges between channels as a method of man- aging switching noise and reducing radiated emissions. the out3/out4 signal pair is delayed from the out1 /out2 signal pair by 4 sys_clk cycles as shown in figure 23 below. the absolute delay time is calculated by mult iplying the period sys_clk by 4. adc/sp selected input source low digital audio inputs (serial port) high analog audio inputs (adc) table 14. input source selection i2s/lj selected serial audio interface format low left-justified high i2s table 15. serial audio interface format selection out1 out2 4 x t sys_clk out3 out4 figure 23. hardware mode pwm output delay
56 ds726pp1 CS4525 6.2.5 digital signal flow in hardware mode, the CS4525 operates as a 2-cha nnel full-bridge pwm amplifier with analog or digital inputs. both the pwm outputs and th e auxiliary serial outputs are unava ilable in hardware mode. to pro- tect against over-temperature conditions, thermal foldback is included for the internal power stages. the digital signal flow is shown in figure 24 below. figure 24. hardware mode digital signal flow 6.2.5.1 high-pass filter the CS4525 includes a high-pass filter at the beginnin g of the digital signal processing chain to remove any dc content from the input signal prior to the rema ining internal digital signal processing blocks. the high-pass filter operates by contin uously subtracting a measure of the dc offset from the input signal; it is always enabled. 6.2.5.2 mute control the CS4525 includes a dedicated mute input pin. when low, the pwm outputs will output silence as modulated signal. when high, the selected input source will be pres ented at the am plifier outputs. it should be noted that the auto-mute, soft-ramp, and zero-crossing detection features are active in hard- ware mode. 6.2.5.3 warning and error reporting the CS4525 is capable of reporting variou s error and warning co nditions on its twr , erroc , and er- ruvte pins. ?the twr pin indicates the presence of a thermal warni ng condition. when active concurrently with the erruvte pin, indicates a thermal error condition. ? the erroc pin indicates the presence of an over-current condition on one or both of the output chan- nels. ? the erruvte pin indicates the presence of a vp undervolt age condition. when active concurrently with the twr pin, indicates a thermal error condition. the trigger point for each warning and error condition is defined in the pwm power output characteristics table on page 20 . each pin implements an active-low open-dr ain driver and requires an external pull-up for proper operation. left full-bridge amplifier output sample rate converter pwm modulator sample rate converter pwm modulator mute thermal foldback thermal foldback high-pass temp & current sense adc/sp stereo analog in serial audio clocks & data i2s/lj serial audio input port multi-bit ? adc en_tfb right full-bridge amplifier output gate drive power stage gate drive power stage gate drive power stage gate drive power stage twr erroc erruvte mute +3db +3db
ds726pp1 57 CS4525 6.2.6 thermal foldback in hardware mode, the CS4525 implements a thermal foldback feature to guard against damaging thermal overload conditions. the thermal foldback feature begi ns limiting the volume of the digital audio input to the amplifier stage as the junction temperatures ri se above the maximum safe operating range specified by the thermal warning tr igger point lis ted in the pwm power output characteristics table on page 20 . this effectively limits the output po wer capability of the devi ce, thereby allowing t he temperatur e to reduce to acceptable levels without fully interrupting operation. as the devi ce cools, the applied attenuation is gradually released until a new thermal equilibrium is reached or all applied attenuation has been released thereby allowing the devi ce to again achieve its full output power capability. attenuation applied due to thermal foldback reduces the audio output level in a linear manner. figure 18 below demonstrates the foldback process. thermal warning conditions w ill only affect the foldback algorithm and cause attenuation to be applied if enabled by the en_tfb pin as shown in table 16 below. en_tfb selected thermal foldback enable state low thermal foldback disabled. high thermal foldback enabled. table 16. thermal foldback enable selection thermal warning threshold t delay 1 2 2 2 2 3 1 foldback attack delay approximately 2 sec. t delay t delay t delay t delay 1 when the junction temperature crosses the thermal warning threshold, the foldback attack delay timer is started. 2 when the foldback attack delay timer reaches t delay seconds, the junction temperature is checked. if it is above the thermal warning threshold, the output vo lume level is lowered by 0.5 db and the foldback attack timer is restarted. the junction temperature is checked after each foldback atta ck timer timeout, and if necessary, the output volume level is lowered accordingly. if the junction temperature is found to be below the th ermal warning threshold, the foldback attack timer is restarted once again, but the output volume level is not altered. the foldback algorithm then proceeds to step 3. 3 the junction temperature is checked once again after the next foldback attack timer timeout. if is has remained below the thermal warning threshold since the last check, the device will begin to re lease any attenuation applied as a result of the foldback event. if the junction temperature crosses the thermal warning threshold agai n, the foldback algo rithm will once again enter step 1. figure 25. foldback process
58 ds726pp1 CS4525 6.2.7 automatic powe r stage shut-down to protect itself from permanent damage , the CS4525 will automatically shut down its internal pwm pow- er output stages when a thermal erro r, pwm power output over-current error, or vp under-voltage condi- tion occurs. in the shut-down state, all digital functions of the device will operate as normal, however the pwm power output pins become high-impedance. the levels of the over-current erro r, thermal error, and vp under-voltage trigger points are listed in the pwm power output characteristics table on page 20 . shut-down will occur auto matically whenever the preset thresholds for thermal error or under-voltage are crossed. when the over-current threshold is crossed, the CS4525 will attempt to automatically resume power out- put operation after an over-current error is encounte red and before placing its pwm power outputs in the shut-down state. upon th e detection of an over-cur rent condition, the cs4 525 will place the pwm power outputs in a high-impedance state, wait approxim ately 85 ms, and then re-engage the power outputs in an attempt to resume normal operation. if another over-current condition is immediately detected, the pwm power outputs will again be placed in a high-impedance st ate before retrying to resume normal op- eration a second time. it will continue this sequence for a maximum of fi ve attempts. afte r the fifth unsuc- cessful attempt, the outputs will remain in the high-impedanc e shut-down state. once in the shut-down state, the rst signal must be toggled low and then high to resume normal device operation. 6.3 pwm modulators and sa mple rate converters the CS4525 includes three pwm modulators and three corresponding sample rate converters, each clocked from the external crystal or system clock app lied at power-up. all three modulator and sample rate converter pairs are available in software mode (see figure 14 on page 29 ), and two pairs are used in hard- ware mode (see figure 24 on page 56 ). one of the characteristics of a pwm modulator is that the frequency content of the out-of-band noise gen- erated is dependent on the pwm switching frequency. as the power stage extern al lc and snubber filter component values are used to attenuate this out-of band energy, their component values are also based on this switching frequency. to easily accommodate input sample rates ranging from 32 khz to 96 khz without requiring the adjustment of output filter component values, the CS4525 utilizes a sample rate converter (src) to keep the pwm switching frequency fixed regardless of the input samp le rate. the src operates by upsampling the variable input sample rate to a fixed output switching ra te, typically 384 khz for most audio applications. table 17 below shows the pwm output switching rate and quantiza tion levels as a function of the supplied external crystal or system clock. additionally, as the output of the src is clocked from a very stable crystal or oscillator, the src also allows the pwm modulator output to be independent of the inpu t serial audio clock jitter. this results in very low jitter pwm output and higher dynamic range. supplied xtal or sys_clk frequency pwm switch rate quantiza tion levels 18.432 mhz 384 khz 48 24.576 mhz 384 khz 64 27.000 mhz 421.875 khz 64 table 17. pwm output switching rates and quantization levels
ds726pp1 59 CS4525 6.4 output filters the filter placed after the pwm outputs can greatly affe ct the output performance. the filter not only reduces radiated emi (snubber filter), but also filters high fr equency content from the switching output before going to the speaker (low-pass lc filter). 6.4.1 half-bridge output filter figure 26 shows the output filter for a half-bridge config uration. the transient-voltage suppression circuit (snubber circuit) is comprised of a capacitor (680 pf) and a resistor (5.6 , 1/8 w) and should be placed as close as possible to the corresponding pw m output pin to greatly reduce radiated emi. the inductor, l1, and capacitor, c1, comprise the low-pass filter. along with the nominal load impedance of the speaker, these values set the cutoff frequency of the filter. table 18 shows the component values for l1 and c1 based on nominal speaker (load) impedance for a corner frequency (-3 db point) of approx- imately 35 khz. c2 is the dc-blocking capacitor. table 19 shows the component values for c2 based on corner frequency (-3 db point) and a nominal speaker (load) impedances of 4 , 6 , and 8 . this capacitor should also be chosen to have a ripple curr ent rating above the amount of current th at will passed through it. load l1 c1 4 22 h 1.0 f 6 33 h 0.68 f 8 47 h 0.47 f table 18. low-pass filter components - half-bridge load corner frequency c2 4 40 hz 1000 f 58 hz 680 f 120 hz 330 f 6 39 hz 680 f 68 hz 390 f 120 hz 220 f 8 42 hz 470 f 60 hz 330 f 110 hz 180 f table 19. dc-blocking capacitors values - half-bridge outx 680 pf c1 5.6 l1 c2 +- vp *diode is rohm rb160m-30 or equivalent figure 26. output filter - half-bridge
60 ds726pp1 CS4525 6.4.2 full-bridge output fi lter (stereo or parallel) figure 27 shows the output filter for a full-bridge configur ation. the transient-voltage suppression circuit (snubber circuit) is comprised of a capacitor (680 pf) and a resistor (5.6 , 1/8 w) on each output pin and should be placed as close as possible to the corres ponding pwm output pins to greatly reduce radiated emi. the inductors, l1, and capacitor, c1, comprise the low-pass filter. along with the nominal load im- pedance of the speaker, these values se t the cutoff frequency of the filter. table 20 shows the component values based on nominal speaker (load) impedance for a corner frequency (-3 db point) of approximately 35 khz. load l1, l2 c1 4 10 h 1.0 f 6 15 h 0.47 f 8 22 h 0.47 f table 20. low-pass filter components - full-bridge outx+ outx- c1 l1 l2 *diode is rohm rb160m-30 or equivalent vp vp 680 pf 5.6 680 pf 5.6 figure 27. output filter - full-bridge
ds726pp1 61 CS4525 6.5 analog inputs very few components are required to interface between the audio source and the CS4525?s analog inputs, ainl and ainr. a single order passive low-pass filter is recommended to prevent high-frequency content from aliasing into the audio band due to the analog-to- digital conversion process. also, a dc-blocking ca- pacitor is required as the CS4525?s anal og inputs are internally biased to vq. the recommended analog input circuit is shown in figure 28 below will accommodate full-scale input volt- ages as defined in the analog input characteristics table on page 19 . this circuit provides the necessary high-frequency filtering with a first-or der passive low-pass filter that ha s less than 0.05 db of attenuation at 24 khz. it also includes a dc bl ocking capacitor to accommodate the analog input pins? bias level. to interface 2 v rms input signals with the CS4525?s analog inputs, an external resistor divider is required. figure 29 shows the recommended input circuit for 2 v rms inputs. it includes a -8.4 db passive attenuator to condition the input signal for the CS4525?s full-scale input voltage, a first-order passive low-pass filter that has less than 0.05 db of attenuation at 24 khz, and a dc blocking capacitor to accommodate for the analog input pins? bias level. the passive attenuator network should be placed as close as possible to the CS4525?s analog input pins to reduce the potential for noise and signal coupling into the analog input traces. it should be noted that the external dc blocking capacitor forms a high- pass filter with the CS4525?s input impedance. both filters shown above have less than 0. 2 db attenuation at 20 hz due to this effect. increas- ing the value of this capacitor will lo wer this high-pass corner frequency, and decreasi ng it?s value will in- crease the corner frequency. CS4525 ainl ainr 1 f 365 1800 pf left input 1 f 365 1800 pf right input 100 k 100 k c0g c0g fi g ure 28. recommended unit y gain in p ut filter CS4525 ainl 100 pf left input c0g 1 f 5.62 k 8.06 k ainr 100 pf right input c0g 1 f 5.62 k 8.06 k figure 29. recommended 2 v rms input filter
62 ds726pp1 CS4525 6.6 serial audio interfaces the CS4525 interfaces to external di gital audio devices via the serial a udio input port and the auxiliary/delay serial ports. the serial audio input port provides support for i2s, left-justified and right-justified data formats and op- erates in slave mode only, with lrck and sclk as in puts. the input lrck signal must be equal to the sample rate, fs and must be synchronous to the serial bit clock, sclk, which is used to sample the data bits. the auxiliary/delay serial po rt (available in softw are mode only) supports i2s an d left-justified data formats and operates in master mode only, wit h aux_lrck and aux_sclk as outputs. each of the supported formats is described in detail in sections 6.6.1 - 6.6.3 below. please refer to the serial audio input port switching specifications and aux serial audio i/o port switching specifications on page 21 and page 22 (respectively) for the precise timing and tolerances of each signal. for additional information, application note an282 presents a tutorial of the 2-channel serial audio interface. an282 can be downloaded from the cirrus logic web site at http://www.cirrus.com . 6.6.1 i2s data format in i2s format, data is rece ived most significant bit first one sclk delay after the transition of lrck and is valid on the rising edge of sclk. the left channel dat a is presented when lrck is low; the right channel data is presented when lrck is high. 6.6.2 left-justified data format in left-justified forma t, data is received most significant bit firs t on the first sclk after a lrck transition and is valid on the rising edge of sclk. the left channel data is presented when lrck is high and the right channel data is pres ented when lrck is low. left channel right channel sdin +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb lrck sclk figure 30. i2s serial audio formats lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 31. left-justified serial audio formats
ds726pp1 63 CS4525 6.6.3 right-justified data format in right-justified format, data is received most signif icant bit first and with the le ast significant bit present- ed on the last sclk before the lrck transition and is valid on the rising edge of sclk. for the right- justified format, the left channel data is presented when lrck is high and the right channel data is pre- sented when lrck is low. 16, 18, 20, and 24 bits per sample are supported. 6.7 integrated vd regulator the CS4525 includes two internal linear regulators, on e from the vd supply voltage to provide a fixed 2.5 v supply to its internal digital blocks, and anothe r from the vd supply voltage to provide a fixed 2.5 v supply to its internal analog blocks. the lvd pin must be set to indicate the voltage present on the vd pin as shown in table 21 below. the output of the digital regulator is presented on th e vd_reg pin and may be used to provide an external device with up to 3ma of current at its nomi nal output voltage of 2.5 v . the output of the analog regulator is presented on the va_reg pin and must only be con nected to the bypass capaci tors as shown in the typ- ical connection diagrams. if a nominal supply voltage of 2.5 v is used as the vd supply (see the recommended operating conditions table on page 18 ), the vd, vd_reg, and va_reg pins must all be connected to the vd supply source. in this configuration, the internal regulators are bypass ed and the external supply source is used to directly drive the internal digital and analog sections. vd connection vd_reg connection va_reg connection lvd connection selectvd bit setting software mode only 5 v supply bypass capacitors only bypass capacitors only vd ?1? - default 3.3 v supply bypass capacitors only bypass capacitors only dgnd ?1? - default 2.5 v supply vd and bypass capacitors vd and bypass capacitors dgnd ?0? table 21. power supply configuration and settings referenced control register location selectvd ............................. ?select vd level (selectvd)? on page 88 left channel right channel 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 sdin lrck sclk figure 32. right-justified serial audio formats
64 ds726pp1 CS4525 6.8 i2c control port description and timing the control port is used to access the registers allo wing the CS4525 to be configured for the desired oper- ational modes and formats. the operation of the contro l port may be completely asynchronous with respect to the audio sample serial port. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in i2c mode, with the CS4525 act- ing as a slave device. sda is a bidirectional data line. data is clocked in to and out of the part by the clock, scl. a 47 k pull-up or pull-down on the aux_lrck/ad0 pi n will set ad0, the least significant bit of the device address. a pull- up to vd will set ad0 to ?1? and a pull-down to dg nd will set ad0 to ?0?. the state of aux_lrck/ad0 is sensed, and ad0 is set upon the release of reset . the signal timings for a read and write cycle are shown in figure 33 and figure 34 . a start condition is de- fined as a falling transition of sda while the clock is hi gh. a stop conditi on is a rising transition while the clock is high. all other transitions of sda occur while th e clock is low. the first byte sent to the CS4525 after a start condition consists of a 7 bit device address field and a r/w bit (high for a read, low for a write). the upper 6 bits of the 7-bit address field are fixed at 100101. to communicate with a CS4525, the device ad- dress field, which is the first byte sent to the cs4 525, should match 100101 followed by the setting of ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or wr itten. if the oper ation is a read, the contents of the register pointed to by the map will be output. settin g the auto increment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the CS4525 after each input byte is read, and is in put to the CS4525 from the microcontroller after each transmitted byte. since the read operation can not set the map, an abort ed write operation is used as a preamble. as shown in figure 34 , the write operation is aborted after the ackno wledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 100101x0 (device address and write operation). receive acknowledge bit. send map byte, au to increment off. receive acknowledge bit. send stop condition, aborting write. (optional.) send start condition. send 100101x1(device address and read operation). 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 33. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda 1 0 0 1 0 1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 34. control port timing, i2c read
ds726pp1 65 CS4525 receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. (optional.) setting the auto increment bit in th e map allows successive reads or wr ites of consecutiv e registers. each byte is separated by an acknowledge bit. 7. pcb layout considerations 7.1 power supply, grounding as with any high-resolution converter, the CS4525 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. extensive use of power and ground planes, ground plan e fill in unused areas and surface mount decoupling capacitors are recommended. decoupling capacitors shoul d be as close to the pins of the CS4525 as pos- sible. the lowest value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS4525 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+ and vq pi ns in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the electrical path from filt+ and agnd. the crd4525 reference design demonstrates the optimu m layout and power sup- ply arrangements. 7.2 qfn thermal pad the CS4525 is available in a compact qfn package. the underside of the qfn package reveals a large metal pad that serves as a thermal relief to provide fo r maximum heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other pcb layers. the crd4525 reference design demonstrates the optimum thermal pad and via configuration. for more information concerning thermal considerations of qfn packages, please refer to cirrus logic ap- plication note an315.
66 ds726pp1 CS4525 8. register qu ick reference this table shows the register names and their associated default values. adr name76543210 01h clock config ensysclk divsysclk c lkfreq1 clkfreq0 hp/mutepol hp/mute phaseshift freqshift page 69 10010000 02h input config adc/sp enanhpf reserved sprat e1 sprate0 dif2 dif1 dif0 page 71 010xx000 03h aux config enauxport dlyportcfg1 dlyportcfg0 auxi2s/lj rchdsel1 rchdsel0 lchdsel1 lchdsel0 page 72 00000100 04h output cfg outputcfg1 outputcf g0 pwmdsel1 pwmdsel0 outputdly3 outputdly2 outputdly1 outputdly0 page 73 00000000 05h foldback cfg selectvp entherm lockadj at tackdly1 attackdly0 enfloor rmpspd1 rmpspd0 page 74 10001011 06h mixer config prescale2 prescale1 prescale0 reserved rchmix1 rchmix0 lchmix1 lchmix0 page 75 00000000 07h tone config deemph loudness endighpf trebfc1 trebfc0 bassfc1 bassfc0 entonectrl page 76 00000010 08h tone control treble3 treble2 treble1 treble0 bass3 bass2 bass1 bass0 page 78 10001000 09h eq config freeze hizpsig bassmgr2 bassmgr1 bassmgr0 reserved enchbpeq enchapeq page 78 00000000 0ah biquad 1 a1 coeff msb ............................................................................................................................ . msb-7 0bh msb-8 ....................................................................................................................... ...... lsb+8 0ch lsb+7 ....................................................................................................................... ...... lsb 0dh biquad 1 a2 coeff msb ............................................................................................................................ . msb-7 0eh msb-8 ....................................................................................................................... ...... lsb+8 0fh lsb+7 ....................................................................................................................... ...... lsb 10h biquad 1 b0 coeff msb ............................................................................................................................ . msb-7 11h msb-8 ....................................................................................................................... ...... lsb+8 12h lsb+7 ....................................................................................................................... ...... lsb 13h biquad 1 b1 coeff msb ............................................................................................................................ . msb-7 14h msb-8 ....................................................................................................................... ...... lsb+8 15h lsb+7 ....................................................................................................................... ...... lsb 16h biquad 1 b2 coeff msb ............................................................................................................................ . msb-7 17h msb-8 ....................................................................................................................... ...... lsb+8 18h lsb+7 ....................................................................................................................... ...... lsb 19h biquad 2 a1 coeff msb ............................................................................................................................ . msb-7 1ah msb-8 ....................................................................................................................... ...... lsb+8 1bh lsb+7 ....................................................................................................................... ...... lsb 1ch biquad 2 a2 coeff msb ............................................................................................................................ . msb-7 1dh msb-8 ....................................................................................................................... ...... lsb+8 1eh lsb+7 ....................................................................................................................... ...... lsb 1fh biquad 2 b0 coeff msb ............................................................................................................................ . msb-7 20h msb-8 ....................................................................................................................... ...... lsb+8 21h lsb+7 ....................................................................................................................... ...... lsb 22h biquad 2 b1 coeff msb ............................................................................................................................ . msb-7 23h msb-8 ....................................................................................................................... ...... lsb+8 24h lsb+7 ....................................................................................................................... ...... lsb
ds726pp1 67 CS4525 25h biquad 2 b2 coeff msb ............................................................................................................................ .msb-7 26h msb-8 ....................................................................................................................... ...... lsb+8 27h lsb+7 ....................................................................................................................... ...... lsb 28h biquad 3 a1 coeff msb ............................................................................................................................ .msb-7 29h msb-8 ....................................................................................................................... ...... lsb+8 2ah lsb+7 ....................................................................................................................... ...... lsb 2bh biquad 3 a2 coeff msb ............................................................................................................................ .msb-7 2ch msb-8 ....................................................................................................................... ...... lsb+8 2dh lsb+7 ....................................................................................................................... ...... lsb 2eh biquad 3 b0 coeff msb ............................................................................................................................ .msb-7 2fh msb-8 ....................................................................................................................... ...... lsb+8 30h lsb+7 ....................................................................................................................... ...... lsb 31h biquad 3 b1 coeff msb ............................................................................................................................ .msb-7 32h msb-8 ....................................................................................................................... ...... lsb+8 33h lsb+7 ....................................................................................................................... ...... lsb 34h biquad 3 b2 coeff msb ............................................................................................................................ .msb-7 35h msb-8 ....................................................................................................................... ...... lsb+8 36h lsb+7 ....................................................................................................................... ...... lsb 37h biquad 4 a1 coeff msb ............................................................................................................................ .msb-7 38h msb-8 ....................................................................................................................... ...... lsb+8 39h lsb+7 ....................................................................................................................... ...... lsb 3ah biquad 4 a2 coeff msb ............................................................................................................................ .msb-7 3bh msb-8 ....................................................................................................................... ...... lsb+8 3ch lsb+7 ....................................................................................................................... ...... lsb 3dh biquad 4 b0 coeff msb ............................................................................................................................ .msb-7 3eh msb-8 ....................................................................................................................... ...... lsb+8 3fh lsb+7 ....................................................................................................................... ...... lsb 40h biquad 4 b1 coeff msb ............................................................................................................................ .msb-7 41h msb-8 ....................................................................................................................... ...... lsb+8 42h lsb+7 ....................................................................................................................... ...... lsb 43h biquad 4 b2 coeff msb ............................................................................................................................ .msb-7 44h msb-8 ....................................................................................................................... ...... lsb+8 45h lsb+7 ....................................................................................................................... ...... lsb 46h biquad 5 a1 coeff msb ............................................................................................................................ .msb-7 47h msb-8 ....................................................................................................................... ...... lsb+8 48h lsb+7 ....................................................................................................................... ...... lsb 49h biquad 5 a2 coeff msb ............................................................................................................................ .msb-7 4ah msb-8 ....................................................................................................................... ...... lsb+8 4bh lsb+7 ....................................................................................................................... ...... lsb 4ch biquad 5 b0 coeff msb ............................................................................................................................ .msb-7 4dh msb-8 ....................................................................................................................... ...... lsb+8 4eh lsb+7 ....................................................................................................................... ...... lsb 4fh biquad 5 b1 coeff msb ............................................................................................................................ .msb-7 50h msb-8 ....................................................................................................................... ...... lsb+8 51h lsb+7 ....................................................................................................................... ...... lsb 52h biquad 5 b2 coeff msb ............................................................................................................................ .msb-7 53h msb-8 ....................................................................................................................... ...... lsb+8 54h lsb+7 ....................................................................................................................... ...... lsb adr name76543210
68 ds726pp1 CS4525 55h volume cfg szcmode1 szcmode0 mute50/50 automute en2way 2wayfreq2 2wayfreq1 2wayfreq0 page 80 10010000 56h sensitivity lowpass3 lowpass2 lowpass1 low pass0 highpass3 highpa ss2 highpass1 highpass0 page 81 00000000 57h master vol mvol7 mvol6 mvol5 mvol4 mvol3 mvol2 mvol1 mvol0 page 82 00101010 58h ch a vol chavol7 chavol6 chavol5 chavol4 chavol3 chavol2 chavol1 chavol0 page 83 00110000 59h ch b vol chbvol7 chbvol6 chbvol5 chbvol4 chbvol3 chbvol2 chbvol1 chbvol0 page 83 00110000 5ah sub vol subvol7 subvol6 subvol5 subvol4 subvol3 subvol2 subvol1 subvol0 page 83 00110000 5bh mute control invadc invsub invch2 invch1 muteadc mutesub mutechb mutecha page 84 00000000 5ch limiter cfg 1 max2 max1 max0 m in2 min1 min0 limitall enlimiter page 85 00000010 5dh limiter cfg 2 reserved reserved rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 page 87 00111111 5eh limiter cfg 3 enthlim reserved ar ate5 arate4 arate3 arate2 arate1 arate0 page 87 00000000 5fh power ctrl autoretry reserved selectv d pdnadc pdnout3/4 pdnout2 pdnout1 pdnall page 88 11111111 60h interrupt srclock adcovfl chovfl amperr srclockm adcovflm chovflm amperrm page 89 xxxx0000 61h int status srclockst adcovflst subovflst ch2ovflst ch1ovflst rampdone reserved reserved page 92 xxxxxx00 62h amp error overcurr4 overcurr3 overcurr2 overcurr1 extampst reserved uvte1 uvte0 page 93 xxxxx0xx 63h device id deviceid4 deviceid3 deviceid2 deviceid1 deviceid0 revid2 revid1 revid0 page 94 11111xxx adr name76543210
ds726pp1 69 CS4525 9. register descriptions all registers are read/write unless ot herwise stated. all ?reserved? bits must maintain their default state. 9.1 clock configuration (address 01h) 9.1.1 sys_clk output enable (ensysclk) default = 1 function: this bit controls the output driver for the sys_clk signal. when clear ed, the output driver is disabled and the sys_clk pin is high-imp edance. when set, the output driv er is enabled. if the sys_clk output is unused , this bit should be set to ?0?b to disable the driver. 9.1.2 sys_clk output divider (divsysclk) default = 0 function: this bit determines t he divider for the xtal clock signa l for generating the sys_clk signal. this divider is only available if the clock source is an external crystal attached to xti/xto and the sys_clk output is enabled. 9.1.3 clock frequency (clkfreq[1:0]) default = 01 function: these bits must be set to identify the nominal clock frequency of the crystal attached to the xti/xto pins or that of the input sys_clk signal. see the xti switching specifications table on page 23 and the sys_clk switching specifications table on page 23 for complete input frequ ency range specifications. 76543210 ensysclk divsysclk clkfreq1 clk freq0 hp/mutepol hp/mute phaseshift freqshift ensysclk setting out put driver state 0 ..........................................output driver disabled. 1 ..........................................output driver enabled. divsysclk setting sys_clk output frequency 0 ..........................................f sys_clk =f xtal 1 ..........................................f sys_clk =f xtal /2 clkfreq[1:0] setting specified nominal input clock frequency 00 ........................................18.432 mhz 01 ........................................24.576 mhz 10 ........................................27.000 mhz 11.........................................reserved
70 ds726pp1 CS4525 9.1.4 hp_detect/mute pin ac tive logic level (hp/mutepol) default = 0 function: this bit determines the active logic level for the hp_detect/mute input signal. 9.1.5 hp_detect/mute pin mode (hp/mute ) default = 0 function: configures the function of hp_detect/mute input pin. see ?headphone detection & hardware mute input? on page 51 for more information. 9.1.6 modulator phase shifting (phaseshift) default = 0 function: when enabled, forces the output of the pwm modulator to output differential si gnals which are the inverse of each other and have been phase shifted by 180 deg rees. this causes, for instance, the differential sig- nal pair to be exactly in phase with one another during a mute condition, thereby reducing the amount of switching current through the load. 9.1.7 am frequency shifting (freqshift) default = 0 function: controls the state of the pwm am frequency shift feature. see ?pwm am frequency shift? on page 51 for more information. hp/mutepol setting headphone detect/mute input polarity 0 .......................................... active low. 1 .......................................... active high. hp/mute setting hp_detect/mute pin function 0 .......................................... mute input signal. 1 .......................................... headphone detect input signal. phaseshift setting modulator phase shift state 0 .......................................... 180o phase shift disabled. 1 .......................................... 180o phase shift enabled. freqshift setting am frequency shift state 0 .......................................... frequency shift disabled. 1 .......................................... frequency shift enabled.
ds726pp1 71 CS4525 9.2 input configuration (address 02h) 9.2.1 input source selection (adc/sp ) default = 0 function: this bit selects the audio input source. 9.2.2 adc high-pass filt er enable (enanhpf) default = 1 function: controls the operation of the adc high-pass filter. 9.2.3 serial port sample rate (sprate[1:0]) - read only function: identifies the sample rate of the incoming lrck sign al on the serial audio input port based on the setting of the clkfreq[1:0] bits in register 01h, the freque ncy of the internal system clock, and the frequency of the input lrck signal. 9.2.4 input serial port digi tal interface format (dif [2:0]) default = 000 function: selects the serial audio interface format used for the data in on sdin. the required relationship between the left/right clock, serial clock and serial data is defined by the digital in terface format and the options are detailed in the section ?serial audio interfaces? on page 62 . 76543210 adc/sp enanhpf reserved sprate1 sprate0 dif2 dif1 dif0 adc/sp setting audio input source 0 ..........................................digital input from the serial audio input port. 1 ..........................................analog input from the internal adc. enanhpf setting adc high-pass filter state 0 ..........................................adc high-pass filter disabled. 1 ..........................................adc high-pass filter enabled. sprate[1:0] setting ident ified input sample rate 00 ........................................32 khz 01 ........................................44.1 khz 10 ........................................48 khz 11.........................................96 khz dif[2:0] setting input serial port serial audio interface format 000 ......................................left-justified, up to 24-bit data. 001 ......................................i2s, up to 24-bit data. 010 ......................................right-justified, 24-bit data. 011.......................................right-justified, 20-bit data. 100 ......................................right-justified, 18-bit data. 101 ......................................right-justified, 16-bit data. 110.......................................reserved. 111 .......................................reserved.
72 ds726pp1 CS4525 9.3 aux port configuration (address 03h) 9.3.1 enable aux serial port (enauxport) default = 0 function: controls the operation of the auxiliary serial port. 9.3.2 delay & warning port co nfiguration (dlyportcfg[1:0]) default = 00 function: controls the operation of the delay and warning port. see ?serial audio delay & warning input port? on page 44 for more information. 9.3.3 aux/delay serial port di gital interface format (auxi2s/lj ) default = 0 function: selects the serial audio interface format for the data on aux_sdout, dly_ sdin, dly_sdout. the re- quired relationship between the left/right clock, serial clock and serial data is defined by the digital in- terface format and the options are detailed in the ?serial audio interfaces? on page 62 . 9.3.4 aux serial port right cha nnel data select (rchdsel[1:0]) default = 01 function: selects the data to be se nt over the right channel of the auxiliary port seri al data output signal. 76543210 enauxport dlyportcfg1 dlyportcfg0 auxi2s/lj rchdsel1 rchdsel0 lchdsel1 lchdsel0 enauxport setting auxiliary port state 0 .......................................... auxiliary port disabled. 1 .......................................... auxiliary port enabled. dlyportcfg[1:0] setting delay port configuration 00 ........................................ port disabled. 01 ........................................ port configured as serial audio delay interface. 10 ........................................ port configured as an external thermal warning indicator fo r the foldback algorithm. 11......................................... port disabled. auxi2s/lj setting auxiliary/delay port serial audio interface format 0 .......................................... left-justified, up to 24-bit. 1 .......................................... i2s, up to 24-bit. rchdsel[1:0] setting aux serial port right channel output data source 00 ........................................ channel a. 01 ........................................ channel b. 10 ........................................ sub channel. 11......................................... channel b crossover high-pass output.
ds726pp1 73 CS4525 9.3.5 aux serial port left cha nnel data select (lchdsel[1:0]) default = 00 function: selects the data to be sent over the left channel of the auxiliary port serial data output signal. 9.4 output configurat ion (address 04h) 9.4.1 output configurat ion (outputcfg[1:0]) default = 00 function: identifies the power output config uration. this parameter can only be changed when all modulators and associated logic are in the power-down state (the pdnall bit is set). attempts to write this register while the pdnall is cleare d will be ignored. see ?output channel configurations? on page 45 for more informa- tion. 9.4.2 pwm signals output da ta select (pwmdsel[1:0]) default = 00 function: selects the pwm data output on the pwm_ sig1 and pwm_sig2 output signals.see ?pwm_sig logic- level output configurations? on page 49 for more information. 9.4.3 channel delay settings (outputdly[3:0]) default = 0000 function: the channel delay bits allow delay adjustment of each of the power output audio channels. the value of this register determines the amount of delay inserted in the output path. the delay time is calculated by multiplying the register value by the period of the sys_clk or crystal input clock source . these bits can lchdsel[1:0] setting aux serial port left channel output data source 00 ........................................channel a. 01 ........................................channel b. 10 ........................................sub channel. 11.........................................channel b crossover low-pass output. 76543210 outputcfg1 outputcfg0 pwmdsel1 pwmdsel0 outputdly3 outputdly2 o utputdly1 outputdly0 outputcfg[1:0] setting power output configuration 00 ........................................channel 1 & 2 full-bridge. 01 ........................................channel 1 & 2 half-bridge + sub channel full-bridge. 10 ........................................channel 1 parallel full-bridge. 11.........................................reserved. pwmdsel setting pwm si gnal output mapping 00 ........................................pwm_sig1 output disabled. pwm_sig2 output disabled. 01 ........................................channel 1 output on pwm_sig1. channel 2 output on pwm_sig2. 10 ........................................channel 1 output on pwm_sig1. sub channel output on pwm_sig2. 11.........................................channel 2 output on pwm_sig1. sub channel output on pwm_sig2.
74 ds726pp1 CS4525 only be changed while all modulators and associated logic are in the power-down state (the pdnall bit is set). attempts to write these bits while t he pdnall bit is cleared will be ignored. see ?pwm channel delay? on page 55 for more information. 9.5 foldback and ramp configuration (address 05h) 9.5.1 select vp l evel (selectvp) default = 1 function: adjusts the pwm modulation index to maximize output power for applications with a nominal vp voltage of less than or equal to 14 v. this bit must remain set for applications with a nominal vp voltage greater than 14 v. 9.5.2 enable thermal foldback (entherm) default = 0 function: enables the thermal foldback feature. see ?thermal foldback? on page 40 for more information. 9.5.3 lock foldback adjust (lockadj) default = 0 function: controls the operation of the fold back lock adjustment feature. see ?thermal foldback? on page 40 for more information. outputdly[3:0] setting output delay in input clock source cycles 0000 .................................... 0 - no delay 0001 .................................... 1 0010 .................................... 2 .................................... 1000 .................................... 8 .................................... 1111 ... .................................. 15 - max delay 76543210 selectvp entherm lockadj attackdly1 attackdly0 enfloor rmpspeed1 rmpspeed0 selectvp setting selected vp level 0 .......................................... vp 14 volts 1 .......................................... vp > 14 volts. entherm setting thermal foldback state 0 .......................................... disabled. 1 .......................................... enabled. lockadj setting foldback adjustment lock state 0 .......................................... attenuation lock disabled. 1 .......................................... attenuation lock enabled.
ds726pp1 75 CS4525 9.5.4 foldback attack de lay (attackdly[1:0]) default = 01 function: controls the foldback attack delay. see ?thermal foldback? on page 40 for more information. 9.5.5 enable foldback floor (enfloor) default = 0 function: controls the foldback attenuation floor feature. see ?thermal foldback? on page 40 for more information. 9.5.6 ramp speed (rmpspd[1:0]) default = 11 function: controls the pwm output ramp speed. see ?pwm popguard transient control? on page 45 for more in- formation. 9.6 mixer / pre-scale c onfiguration (address 06h) 9.6.1 pre-scale attenua tion (prescale[2:0]) default = 000 function: controls the pre-scale attenuation level. see ?pre-scaler? on page 30 for more information. attackdly[1:0] setting foldback attack time 00 ........................................approximately 0.5 seconds. 01 ........................................approximately 1.0 seconds. 10 ........................................approximately 1.5 seconds. 11.........................................approximately 2.0 seconds. enfloor setting attenuation floor 0 ..........................................no foldback attenuation floor imposed. 1 ..........................................maximum foldback attenuation limited to -30 db. rmpspd[1:0] setting ramp speed 00 ........................................fastest ramp speed 10 ........................................slowest ramp speed 11.........................................immediate. pwm popguard disabled. 76543210 prescale2 prescale1 prescale0 reserved rchmix1 rchmix0 lchmix1 lchmix0 prescale[2:0] setting pre-scale attenuation setting 000 ......................................no pre-scale attenuation applied. 001 ......................................-2.0 db 010 ......................................-4.0 db ...................................... 100 ......................................-8.0 db ...................................... 111 .......................................-14.0 db
76 ds726pp1 CS4525 9.6.2 right channel mixer (rchmix[1:0]) default = 00 function: controls the right channel mixer output. see ?channel mixer? on page 30 for more information. 9.6.3 left channel mixer (lchmix[1:0]) default = 00 function: controls the left channel mixer output. see ?channel mixer? on page 30 for more information. 9.7 tone configuration (address 07h) 9.7.1 de-emphasis control (deemph) default = 0 function: controls the operation of the internal de-emphasis filter. see ?de-emphasis? on page 31 for more infor- mation. 9.7.2 adaptive loudness comp ensation control (loudness) default = 0 function: controls the operation of the adaptive loudness compensation feature. see ?adaptive loudness compen- sation? on page 34 for more information. rchmix[1:0] setting right channe l mixer output on channel b 00 ........................................ right channel 01 ........................................ (left channel + right channel) / 2 10 ........................................ (left channel + right channel) / 2 11......................................... left channel lchmix[1:0] setting left channel mixer output on channel a 00 ........................................ left channel 01 ........................................ (left channel + right channel) / 2 10 ........................................ (left channel + right channel) / 2 11......................................... right channel 76543210 deemph loudness endighpf trebfc1 trebfc0 bassfc1 bassfc0 entonectrl deemph setting de-emphasis state 0 .......................................... no de-emphasis applied. 1 .......................................... 44.1 khz 50/15 s de-emphasis filter applied. loudness setting adaptive loudness compensation state 0 .......................................... disabled. 1 .......................................... enabled.
ds726pp1 77 CS4525 9.7.3 digital signal processing high-pass filter (endighpf) default = 0 function: controls the operation of the digital si gnal processing high-pass filter. see ?digital signal processing high-pass filter? on page 30 for more information. 9.7.4 treble corner frequency (trebfc[1:0]) default = 00 function: sets the corner frequency for the treble shelving filter as shown below. 9.7.5 bass corner frequency (bassfc[1:0]) default = 01 function: sets the corner frequency for the bass shelving filter as shown below. 9.7.6 tone control enable (entonectrl) default = 0 function: when set, enables the bass and treble shelving filters. when cleared, disables the bass and treble shelv- ing filters. endighpf setting digital signal processing high-pass filter state 0 ..........................................digital signal processi ng high-pass filter disabled. 1 ..........................................digital signal proces sing high-pass filter enabled. trebfc[1:0] setting treble corner frequency 00 ........................................selects treble fc 0 - approximately 5 khz 01 ........................................selects treble fc 1 - approximately 7 khz 10 ........................................selects treble fc 2 - approximately 10 khz 11.........................................selects treble fc 3 - approximately 15 khz bassfc[1:0] setting bass corner frequency 00 ........................................selects bass fc 0 - approximately 50 hz 01 ........................................selects bass fc 1 - approximately 100 hz 10 ........................................selects bass fc 2 - approximately 200 hz 11.........................................selects bass fc 3 - approximately 250 hz entonectrl setting tone control filter state 0 ..........................................bass and treble s helving filters disabled. 1 ..........................................bass and treble shelving filters enabled.
78 ds726pp1 CS4525 9.8 tone control (address 08h) 9.8.1 treble gain level (treb[3:0]) default = 1000 function: sets the gain/attenuation level of the treble shelving filter.the level can be adjusted in 1.5 db steps from +12.0 to -10.5 db. 9.8.2 bass gain level (bass[3:0]) default = 1000 function: sets the gain/attenuation level of the bass shelving filter. the level can be adjusted in 1.5 db steps from +12.0 to -10.5 db. 9.9 2.1 bass manager/parametric eq control (address 09h) 9.9.1 freeze controls (freeze) default = 0 function: this function will freeze th e previous output of, and a llow modifications to be ma de to the master volume control (address 57h), channel x volume control (address 58h - 5ah), and bi-quad coefficient registers for channel a, and channel b (address 0ah - 54h) without the changes taking effect until the freeze bit is disabled. to make multiple changes in these control port registers take effect simultaneously, enable the freeze bit, make all register changes, then disable the freeze bit. 76543210 treble3 treble2 treble1 treble0 bass3 bass2 bass1 bass0 treb[3:0] setting treble shelving filter gain/attenuation 0000 .................................... +12 db 0001 .................................... +10.5 db ..................................... 1000 .................................... 0 db ..................................... 1110 ..................................... -9.0 db 1111 ... .................................. -10.5 db bass[3:0] setting bass shelving filter gain/attenuation 0000 .................................... +12 db 0001 .................................... +10.5 db ..................................... 1000 .................................... 0 db ..................................... 1110 ..................................... -9.0 db 1111 ... .................................. -10.5 db 76543210 freeze hizpsig bassmgr2 bassmgr1 bassmgr0 reserved enchbpeq enchapeq freeze setting register freeze state 0 .......................................... register freeze disabled. 1 .......................................... register freeze enabled.
ds726pp1 79 CS4525 9.9.2 hi-z pwm_sig outputs (hizpsig ) default = 0 function: when cleared, the pwm_sig1 and pwm_sig2 output drivers are placed in a high-impedance state. when set, the pwm_sig1 and pwm_sig2 output driv ers are active. it should be noted that the function of the pwm_sig outputs is determined by the pwmdsel[1:0] bits in register 04h. 9.9.3 bass cross-over frequency (bassmgr[2:0]) default = 000 function: controls the operation and cross-over frequency of the bass manager. see ?bass management? on page 35 for more information. 9.9.4 enable channel b pa rametric eq (enchbpeq) default = 0 function: enables the parametric eq bi-quad filters for channel b. 9.9.5 enable channel a pa rametric eq (enchapeq) default = 0 function: enables the parametric eq bi-quad filters for channel a. hizpsig setting pwm_sig output driver state 0 ..........................................high impedance. 1 ..........................................drivers active. bassmgr[2:0] setting bass manager crossover setting 000 ......................................bass manager disabled. 001 ......................................selects bass manager frequency 1 - approximately 80 hz 010 ......................................selects bass manager frequency 2 - approximately 120 hz 011.......................................selects bass manager frequency 3 - approximately 160 hz 100 ......................................selects bass manager frequency 4 - approximately 200 hz 101 ......................................selects bass manager frequency 5 - approximately 240 hz 110.......................................selects bass manager frequency 6 - approximately 280 hz 111 .......................................selects bass manager frequency 7 - approximately 320 hz enchbpeq setting channel b parametric eq state 0 ..........................................disabled. 1 ..........................................enabled. enchapeq setting channel a parametric eq state 0 ..........................................disabled. 1 ..........................................enabled.
80 ds726pp1 CS4525 9.10 volume and 2-way cross-o ver configuratio n (address 55h) 9.10.1 soft ramp and zero cr oss control (szcmode[1:0]) default = 10 function: sets the soft ramp and zero cro ssing detection modes by which volu me and muting changes will be im- plemented. 9.10.2 enable 50% duty cycle for mute condition (mute50/50) default = 0 function: when set, the amplifiers will output a non-modulated 50%-duty-cycle signal for all mute conditions. this bit does not cause a mute condition to occur. the mute50/50 bit only defines operation during a normal mute condition. 9.10.3 auto-mute (automute) default = 1 function: when enabled, the outputs of t he CS4525 will mute following the rece ption of 8192 c onsecutive audio samples of static 0 or -1. a single sample of non- static data will release the mute. detection and muting is done independently for each channel. see ?volume and muting control? on page 36 for more informa- tion. 76543210 szcmode1 szcmode0 mute50/50 automute e n2way 2wayfreq2 2wayfreq1 2wayfreq0 szcmode[1:0] setting soft ramp & zero crossing mode 00 ........................................ immediate change when immediate change is selected, all level c hanges will take effect immediately in one step. 01 ........................................ zero cross zero cross dictates that signal level changes, both muting and att enuation, will oc cur on a signal zero crossing to minimize audibl e artifacts. the requested level change will occur after a timeout period (approximately 18.7 ms for a pwm switch rate of 384/768 khz and 17.0 ms for a pwm switch rate of 421.875/843.75 khz) if the signal does not encounter a zero crossing. the zero cross function is independently monitor ed and implemented for each channel. 10 ........................................ soft ramp soft ramp allows level changes, both muting and attenuation, to be impl emented by incrementally ramping, in ? db steps, from the current level to the new level at a rate of ? db per 4 sample peri- ods for 32, 44.1, and 48 khz, and ? db per 8 sample periods for 96 khz. 11......................................... soft ramp on zero cross soft ramp on zero cross dictates that signal leve l changes, both muting and att enuation, will occur in ? db steps and be implemented on a signal zero cros sing. the ? db level change will occur after a timeout period (approximately 18.7 ms for a pwm switch rate of 384/768 khz and 17.0 ms for a pwm switch rate of 421.875/843.75 khz) if the si gnal does not encounter a zero crossing. the zero cross function is independently monitor ed and implemented for each channel. mute50/50 setting 50% duty cycle mute state 0 .......................................... 50% duty cycle for mute conditions disabled. 1 .......................................... 50% duty cycle for mute conditions enabled. automute setting automute state 0 .......................................... auto-mute on static 0?s or -1?s disabled. 1 .......................................... auto-mute on static 0?s or -1?s enabled.
ds726pp1 81 CS4525 9.10.4 enable 2-way crossover (en2way) default = 0 function: enables the 2-way crossover filters for channel 1 and channel 2. 9.10.5 2-way cross-over fr equency (2wayfreq[2:0]) default = 000 function: selects the cross-over frequency for the 2-way linkwitz-riley filters. 9.11 channel a & b: 2-way se nsitivity control (address 56h) 9.11.1 channel a and channel b low-pass sensitivity adjust (lowpass[3:0]) default = 0000 function: controls the 2-way cro ss-over low-pass sensit ivity adjustment. see ?2-way crossover & sensitivity con- trol? on page 41 for more information. en2way setting 2-way crossover state 0 ..........................................2-way crossover disabled. 1 ..........................................2-way crossover enabled. 2wayfreq setting 2-way crossover frequency 000 ......................................selects x-over freq 0 - approximately 2.0 khz 001 ......................................selects x-over freq 1 - approximately 2.2 khz 010 ......................................selects x-over freq 2 - approximately 2.4 khz 011.......................................selects x-over freq 3 - approximately 2.6 khz 100 ......................................selects x-over freq 4 - approximately 2.8 khz 101 ......................................selects x-over freq 5 - approximately 3.0 khz 110.......................................selects x-over freq 6 - approximately 3.2 khz 111 .......................................selects x-over freq 7 - approximately 3.4 khz 76543210 lowpass3 lowpass2 lowpass1 lowpass0 highpass3 highpass2 highpass1 highpass0 lowpass[3:0] setting sensitivity compensation level 0000 ....................................0.0 db 0001 ....................................-0.5 db 0010 ....................................-1.0 db ..................................... 1000 ....................................-4.0 db ..................................... 1110 .....................................-7.0 db 1111 .....................................-7.5 db
82 ds726pp1 CS4525 9.11.2 channel a and channel b high-pa ss sensitivity adjust (highpass[3:0]) default = 0000 function: controls the 2-way cross-over high -pass sensitivity adjustment. see ?2-way crossover & sensitivity con- trol? on page 41 for more information. 9.12 master volume control (address 57h) 9.12.1 master volume control (mvol[7:0]) default = 2ah function: sets the gain/attenuation level of the master volume control. see ?volume and muting control? on page 36 for more information. highpass[3:0] setting sensitivity compensation level 0000 .................................... 0.0 db 0001 .................................... -0.5 db 0010 .................................... -1.0 db ..................................... 1000 .................................... -4.0 db ..................................... 1110 ..................................... -7.0 db 1111 ... .................................. -7.5 db 76543210 mvol7 mvol6 mvol5 mvol4 mvol3 mvol2 mvol1 mvol0 mvol[7:0] setting master volume setting 0000 0000 ........................... +24 db ............................ 0010 1010 ........................... +3 db ............................ 0011 0000............................ 0.0 db 0011 0001............................ -0.5 db 0011 0010............................ -1.0 db ............................ 1111 1110 ............................. -103.0 db 1111 1111 ............................. master mute
ds726pp1 83 CS4525 9.13 channel a and b volume control (address 58h & 59h) 9.13.1 channel x volume control (chxvol[7:0]) default = 30h function: sets the gain/attenuation levels of channel a and channel b. see ?volume and muting control? on page 36 for more information. 9.14 sub channel volume control (address 5ah) 9.14.1 sub channel volume control (subvol[7:0]) default = 30h function: sets the gain/attenuation levels of the sub channel. see ?volume and muting control? on page 36 for more information. 76543210 chxvol7 chxvol6 chxvol5 chxvol4 chxvol3 chxvol2 chxvol1 chxvol0 chxvol[7:0] setting chann el x volume setting 0000 0000 ...........................+24 db ............................ 0011 0000............................0.0 db 0011 0001............................-0.5 db 0011 0010............................-1.0 db ............................ 1111 1110.............................-103.0 db 1111 1111 .............................channel mute 76543210 subvol7 subvol6 subvol5 subvol4 subvol3 subvol2 subvol1 subvol0 subvol[7:0] setting sub channel volume setting 0000 0000 ...........................+24 db ............................ 0011 0000............................0.0 db 0011 0001............................-0.5 db 0011 0010............................-1.0 db ............................ 1111 1110.............................-103.0 db 1111 1111 .............................channel mute
84 ds726pp1 CS4525 9.15 mute/invert co ntrol (address 5bh) 9.15.1 adc invert signal polarity (invadc) default = 0 function: when set, the signal polarity of the adc will be inverted. 9.15.2 invert channel pwm si gnal polarity (invchx) default = 0 function: when set, the respective channel?s power and logic-level pwm output signal polarity will be inverted. the serial output on the auxiliary and delay ports are unaffected. 9.15.3 invert sub pwm sign al polarity (invsub) default = 0 function: when set, the sub channel?s power and logic-level pwm output polarity w ill be inverted. the serial output on the auxiliary port is unaffected. 9.15.4 adc channel mute (muteadc) default = 0 function: the output of the adc will mute when enabled. 9.15.5 independent channel a & b mute (mutechx) default = 0 function: the respective channel?s power pwm, logic-level pwm, and auxiliary se rial data outputs will enter a mute state when enabled. the delay serial output will be unaffected if the delay port is enabled. the muting 76543210 invadc invsub invch2 invch1 muteadc mutesub mutechb mutecha invadc setting adc signal inversion state 0 .......................................... adc signal polarity not inverted. 1 .......................................... adc signal polarity inverted. invchx setting channel x pwm signal inversion state 0 .......................................... channel x pwm signal polarity not inverted. 1 .......................................... channel x pwm signal polarity inverted. invsub setting sub channel pwm signal inversion state 0 .......................................... sub channel pwm signal polarity not inverted. 1 .......................................... sub channel pwm signal polarity inverted. muteadc setting adc mute state 0 .......................................... adc un-muted. 1 .......................................... adc muted.
ds726pp1 85 CS4525 function is affected, similar to attenuation changes, by the soft and zero cross bits (szcmode[1:0]). see ?volume and muting control? on page 36 for more information. 9.15.6 sub channel mute (mutesub) default = 0 function: the sub channel?s power pwm, logic-level pwm, and au xiliary serial data outp uts will enter a mute state when enabled. the muting function is affected, simila r to attenuation changes, by the soft and zero cross bits (szcmode[1:0]). see ?volume and muting control? on page 36 for more information. 9.16 limiter configurat ion 1 (address 5ch) 9.16.1 maximum threshold (max[2:0]) default = 000 function: sets the maximum level, be low full scale, at which to limit and attenuate the output signal at the limiter attack rate. 9.16.2 minimum threshold (min[2:0]) default = 000 function: sets a minimum level below full scale at which the limiter will begin to release its applied attenuation. mutechx setting channel x pwm mute state 0 ..........................................channel x pwm outputs un-muted. 1 ..........................................channel x pwm outputs muted. mutesub setting sub channel pwm mute state 0 ..........................................sub channel pwm outputs un-muted. 1 ..........................................sub channel pwm outputs muted. 76543210 max2 max1 max0 min2 min1 min0 limitall enlimiter max[2:0] setting maximum threshold setting 000 ......................................0.0 db 001 ......................................-3.0 db 010 ......................................-6.0 db 011.......................................-9.0 db 100 ......................................-12.0 db 101 ......................................-18.0 db 110.......................................-24.0 db 111 .......................................-30.0 db min[2:0] setting minim um threshold setting 000 ......................................0.0 db 001 ......................................-3.0 db 010 ......................................-6.0 db 011.......................................-9.0 db 100 ......................................-12.0 db 101 ......................................-18.0 db 110.......................................-24.0 db 111 .......................................-30.0 db
86 ds726pp1 CS4525 9.16.3 peak signal limit a ll channels (limitall) default = 1 function: when cleared, th e peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clippi ng. the other chann els will not be affected. wh en set, the peak signal limiter will limit the maximum signal am plitude to prevent clip ping on all channels in response to any single channel indicating clipping. see ?peak signal limiter? on page 37 for more information. 9.16.4 peak detect and limi ter enable (enlimiter) default = 0 function: limits the maximum signal amplitude to prevent clipping when this func tion is enabled. peak signal limit- ing is performed by digital attenuation. limitall setting limit all channels configuration 0 .......................................... only individual channels affected by any limiter event. 1 .......................................... all channels affected by any limiter event. enlimiter setting peak signal limiter state 0 .......................................... peak signal limiter disabled. 1 .......................................... peak signal limiter enabled.
ds726pp1 87 CS4525 9.17 limiter configurat ion 2 (address 5dh) 9.17.1 limiter release rate (rrate[5:0]) default = 111111 function: sets the rate at which the limiter releases the digi tal attenuation from levels below the minimum setting in the limiter threshold register. the limiter release rate is a function of the sampling frequency, fs, and the soft and zero cross setting. 9.18 limiter configurat ion 3 (address 5eh) 9.18.1 enable thermal limiter (enthlim) default = 0 function: when set, enables the thermal limiter function. the ther mal limiter function adds an additional -3db of at- tenuation to the min and max settings of the peak sig nal limiter the first time a thermal warning is detected after the thermal limiter function has been enabled. for more details, see the ?thermal limiter? section on page 39 . 9.18.2 limiter attack rate (arate[5:0]) default = 000000 function: sets the rate at which the limiter attenuates the ana log output from levels above the maximum setting in the limiter threshold register. the lim iter attack rate is a function of the sampling frequency, fs, and the soft and zero cross setting. 76543210 reserved reserved rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 rrate[5:0] setting limiter release rate 000000 ................................fastest release. ................................... 111111 ..................................slowest release. 76543210 enthlim reserved arate5 arate4 arate3 arate2 arate1 arate0 enthlim setting thermal limiter state 0 ..........................................thermal limiter disabled. 1 ..........................................thermal limiter enabled. arate[5:0] setting limiter attack rate 00000 ..................................fastest attack. ................................... 11111....................................slowest attack.
88 ds726pp1 CS4525 9.19 power control (address 5fh) 9.19.1 automatic power st age retry (autoretry) default = 1 function: enables the auto-retry function upon over-current error. see ?automatic power stage shut-down? on page 53 . 9.19.2 select vd level (selectvd) default = 1 function: this bit selects between a vd of 2.5 v, 3.3 v, or 5.0 v. 9.19.3 power down adc (pdnadc) default = 1 function: the adc will enter a power down st ate when this bit is enabled. 9.19.4 power down pwm power output x (pdnoutx) default = 1 function: when set, the specific pwm power output will enter a power-down state. only the output powe r stage is powered down. the pwm modulator is not affected, nor is the setup or delay register values. when set to normal operation, the specific ou tput will power up according to the state of the rmpspd[1:0] bits and the channel output configuration selected. when tran sitioning from normal operation to power down, the specific output will power down acco rding to the state of the rmpspd[1 :0] bits and the channel output con- figuration selected. the entire divide will enter a low-power st ate when this func tion is enabled: 76543210 autoretry reserved selectvd pdnadc pdnout3/4 pdnout2 pdnout1 pdnall autoretry setting auto-retry state 0 .......................................... auto-retry feature disabled. 1 .......................................... auto-retry feature enabled. selectvd setting selected vd level 0 .......................................... vd = 2.5 v. 1 .......................................... vd = 3.3 v or 5.0 v. pdnadc setting adc power-down state 0 .......................................... normal adc operation. 1 .......................................... adc power-down enabled. pdnchx setting power output x power-down state 0 .......................................... normal power output x operation. 1 .......................................... power output x power-down enabled.
ds726pp1 89 CS4525 9.19.5 power down (pdnall) default = 1 function: the CS4525 will enter a power-down state when this function is enabled: 1. the power pwm outputs will be he ld in a high-impedance state. 2. the logic-level pwm outputs will contin uously drive a logic ?0? if the hizpsig bit is set and will be held in a high-impedance state if the hizpsig bit is clear. 3. aux_sdout, the auxiliary serial data output, will be driven to a digital-low. aux_lrck and aux_sclk, the auxiliary serial output?s clocks, will co ntinue to operat e if the enauxport bit is set, adc/sp is cleared, and the serial audio input receives a valid sc lk and lrck; otherwise they will also be driven to a digital-low voltage. 4. dly_sdout, the delay serial data output, will output the unprocessed audio data from sdata if enauxport is set, dlyportcfg[1:0] is configured for serial output delay interface, adc/sp is cleared, and the serial audio input port receives a valid sclk, lrck, and sdata. otherwise, it will drive a low voltage. the contents of the control registers are retained in this state. once the pdnall bit is disabled, the pow- ered and logic-level pwm ou tputs will first perform a click-free star t-up function and then re sume normal operation. the pdnall bit defaults to ?enabled? on power-up and mu st be disabled before normal operation can occur. 9.20 interrupt (address 60h) bits [7:4] in this register are read only. a ?1?b in thes e bit positions indicates that the associated condition has oc- curred at least once since the register was last read. a ?0 ?b indicates that the associated condition has not occurred since the last reading of the register. reading the register resets bits to [7:4] ?0?b. these bits are considered ?edge- triggered? events. the operation of thes e 4 bits is not affected by the interr upt mask bits and the condition of each bit can be polled instead of generating an interrupt as required. 9.20.1 src lock state transition interrupt (srclock) function: this bit is read only. when set, indicates that the src has transitioned from an unlock to lock state or from a lock state to an unlock state since the last re ad of this register. conditions which cause the src to transition states, such as loss of lrck, sclk, an lrck ratio change, or the src achieving lock, will cause this bit to be set. this in terrupt bit is an edge-triggered event and will be cleared following a read of this register. if this bit is set, indicating a src state change condit ion, and the srclockm bit is set, the int pin will go active. to determine the current lock state of the src, read the srclockst bit in the interrupt status reg- ister. pdnall setting device power-down state 0 ..........................................normal device operation. 1 ..........................................device power-down enabled. 7 6 5 4 3210 srclock adcovfl chovfl amperr srcstatem adcovflm chovflm amperrm srclock setting src lock state change status 0 ..........................................src lock state unchanged since last read of this register. 1 ..........................................src lock state changed since last read of this register.
90 ds726pp1 CS4525 9.20.2 adc overflow interrupt (adcovfl) function: this bit is read only. when set, indicates that an over-range condition occurred anywhere in the CS4525 adc signal path and has been clipped to positive or ne gative full scale as appropriate since the last read of this register. this in terrupt bit is an edg e-triggered event a nd will be cleared following a read of this register. if this bit is set, indicating an adc over-range condition, and the adco vflm bit is set, the int pin will go active. to determine the current overflow state of the adc, read the adcovflst bit in the interrupt status register. 9.20.3 channel overflow interrupt (chovfl) function: this bit is read only. when set, indicates that the m agnitude of an output sample on channel 1, 2, or the sub channel has exceeded full scale and has been clipped to positive or negative full scale as appropriate since the last read of this register. this interrupt bit is an edge-triggered event and will be cleared following a read of this register. if this bit is set, indicating a channel over-range conditio n, and the chovflm bit is set, the int pin will go active. to determine the current ov erflow state of each channel, re ad the chxovflst and subovflst bits in the interrupt status register. 9.20.4 amplifier error in terrupt bit (amperr) function: this bit is read only. when set, indicates that an erro r was detected in the power amplifier section since the last read of this register. this interrupt bit is an edge-triggered event an d will be cleared following a read of this register. this bit is the logical or of all the bits in the amplifier error status register. read the amplifier error status register to determine which condition occurred. if this bit is set, indicating an am plifier stage error condition, and the amperrm bit is set to a ?1?b, the int pin will go active. to determine the actual current state of the amplifier error conditi on, read the amplifier error status register. 9.20.5 mask for src state (srclockm) default = 0 function: this bit serves as a mask for the src status interrup t source. if this bit is set, the srclock interrupt is unmasked, meaning that if the srcl ock bit is set, the int pin will go active. if the srclockm bit is adcovfl setting adc overflow event status 0 .......................................... adc overflow condition has not oc curred since last read of this register. 1 .......................................... adc overflow condition has occu rred since last read of this register. chovfl setting channel overflow event status 0 .......................................... a channel overflow condition has not oc curred since last read of this register. 1 .......................................... a channel overflow condition has oc curred since last read of this register. amperr setting amplifier error event status 0 .......................................... an amplifier error condition has not oc curred since last read of this register. 1 .......................................... an amplifier error condition has occu rred since last read of this register.
ds726pp1 91 CS4525 cleared, the srclock condit ion is masked, meaning that its occurr ence will not affect the int pin. how- ever, the srclock and srclockst bits will contin ue to reflect the lock status of the src. 9.20.6 mask for adc overflow (adcovflm) default = 0 function: this bit serves as a mask for the adc overflow interr upt source. if this bit is set, the adcovfl interrupt is unmasked, meaning that if the adcovfl bit is set, the int pin will go active. if the adcovflm bit is cleared, the adcovfl condition is masked, m eaning that its occurrence will not a ffect the int pin. however, the adcovfl and adcovflst bits will continue to reflect the overflow state of the adc. 9.20.7 mask for channel x a nd sub overflow (chovflm) default = 0 function: this bit serves as a mask for the channel 1, 2, and sub overflow interrupt source. if this bit is set, the cho- vfl interrupt is unmasked, meaning that if the chovfl bit is set, the int pin will go active. if the chovflm bit is cleared, the chovfl c ondition is masked, meaning that its occu rrence will not affect the int pin. how- ever, the chovfl, chxovflst, and subo vflst bits will continue to reflect th e overflow state of the individual channels. 9.20.8 mask for amplif ier error (amperrm) default = 0 function: this bit serves as a mask for the amp lifier error interrupt sour ces. if this bit is set, the amperr interrupt is unmasked, meaning that if the amperr bit is set, the int pin will go acti ve. if the amperrm bit is cleared, the amperr condition is ma sked, meaning that its occurrence will no t affect the int pin. however, the am- perr and the amplifier er ror bits in the amplifier erro r status register will continue to reflect the status of the amplifier error conditions. srclockm setting srclock int pin mask state 0 ..........................................srclock condition masked. 1 ..........................................srclock condition un-masked. adcovflm setting adcovfl int pin mask state 0 ..........................................adcovfl condition masked. 1 ..........................................adcovfl condition un-masked. chovflm setting chovfl int pin mask state 0 ..........................................chovfl condition masked. 1 ..........................................chovfl condition un-masked. amperrm setting amperr int pin mask state 0 ..........................................amperr condition masked. 1 ..........................................amperr condition un-masked.
92 ds726pp1 CS4525 9.21 interrupt status (address 61h) - read only all bits in this register are consider ed ?level-triggered? events, meaning as long as a condition continues, the corre- sponding bit will remain set. these status bits are not affected by the interrupt mask bit and the condition of each bit can be polled. these bits will not be cl eared following a read to this register, nor can t hey be written to cause an interrupt condition. 9.21.1 src state tran sition (srclockst) function: this bit is read only and reflects the current lock st ate of the src. when set, indicates the src is currently locked. when cleared, indicates the src is currently unlocked. 9.21.2 adc overflow (adcovflst) function: this bit is read only and will identify the presence of an overflow condition wit hin the adc. when set, in- dicates that an over-range condition is currently occurring in the CS4525 adc signal path and has been clipped to positive or negative full scale. 9.21.3 sub overflow (subovflst) function: this bit is read only and will identif y the presence of an overflow condi tion anywhere in the sub channel?s signal path. when set, indicates that an over-range condition is currently occurring in the sub channel?s signal path and has been clipped to positive or negative full scale. 9.21.4 channel x overflow (chxovflst) function: these bits are read only and will iden tify the presence of an overflow condition anywhere in the associated channel?s signal path. when set, indicates that an over -range condition is currently occurring in the chan- nel?s signal path and has been clipped to positive or negative full scale. 76 5 4 3210 srclockst adcovflst subovflst ch2ovflst ch1ovflst rampdone reserved reserved srclockst setting src lock state 0 .......................................... src is currently unlocked. 1 .......................................... src is currently locked. adcovflst setting adc overflow state 0 .......................................... an adc overflow conditi on is not currently present. 1 .......................................... an adc overflow condi tion is currently present. subovflst setting sub overflow state 0 .......................................... an overflow condition is not currently present on the sub channel. 1 .......................................... an overflow condition is currently present on the sub channel. chxovflst setting channel x overflow state 0 .......................................... an overflow condition is not currently present on channel x. 1 .......................................... an overflow condition is currently present on channel x.
ds726pp1 93 CS4525 9.21.5 ramp-up cycle complete (rampdone) function: when set, indicates that all active channels have completed the configured ramp-up interval. 9.22 amplifier error status (address 62h) - read only all bits in this register are considered ?level-triggered? events, meaning as lo ng as a condition continues, the corre- sponding bit will remain set. these status bits are not affected by the interrupt mask bit and the condition of each bit can be polled. these bits will not be cl eared following a read to th is register, nor can they be writ ten to cause an interrupt condition. 9.22.1 over-current detected on channel x (overcurrx) function: when set, indicates an over current condition is currently present on the corresponding amplifier output. 9.22.2 external amplifier state (extampst) function: when set, indicates a thermal warnin g condition is currently being reported by an external amplifier. for proper operation, the delay serial port must be configured to support an external thermal warning input signal. this status bit reflects the active stat e of the external thermal warning input signal. 9.22.3 under voltage / thermal error state (uvte[1:0]) function: indicates the operational status of the amplifier. these bits can identify a thermal warning condition, a thermal error condition, or an under voltage conditio n. the thresholds for each of these conditions is listed in the pwm power output characteristics table on page 20 . rampdone setting ramp completion state 0 ..........................................ramp-up interval not completed on all channels. 1 ..........................................ramp-up interval completed on all channels. 76543210 overcurr4 overcurr3 overcurr2 overcurr1 extamperr reserved uvte1 uvte0 overcurrx setting amplifie r over-current status 0 ..........................................an over current condition is not currently present on amplifier output x. 1 ..........................................an over current condition is currently present on amplifier output x. extampst setting external amplifier status 0 ..........................................a thermal warning condition is not cu rrently being reported by an external amplifier . 1 ..........................................a thermal warning condition is current ly being reported by an external amplifier. uvte[1:0] setting under voltage & thermal error status 00 ........................................the device is operating normally. 01 ........................................the device is operating normally; howeve r a thermal warning c ondition is being report ed. 10 ........................................an under voltage condition is currently present. 11.........................................a thermal error condition is currently present.
94 ds726pp1 CS4525 9.23 device i.d. and revi sion (address 63h) - read only 9.23.1 device identifi cation (deviceid[4:0]) default =11111 function: identification code for the CS4525. 9.23.2 device revision (revid[2:0]) function: identifies the CS4525 device revision. 76543210 deviceid4 deviceid3 deviceid2 devic eid1 deviceid0 revid2 revid1 revid0 deviceid[4:0] setting device id notes 11111.. .................................. permanent device identification code. revid[2:0] setting device revision 000 ...................................... revision a0 and b0. 010 ...................................... revision c0.
ds726pp1 95 CS4525 10.parameter definitions dynamic range (dyr) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth, typically 20 hz to 20 khz. dynamic range is a signal-to-noise ratio measurement over the spec- ified band width made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this meas urement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. ex- pressed in decibels. total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured as suggested in aes17-1991 annex a. frequency response fr is the deviation in signal level verses frequen cy. the 0 db reference point is 1 khz. the amplitude cor- ner, ac, lists the maximum deviation in amplitude abo ve and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maxi- mum frequency inclusive. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with no signal to the input under test and a full-sc ale signal applied to the ot her channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain drift the change in gain value with temperature. units in ppm/c. f s sampling frequency. resolution the number of bits in a serial audio data word. src sample rate converter. converts data derived at one sample rate to a differing sample rate. 11.references 1. cirrus logic, ? an18: layout and design rules for data converters and other mixed signal devices ,? version 6.0, february 1998. 2. cirrus logic, ? an22: overview of digital au dio interface data structures , version 2.0 ?, february 1998.; a useful tutorial on digital audio specifications. 3. philips semiconductor, ? the i2c-bus specification: version 2 ,? dec. 1998. http://www.semicondu ctors.philips.com
96 ds726pp1 CS4525 12.package dimensions notes: 1. dimensioning and tolerance per asme y4.5m - 1994. 2. dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. inches millimeters note dim min nom max min nom max a----0.0354----0.901 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1,2 d 0.3543 bsc 9.00 bsc 1 d2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1 e 0.3543 bsc 9.00 bsc 1 e2 0.2618 0.2677 0.2736 6.65 6.80 6.95 1 e 0.0256 bsc 0.65 bsc 1 l 0.0177 0.0217 0.0276 0.45 0.55 0.70 1 jedec #: mo-220 controlling dimension is millimeters. table 22: side view a1 bottom view top view a pin #1 id d e d2 l b e pin #1 id e2 48l qfn (9 9 mm body) package drawing
ds726pp1 97 CS4525 13.thermal characteristics 13.1 thermal flag this device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the pcb. to enhance the thermal dissipatio n capabilities of the system, th is metal plane should be cou- pled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the pcb. in either case, it is beneficial to use copper fill in any unused regions inside the pcb layout, especially those immediately surrounding the CS4525. in addition to impr oving in electrical perform ance, this practice also aids in heat dissipation. the heat dissipation capability require d of the metal plane for a given output power can be calculated as follows: ca = [(t j(max) - t a ) / p d ] - jc where, ca = thermal resistance of the metal plane in c/watt t j(max) = maximum rated operating junction temperature in c, equal to 150 c t a = ambient temperature in c p d = rms power dissipation of the device, equal to 0.15*p rms (assuming 85% efficiency) jc = junction-to-case thermal resi stance of the device in c/watt 14.ordering information parameter symbol min typ max units junction to case thermal impedance jc -1 -c/watt product description package pb-free grade temp range container order# CS4525 digital audio amp with integrated adc 48-qfn yes commercial -10 to +70c rail CS4525-cnz tape and reel CS4525-cnzr crd4525-q1 4 layer / 1oz. copper reference design board - - - - - crd4525-q1 crd4525-d1 2 layer / 1oz. copper reference design board - - - - - crd4525-d1
98 ds726pp1 CS4525 15.revision history release changes a1 initial release a2 incorporates functional updates a3 the following items were updated: figure 1. typical connection diagram - software mode on page 13 figure 2. typical connection diagram - hardware mode on page 14 section 6.1.1.1 ? sys_clk input clock mode? on page 26 section 6.1.1.2 ?crystal oscillator mode? on page 27 section 6.1.7.2 ?pwm popguard transient control? on page 45 table 12, ?output of pwm_ sig outputs,? on page 52 pp1 the following items were updated: ?analog input characteristics? on page 19 ?pwm power output characteristics? on page 20 ?xti switching specif ications? on page 23 ?sys_clk switching specifications? on page 23 ?digital interface specifications? on page 25 section 6.4.1 ?half-bridge output filter? on page 59 section 6.4.2 ?full-bridge output filter (stereo or parallel)? on page 60 table 21, ?power supply configuration and settings,? on page 63 section 9.19.2 ?select vd level (selectvd)? on page 88 contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its sub- sidiaries (?cirrus?) believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnif ication, and limitation of liability. no responsibility is assu med by cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or ot her rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other cr itical applications. inclusion of cirrus pr oducts in such applic ations is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, directors, em ployees, distribu tors and other agents from any and all liability, including attorneys? fees an d costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor.

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