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1 ? fn6026.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2002-2004. all rights reserved. all other trademarks mentioned are the property of their respective owners. ISL5585 3.3v ringing slic family for voice over broadband (vob) the 3.3v family of ringing sub scriber line interface circuits (slic) supports analog plain old telephone service (pots) in short and medium loop length, wireless and wireline voice over broadband applications. ideally suited for customer premise equipment, this family of products offers flexibility to designers with high ringing voltage and low power consumption syst em requirements. the ISL5585 family is capable of operating with 100v ringing battery supply, which translates directly to the amount of ringing voltage supplied to the subscriber. with the high operating voltage, subscriber loop lengths can be extended to 500 ? (i.e., 5,000 feet) and beyond, allowing this family to serve emerging fiber in the loop (fitl) markets. other key features across the product family include: 3.3v v cc operation, low power consumption, ringing using sinusoidal or trapezoidal waveforms, robust auto-detection mechanisms for when subscribers go on or off hook, and minimal external discret e application components. integrated test access features are also offered on selected products to support loopback testing as well as line measurement tests. there are ten product offeri ngs of the ISL5585 providing various grades of ringing battery voltage and longitudinal balance. block diagram features ? 3.3v operation ? onboard ringing generation ? low standby power consumption (75v, 65mw) ? programmable transient current limit ? improved off hook software interface ? integrated mtu dc characteristics ? low external component count ? silent polarity reversal ? pulse metering and on hook transmission ? tip open ground start operation ? balanced and unbalanced ringing ? thermal shutdown with alarm indicator ? 28 lead surface mount packaging ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available applications ? short loop access platforms ? voice over internet protocol (voip) ? voice over cable and dsl modems ? internet protocol pbx ? fiberto the home (ftth) ? remote subscriber units ? ethernet terminal adapters related literature ? an1038, user?s guide for development board ? an9824, modeling of the ac loop ? tb379 thermal characterization of packages for ics ? an9922, thermal characterization and modeling of the rslic18 in the micro leadframe package vrs aux vtx -in vfb f2 f1 f0 ilim sw- rt det alm 2-wire port pol cdc vbh vbl bsel swc transient current limit sw+ tip ring tl sh e0 battery switch ringing port 4-wire port test access transmit sensing control logic detector logic dc control data sheet july 2004
2 ordering information part number high battery (vbh) longitudinal balance full test temp. range c package pkg. dwg. # 100v 85v 75v 58db 53db ISL5585aim ??? -40 to 85 28 ld plcc n28.45 ISL5585bim ?? ? -40 to 85 28 ld plcc n28.45 ISL5585cim ??? -40 to 85 28 ld plcc n28.45 ISL5585dim ??? -40 to 85 28 ld plcc n28.45 ISL5585ecm ?? 0 to 75 28 ld plcc n28.45 ISL5585ecr ?? 0 to 75 32 pad qfn l32.7x7 * ISL5585ecrz (note) ?? 0 to 75 32 pad qfn (pb-free) l32.7x7 * ISL5585fcm ??? 0 to 85 28 ld plcc n28.45 ISL5585fcr ??? 0 to 85 32 pad qfn l32.7x7 * ISL5585fcrz (note) ??? 0 to 85 32 pad qfn (pb-free) l32.7x7 * ISL5585gcm ??? 0 to 85 28 ld plcc n28.45 ISL5585gcr ??? 0 to 85 32 pad qfn l32.7x7 * ISL5585gcrz (note) ??? 0 to 85 32 pad qfn (pb-free) l32.7x7 * ISL5585 xxx evaluation board pl atform, including codec. also available in tape and reel * reference ?special considerations for the qfn package? text. note: intersil pb-free products employ special pb -free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free solder ing operations. intersil pb-free products are msl classified at pb -free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. device operating modes mode f2 f1 f0 e0 = 1 e0 = 0 ISL5585a ISL5585b ISL5585c ISL5585d ISL5585e ISL5585f ISL5585g low power standby 0 0 0 shd gkd ??????? forward active 0 0 1 shd gkd ??????? unbalanced ringing 0 1 0 rtd rtd ? reverse active 0 1 1 shd gkd ??????? ringing 1 0 0 rtd rtd ??????? forward loop back 1 0 1 shd gkd ???? ?? tip open 1 1 0 shd gkd ???? ?? power denial 1 1 1 n/a n/a ??????? ISL5585
3 pinouts ISL5585 (plcc) top view ISL5585 qfn top view ring ilim rt cdc aux vrs pol tl bsel sh -in vfb v cc vtx bgnd tip sw- e0 det alm agnd sw+ v bl v bh swc f2 f1 f0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 19 20 21 22 23 24 25 26 27 28 v bh v bl bgnd tip nc ring scc sh det alm agnd bsel tl pol vrs nc sw+ sw- swc f2 f1 f0 e0 nc ilim rt cdc vcc -in vfb vtx aux 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910111213141516 pin description plcc qfn symbol description 1 29 tip tip power amplifier output. 2 30 bgnd battery ground - to be connected to zero potential. all l oop current and longitudinal current flow from this ground. internally separate from agnd. this ground must be connected to the same potential as agnd. 3 31 vbl low battery supply connection. 4 32 vbh high battery supply connection for the most negative battery. 5 1 sw+ uncommitted switch positive terminal. 6 2 sw- uncommitted switch negative terminal. 7 3 swc switch control input. this ttl compatible input controls the uncommitted switch, with a logic ?0? enabling the switch and logic ?1? disabling the switch. 8 4 f2 mode control input - msb. f2-f0 for the ttl compatible par allel control interface for cont rolling the various modes of operation of the device. 9 5 f1 mode control input. 10 6 f0 mode control input. 11 7 e0 detector output selection input. this ttl input contro ls the multiplexing of the shd (e0 = 1) and gkd (e0 = 0) comparator outputs to the det output based upon the state at the f2-f0 pins (see the de vice operating modes table shown on page 2). 12 9 det detector output - this ttl output provides on-hook /off-hook status of the loop based upon the selected operating mode. the detected output will either be switch hook, grou nd key or ring trip (see the device operating modes table shown on page 2). det will be latched low following a ring trip. unlatching the det pin is accomplished by changing logic state. 13 10 alm thermal shutdown alarm. this pin signals the internal die temperature has exceeded safe operating temperature (approximately 175c) and the device has been powered down automatically. 14 11 agnd analog ground reference. this pi n should be externally connected to bgnd. 15 12 bsel selects between high and low battery, with a logic ?1? selecting the high battery and logic ?0? the low battery. ISL5585
4 16 13 tl programming pin for the transient current limi t feature, set by an external resistor to ground. 17 14 pol external capacitor on this pi n sets the polarity reversal time. 18 15 vrs ringing signal input - analog input for driving 2-wire interface while in ring mode. 19 17 aux auxiliary input - float if not used. 20 18 vtx transmit output voltage - output of impedance matching amplifier, ac couples through a resistor to codec. 21 19 vfb feedback voltage for impedance matching. this voltage is scaled to accomplish impedance matching. the cfb capacitor connects between this pin and the -in pin. t he cfb cap needs to be non-polarized for proper device operation in the reverse active mode. ceramic surfac e mount capacitors (1206 body st yle) are available from panasonic with a 6.3v voltage rating. these can be used for cfb since it is internally li mited to approximately 3v. 22 20 -in analog receive voltage - 4-wire analog audio input volt age. connects to codec via re ceive gain setting resistor r in (see figure 18). resistor r in needs to be as close to the -in pin as possible to minimize parasitic capacitance. 23 21 vcc positive voltage power supply,+3.3v 24 22 cdc dc biasing filter capacitor - connects between this pin and v cc .the cdc capacitor may be either polarized or non polarized with a 6.3v voltage rating. 25 23 rt ring trip filter network. 26 24 ilim loop current limit programming resistor. 27 25 sh switch hook detection th reshold programming resistor. --- 26 scc substrate common connection - connect this pin to vbh s upply. this pin is used to c onnect the substrate of the die and the thermal heatsink plane of the qfn package. 28 27 ring ring power amplifier output. pin description plcc qfn symbol description ISL5585
5 absolute m aximum ratings t a = 25c thermal information maximum supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v v cc - v bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110v uncommitted switch voltage . . . . . . . . . . . . . . . . . . . . . . . -110v maximum tip/ring negative voltage pulse (note 8) . . . . . . vbh -15v maximum tip/ring positive voltage pulse (note 8) . . . . . . . . . . . .+8v esd (human body model). . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v operating conditions temperature range commercial (c suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 85c industrial (i suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c positive power supply (v cc ). . . . . . . . . . . . . . . . . . . . +3.3v 10% low battery power supply (v bl ) . . . . . . . . . . . . . -16v to -52v, 5% high battery power supply (v bh ) ISL5585aim, cim, gcm, gcr . . . . . . . . . . . . . . v bl to 100v, 5% ISL5585bim, dim. . . . . . . . . . . . . . . . . . . . . . . . v bl to -85v, 10% ISL5585ecm, ecr, fcm, fcr. . . . . . . . . . . . . v bl to -75v, 10% uncommitted switch (loop back or relay driver) . . . . . +5v to -100v thermal resistance (typical) ja (c/w) jc (c/w) plcc (note 1) . . . . . . . . . . . . . . . . . . . 55 n/a qfn (note 2) . . . . . . . . . . . . . . . . . . . . 28 1 maximum junction temperature plastic . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c (plcc - lead tips only) for recommended soldering conditions see tech brief tb389. die characteristics substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v bh process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar-di caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. 2. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. jc, the ?case temp? is measured at the center of the expos ed metal pad on the package underside. see tech brief tb379. electrical specifications unless otherwise specified, t a = -40c to 85c for industrial (i) grade and t a = 0c to 85c for commercial (c) grade, v bl = -24v, v bh = -100v, -85v or -75v, v cc = +3.3v, agnd = bgnd = 0v, loop current limit = 25ma. all ac transmission parameters are specified at 600w 2-wire term inating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0w. parameter test conditions min typ max units ringing parameters vrs input impedance (note 3) 450 - - k ? differential ringing gain (note 4) balanced ringing, vrs to 2-wire, r load = 78 80 82 v/v unbalanced ringing, vrs to 2-wire, r load = 38 40 42 v/v centering voltage accuracy tip, referenced to v bh /2 + 0.5 (note 9) - 2.5 - v ring, referenced to v bh /2 + 0.5 - 2.5 - v open circuit ringing voltage balanced ringing, vrs input=0.840v rms -67-v rms unbalanced ringing, vrs input=0.840v rms - 33.5 - v rms ringing voltage total distortion r l =1.3 k ? , v t-r =|v bh | -5 - - 4.0 % 4-wire to 2-wire ringing off isolation a ctive mode, referenced to vrs input - 90 - db 2-wire to 4-wire transmit isolation ringing mode referenced to the differential ringing amplitude -80-db ac transmission parameters auxiliary input impedance (note 3) 160 - - k ? transmit output impedance (note 3) - - 1 ? 4-wire port overload level thd=1% - 1.0 - v pk 2-wire port overload level thd=1% 3.1 3.5 - v pk ISL5585
6 2-wire return loss 300hz - 24 - db 1khz - 40 - db 3.4khz - 21 - db 2-wire longitudinal balance (notes 5, 6) 300hz to 1khz forward active, grade a and b 58 62 - db forward active, grade c, d and e 53 59 - db 2-wire longitudinal balance (notes 5, 6) 1khz to 3.4khz forward active, grade a and b 54 58 - db forward active, grade c, d and e 53 58 - db 4-wire longitudinal balance (notes 5, 6) 300hz to 1khz forward active, grade a and b 58 67 - db forward active, grade c, d and e 53 64 - db 4-wire longitudinal balance (notes 5, 6) 1khz to 3.4khz forward active, grade a and b 54 66 - db forward active, grade c, d and e 53 63 - db 2-wire to 4-wire level linearity 4-wire to 2-wire level linearity referenced to -10dbm +3 to -40dbm, 1khz - 0.025 - db -40 to -50dbm, 1khz - 0.050 - db -50 to -55dbm, 1khz - 0.100 - db longitudinal current capability per wire (note 3) oht, active 20 - - ma rms 4-wire to 2-wire insertion loss -0.20 0.00 +0.20 db 2-wire to 4-wire insertion loss -6.22 -6.02 -5.82 db 4-wire to 4-wire insertion loss -6.22 -6.02 -5.82 db forward active idle channel noise (note 6) 2-wire c-message, t=25c - 10 13 dbrnc 4-wire c-message, t=25c - 4 7 dbrnc reverse active idle channel noise (note 6) 2-wire c-message, t=25c - 10 13 dbrnc 4-wire c-message, t=25c - 4 7 dbrnc dc parameters off hook loop current limit programming accu racy(1% programming resistor) -8.5 - +8.5 % programming range 15 - 45 ma off hook transient current limit programming accuracy (1% programming resistor) -20 - +20 % programming range 40 - 100 ma loop current during low power standby forward polarity only 18 - 26 ma open circuit voltage (|tip - ring|) v bl =-16v - 8.0 - v dc v bl =-24v 14 15.5 17 v dc v bh > -60v 43 49 - v dc low power standby, open circuit voltage (tip - ring) v bl =-48v - 44.5 - v dc v bh > -60v 43 51.5 - v dc absolute open circuit voltage v rg in lps and fa; v tg in ra; v bh > -60v - -53 -56 v dc test access functions switch on voltage i ol =45ma - 0.20 0.60 v loopback max battery (v bl or v bh ) - - 52 v electrical specifications unless otherwise specified, t a = -40c to 85c for industrial (i) grade and t a = 0c to 85c for commercial (c) grade, v bl = -24v, v bh = -100v, -85v or -75v, v cc = +3.3v, agnd = bgnd = 0v, loop current limit = 25ma. all ac transmission parameters are specified at 600w 2-wire term inating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0w. (continued) parameter test conditions min typ max units ISL5585 1
7 loop detectors and supervisory functions switch hook programming range 5-15ma switch hook programming accuracy (1% programming resistor) -10 - +10 % dial pulse distortion -1.0- % ring trip comparator threshold 1.12 1.25 1.37 v ring trip programming current accuracy (1% programming resistor) -10 - +10 % ground key threshold -12-ma e0 transition, det output delay -20- s thermal alarm output ic junction temperature - 175 - c logic inputs (f0, f1, f2, e0, swc, bsel) input low voltage --0.8v input high voltage 2.0 - - v input low current v il =0.4v -20 -10 - a input high current v ih =2.4v - - 1 a logic outputs (det , alm ) output low voltage i ol =1ma - .15 0.4 v output high voltage i oh =100 a2.42.8-v supply currents low power standby, bsel=1 i cc -3.96.0ma i bh - 0.66 0.90 ma forward or reverse active , bsel=0 i cc -4.96.5ma i bl -1.22.5ma forward active, bsel=1 i cc -7.09.5ma i bl -0.92.0ma i bh -2.23.0ma ringing, bsel=1 (balanced ringing, 100) i cc -6.49.0ma i bl -1.01.3ma i bh -2.03.0ma ringing, bsel=1 (unbalanced ringing, 010) i cc -9.39.0ma i bl -1.01.3ma i bh -2.43.0ma forward loopback, bsel=0 i cc - 10.3 13.5 ma i bl - 23.5 32 ma tip open, bsel=1 i cc -3.85.5ma i bl -0.41.0ma i bh -0.61.0ma electrical specifications unless otherwise specified, t a = -40c to 85c for industrial (i) grade and t a = 0c to 85c for commercial (c) grade, v bl = -24v, v bh = -100v, -85v or -75v, v cc = +3.3v, agnd = bgnd = 0v, loop current limit = 25ma. all ac transmission parameters are specified at 600w 2-wire term inating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0w. (continued) parameter test conditions min typ max units ISL5585
8 power denial, bsel=0 or 1 i cc -4.06.0ma i bl -0.41.0 i bh -0.40.6ma on hook power dissipation (note 7) forward or reverse v bl =-24v - 55 - mw low power standby v bh =-100v - 85 - mw v bh =-85v - 75 - mw v bh =-75v - 65 - mw ringing v bh =-100v - 250 - mw v bh =-85v - 230 - mw v bh =-75v - 225 - mw off hook power dissipation (note 7) forward or reverse v b =-24v - 305 - mw power supply rejection ratio v cc to 2-wire f=300hz - 40 - db f=1khz - 35 - db f=3.4khz - 28 - db v cc to 4-wire f=300hz - 45 - db f=1khz - 43 - db f=3.4khz - 33 - db v bl to 2-wire 300hz f 3.4khz - 30 - db v bl to 4-wire 300hz f 3.4khz - 35 - db v bh to 2-wire 300hz f 3.4khz - 33 - db v bh to 4-wire 300hz f 1khz - 40 - db 1khz < f 3.4khz - 45 - db notes: 3. these parameters are controlled via design or process parameters and are not direct ly tested. these parameters are characteri zed upon initial design release and upon design changes whic h would affect these characteristics. 4. differential ringing gain is measured with vrs = 0.795v rms for -100v devices, vrs = 0.663 v rms for -85v devices and vrs = 0.575v rms for -75v devices. 5. longitudinal balance is tested per ieee455-1985, with 368 ? per tip and ring terminal. 6. these parameters are tested 100% at room temperature. these parameters are guaranteed not tested across temperature via stati stical characterization and design. 7. the power dissipation is based on act ual device measurements and will be less than worst case calculations based on data shee t supply current limits. 8. characterized with 2 x 10 s, and 10 x 1000 s first level lightning surge waveforms (gr-1089-core) 9. for unbalanced ringing the tip terminal is offset to 0v and the ring term inal is centered at vbh/2 + 0.5v. electrical specifications unless otherwise specified, t a = -40c to 85c for industrial (i) grade and t a = 0c to 85c for commercial (c) grade, v bl = -24v, v bh = -100v, -85v or -75v, v cc = +3.3v, agnd = bgnd = 0v, loop current limit = 25ma. all ac transmission parameters are specified at 600w 2-wire term inating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0w. (continued) parameter test conditions min typ max units ISL5585
9 design equations switch hook detect the switch hook detect threshold is set by a single external resistor, r sh . equation 1 is used to calculate the value of r sh . the term i sh is the desired dc loop current threshold. the loop current threshold programming range is from 5ma to 15ma (40k ? < r sh <120k ? ). ground key detect the ground key detector senses a dc current imbalance between the tip and ring terminals when the ring terminal is connected to ground. the ground key detect threshold is not externally programmable and is internally fixed to 12ma regardless of the switch hook threshold. ring trip detect the ring trip detect threshold is set by a single external resistor, r rt . i rt should be set between the peak ringing current and the peak off hook current while still ringing. in addition, the ring trip current must be set below the transient current limit, including tolerances. the capacitor c rt , in parallel with r rt , will set the ring trip response time. loop current limit the loop current limit of the device is programmed by the external resistor r il . the value of r il can be calculated using equation 3. the term i lim is the desired loop current limit. the loop current limit programming range is from 15ma to 45ma (39k ? < r il <117k ? ). transient current limit the drive current capability of the output tip and ring amplifiers is programmed by an external resistor r tl . this output current limit is separat e from the dc loop current limit function. the current lim it circuit works in both the source and sink direction, with an internally fixed offset to prevent the current limit fu nctions from turning on simultaneously. the current lim it function is provided by sensing line current and reducing the voltage drive to the load when the externally set threshold is exceeded, hence forcing a constant source or sink current. transient source current programming the source current is externally programmed as shown in equation 4. for example a source current limit setting of 95ma is programmed with a 18.7k ? (r tl) resistor connected from the tl pin of the device to ground. this setting determines the maximum amount of current which flows from tip to ring during an off hook event until th e dc loop current limit responds. in addition this setting also determines the amount of current which will flow from tip or ring when external battery faults occur. transient sink current programming the sink current limit is inter nally offset 20% higher than the externally programmed source current limit setting. if the source current limit is se t to 95ma, the sink current limit will be 114ma. this setting will determine the maximum current that flows into tip or ring when external ground faults occur. understanding transient current limit each tip and ring amplifier is designed to limit source current and sink current. figure 1 s hows the functionality of the circuit for the case of limiting the source current. a similar diagram applies to the sink current limit with current polarity changed accordingly. during normal operation, the error current (i err ) is zero and the output voltage is determi ned by the signal current (i sig ) multiplied by the 200k feedback resistor. with the current polarity as shown for i sig , the output voltage moves positivewith respect to half ba ttery. assuming the amplifier output is driving a load at a more negative potential, the amplifier output will source current. during excessive output source current flow, the scaled output current (i o /k) exceeds the reference current (i ref ) forcing an error current (i err ). with the polarity as shown the error current subtracts from the signal current, which reduces the amplifier output vo ltage. by reduc ing the output voltage the source current to the load is decreased and the output current is limited. setting the proper transient current limit since this feature programs the maximum output current of the device, the setting must be high enough to allow for r sh 600 i sh ? = (eq. 1) r rt 1800 i rt ? = (eq. 2) r il 1760 i lim ------------ - = (eq. 3) r tl 1650 i src ------------- = (eq. 4) i snk 1.20 i src = (eq. 5) figure 1. current limit functional diagram tip or ring + - i ref = 1.21/tl i o i o /k i err i sig 20 200k vb/2 ISL5585
10 detection of ring trip or programmed off hook loop current, whichever is greater. to allow for proper ring trip op eration, the transient current limit setting should be set at le ast 25% higher than the peak ring trip current setting. setti ng the transient current 25% higher should account for programming tolerances of both the ring trip threshold and the transient current limit. if loop current is larger than ring trip current (low ren applications) then the transient cu rrent limit should be set at least 35% higher than the loop cu rrent setting. the slightly higher offset accounts for the slope of the loop current limit function. attention to detail should be exercised when programming the transient current limit setting. if ring trip detect does not occur while ringing, then re-examine the transient current limit and ring trip threshold settings. dc loop feed the feedback mechanism for monitoring the dc portion of the loop current is the loop dete ctor. a low pass filter is used in the feedback to block voice band signals from interfering with the loop current limit function. the pole of the low pass filter is set by the external capacitor c dc . the value of the external capacitor should be 4.7 f, 6.3v rated polarized or non-polarized capacitor. most applications will operate the device from low battery while off hook. the dc feed characteristic of the device will drive tip and ring towards half battery to regulate the dc loop current. for light loads or long loops, tip will be near -4v and ring will be near v vbl + 5v. figure 2 shows the dc feed characteristic in terms of tip to ring voltage and loop current. the point on the y-axis labeled v tr(oc) is the open circuit tip to ring voltage and is defined by the feed battery voltage in equation 6. figure 3 illustrates the actual loop current for a given set of loop conditions. the loop conditions are determined by the low battery voltage and the dc loop impedance. the dc loop impedance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook dc resistance. the slope of the feed characteri stic and the battery voltage define the maximum loop current on the shortest possible loop as the short circuit current i sc . the term i lim is the programmed current limit, 1760/r il . the line segment i a represents the constant current region of the loop current limit function. process variations in the ISL5585 effect the i lim and 11.11k ? slope in equation 8. all units are tested with: a 300 ? load across tip and ring, v bat =-24v and i lim set to 25ma. equation 8 can be used to predict the ideal current at this setting (25.76ma). all units are tested to be within 8.5% of this ideal value (23.57ma to 27.95ma). the maximum loop impedance for a programmed loop current is defined as r knee . when r knee is exceeded, the device will transition from constant current feed to consta nt voltage or resistive feed. the line segment i b represents the resi stive feed portion of the load characteristic impedance matching the impedance of the device is programmed with the external component r s . r s is the gain setting resistor for the transmit amplifier that pr ovides impedance matching. if complex impedance matching is required, then a complex network can be substituted for r s . the feedback mechanism for monitoring the ac portion of the loop current consists of two amplifiers, the sense amplifier (sa) and the transm it amplifier (ta). the ac feedback signal is used for impedance synthesis. a detailed model of the ac feed back loop is shown in figure 4. figure 2. dc feed characteristic m = ( ? v tr / ? i l ) = 11.1k ? i loop (ma) i lim v tr(oc) v tr , dc (v) long loop short loop v tr oc () v bl 9 ? = (eq. 6) figure 3. i loop vs. r loop load characteristic r loop (? ) r knee i lim i loop (ma) i sc i a i b 2r p long loop short loop m=11.11k m=vtr(oc)/rloop constant current constant voltage or resistive feed i sc i lim v tr oc () 2r p i lim ? 11.11k ----------------------------------------------------- - + = (eq. 7) i a i lim v tr oc () r loop i lim ? 11.11k -------------------------------------------------------------- + = (eq. 8) r knee v tr oc () i lim ------------------------ = (eq. 9) i b v tr oc () r loop ------------------------ = (eq. 10) ISL5585
11 the gain of the transmit amplifier, set by r s , determines the programmed impedance of the device. the capacitor c fb blocks the dc component of the loop current. the ground symbols in the model represent ac grounds, not actual dc potentials. the sense amplifier is configur ed as a 4 input differential amplifier with a gain of 3/4. the voltage at the output of the sense amplifier (v sa ) is calculated using superposition. v sa 1 is the voltage resulting from v1, v sa 2 is the voltage resulting from v2 and so on (reference figure 4). where ? v is equal to i m r sense (r sense = 20 ? ) the voltage at vtx is equal to: v tr is defined in figure 4, note polarity assigned to v tr : setting v in equal to zero in eq 18, defining z o = -v tr / ? i m and substituting it into eq18 will enable the user to determine the required feedback to match the line impedance at v 2w as shown in equation 19. 2-wire impedance matching z o is the source impedance of the device and is defined as. z l is the line impedance and r p is the external protection resistor. r s is defined as: v sa 1 3 4 -- - v 1 () ? = (eq. 11) v sa 2 3 4 -- - v 2 () = (eq. 12) v sa 3 3 4 -- - v 3 () ? = (eq. 13) v sa 4 3 4 -- - v 4 () = (eq. 14) v sa v 2 v 1 ? () v 4 v 3 ? () + [] 3 4 -- - v ? v ? + [] 3 4 -- - == (eq. 15) v sa 2i m ? 20 () 3 4 -- - i m 30 ? == (eq. 16) v tx v in r s r in --------- - ?? ?? ?? ? v sa ? r s 8k ------- - ?? ?? v in r s r in --------- - ?? ?? ?? ? i m 30 ? () ? r s 8k ------- - ?? ?? == (eq. 17) v tr 2v tx () 2v in r s r in --------- - ?? ?? ?? i m 30 ? () r s 8k ------- - ?? ?? + ?? ?? ?? == (eq. 18) z o 1 133.33 ----------------- - r s = (eq. 19) z o z l 2r p ? = (eq. 20) r s 133.33 z l 2r p ? () = (eq. 21) figure 4. ac signal transmission model aux tip ring e g v tr i m v tx r p r p + - + - - + i m z l + - r + - r r sense + - v sa = ? i m 30 i x i x + - i x + - + - + - i m + - 20 ? 20 ? v 2w + - intersil ISL5585 v tx z 0 1:1 + - c fb vfb -in ta r r r s 8k 3r 3r 4r 4r 4r 4r i x sense feedback receive block v 1 v 2 v 3 v 4 i m + - i m + - r sense amplifier feed amplifier feed v in from codec r in amplifier amplifier ISL5585
12 complex impedance synthesis substituting the impedance programming resistor, r s , with a complex programming network provides complex impedance synthesis. the reference designators in the programming network match the evaluation board. the component r s has a different design equation than the r s used for resistive impedance synthesis. the design equations for each component are provided below. substituting eq 17 for vtx with aux =0 and ? i m = -v 2w /z l gives us eq 26. note: aux input is not used. substitute eq 17 into eq 21 substitute eq 26 into eq 27 substitute equation 19 for r s /8k in equation 28. simplifying substitute equation 30 into equation 31 and combine terms where: v in = the input voltage at th e -in pinthrough resistor r in . aux = auxiliary input of slic. not used for ac gains. v sa = an internal node voltage that is a function of the loop current and the output of the sense amplifier. i x = internal current in the slic that is the difference between the input receive current and the feedback current. i m = the ac metallic current. r p = a protection resistor (typical 49.9 ? ). r s = an external resistor/network for matching the line impedance. v tr = the tip to ring voltage at the output pins of the slic. v 2w = the tip to ring voltage including the voltage across the protection resistors. z l = the line impedance. z o = the source impedance of the device. 4-wire to 2-wire gain 4-wire to 2-wire gain across the ISL5585 is equal to the v 2w divided by the input voltage v in , reference figure 4. the receive gain is calculated using equation 32. equation 33 expresses the receive gain (v in to v 2w ) in terms of network impedances. from equation 21, the value of r s was set to match the line impedance (z l ) to the ISL5585 plus the protection resistors (z 0 + 2r p ). this results in a 4-wire to 2-wire gain equal to r s /r in , as shown in eq. 33. 2-wire to 4-wire gain the 2-wire to 4-wire gain is equal to v tx /e g with v in = 0, reference figure 4. from equation 30 with v in = 0 substituting equation 35 into equation 34 and simplify. figure 5. complex programming network 2-wire network r 1 r 2 c 2 programming network r series r parallel c parallel r series 133.3 r 1 2r p () ? () = (eq. 22) r parallel 133.3 r 2 = (eq. 23) c parallel c 2 133.3 ? = (eq. 24) i x aux r ------------ - + v tx r ---------- - = node equation (eq. 25) at ISL5585 aux input, figure 4 i x v tx r ---------- - v in r --------- r s r in --------- - ?? ?? ?? ? v 2w 30 z l ----------------- - ?? ?? ?? ? r s r8k ----------- ?? ?? == (eq. 26) i x r - v tr + i x r = 0 loop equation (eq. 27) at ISL5585 feed amplifiers and load. v tr 2v in r s r in --------- - ?? ?? ?? ? 2v 2w 30 z l --------------------- - ?? ?? ?? r s 8k ------- - ?? ?? + = (eq. 28) v tr 2v in r s r in --------- - ?? ?? ?? ? 2v 2w 30 z l --------------------- - ?? ?? ?? 133.33z o 8k -------------------------- ?? ?? + = (eq. 29) v tr 2v in r s r in --------- - ?? ?? ?? ? v 2w z l ---------- - ?? ?? ?? z o () + = (eq. 30) v 2w -i m 2r p + v tr = 0 loop equation (eq. 31) at tip/ring interface v 2w z l z o 2r p ++ z l -------------------------------------- 2v in r s r in --------- - = (eq. 32) g 4-2 = v 2w v in ----------- - = 2 r s r in --------- - ?? ?? ?? z l z l z o + + 2 rp --------------------------------------- - 2 z l z l z l + ------------------- - r s r in --------- - == (eq. 33) e ? g z l i m 2r p i m v tr ? + + 0 = loop equation (eq. 34) v tr z o v 2w z l -------------------- = (eq. 35) e g v 2w z l 2r p z o ++ z l -------------------------------------- - ? = (eq. 36) ISL5585
13 substituting equation 19 into equation 17 (v in =0) and defining ? i m = -v 2w /z l results in equation 37 for vtx. combining equations 36 and 37 results in equation 38. a more useful form of the equat ion is rewritten in terms of v tx /v 2w . a voltage divider equation is written to convert from e g to v 2w as shown in equation 39. substituting z l = z o + 2 rp and rearranging equation 39 in terms of e g results in equation 40. substituting equation 40 into equation 38 results in an equation for 2-wire to 4-wire gai n that?s a function of the synthesized input impedance of the slic and the protection resistors. if z l is set to 600 ? , z o is programmed with r s to be 498.76 ? (66.5k ? /133.33), and r p is equal to 49.9 ? . this results in a 2-wire to 4-wire gain of 0.416 or -7.6db. when the protection resistors are set to zero, the transmit gain is -6db. transhybrid gain the transhybrid gain is defined as the 4-wire to 4-wire gain (g 44 ). understanding phase across the ISL5585 4-wire to 2-wire phase the phase of a signal through the ISL5585 is dependent upon whether the source is drivin g the signal 4-wire to 2-wire or 2-wire to 4-wire. figure 6 illustrates the phase of the input signal across the ISL5585 when the signal is applied at the -in pin of the ISL5585 through the r in resistor. the transmit amplifier (ta) inverts the signal 180 degrees at the vtx pin. the feedback around the tip amplifier inverts the signal again on the tip lead. the input signal will cause ac loop current to flow through the 20 ? sense resistors in the direction from v 1 to v2 and v3 to v4. this results in an inverted signal (referenced from tip) on the vsa and thus the vfb pin. this out of phase signal is the signal used by the feedback path to match the line impedance of the 2-wire side. 2-wire to 4-wire phase figure 7 illustrates the phase of the input signal across the ISL5585 when the signal is applied across tip and ring. when you?re driving the 2-wi re side with a source the ISL5585 looks like a predetermined impedance (programmed with resistor rs). the current flows through the 20 ? sense resistors in the direction v2 to v1 and v4 to v3. this results in a non-inver ted signal (referenced from tip) on the vsa and thus the vfb pin. this signal is then inverted by the ta amplifier and the signal appearing on the vtx putput is out of phase with the signal on tip. summary of the phase through the ISL5585 4-wire to 2-wire (v in to v 2w ) is 180 out of phase 2-wire to 4-wire (v 2w to v tx ) is 180 out of phase 4-wire to 4-wire (v in to v tx ) is 180 out of phase v tx v 2w 2 ------------ z l 2r p ? z l ------------------------ = (eq. 37) g 2-4 = v tx e g ---------- = z l 2r p ? 2z l 2r p z o ++ () ----------------------------------------------- - ? z o 2z l 2r p z o ++ () ----------------------------------------------- - ? = (eq. 38) v 2w = z o + 2 rp z l z o + + 2 rp --------------------------------------- - ?? ?? ?? e g (eq. 39) e g = 2v 2w (eq. 40) g 2-4 = v tx v 2w ----------- - = z o z l 2r p z o ++ () ------------------------------------------- - ?? ?? ?? ? 0.416 = (eq. 41) g 44 g 42 g 24 r s r in --------- - ?? ?? ?? ? z o z l 2r p z o ++ -------------------------------------- - ?? ?? ?? == (eq. 42) ISL5585
14 figure 6. 4-wire to 2-wire signal phase across the ISL5585 aux tip ring i m v tx r p r p - + i m z l + - r + - r r sense + - v sa = ? i m 30 i x i x + - i x + - + - + - 20 ? 20 ? v 2w + - intersil ISL5585 v tx 1:1 + - c fb vfb -in ta r r r s 8k 3r 3r 4r 4r 4r 4r i x sense receive block v 1 v 2 v 3 v 4 i m + - i m + - r sense amplifier feed amplifier feed v in from codec r in 2-wire side 4-wire side input amplifier figure 7. 2-wire to 4-wire signal phase across the ISL5585 aux tip ring i m v tx r p r p - + i m + - r + - r r sense + - v sa = ? i m 30 i x i x + - i x + - + - + - 20 ? 20 ? v 2w + - intersil ISL5585 v tx 1:1 + - c fb vfb -in ta r r r s 8k 3r 3r 4r 4r 4r 4r i x sense receive block v 1 v 2 v 3 v 4 i m + - i m + - r sense amplifier feed amplifier feed v in from codec r in 2-wire side 4-wire side input amplifier ISL5585
15 low power standby overview the low power standby mode (lps, 000) should be used during idle line conditions. the device is designed to operate from the high battery during this mode. most of the internal circuitry is powered down, resulting in low power dissipation. if the 2-wire (tip/ring) dc voltage requirements are not critical during idle line conditions, the device may be operated from the low batter y. operation from the low battery will decrease the standby power dissipation. 2-wire interface during lps, the 2-wire interface is maintained with internal switches and voltage references. the tip and ring amplifiers are turned off to conserve power. the device will provide mtu compliance, loop cu rrent and loop supervision. figure 8 represents the internal circuitry providing the 2-wire interface during low power standby. mtu compliance maintenance termination unit or mtu compliance places dc voltage requirements on the 2-wire terminals during idle line conditions. the minimum idle voltage is 42.75v. the high side of the mtu range is 56v. the voltage is expressed as the difference between tip and ring. the tip voltage is held near ground through a 600 ? resistor and switch. the ring voltage is limited to a maximum of -56v (by mtu ref) when operat ing from either the high or low battery. a switch and 600 ? resistor connect the mtu reference to the ring terminal. when the high battery voltage exceeds the mtu reference of -56v, the ring terminal will be clamped by the internal reference (typically - 54v). the same ring relationships apply when operating from the low battery voltage. for high battery voltages (v bh ) less than or equal to the internal mtu reference threshold: loop current during lps, the device will pr ovide current to a load. the current path is through resistors and switches, and is a function of the off hook loop resistance (r loop ). this includes the off hook phone resistance and copper loop resistance. the current available during lps is determined by equation 44. internal current limiting of the standby switches will limit the maximum current to approximately 20ma. another loop current related parameter is longitudinal current capability. the longitudinal current capability is reduced. the reduction in longitudinal current capability is a result of turning off the tip and ring amplifiers. on hook power dissipation the on hook power dissipation of the device during lps is determined by the operating voltages and quiescent currents and is calculated using equation 45. the quiescent current terms are specified in the electrical tables for each operating mode. load power dissipation is not a factor since this is an on hook mode. some applications may specify a standby current. the standby current may be a charging current required for modern telephone electronics. standby current power dissipation any standby line current, i slc , introduces an additional power dissipation term p slc . equation 46 illustrates the power contribution is zero wh en the standby line current is zero. if the battery voltage is less than -54v (the mtu clamp is off), the standby line current power contribution reduces to equation 47. table 1. device interfaces during lps interface on off notes receive x ac transmission, impedance matching and ringing are disabled during this mode. ringing x transmit x 2-wire x amplifiers disabled. loop detect x switch hook or ground key. figure 8. lps 2-wire interface circuit diagram tip amp ring amp tip ring mtu ref gnd 600 ? 600 ? v ring v bh 5 + = (eq. 43) i loop 1 ? 54 ? () ? () 600 600 r loop ++ () ? = (eq. 44) p lps v bh i bhq v bl i blq v cc i ccq ++ = (eq. 45) p slc i slc v bh 54 ? 1i slc x1200 ++ () = (eq. 46) p slc i slc v bh 1i slc x1200 ++ () = (eq. 47) ISL5585
16 most applications do not specify charging current requirements during standby. w hen specified, the typical charging current may be as high as 5ma . forward active overview the forward active mode (fa, 001) is the primary ac transmission mode of the device. on hook transmission, dc loop feed and voice transmission are supported during forward active. loop supervision is provided by either the switch hook detector (e0 = 1) or the gr ound key detector (e0 = 0). the device may be operated from eit her high or low battery for on- hook transmission and low battery for loop feed. on-hook transmission the primary purpose of on hook transmission will be to support caller id and other advanced signalling features. the transmission over load level while on hook is 1 v peak . when operating from the high bat tery, the dc voltages at tip and ring are mtu compliant. the typical tip voltage is -4v and the ring voltage is a function of the battery voltage for battery voltages less than -60v as shown in equation 48. loop supervision is provided by the switch hook detector at the det output. when det goes low, the low battery should be selected for dc loop feed and voice transmission. feed architecture the design implements a voltage feed current sense architecture. the device controls the voltage across tip and ring based on the sensing of load current.internal resistors (r cs ) are placed in series with tip and ring outputs to provide the current sensing. the diagram below illustrates the concept. by monitoring the current at th e amplifier output, a negative feedback mechanism sets the output voltage for a defined load. the amplifier gains are set by resistor ratios (r a , r b , r c ) providing all the perfor mance benefits of matched resistors. the internal sense resistor, r cs , is much smaller than the gain resistors and is typically 20 ? for this device. the feedback mechanism, k s , represents the amplifier configuration providin g the negative feedback. transhybrid balance the final step in completing the impedance synthesis design is calculating the necessary gains for transhybrid balance. the ac feed back loop produces an echo at the v tx output of the signal injected at v in . the echo must be cancelled to maintain voice quality. most applications will use a summing amplifier in the codec front end as shown in figure 10 to cancel the echo signal. the resistor ratio, r f /r a , provides the final adjustment for the transmit gain, g tx (v 2w to pcm, figure 18). the transmit gain is calculated using equation 49. most applications set r f = r a , hence the device 2-wire to 4-wire equals the transmit gain. typically r a is greater than 20k ? to prevent loading of the device transmit output. the value of the rf resistor should greater than the minimum load spec of the codec?s internal amplifier (typical value 30.1k ? ). the resistor ratio, r f /r b , is determined by the transhybrid gain of the device, g 44 . r f is previously defined by the transmit gain requirement and r b is calculated using equation 50. power dissipation the power dissipated by the device during on hook transmission is strictly a function of the quiescent currents for each supply voltage during forward active operation. off hook power dissipation is increased above the quiescent power dissipation by the dc load. if the loop length is less than or equal to r knee , the device is pr oviding constant current, i a , and the power dissipation is calculated using equation 52. v ring v bh 5 + = (eq. 48) figure 9. voltage feed current sense diagram + - + - v in v out r c r cs r l r b r a k s figure 10. transhybrid balance interface + - r f r a r b ISL5585 codec +2.4v rx out tx in -in aux vtx r r + - 1:1 r s t a r in g tx g ? 24 r f r a ------- - ?? ?? ?? z o z l 2r p z o ++ () ------------------------------------------- - ?? ?? ?? r f r a ------- - ?? ?? ?? ? == (eq. 49) r b r a g 44 ---------- = r a r in r s --------- - ?? ?? ?? z l 2r p z o ++ z o -------------------------------------- - ?? ?? ?? = (eq. 50) p faq v bh i bhq v bl i blq v cc i ccq ++ = (eq. 51) p fa ia () p fa q () v bl xi a () r loop xi 2 a () ? + = (eq. 52) ISL5585
17 if the loop length is greater than r knee , the device is operating in the constant voltag e, resistive feed region. the power dissipated in this region is calculated using equation 53. since the current relationship s are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations. reverse active overview the reverse active mode (ra, 011) provides the same functionality as the forward active mode. on hook transmission, dc loop feed and voice transmission are supported. loop supervision is pr ovided by either the switch hook detector (e0 = 1) or the ground key detector (e0 = 0). the device may be operated from either high or low battery. during reverse active the tip and ring dc voltage characteristics exchange roles. that is, ring is typically 4v below ground and tip is typically 4v more positive than battery. otherwise, all feed and voice transmission characteristics are identical to forward active. silent polarity reversal changing from forward active to reverse active or vice versa is referred to as polarity reversal. many applications require slew rate control of the polarity reversal event. requirements range from minimizing cross talk to protocol signalling. the device uses an external low voltage capacitor, c pol , to set the reversal time. once programmed, the reversal time will remain nearly constant over various load conditions. in addition, the reversal timing capac itor is isolated from the ac loop, therefore loop stability is not impacted. the internal circuitry used to se t the polarity re versal time is shown in figure 11. during forward active, the current from source i1 charges the external timing capacitor c pol and the switch is open. the internal resistor provides a clamping function for voltages on the pol node. during reverse active, the switch closes and i2 (roughly twice i1) pulls current from i1 and the timing capacitor. the current at the pol node provides the drive to a differential pair which controls the reversal time of the tip and ring dc voltages. where ? time is the required reversal time. polarized capacitors may be used for c pol . the low voltage at the pol pin and minimal voltage excursion 0.75v, are well suited to polarized capacitors. power dissipation the power dissipation equations for forward active operation also apply to the reverse active mode. ringing overview the ringing mode (rng, 100) provides linear amplification to support a variety of ringing waveforms. a programmable ring trip function provides loop supervision and auto disconnect upon ring trip. the device is designed to operate from the high battery during this mode. architecture the device provides linear amplif ication to the signal applied to the ringing input, v rs . the differential ringing gain of the device is 80v/v. the circuit model for the ringing path is shown in figure 12. the voltage gain from the vrs input to the tip output is 40v/v. the resistor ratio provid es a gain of 8 and the current mirror provides a gain of 5. the voltage gain from the vrs input to the ring output is -40v/v. the equations for the tip and ring outputs during ringing are provided below. when the input signal at vrs is zero, the tip and ring amplifier outputs are centered at half battery. the device provides auto centering fo r easy implementation of sinusoidal ringing waveforms. both ac and dc control of the tip and ring outputs is availabl e during ringing. this feature allows for dc offsets as part of the ringing waveform. p fa ib () p fa q () v bl xi b () r loop xi 2 b () ? + = (eq. 53) figure 11. reversal timing control c pol pol i 1 75k ? i 2 c pol ? time 75000 ---------------- = (eq. 54) figure 12. linear ringing model tip ring vrs r/8 r r + - + - 5:1 20 20 + - + - 600k v bh 2 v t v bh 2 ----------- 40 vrs () + = (eq. 55) v r v bh 2 ----------- 40 vrs () ? = (eq. 56) ISL5585
18 ringing input the ringing input, v rs , is a high impedance input. the high impedance allows the use of low value capacitors for ac coupling the ring signal. the v rs input is enabled only during the ringing mode, therefor e a free running oscillator may be connected to vrs at all times. when operating from a battery of -100v, each amplifier, tip and ring, will swing a maximum of 95v p-p . hence, the maximum signal swing at vrs to achieve full scale ringing is approximately 2.4v p-p . the low signal levels are compatible with the output voltage range of the codec. the digital nature of the codec ideally su its it for the function of programmable ringing generator. logic control ringing patterns consist of silent intervals. the ringing to silent pattern is called the ri nging cadence. during the silent portion of ringing, the device can be programmed to any other operating mode. the most likely candidates are low power standby or forward ac tive. dependi ng on system requirements, the low or hi gh battery may be selected. loop supervision is provided with the ring trip detector. the ring trip detector senses the change in loop current when the phone is taken off hook. the loop detector full wave rectifies the ringing current, which is then filtered with external components r rt and c rt . the resistor r rt sets the trip threshold and the capacitor c rt sets the trip response time. most applications will require a trip response time less than 150ms. three very distinct actions o ccur when the devices detects a ring trip. first, the det output is latched low. the latching mechanism eliminates the need for software filtering of the detector output. the latch is cleared when the operating mode is changed externally. second, the vrs input is disabled, removing the ring signal from the line. third, the device is internally forced to the forward active mode. power dissipation the power dissipation during ringing is dictated by the load driving requirements and the ringing waveform. the key to valid power calculations is the correct definition of average and rms currents. the average current defines the high battery supply current. the rms current defines the load current. the cadence provides a time averaging reduction in the peak power. the total power dissipation consists of ringing power, p r , and the silent interval power, p s . the terms t r and t s represent the cadence. the ringing interval is t r and the silent interval is t s . the typical cadence ratio t r :t s is 1:2. the quiescent power of the device in the ringing mode is defined in equation 58. the total power during the ringi ng interval is the sum of the quiescent power and loading power: for sinusoidal waveforms, the average current, i avg , is defined in equation 60. the silent interval power dissipation will be determined by the quiescent power of th e selected operating mode. unbalanced ringing the ISL5585gcm offers unbalanced ringing mode (010). this feature accommodates some analog pbx trunk lines that require the tip terminal to be held near ground for the duration of the ringing bursts. the tip terminal is offset to 0v?s with an internal current source that is applied to the inverting input of the tip amplifier. this reduces the differential ringing gain to 40v/v. the ring terminal will center at vbh/2 and swing fr om -vbh to ground. as in balanced ringing, off hook detection is accomplished by sensing the peak current and comparing it to a preset threshold. this allows the same sensing, comparing and threshold circuitry to be used in both ringing modes. this mode of operation does not require any additional external components. forward loop back overview the forward loop back mode (flb, 101) provides test capability for the device. an internal signal path is enabled allowing for both dc and ac verification. the internal 600 ? terminating resistor has a tolerance of 20%. the device is intended to operate from only the low battery during this mode. architecture when the forward loop back mode is initiated internal switches connect a 600 ? load across the outputs of the tip and ring amplifiers. p rng p r t r t r t s + -------------- p s t s t r t s + -------------- + = (eq. 57) p rq () v bh i bhq v bl i blq v cc i ccq ++ = (eq. 58) p r p rq () v bh i avg v rms 2 z ren r loop + ------------------------------------------ ? + = (eq. 59) i avg 2 -- - ?? ?? v rms 2 z ren r loop + ------------------------------------------ = (eq. 60) figure 13. forward loop back internal termination ring amp tip amp ring tip 600 ? ISL5585
19 dc verification when the internal signal path is provided, dc current will flow from tip to ring. the dc current will force det low, indicating the presence of loop current. in addition, the alm output will also go low. this does not indicate a thermal alarm condition. rather, proper logic operation is verified in the event of a thermal shutdown. in addition to verifying device functionality, toggling the logic outputs verifies the interface to the system controller. ac verification the entire ac loop of the device is active during the forward loop back mode. therefore a 4-wire to 4-wire level test capability is provided. depending on the transhybrid balance implementation, test coverage is provided by a one or two step process. system architectures which ca nnot disable the transhybrid function would require a two step process. the first step would be to send a test tone to the device while on hook and not in forward loop back mode. the return signal would be the test level times the gain r f /r a of the transhybrid amplifier. since the device would not be terminated, cancellation would not occur. the second step would be to program the device to flb and resend the test tone. the return signal would be much lower in amplitude than the first step, indicating the device was active and the internal termination attenuated the return signal. system architectures which disable the transhybrid function would achieve test coverage with a signal step. once the transhybrid function is disable, program the device for flb and send the test tone. the return signal level is determined by the 4-wire to 4-wire gain of the device. tip open overview the tip open mode (110) is intended for compatibility for pbx type interfaces. used during idle line conditions, the device does not provide transm ission. loop supervision is provided by either the switch hook detector (e0 = 1) or the ground key detector (e0 = 0). the ground key detector will be used in most applications. the device may be operated from either high or low battery. functionality during tip open operation, the tip switch is disabled and the ring switch is enabled. the minimum tip impedance is 30k ? . the only active path through the device will be the ring switch. in keeping with the mtu characteristics of the device, ring will not exceed -56v when operating from the high battery. though mtu does not apply to tip open, safety requirements are satisfied. power denial overview the power denial mode (111) will shutdown the entire device except for the logic interface. loop supervision is not provided. this mode may be used as a sleep mode or to shut down in the presence of a persistent thermal alarm. switching between high and lo w battery will have no effect during power denial. functionality during power denial, both the tip and ring amplifiers are disabled, representing high impedances. the voltages at both outputs are near ground. thermal shutdown in the event the safe die temperature is exceeded, the alm output will go low and det will go high and the part will automatically shut down. when the device cools, alm will go high and det will reflect the loop status. if the thermal fault persists, alm will go low again and the part will shut down. programming power denial will permanently shutdown the device and stop t he self cooling cycling. battery switching overview the integrated battery switch selects between the high battery and low battery. the battery switch is controlled with the logic input bsel. when bsel is a logic high, the high battery is selected and when a logic low, the low battery is selected. all opera ting modes of the device will operate from high or low battery except forward loop back, which requires low battery for thermal reasons. functionality the logic control is independent of the operating mode decode. independent logic control provides the most flexibility and will support all application configurations. when changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. in most cases, this will minimize overall power dissipation and prev ent glitches on the det output. the only external component required to support the battery switch is a diode in series with the v bh supply lead. in the event that high battery is re moved, the diode allows the device to transition to low battery operation. low battery operation all off hook operating conditions should use the low battery. the prime benefit will be reduced power dissipation. the typical low battery for the devi ce is -24v. however this may be increased to support longer loop lengths or high loop current requirements. standby conditions may also operate from the low battery if mtu compliance is not required, further reducing standby power dissipation. ISL5585
20 high battery operation other than during ringing, the high battery should be used for standby conditions which must provide mtu compliance. during standby operation the power consumption is typically 85mw with -100v battery. if ringing requirements do not require full 100v operation, then a lower battery will result in lower standby power. high voltage decoupling the 100v rating of the device will require a capacitor of higher voltage rating for decoupling. suggested decoupling values for all device pins are 0.1 f. standard surface mount ceramic capacitors are rated at 100v. for applications driven at low cost and small size, the decoupling scheme shown below could be implemented. it is important to place the external diode between the vbh pin and the decoupling capacitor. attaching the decoupling capacitor directly to the vbh pin will degrade the reliability of the device. refer to figure 14 for the proper arrangement. this applies to both single and stacked and decoupling arrangements. if vbl and vbh are tied together to override the battery switch function, then the external diode is not needed and the decoupling may be attached directly to vbh. uncommitted switch overview the uncommitted switch is a three terminal device designed for flexibility. the independent logic control input, swc , allows switch operation regardless of device operating mode. the switch is activated by a logic low. the positive and negative terminals of the device are labeled sw+ and sw- respectively. relay driver the uncommitted switch may be used as a relay driver by connecting sw+ to the relay coil and sw- to ground. the switch is designed to have a maximum on voltage of 0.6v with a load current of 45ma. since the device provides the ringing waveform, the relay functions which may be supported include subscriber disconnect, test access or line interface bypass. an external snubber diode is not require d when using the uncommitted switch as a relay driver. test load the switch may be used to connect test loads across tip and ring. the test loads can provide external test termination for the device. proper connection of the uncommitted switch to tip and ring is shown below. the diode in series with the test load blocks current from flowing through the uncommitted switch when the polarity of the tip and ring terminals are reversed. in addition to the reverse active state, the polarity of tip and ring are reversed for half of the ringing cycle. with independent logic control and the blocking diode, the uncommitted switch may be continuously connected to the tip and ring terminals. figure 14. alternate decoupling scheme vbh vbl 0.22 0.22 ISL5585 figure 15. external relay switching relay sw+ sw- swc +v figure 16. test load switching ring tip test load sw+ sw- swc ISL5585
21 special considerations for the qfn package the new quad flatpack no-lead (qfn) package offers a significant footprint reduction (65%) and improved thermal performance with respect to the 28 lead plcc. to realize the thermal enhancements and maintain the high voltage (-100v) performance, the exposed pad on the bottom of the qfn package should be soldered to a power/heat sink plane that is electrically connected to the ISL5585 s ubstrate c ommon c onnection (scc) pin. the heat is distributed evenly across the board by way of the heat sink plane. this is accomplished by using conductive thermal vias. reference technical brief tb379 and an9922 for additional information on thermal characterization and board layout considerations. table 2. ISL5585 3v application circuit components component value tol rating u1 - ringing slic ISL5585 n/a n/a r tl 18.7k ? 1% 0.1w r rt 23.7k ? 1% 0.1w r sh 49.9k ? 1% 0.1w r il 71.5k ? 1% 0.1w r s 66.5k ? 1% 0.1w r f 30.1k ? 1% 0.1w r a 36.5k ? 1% 0.1w r b 42.2kk ? 1% 0.1w r in 45.3k ? 1% 0.1w c rs , c tx , c rt , c pol 0.47 f 20% 10v c dc , c fb 4.7 f 20% 6.3v c ps1 0.1 f 20% >100v c ps2 , c ps3 0.1 f 20% 100v d 1 1n400x type with breakdown > 100v. r p1 , r p2 standard applications will use 49 ? per side. protection resistor values are application dependent and will be determined by protection requirements. design parameters: ring trip threshold = 76ma peak , switch hook threshold = 12ma, loop current limi t = 24.6ma, synthesize device impedance = (3*66.5k ?) /400 = 498.8 ? , with 49.9 ? protection resistors, impedance across tip and ring terminals = 599 ? . transient current limit = 95ma. figure 17. ISL5585 3.3v application circuit aux vrs tip vfb bgnd agnd ring vtx -in sh rt cdc ilim ISL5585 v cc pol c rs r il c fb r s r sh c rt r rt c pol c dc u 1 r p1 r p2 vcc vbl vbh d 1 1n4004 c ps1 c ps3 c ps2 tl r tl + - r f r a r b codec +2.4v tx in r in v 2w + - pcm to v 2w gain = +3.33db, digital gain set to 0db v 2w to pcm gain = -9.3 db, digital gain set to 0db digital gain 0db digital gain 0db pcm pcm 0 dbm0, codec output voltage = 0.531vrms 0 dbm0, v 2w = 0.7795vrms design equations r s = 133.33(z l - 2r p ) gain pcm to v 2w = r s /r in = 66.5k/45.3k =1.46 66.5k ? 45.3k ? v 2w to pcm gain = v 2w (g 2-4 )(r f /r a ) = (0.7795)(0.416)(30.1k/36.5k) = 0.267 30.1k ? 36.5k ? 42.2k ? 0.47uf 0.47uf 0.47uf db gain =20log (0.7795/ 0.531) = +3.33db db gain =20log (0.267/0.7795) = - 9.3db 600 ? 49.9 ? 49.9 ? ISL5585
22 ISL5585 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l32.7x7 32 lead quad flat no-lead plastic package (compliant to jedec mo-220vkkc issue c) symbol millimeters notes min typ max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 7.00 bsc - d1 6.75 bsc 9 d2 4.55 4.70 4.85 7, 8 e 7.00 bsc - e1 6.75 bsc 9 e2 4.55 4.70 4.85 7, 8 e 0.65 bsc - k0.25--- l 0.50 0.60 0.75 8 l1 - - 0.15 10 n322 nd 8 3 ne 8 3 p- -0.609 --129 rev. 4 8/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL5585 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97

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