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general description the max1992/max1993 pulse-width modulation (pwm) controllers provide high-efficiency, excellent transient response, and high dc output accuracy. the devices step down high-voltage batteries to generate low- voltage cpu core or chipset/ram supplies in notebook computers. maxim? proprietary quick-pwm quick-response, con- stant on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on?response to load transients, while maintaining a relatively constant switching frequency. efficiency is enhanced by the ability to drive very large synchronous- rectifier mosfets. current sensing to ensure reliable overload and inductor saturation protection is available using an external current-sense resistor in series with the output. alternatively, the controller can sense the current across the synchronous rectifier alone or use lossless inductor sensing for lowest power dissipation. single-stage buck conversion allows the max1992/ max1993 to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down from another system supply rail instead of the battery) at the maximum switching fre- quency allows the minimum possible physical size. the max1992 powers the cpu core, chipset, dram, or other supply rails as low as 0.7v. the max1993 powers chipsets and graphics processor cores, which require dynamically adjustable output voltages. the max1993 provides a tracking input that can be used for active ter- mination buses. the max1992/max1993 are available in a 24-pin thin qfn package with optional overvoltage and undervoltage protection. for dual step-down pwm controllers with inductor satu- ration protection, external reference input voltage, and dynamically selectable output voltages, refer to the max1540/max1541 data sheet. applications notebook computers core/io supplies as low as 0.7v 1.8v and 2.5v supplies ddr memory termination (max1993) active termination buses (max1993) cpu/chipset/gpu with dynamic voltage cores (max1993) features ? inductor saturation protection ? accurate current limit ? ultra-high efficiency ? quick-pwm with 100ns load-step response ? max1992 1.8v/2.5v fixed or 0.7v to 5.5v adjustable output range ? max1993 external reference input dynamically selectable output voltage (0.7v to 5.5v) optional power-good and fault blanking during transitions ? ?% v out accuracy over line and load ? 2v to 28v battery input range (v in ) ? 200/300/450/600khz switching frequency ? overvoltage/undervoltage protection option ? 1.7ms digital soft-start ? drives large synchronous rectifier fets ? 2v ?.7% reference output ? power-good window comparator max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ________________________________________________________________ maxim integrated products 1 18 17 16 15 14 19 20 21 22 23 12345 8 9 10 11 12 thin qfn 4mm x 4mm top view max1992 csn vdd pgnd agnd vcc shdn 24 ovp/uvp csp fb n.c. 7 n.c out ilim pgood 6 ref lsat n.c. ton dl bst lx dh v+ 13 skip a "+" sign will replace the first pin indicator on lead-free packages. pin configurations 19-2661; rev 1; 9/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. quick-pwm is a trademark of maxim integrated products, inc. ordering information part temp range pin-package max1992 etg -40? to +85? 24 thin qfn 4mm 4mm MAX1992ETG+ -40? to +85? 24 thin qfn 4mm 4mm max1993 etg -40? to +85? 24 thin qfn 4mm 4mm max1993etg+ -40? to +85? 24 thin qfn 4mm 4mm pin configurations continued at end of data sheet. + denotes lead-free package.
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 2 _______________________________________________________________________________________ absolute maximum ratings (note 1) electrical characteristics (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to agnd............................................................-0.3v to +30v v cc to agnd............................................................-0.3v to +6v v dd to pgnd............................................................-0.3v to +6v pgood, ilim, skip , shdn to agnd ......................-0.3v to +6v refin, fb, csp to agnd.........................................-0.3v to +6v gate, od to gnd (max1993 only) .........................-0.3v to +6v ton, ovp/uvp, lsat to agnd .................-0.3v to (v cc + 0.3v) ref, out to agnd ....................................-0.3v to (v cc + 0.3v) fblank to gnd (max1993 only) ..............-0.3v to (v cc + 0.3v) dl to pgnd................................................-0.3v to (v dd + 0.3v) csn to agnd............................................................-2v to +30v dh to lx .....................................................-0.3v to (bst + 0.3v) lx to agnd ...............................................................-2v to +30v bst to lx..................................................................-0.3v to +6v agnd to pgnd (max1992 only) ..........................-0.3v to +0.3v ref short circuit to agnd.........................................continuous continuous power dissipation (t a = +70?) 24-pin 4mm x 4mm thin qfn (derated 20.8mw/? above +70?)...........................1667mw operating temperature range max199_etg ..................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? note 1: for the max1993, agnd and pgnd refer to a single pin designated gnd. parameter symbol conditions min typ max units pwm controller v in battery voltage, v+ 2 28 input voltage range v bias v cc , v dd 4.5 5.5 v fb = gnd 2.475 2.5 2.525 output voltage accuracy (max1992 fixed) v out max1992 v+ = 4.5v to 28v, skip = v cc (note 2) fb = v cc 1.782 1.8 1.818 v feedback voltage accuracy (max1992 adjustable) v fb max1992 v+ = 4.5v to 28v, skip = v cc (note 2) 0.693 0.7 0.707 v refin = 0.35 ref 0.693 0.7 0.707 feedback voltage accuracy (max1993) v fb max1993 v+ = 4.5v to 28v, skip = v cc (note 2) refin = ref 1.980 2 2.020 v load regulation error i load = 0 to 3a, skip = v cc 0.1 % line regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v 0.25 % fb input bias current i fb -0.1 +0.1 ? output adjust range 0.7 5.5 v fb = gnd 90 190 350 max1992 fb = v cc or adjustable 70 145 270 out input resistance r out max1993 400 800 1400 k out discharge mode on-resistance r discharge 10 25 out synchronous rectifier discharge mode turn-on level 0.2 0.3 0.4 v soft-start ramp time t ss rising edge on shdn to full current limit 1.7 ms
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units ton = gnd (600khz) 170 194 219 ton = ref (450khz) 213 243 273 ton = open (300khz) 316 352 389 on-time t on v+ = 15v, v out = 1.5v (note 3) ton = v cc (200khz) 461 516 571 ns minimum off-time t off ( min ) (note 3) 400 500 ns fb forced above the regulation point, lsat = gnd 0.55 0.85 quiescent supply current (v cc ) i cc fb forced above the regulation point, v lsat > 0.5v 1 ma quiescent supply current (v dd ) i dd fb forced above the regulation point <1 5 a quiescent supply current (v+) i v+ 25 40 ? shutdown supply current (v cc ) shdn = gnd <1 7 a shutdown supply current (v dd ) shdn = gnd <1 5 a shutdown supply current (v+) shdn = gnd, v+ = 28v, v cc = v dd = 0 or 5v <1 5 a reference t a = +25? to +85? 1.986 2 2.014 reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 t a = 0? to +85? 1.983 2 2.017 v reference load regulation v ref i ref = -10? to 50? -0.01 +0.01 v ref lockout voltage v ref ( uvlo ) rising edge, hysteresis = 350mv 1.95 v refin voltage range 0.7 v ref v refin input bias current i refin 0.01 0.05 ? fault detection overvoltage trip threshold with respect to error comparator threshold, ovp/uvp = v cc 12 16 20 % overvoltage fault propagation delay t ovp fb forced 2% above trip threshold 10 ? output undervoltage protection trip threshold with respect to error comparator threshold, ovp/uvp = v cc 65 70 75 % output undervoltage protection blanking time t blank from rising edge of shdn 10 35 ms output undervoltage fault propagation delay t uvp 10 ? pgood lower trip threshold with respect to error comparator threshold, hysteresis = 1% -13 -10 -7 % pgood upper trip threshold with respect to error comparator threshold, hysteresis = 1% +7 +10 +13 % pgood propagation delay t pgood fb forced 2% beyond pgood trip threshold 10 ?
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units pgood output low voltage i sink = 4ma 0.3 v pgood leakage current i pgood fb = ref (pgood high impedance), pgood forced to 5.5v 1a fblank = v cc 120 218 320 fblank = open 80 140 205 fault blanking time t fblank fblank = ref 35 63 95 ? thermal shutdown threshold t shdn hysteresis = 15? 160 ? v cc undervoltage lockout threshold v uvlo ( vcc ) rising edge, pwm disabled below this level hysteresis = 20mv 4.1 4.25 4.4 v current limit ilim adjustment range 0.25 2.00 v csp 0 2.7 current-limit input range csn -0.3 +28.0 v csp/csn input current -0.5 +0.5 ? valley current-limit threshold (fixed) v lim ( val ) v csp - v csn , ilim = v cc 45 50 55 mv v ilim = 250mv 15 25 35 valley current-limit threshold (adjustable) v lim ( val ) v csp - v csn v ilim = 2.00v 170 200 230 mv current-limit threshold (negative) v neg v csp - v csn , skip = ilim = v cc , t a = +25? -75 -60 -45 mv current-limit threshold (zero crossing) v zx with respect to valley current-limit threshold, v csp - v csn , skip = gnd, ilim = v cc 2.5 mv lsat = v cc 180 200 220 lsat = open 157 175 193 inductor saturation current-limit threshold with respect to valley current-limit threshold, ilim = v cc lsat = ref 135 150 165 % ilim saturation fault sink current i ilim ( lsat ) v csp - v csn > inductor saturation current limit, 0.25v < v ilim < 2.0v 468a ilim leakage current v csp - v csn < inductor saturation current limit 0.1 ? gate drivers dh gate driver on-resistance r dh bst - lx forced to 5v 1.5 5 dl, high state 1.5 5 dl gate driver on-resistance r dl dl, low state 0.6 3 dh gate driver source/sink current i dh dh forced to 2.5v, bst - lx forced to 5v 1 a dl gate driver source current i dl ( source ) dl forced to 2.5v 1 a
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages _______________________________________________________________________________________ 5 electrical characteristics (continued) (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dl gate driver sink current i dl ( sink ) dl forced to 2.5v 3 a dl rising 35 dead time t dead dh rising 26 ns inputs and outputs od on-resistance r od gate = v cc 10 25 od leakage current gate = gnd, od forced to 5.5v 1 200 na logic input threshold shdn , skip , gate rising edge, hysteresis = 225mv 1.20 1.7 2.20 v logic input current shdn , skip , gate -1 +1 ? high 1.9 2.0 2.1 dual mode threshold voltage max1992 fb low 0.05 0.1 0.15 v high v cc - 0.4v open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, ovp/uvp, lsat, fblank low 0.5 v four-level logic input current ton, ovp/uvp, lsat, fblank forced to gnd or v cc -3 +3 ? electrical characteristics (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = -40? to +85? , unless otherwise noted.) (note 4) parameter symbol conditions min max units pwm controller v in battery voltage, v+ 2 28 input voltage range v bias v cc , v dd 4.5 5.5 v fb = gnd 2.462 2.538 output voltage accuracy (max1992 fixed) v out max1992, v+ = 4.5v to 28v, skip = v cc (note 2) fb = v cc 1.773 1.827 v feedback voltage accuracy (max1992 adjustable) v fb max1992, v+ = 4.5v to 28v, skip = v cc (note 2) 0.689 0.711 v refin = 0.35 ref 0.689 0.711 feedback voltage accuracy (max1993) v fb max1993, v+ = 4.5v to 28v, skip = v cc (note 2) refin = ref 1.970 2.030 v ton = gnd (600khz) 170 219 ton = ref (450khz) 213 273 ton = open (300khz) 316 389 on-time t on v+ = 15v, v out = 1.5v (note 3) ton = v cc (200khz) 461 571 ns dual mode is a trademark of maxim integrated products, inc.
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 6 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = -40? to +85? , unless otherwise noted.) (note 4) parameter symbol conditions min max units minimum off-time t off ( min ) (note 3) 500 ns fb forced above the regulation point, lsat = gnd 0.85 quiescent supply current (v cc ) i cc fb forced above the regulation point, v lsat > 0.5v 1.0 ma quiescent supply current (v dd ) i dd fb forced above the regulation point 5 ? quiescent supply current (v+) i v+ 40 ? shutdown supply current (v cc ) shdn = gnd 7 a shutdown supply current (v dd ) shdn = gnd 5 a shutdown supply current (v+) shdn = gnd, v+ = 28v, v cc = v dd = 0 or 5v 5a reference reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.980 2.020 v refin voltage range 0.7 v ref v fault detection overvoltage trip threshold with respect to error comparator threshold, ovp/uvp = v cc 10 20 % output undervoltage protection trip threshold with respect to error comparator threshold, ovp/uvp = v cc 65 75 % pgood lower trip threshold with respect to error comparator threshold, hysteresis = 1% -14 -6 % pgood upper trip threshold with respect to error comparator threshold, hysteresis = 1% +6 +14 % v cc undervoltage lockout threshold v uvlo ( vcc ) rising edge, pwm disabled below this level hysteresis = 20mv 4.1 4.4 v current limit csp 0 2.7 current-limit input range csn -0.3 +28.0 v valley current-limit threshold (fixed) v lim ( val ) v csp - v csn , ilim = v cc 35 65 mv valley current-limit threshold (adjustable) v lim ( val ) v csp - v csn , v ilim = 2.00v 160 240 mv
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages _______________________________________________________________________________________ 7 electrical characteristics (continued) (v+ = 15v, v cc = v dd = shdn = 5v, skip = gnd, t a = -40? to +85? , unless otherwise noted.) (note 4) parameter symbol conditions min max units inputs and outputs logic input threshold shdn , skip , gate rising edge, hysteresis = 225mv 1.20 2.20 v high 1.9 2.1 dual mode threshold voltage max1992 fb low 0.05 0.15 v high v cc - 0.4v open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, ovp/uvp, lsat, fblank low 0.5 v note 2: when the inductor is in continuous conduction, the output voltage has a dc regulation level higher than the error compara- tor threshold by 50% of the output ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regulation level higher than the trip level by approximately 1.5% due to slope compensation. note 3: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = gnd, v bst = 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times can differ due to mosfet switching speeds. note 4: specifications to -40? are guaranteed by design, not production tested. typical operating characteristics (max1992 circuit of figure 1, max1993 circuit of figure 9, v in = 12v, v dd = v cc = 5v, skip = v cc , ton = open, t a = +25?, unless otherwise noted.) efficiency vs. load current (v out = 2.5v) max1992 toc01 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 v in = 7v v in = 12v v in = 20v skip = gnd skip = v cc 2.5v output voltage vs. load current max1992 toc02 load current (a) output voltage (v) 4 3 1 2 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.47 05 skip = gnd skip = v cc v in = 7v v in = 20v efficiency vs. load current (v out = 1.8v) max1992 toc03 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 v in = 7v v in = 12v v in = 20v skip = gnd skip = v cc
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 8 _______________________________________________________________________________________ typical operating characteristics (continued) (max1992 circuit of figure 1, max1993 circuit of figure 9, v in = 12v, v dd = v cc = 5v, skip = v cc , ton = open, t a = +25?, unless otherwise noted.) 1.8v output voltage vs. load current max1992 toc04 load current (a) output voltage (v) 4 3 2 1 1.81 1.82 1.83 1.84 1.85 1.80 05 skip = gnd skip = v cc v in = 7v v in = 20v switching frequency vs. load current max1992 toc05 load current (a) switching frequency (khz) 4 3 1 2 50 100 150 200 250 300 350 400 0 05 skip = gnd skip = v cc switching frequency vs. input voltage max1992 toc06 input voltage (v) switching frequency (khz) 24 20 16 12 8 4 240 280 320 360 400 200 028 no load 4a load switching frequency vs. temperature max1992 toc07 temperature ( c) switching frequency (khz) 60 35 10 -15 240 280 320 360 400 200 -40 85 4a load no load maximum output current vs. input voltage max1992 toc08 input voltage (v) maximum i out (a) 24 20 16 12 8 4 4.3 4.6 4.9 5.2 5.5 4.0 028 maximum output current vs. temperature max1992 toc09 temperature ( c) maximum i out (a) 60 35 -15 10 4.9 5.0 5.1 5.2 4.8 -40 85 no-load supply current vs. input voltage (forced-pwm mode) max1992 toc10 input voltage (v) supply current (ma) 24 20 12 16 8 4 1 2 3 4 5 6 7 8 9 10 0 028 i bias i in skip = v cc no-load supply current vs. input voltage (skip mode) max1992 toc11 input voltage (v) supply current (ma) 24 20 16 12 8 4 0.3 0.6 0.9 1.2 1.5 0 028 i in i bias skip = agnd reference load regulation max1992 toc12 i ref ( a) reference voltage (v) 80 60 40 20 0 1.994 1.998 2.002 2.006 2.010 1.990 -20 100
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages _______________________________________________________________________________________ 9 ilim saturation fault current vs. ilim voltage max1992 toc13 v ilim (v) i ilim(lsat) ( a) 1.6 1.2 0.8 0.4 1 2 3 4 5 6 7 0 0 2.0 startup waveforms (heavy load) max1992 toc14 400 s/div 2a 5v 0 b a d c 0 0 5v 2v 4a 0 a. shdn = 0 to 5v; 5v/div b. inductor current: 2a/div c. output voltage (v out ): 2v/div d. pgood: 5v/div, 0.7 load startup waveforms (light load) max1992 toc15 200 s/div 2a 5v 3v b a d c 0 0 0 0 a. shdn = 0 to 5v; 5v/div b. inductor current: 2a/div c. output voltage (v out ): 2v/div d. pgood: 5v/div, 100 load shutdown waveforms (discharge mode disabled) max1992 toc16 20ms/div b a e c a. shdn = 5v to 0; 5v/div b. inductor current: 2a/div c. dl: 5v/div d. output voltage (v out ): 2v/div e. pgood: 5v/div, 100 load, ovp/uvp = open or g d shutdown waveforms (discharge mode enabled) max1992 toc17 1.0ms/div b a e c a. shdn = 5v to 0; 5v/div b. inductor current: 2a/div c. dl: 5v/div d. output voltage (v out ): 2v/div e. pgood: 5v/div, 100 load, ovp/uvp = v cc or ref d 5v 5v 0 0 5v 2.5v 0 0 load transient (forced-pwm operation) max1992 toc18 20 s/div b a c a. load: i out = 0.2a to 4a; 5a/div b. 2.5v output: 100mv/div c. inductor current: 5a/div d. lx: 10v/div, skip = v cc d 2.5v 4a 2.4v 0 0 5a 2.6v 0 12v typical operating characteristics (continued) (max1992 circuit of figure 1, max1993 circuit of figure 9, v in = 12v, v dd = v cc = 5v, skip = v cc , ton = open, t a = +25?, unless otherwise noted.)
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 10 ______________________________________________________________________________________ typical operating characteristics (continued) (max1992 circuit of figure 1, max1993 circuit of figure 9, v in = 12v, v dd = v cc = 5v, skip = v cc , ton = open, t a = +25?, unless otherwise noted.) load transient (pulse-skipping operation) max1992 toc19 20 s/div b a c a. load: i out = 0.2a to 4a; 5a/div b. 2.5v output: 100mv/div c. inductor current: 5a/div d. lx: 10v/div, skip = gnd d 2.5v 4a 2.4v 0 0 5a 2.6v 0 12v output overload waveforms (uvp disabled) max1992 toc20 40 s/div b a c a. load current (0 to 250m ): 10a/div b. 2.5v output: 2v/div c. inductor current: 5a/div d. pgood: 5v/div, ovp/uvp = open or gnd d 2.5v 10a 0 0 0 5a 0 5v output overload waveforms (uvp enabled) max1992 toc21 20 s/div b a c a. load current (0 to 250m ): 10a/div b. 2.5v output: 2v/div c. dl: 5v/div d. inductor current: 5a/div e. pgood: 5v/div, ovp/uvp = v cc or ref e 2.5v 10a 0 0 0 5a 0 5v d 5v 0 inductor saturation protection (lsat disabled) max1992 toc22 20 s/div b a c a. load current: i out = 0 to 5a; 5a/div b. 2.5v output: 200mv/div c. v ilim : 100mv/div d. inductor current: 5a/div; lsat = agnd; l = 3.3 h, 3.5a 2.5v 5a 0 0 7.5a d 0.67v inductor saturation protection ( v ilim = 200mv) max1992 toc23 20 s/div b a c a. load current: i out = 0 to 5a; 5a/div b. 2.5v output: 200mv/div c. v ilim : 200mv/div d. inductor current: 5a/div, lsat = ref; l = 3.3 h, 3.5a 2.5v 5a 0 0 7.5a d 0.67v 0.47v inductor saturation protection ( v ilim = 400mv) max1992 toc24 20 s/div b a c a. load current: i out = 0 to 5a; 5a/div b. 2.5v output: 1v/div c. pgood: 5v/div d. v ilim : 400mv/div e. inductor current: 5a/div, lsat = ref; l = 3.3 h, 3.5a 2.5v 5a 0 0 7.5a d 0.67v e 5v
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 11 max1993 dynamic output voltage transition (c refin = 1nf) max1992 toc25 100 s/div b a c 1.5v 1.5v 2.5a -2.5a 5v 5v 0 0 d e 1.0v a. v gate = 0 to 5v; 5v/div b. output = 1.5v to 1.0v; 0.5v/div c. v refin : 0.5v/div d. pgood: 5v/div e. inductor current: 2.5a/div 100ma load, skip = gnd, circuit of figure 9 max1993 dynamic output voltage transition (c refin = 100pf) max1992 toc26 40 s/div b a c 1.5v 1.5v 5a -5a 5v 5v 0 0 d e 1.0v a. v gate = 0 to 5v; 5v/div b. output = 1.5v to 1.0v; 0.5v/div c. v refin : 0.5v/div d. pgood: 5v/div e. inductor current: 2.5a/div 100ma load, skip = gnd, circuit of figure 9 typical operating characteristics (continued) (max1992 circuit of figure 1, max1993 circuit of figure 9, v in = 12v, v dd = v cc = 5v, skip = v cc , ton = open, t a = +25?, unless otherwise noted.) pin description pin max1992 max1993 name function 11ton on-time selection control input. this four-level logic input sets the k-factor value used to determine the dh on-time (see the on-time one-shot section). connect to analog ground (agnd or gnd), ref, v cc , or leave ton unconnected to select the following nominal switching frequencies: v cc = 200khz open = 300khz ref = 450khz agnd = 600khz 2, 7, 8 n.c. no connection. not internally connected. 2 fblank fault blanking control input. this four-level logic input enables or disables fault blanking, and sets the minimum forced-pwm operation time (t fblank ). when fault blanking is enabled, pgood, ovp protection, and uvp protection are blanked for the selected time period after a transition is detected on gate. additionally, the controller enters forced-pwm mode for the duration of t fblank anytime gate changes states. connect fblank as follows: v cc = 140? (min) t fblank , fault blanking enabled open = 90? (min) t fblank , fault blanking enabled ref = 40? (min) t fblank , fault blanking enabled agnd = 90? (min) t fblank , fault blanking disabled
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 12 ______________________________________________________________________________________ pin description (continued) pin max1992 max1993 name function 3 3 lsat inductor saturation control input. this four-level logic input sets the inductor current saturation limit as a multiple of the valley current-limit threshold set by ilim, or disables the function if not required. connect lsat to the following pins to set the saturation current limit: v cc = 2 i lim(val) open = 1.75 i lim(val) ref = 1.5 i lim(val) agnd = disable lsat protection see the inductor saturation limit and setting the current limit sections. 4 4 pgood open-drain power-good output. pgood is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. after the soft-start circuit has terminated, pgood becomes high impedance if the output is in regulation. for the max1993, pgood is blanked?orced high-impedance state?hen fblank is enabled and the controller detects a transition on gate. 5 5 ilim valley current-limit threshold adjustment. the valley current-limit threshold defaults to 50mv if ilim is tied to v cc . in adjustable mode, the valley current-limit threshold across csp and csn is precisely 1/10th the voltage seen at ilim over a 250mv to 2.5v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. when the inductor saturation protection threshold is exceeded, ilim sinks 6?. see the current-limit protection (ilim) section. 6 6 ref 2.0v reference voltage output. bypass ref to analog ground with a 0.1? or greater ceramic capacitor. the reference can source up to 50? for external loads. loading ref degrades output voltage accuracy according to the ref load regulation error. the reference is disabled when the max1992/max1993 is shut down. 7 refin external reference input. refin sets the feedback regulation voltage (v fb = v refin ) of the max1993. 8 od open-drain output. controlled by gate. 99fb feedback input. max1992: connect to v cc for a +1.8v fixed output or to agnd for a +2.5v fixed output. for an adjustable output (0.7v to 5.5v), connect fb to a resistive divider from the output voltage. the fb regulation level is +0.7v. max1993: the fb regulation level is set by the voltage at refin. 10 10 out output voltage sense. connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (figures 1 and 9). out senses the output voltage to determine the on-time for the high-side switching mosfet. for the max1992, out also serves as the feedback input when using the preset internal output voltages as shown in figure 7. when discharge mode is enabled by ovp/uvp, the output capacitor is discharged through an internal 10 resistor connected between out and ground. 11 11 csp positive current-sense input. connect to the positive terminal of the current-sense element. figure 10 and table 7 describe several current-sensing options. the pwm controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ilim.
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 13 pin description (continued) pin max1992 max1993 name function 12 12 csn negative current-sense input. connect to the negative terminal of the current-sense element. figure 10 and table 7 describe several current-sensing options. the pwm controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ilim. 13 13 skip pulse-skipping control input. connect skip to v cc for low-noise, forced-pwm mode or connect skip to analog ground (agnd or gnd) to enable pulse-skipping operation. 14 14 v+ battery voltage-sense connection. the controller only uses v+ to set the on-time one- shot timing. the dh on-time is inversely proportional to input voltage over a range of 2v to 28v. 15 15 dh high-side gate-driver output. dh swings from lx to bst. 16 16 lx inductor connection. connect lx to the switched side of the inductor. lx serves as the lower supply rail for the dh high-side gate driver. 17 17 bst boost flying capacitor connection. connect to an external capacitor and diode as shown in figure 6. an optional resistor in series with bst allows the dh pullup current to be adjusted. 18 18 dl low-side gate-driver output. dl swings from pgnd to v dd (max1992) or gnd to v dd (max1993). 19 19 v dd supply voltage input for the dl gate driver. connect to the system supply voltage (+4.5v to +5.5v). bypass v dd to pgnd with a 1? or greater ceramic capacitor. 20 pgnd power ground. ground connection for the dl low-side gate driver. 20 gnd analog and power ground. agnd and pgnd connect together internally. connect backside pad to gnd. 21 agnd analog ground. connect backside pad to agnd. 21 gate buffered n-channel mosfet gate input. a logic low on gate turns off the internal mosfet so od appears as a high impedance. a logic high on gate turns on the internal mosfet, pulling od to ground. 22 22 v cc analog supply input. connect to the system supply voltage (+4.5v to +5.5v) through a series 20 resistor. bypass v cc to analog ground with a 1? or greater ceramic capacitor.
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 14 ______________________________________________________________________________________ pin description (continued) pin max1992 max1993 name function 23 23 shdn shutdown control input. connect to v cc for normal operation. connect to analog ground to put the controller into its 1? shutdown state. when discharge mode is enabled by ovp/uvp, the output is discharged through a 10 resistor between out and ground, and dl is forced high after v out drops below 0.3v. when discharge mode is disabled by ovp/uvp, out remains a high-impedance input and dl is forced low, so lx also appears as a high-impedance input. a rising edge on shdn clears the fault-protection latch. 24 24 ovp/uvp overvoltage/undervoltage protection and discharge mode control input. this four- level logic input selects between various output fault-protection options (table 6) by selectively enabling ovp protection and uvp protection. when enabled, the ovp limit defaults at 116% of the nominal output voltage, and the uvp limit defaults at 70% of the nominal output voltage. discharge mode is enabled when uvp protection is also enabled. connect ovp/uvp to the following pins for the desired function: v cc = enable ovp and discharge mode, enable uvp open = enable ovp and discharge mode, disable uvp ref = disable ovp and discharge mode, enable uvp agnd = disable ovp and discharge mode, and uvp see the fault protection and shutdown and output discharge sections. table 1. component selection for standard applications v out = 2.5v at 5a (figure 1) v out = 1.8v at 5a v out = 1.0v / 1.5v at 4a (figure 9) component v in = 7v to 24v, ton = open (300khz) v in = 7v to 24v, ton = open (300khz) v in = 4.5v to 5.5v, ton = gnd (600khz) max1992 fb = agnd fb = v cc not recommended max1993 adjustable fb, refin = ref fb = out, v refin = 1.8v fb = out, v refin = 1.0v / 1.5v c in , input capacitor 10?, 25v taiyo yuden tmk432bj106km 10?, 25v taiyo yuden tmk432bj106km 100?, 10v sanyo poscap 10tpa100m c out , output capacitor 220?, 4v, 15m sanyo poscap 6tpd220m n h high-side mosfet fairchild semiconductor 1/2 fds6982a fairchild semiconductor 1/2 fds6982a fairchild semiconductor 1/2 fds6982s n l low-side mosfet fairchild semiconductor 1/2 fds6982a fairchild semiconductor 1/2 fds6982a fairchild semiconductor 1/2 fds6982s d l schottky rectifier (optional) nihon ep10qs03l 1a, 30v, 0.45vf nihon ep10qs03l 1a, 30v, 0.45vf nihon ep10qs03l 1a, 30v, 0.45vf l1 inductor 4.3? sumida cdep105(l) 3.2? sumida cdep105(l) 1.4? sumida cdep105(l) r sense 15m ?% 0.5w resistor irc lr2010-01-r015f or dale wsl-2010-r015f 15m ?% 0.5w resistor irc lr2010-01-r015f or dale wsl-2010-r015f 15m ?% 0.5w resistor irc lr2010-01-r015f or dale wsl-2010-r015f
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 15 table 2. component suppliers supplier phone website central semiconductor 631-435-1110 (usa) www.centralsemi.com coilcraft 800-322-2645 (usa) www.coilcraft.com coiltronics 561-752-5000 (usa) www.coiltronics.com fairchild semiconductor 888-522-5372 (usa) www.fairchildsemi.com international rectifier 310-322-3331 (usa) www.irf.com kemet 408-986-0424 (usa) www.kemet.com panasonic 714-373-7366 (usa) www.panasonic.com sanyo 65-231-3226 (singapore) 408-749-9714 (usa) www.secc.co.jp siliconix (vishay) 203-268-6261 (usa) www.vishay.com sumida 408-982-9660 (usa) www.sumida.com taiyo yuden 03-3667-3408 (japan) 408-573-4150 (usa) www.t-yuden.com tdk 847-803-6100 (usa) 81-3-5201-7241 (japan) www.component.tdk.com toko 858-675-8013 (usa) www.tokoam.com max1992 power good on off float (300khz) c1 1 f c2 1 f output (v out ) 2.5v c out 220 f input (v in )* 7v to 20v +5v bias supply d bst cmpsh-3 c bst 0.1 f l1 4.3 h r sense 15m n h n l c in 10 f v cc v dd shdn pgood lsat skip ref ilim analog ground *lower input voltages require additional input capacitance. see table 1 for component specifications. bold lines indicate high current traces. ovp/uvp fb out csn csp pgnd dl dh bst v+ r1 20 ton lx agnd d l r2 100k c ref 0.22 f c ilim 470pf r3 100k r4 49.9k power ground figure 1. max1992 standard application circuit
max1992/max1993 detailed description the max1992/max1993 buck controllers are ideal for low-voltage power supplies for notebook computers. maxim? proprietary quick-pwm pulse-width modulator in the max1992/max1993 is designed for handling fast load steps while maintaining a relatively constant oper- ating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architec- ture circumvents the poor load-transient timing prob- lems of fixed-frequency current-mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time pwm schemes. see table 1 for component selections and table 2 for a list of component suppliers. +5v bias supply (v cc and v dd ) the max1992/max1993 require an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebook? 95%-efficient 5v system sup- ply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to sup- ply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an external linear regulator such as the max1615. the 5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f sw (q g(low) + q g(high) ) = 2ma to 20ma (typ) where i cc is 550? (typ), f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheet? total gate-charge specification limits at v gs = 5v. the v+ battery input and 5v bias inputs (v cc and v dd ) can be connected together if the input source is a fixed 4.5v to 5.5v supply. if the 5v bias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the bat- tery voltage is present in order to ensure startup. free-running constant-on-time pwm controller with input feed forward the quick-pwm control architecture is a pseudofixed- frequency, constant on-time, current-mode regulator with voltage feed forward (figure 2). this architecture relies on the output filter capacitor? esr to act as a current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined sole- ly by a one-shot whose pulse width is inversely propor- tional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off- time (400ns typ). the on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the mini- mum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v+ input and is proportional to the output voltage: on-time = k (v out + 0.075v) / v in quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 16 ______________________________________________________________________________________ table 3. approximate k-factor errors ton setting (khz) typical k-factor (?) k-factor error (%) minimum v in at v out = 2.5v (h = 1.5) (v) typical application comments 200 (ton = v cc ) 5.0 ?0 3.14 4-cell li+ notebook use for absolute best efficiency 300 (ton = open) 3.3 ?0 3.47 4-cell li+ notebook considered mainstream by current standards 450 (ton = ref) 2.2 ?2.5 4.13 3-cell li+ notebook useful in 3-cell systems for lighter loads than the cpu core or where size is key 600 (ton = gnd) 1.7 ?2.5 5.61 +5v input good operating point for compound buck designs or desktop circuits
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 17 max1992 max1993 max1993 only out ilim ovp/uvp skip csp zero crossing csn *od pgood *gate *fblank blank 1-shot t off(min) trig q lx dh bst on-time compute v+ ton trig 1-shot q error amp enable ovp enable uvp 1.14 x intref 0.7 x intref 0.9 x intref 1.1 x intref t on quad level decode fblank decode and timer fault latch blank 20ms timer por r s q lsat pgnd dl v dd s r q r s q csp csn r 9r 0.5v quad level decode saturation limit csp ilim fb *refin 13r 0.7v 7r out shdn ref v cc agnd v cc - 1.0v csn current limit intref 2.0v ref max1992 fb decode (figure 7) *max1993 only. in the max1993, agnd and pgnd are internally connected and called gnd. discharge logic max1992 vs. max1993 internal option figure 2. max1992/max1993 functional diagram
max1992/max1993 where k (switching period) is set by the ton pin-strap connection (table 3), and 0.075v is an approximation to accommodate the expected drop across the low-side mosfet switch. this algorithm results in a nearly con- stant switching frequency despite the lack of a fixed-fre- quency clock generator. the benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; 2) the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics (approximately ?2.5% at 600khz and 450khz and ?0% at 200khz and 300khz). on-times at operating points far removed from the conditions specified in the electrical characteristics can vary over a wider range. for example, the 600khz setting typically runs approxi- mately 10% slower with inputs much greater than 5v due to the very short on-times required. the constant on-time translates only roughly to a constant switching frequency. the on-times guaranteed in the electrical characteristics are influenced by resistive loss- es and by switching delays in the high-side mosfet. resistive losses?ncluding the inductor, both mosfets, output capacitor esr, and pc board copper losses in the output and ground?end to raise the switching frequency as the load increases. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times are added to the effective on- time. it occurs only in pwm mode ( skip = v cc ) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor? emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switch- ing frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, includ- ing the high-side switch, inductor, and pc board resis- tances; and t on is the on-time calculated by the max1992/max1993. automatic pulse-skipping mode ( skip = gnd) in skip mode ( skip = gnd), an inherent automatic switchover to pfm takes place at light loads (figure 3). this switchover is affected by a comparator that trun- cates the low-side switch on-time at the inductor cur- rent? zero crossing. the zero-crossing comparator differentially senses the inductor current across the cur- rent-sense resistor (csp to csn). once v csp - v csn drops below 5% of the current-limit threshold (2.5mv for the default 50mv current-limit threshold), the com- parator forces dl low (figure 2). this mechanism caus- es the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to one-half the peak-to-peak ripple current, which is a function of the inductor value (figure 3). this threshold is relatively constant, with only a minor dependence on battery voltage: where k is the on-time scale factor (table 3). for exam- ple, in the standard application circuit (k = 3.3?, v out = 2.5v, v in = 12v, and l = 4.3h), the pulse-skipping switchover occurs at: the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switch- ing waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broad- er efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resis- tance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). 25 33 243 12 2 5 12 076 .. . . . vs h vv v a ? ? ? ? ? ? ? ? ? ? ? ? ? = i vk l vv v load skip out in out in () ? ? ? ? ? ? ? ? ? ? ? ? ? 2 f vv tvv sw out drop on in drop = + + () 1 2 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 18 ______________________________________________________________________________________
dc output accuracy specifications refer to the thresh- old of the error comparator. when the inductor is in continuous conduction, the max1992/max1993 regu- late the valley of the output ripple, so the actual dc out- put voltage is higher than the trip level by 50% of the output ripple voltage. in discontinuous conduction ( skip = gnd and i out < i load(skip) ), the output volt- age has a dc regulation level higher than the error- comparator threshold by approximately 1.5% because of slope compensation. forced-pwm mode ( skip = v cc ) the low-noise forced-pwm mode ( skip = v cc ) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate- drive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while dh maintains a duty factor of v out /v in . forced-pwm mode keeps the switching frequency fairly constant. however, forced-pwm opera- tion comes at a cost: the no-load 5v bias current remains between 2ma and 20ma, depending on the external mosfets and switching frequency. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, and providing sink-current capability for dynamic out- put voltage adjustment. the max1993 uses forced- pwm operation during all dynamic output voltage transitions (gate transition detected) in order to ensure fast, accurate transitions. because forced-pwm opera- tion disables the zero-crossing comparator, the induc- tor current reverses under light loads, quickly discharging the output capacitors. fblank determines how long the max1993 maintains forced-pwm opera- tion?40? (fblank = v cc ), 90? (fblank = open or agnd), or 40? (fblank = ref). current-limit protection (ilim) valley current limit the current-limit circuit employs a unique ?alley?cur- rent-sensing algorithm that uses a current-sense resis- tor between csp and csn as the current-sensing element (figure 10). if the magnitude of the current- sense signal is above the valley current-limit threshold, the pwm controller is not allowed to initiate a new cycle (figure 5). the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current- limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. when combined with the under- voltage protection circuit, this current-limit method is effective in almost every circumstance. max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 19 inductor current i load = i peak /2 on-time 0 time i peak l v in - v out i t = figure 3. pulse-skipping/discontinuous crossover point max1992 max1993 ref ilim 6 a c ref to valley current-limit comparator (figure 2) from lsat comparator and logic (figure 2) c ilim r b r a figure 4. adjustable current-limit threshold inductor current i limit i load 0 time i peak i lim(val) = i load(max) 1- lir 2 () figure 5. ?alley?current-limit threshold point
max1992/max1993 in forced-pwm mode, the max1992/max1993 also implement a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approxi- mately 120% of the positive current limit and tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with an external resistor-divider at ilim. a 2? to 20? divider current is recommended for accuracy and noise immunity. the current-limit threshold adjustment range is from 25mv to 200mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ilim. the threshold defaults to 50mv when ilim is con- nected to v cc . the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the dif- ferential current-sense signals seen by csp and csn. place the ic close to the sense resistor with short, direct traces, making a kelvin-sense connection to the current-sense resistor. inductor saturation limit the lsat connection selects an upper current-sense limit as the inductor saturation threshold or disables the inductor saturation protection feature altogether (lsat = gnd). when enabled, the inductor saturation thresh- old is set as a multiple of the positive valley current-limit threshold (table 4) and tracks the valley current limit when ilim is adjusted. the inductor saturation thresh- old should be selected to give sufficient headroom above the peak inductor current so switching noise does not accidentally trip the saturation protection. selecting too high a threshold can cause an inductor saturation to go undetected. for an inductor with a low lir (the ratio of the inductor ripple current to the designed maximum load current) of approximately 20%, the lowest saturation threshold of 1.5 x i lim(val) (lsat = ref) may be acceptable. when using an inductor with a higher lir, increase the inductor satura- tion threshold accordingly. when inductor saturation is enabled, the max1992/ max1993 continuously monitor the inductor current through the voltage across the current-sense resistor. when the inductor saturation threshold is exceeded, the max1992/max1993 immediately turn off the high-side gate driver and enable a 6a discharge current on ilim (figure 4) at the beginning of the next dh on-time. this reduces the voltage on ilim by v ilim where: where i ilim(lsat) is 6? ilim saturation fault sink cur- rent (see the electrical characteristics table). when using the default 50mv valley current-limit threshold (ilim = v cc ), the ilim saturation fault sink current does not lower the current-limit threshold (see figure 2). if the inductor current remains below the saturation threshold during the next cycle, the ilim discharge cur- rent is disabled, and the ilim voltage returns to its orig- inal set point. the inductor should not remain in saturation once the controller reduces the valley current limit. however, if the inductor remains in saturation, the output voltage may drop low enough to trip the under- voltage fault protection (uvp enabled), causing the max1992/max1993 to shut down and latch off. adding a capacitor from ilim to gnd slows the ilim voltage change by the time constant = (r a //r b ) x c ilim . a suitable time constant is between 5 to 10 switching cycles. if the inductor saturation occurs only during a short load transient, the time constant allows the power supply to recover before the output voltage drops below the output undervoltage threshold. set v ilim to be at least 30% (lir) of the ilim set volt- age. calculate r a and r b using the equations below: inductor saturation works best using a current-sense resistor in series with the inductor. a low-side current- sense resistor configuration can sense the saturation r v i v v with v v set at r r v v a ref ilim lsat ilim ilim set ilim ilim set b a ref ilim set = ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? () () () () % 30 1 v rr rr i ilim ab ab ilim lsat =? + ? ? ? ? ? ? () quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 20 ______________________________________________________________________________________ table 4. lsat configuration table lsat inductor saturation threshold v cc 2.00 i lim(val) open 1.75 i lim(val) ref 1.50 i lim(val) gnd disabled
current only at the start of the off-cycle. see setting the current limit section for various current-sense configu- rations (figure 10) and lsat recommendations. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder- ately sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differ- ential exists. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turn- ing on until dl is off. a similar adaptive dead-time circuit monitors the dh output, preventing the low-side mosfet from turning on until dh is off. there must be a low-resis- tance, low-inductance path from the dl and dh drivers to the mosfet gates in order for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the max1992/max1993 interpret the mosfet gates as ?ff?while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl low is robust, with a 0.6 (typ) on-resistance. this helps prevent dl from being pulled up because of capacitive coupling from the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switches from ground to v in . applications with high-input voltages and long induc- tive driver traces can require additional gate-to-source capacitance to ensure that fast-rising lx edges do not pull up the low-side mosfets gate, causing shoot- through currents. the capacitive coupling between lx and dl created by the mosfet? gate-to-drain capaci- tance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold. lot-to-lot variation of the threshold voltage can cause problems in marginal designs. alternatively, adding a resistor of less than 10 in series with bst can remedy the problem by increasing the turn-on time of the high- side mosfet without degrading the turn-off time (figure 6). por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and soft-start counter, powering up the reference, and preparing the pwm for operation. until v cc reaches 4.25v (typ), v cc undervoltage lockout (uvlo) circuitry inhibits switch- ing. the controller inhibits switching by pulling dh low and holding dl low when ovp and shutdown dis- charge are disabled or forcing dl high when ovp and shutdown discharge are enabled (table 6). when v cc rises above 4.25v, the controller activates the pwm controller and initializes soft-start. soft-start allows a gradual increase of the internal current- limit level during startup to reduce the input surge cur- rents. the max1992/max1993 divide the soft-start period into five phases. during the first phase, the controller lim- its the current limit to only 20% of the full current limit. if the output does not reach regulation within 425?, soft- start enters the second phase, and the current limit is increased by another 20%. this process repeats until the maximum current limit is reached after 1.7ms or when the output reaches the nominal regulation voltage, whichever occurs first (see soft-start waveforms in the typical operating characteristics ). adding a capacitor in parallel with the external ilim resistors creates a continuously adjustable analog soft-start function. vv c c gs th in rss iss () < ? ? ? ? ? ? max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 21 max1992 max1993 v dd bst dh lx (r bst )* (c nl )* d bst c bst c byp input (v in ) n h l v dd dl pgnd n l (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. figure 6. optional gate driver circuitry
max1992/max1993 power-good output (pgood) pgood is the open-drain output for a window com- parator that continuously monitors the output. pgood is actively held low in shutdown and during soft-start. after the digital soft-start terminates, pgood becomes high impedance as long as the output voltage is within ?0% of the nominal regulation voltage set by fb. when the output voltage drops 10% below or rises 10% above the nominal regulation voltage, the max1992/ max1993 pull pgood low. any fault condition forces pgood low until the fault latch is cleared by toggling shdn or cycling v cc power below 1v. for logic level output voltages, connect an external pullup resistor between pgood and v cc . a 100k resistor works well in most applications. note that the pgood window detector is completely independent of the overvoltage and undervoltage pro- tection fault detectors. fault blanking (max1993 fblank) the max1993 automatically enters forced-pwm opera- tion during all dynamic output voltage transitions (gate transition detected) in order to ensure fast, accurate transitions. fblank determines how long the max1993 maintains forced-pwm operation (table 5)?t least 140? (fblank = v cc ), 90? (fblank = open or gnd), or 40? (fblank = ref). when fault blanking is enabled (fblank = v cc , open, or ref), the max1993 also disables the overvoltage and undervoltage fault protection and forces pgood to a high-impedance state during the transition period selected by fblank (table 5). this prevents fault pro- tection from latching off the controller and the pgood signal from going low when the output voltage change ( v out ) cannot occur as fast as the refin voltage change ( v refin ). shutdown and output discharge when output discharge is enabled (ovp/uvp = v cc or open) and shdn is pulled low, or the output undervolt- age fault latch is set (ovp/uvp = v cc or ref), the max1992/max1993 discharge the output through an internal 10 switch to ground. while the output is dis- charging, dl is forced low and the pwm controller is disabled, but the reference remains active to provide an accurate threshold. once the output voltage drops below 0.3v, the max1992/max1993 shut down the ref- erence and pull dl high, effectively clamping the out- put and lx switching node to ground. when output discharge is disabled (ovp/uvp = ref or gnd), the controller does not actively discharge the out- put, and the dl driver remains low. under these condi- tions, the output discharge rate is determined by the load current and output capacitance. the controller detects and latches the discharge mode state set by ovp/uvp on startup. fault protection the max1992/max1993 provide over/undervoltage fault protection. drive ovp/uvp to enable and disable fault protection as shown in table 6. once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. overvoltage protection (ovp) when the output voltage rises above 116% of the nomi- nal regulation voltage and ovp is enabled (ovp/uvp = v cc or open), the ovp circuit sets the fault latch, shuts down the pwm controller, and immediately pulls dh low and forces dl high. this turns on the synchronous rectifi- er mosfet with 100% duty, rapidly discharging the out- put capacitor and clamping the output to ground. note that immediately latching dl high can cause the output voltage to go slightly negative due to energy stored in the output lc at the instant the ovp occurs. if the load cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse- polarity clamp. if the condition that caused the overvolt- age persists (such as a shorted high-side mosfet), the battery fuse blows. ovp is ignored when transitions are detected on gate (max1993 only, fblank enabled). toggle shdn or cycle v cc power below 1v to clear the fault latch and restart the controller. ovp is disabled when ovp/uvp is connected to ref or gnd (table 6). quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 22 ______________________________________________________________________________________ table 5. fblank configuration table fblank fault blanking minimum forced- pwm duration (s) v cc enabled 140 open enabled 90 ref enabled 40 gnd disabled 90
undervoltage protection (uvp) when the output voltage drops below 70%, the nominal regulation voltage and the uvp are enabled (ovp/uvp = v cc or ref), and the controller sets the fault latch and begins the discharge mode (see the shutdown and output discharge section). when the output voltage drops to 0.3v, the synchronous rectifiers turn on, clamp- ing the outputs to gnd. uvp is ignored for at least 10ms (min) after startup ( shdn rising edge) and when transi- tions are detected on gate (max1993 only, fblank enabled). toggle shdn or cycle v cc power below 1v to clear the fault latch and restart the controller. uvp is disabled when ovp/uvp is left open or connect- ed to gnd (table 6). thermal fault protection the max1992/max1993 feature a thermal fault protec- tion circuit. when the junction temperature rises above +160?, a thermal sensor activates the fault latch, pulls pgood low, and shuts down using discharge mode regardless of the ovp/uvp setting. toggle shdn or cycle v cc power below 1v to reactivate the controller after the junction temperature cools by 15?. output voltage preset output voltages (max1992 only) the max1992? dual mode operation allows the selec- tion of common voltages without requiring external components (figure 7). connect fb to agnd for a fixed 2.5v output, to v cc for a fixed 1.8v output, or con- nect fb directly to out for a fixed 0.7v output. setting v out with a resistive voltage-divider at fb the output voltage can be adjusted from 0.7v to 5.5v using a resistive voltage-divider (figure 8). the max1992 regulates fb to a fixed reference voltage (0.7v). alternatively, the max1993 regulates fb to the voltage set at refin, making the max1993 ideal for memory applications in which the termination supply must track the supply voltage. the adjusted output voltage is: where v fb is 0.7v for the max1992 and v fb = v refin for the max1993. vv r r out fb c d =+ ? ? ? ? ? ? 1 max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 23 table 6. fault protection and shutdown setting truth table ovp/uvp shdn discharge* uvp protection ovp protection thermal protection v cc yes. dl forced high when shut down. enabled. discharge sequence activated; dl forced high when shut down. enabled. dh pulled low and dl forced high. enabled. discharge sequence activated; dl forced high when shut down. open yes. dl forced high when shut down. disabled. enabled. dh pulled low and dl forced high. enabled. discharge sequence activated; dl forced high when shut down. ref no. dl forced low when shut down. enabled. discharge sequence activated; dl forced high when shut down. disabled. enabled. discharge sequence activated; dl forced high when shut down. gnd no. dl forced low when shut down. disabled. disabled. enabled. discharge sequence activated; dl forced high when shut down. * discharge-mode state latched on power-up. max1992 to error amplifier fb ref (2.0v) 0.1 x ref (0.2v) 2.5v (fixed) 1.8v (fixed) out figure 7. dual-mode feedback decoder (max1992)
max1992/max1993 dynamic output voltages (max1993 only) the max1993 regulates fb to the voltage set at refin. by changing the voltage at refin, the max1993 can be used in applications that require dynamic output voltage changes between two set points. figure 9 shows a dynamically adjustable resistive voltage- divider network at refin. using the gate signal and open-drain output (od), a resistor can be switched in and out of the refin resistor-divider, changing the volt- age at refin. a logic high on gate turns on the inter- nal n-channel mosfet, forcing od to a low- impedance state. a logic low on gate disables the n- channel mosfet, so od is high impedance. the two output voltages (fb = out) are determined by the fol- lowing equations: the max1993 automatically enters forced-pwm opera- tion on the rising and falling edges of gate and remains in forced-pwm mode for a minimum time selected by fblank (table 5). forced-pwm operation is required to ensure fast, accurate negative voltage transitions when refin is lowered. because forced- pwm operation disables the zero-crossing comparator, the inductor current can reverse under light loads, quickly discharging the output capacitors. if fault blank- ing is enabled, the max1993 also disables the overvolt- age and undervoltage fault protection and forces pgood to a high-impedance state for the period selected by fblank (table 5). for a step voltage change at refin, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. the inductor current ramp is limited by the voltage across the inductor and the inductance. the total output capacitance determines how much current is needed to change the output volt- age. additional load current slows the output voltage change during a positive refin voltage change, and speeds the output voltage change during a negative refin voltage change. increasing the current-limit set- ting speeds a positive output voltage change. adding a capacitor across refin and gnd filters noise and controls the rate-of-change of the refin voltage during dynamic transitions. with the additional capaci- tance, the refin voltage slews between the two set points with a time constant determined by the equiva- lent parallel resistance seen by the slew capacitor (c refin ). referring to figure 9, the time constant for a positive refin voltage transition is: and the time constant for a negative refin voltage transition is: neg refin rr rr c = + ? ? ? ? ? ? 56 56 pos refin rrr rrr c = + () ++ () ? ? ? ? ? ? ? ? 567 567 vv r rr vv rr rrr out low ref out high ref () () = + ? ? ? ? ? ? = + () ++ () ? ? ? ? ? ? ? ? 6 56 67 567 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 24 ______________________________________________________________________________________ max1992 max1993 dl pgnd agnd lx l fb csn csp r d r c c out r sense n l out figure 8. setting v out with a resistive voltage-divider
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 25 max1993 power good on off c1 1 f c2 1 f output v out(high) = 1.5v v out(low) = 1.0v c out 220 f input (v in )* 4.5v to 5.5v +5v bias supply d bst cmpsh-3 c bst 0.1 f l1 1.4 h r sense 15m n h n l c in 10 f v cc v dd shdn pgood lsat ilim gnd (600khz) float (90 s min, fault blanking) v out (low) v out (high) od refin analog ground *lower input voltages require additional input capacitance. see table 1 for component specifications. bold lines indicate high current traces. fblank ton out csn csp gnd dl dh bst v+ r1 20 ref lx fb skip gate d l r2 100k c refin 470pf r6 75k r7 150k power ground r5 75k c ilim 470pf r3 100k r4 49.9k c ref 0.22 f ovp/uvp v out (low) = v ref r6 r5 + r6 ( ) v out (high) = v ref r6 + r7 r5 + (r6 + r7) [ ] figure 9. max1993 standard application circuit
max1992/max1993 design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range . the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to con- nectors, fuses, and battery selector switches. if there is a choice, lower input voltages result in better effi- ciency. maximum load current . there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. switching frequency . this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses pro- portional to frequency and v in 2 . the optimum fre- quency is also a moving target, due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical. inductor operating point . this choice provides trade-offs: size vs. efficiency and transient response vs. output ripple. low inductor values provide better transient response and smaller physical size but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum prac- tical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum oper- ating point is usually found between 20% and 50% ripple current. when pulse skipping ( skip low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 5a, v in = 12v, v out = 2.5v, f sw = 300khz, 30% ripple current or lir = 0.3 find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): most inductor manufacturers provide inductors in stan- dard values, such as 1.0?, 1.5?, 2.2?, 3.3?, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load induc- tance decreases linearly with increasing current), evalu- ate the lir with properly scaled inductance values. transient response the inductor ripple current also affects transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: where t off(min) is the minimum off-time (see the electrical characteristics ) and k is from table 3. v li vk v t cv vv k v t sag load max out in off min out out in out in off min = () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? () () () 2 2 ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vv v khz a h = ? () = 25 12 25 12 300 5 0 3 440 .. . . l vvv v f i lir out in out in sw load max = () ? () quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 26 ______________________________________________________________________________________
the overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i lim(val) equals the minimum valley current-limit threshold voltage divided by the current-sense resis- tance (r sense ). for the 50mv default setting, the mini- mum valley current-limit threshold is 40mv. connect ilim to v cc for a default 50mv valley current- limit threshold. in adjustable mode, the valley current- limit threshold is precisely 1/10th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to analog ground (gnd) with ilim connected to the center tap. the external 250mv to 2v adjustment range corresponds to a 25mv to 200mv valley current-limit threshold. when adjusting the cur- rent limit, use 1% tolerance resistors and a divider cur- rent of approximately 10? to prevent significant inaccuracy in the valley current-limit tolerance. the current-sense method (figure 10) and magnitude determine the achievable current-limit accuracy and power loss (table 7). typically, higher current-sense voltage limits provide tighter accuracy but also dissi- pate more power. most applications employ a valley current-sense volt- age (v lim(val) ) of 50mv to 100mv, so the sense resis- tor can be determined by: r sense = v lim(val) / i lim(val) for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 10a. this configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor saturation protection. for low output voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side mosfet (n l ) and power ground (figure 10b) with csn connected to the drain of n l and csp connected to power ground. in this configuration, the additional current-sense resis- tance only dissipates power when n l is conducting current. inductor saturation protection must be dis- abled with this configuration (lsat = gnd) because the inductor current is only properly sensed when the low-side mosfet is turned on. for high-power applications that do not require high- accuracy current sensing or inductor saturation protec- tion, the max1992/max1993 can use the low-side mosfet? on-resistance as the current-sense element (r sense = r ds(on) ) by connecting csn to the drain of n l and csp to the source of n l (figure 10c). use the worst-case maximum value for r ds(on) from the mosfet data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each ? of temper- ature rise. inductor saturation protection must be dis- abled with this configuration (lsat = gnd) because the inductor current is properly sensed only when the low-side mosfet is turned on. ii i lir lim val load max load max () ( ) () > ? ? ? ? ? ? ? 2 v il cv soar load max out out () () 2 2 max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 27 table 7. current-sense configurations method current-sense accuracy inductor saturation protection current-sense power loss (efficiency) a) output current-sense resistor high allowed (highest accuracy) r sense x i out 2 b) low-side current-sense resistor high not allowed (lsat = gnd) c) low-side mosfet on-resistance low not allowed (lsat = gnd) no additional loss d) equivalent inductor dc resistance low allowed no additional loss 1 2 ? ? ? ? ? ? ? v v ri out in sense out
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 28 ______________________________________________________________________________________ max1992 max1993 v out c out v in l inductor r l c in lsat d) lossless inductor sensing csn csp gnd dl dh lx disable lsat c eq r eq r bias = r eq max1992 max1993 v out c out v in l c in lsat c) low-side mosfet sensing csp gnd csn dl dh lx disable lsat max1992 max1993 v out c out v in l c in r sense lsat b) low-side series resistor sensing csp gnd csn dl dh lx connect to preferred lsat setting max1992 max1993 v out c out v in l c in lsat a) output series resistor sensing gnd dl dh lx connect to preferred lsat setting csn csp r sense figure 10. current-sense configurations
alternatively, high-power applications that require inductor saturation protection can constantly detect the inductor current by connecting a series rc circuit across the inductor (figure 10d) with an equivalent time constant: where r l is the inductor? series dc resistance. in this configuration, the current-sense resistance is equiva- lent to the inductor? dc resistance (r sense = r l ). use the worst-case inductance and r l values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. in all cases, ensure an acceptable valley current-limit threshold voltage and inductor saturation configura- tions despite inaccuracies in sense resistance values. output capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. for processor core voltage converters and other appli- cations in which the output is subject to violent load transients, the output capacitor? size depends on how much esr is needed to prevent the output from dip- ping too low under a load transient. ignoring the sag due to finite capacitance: in applications without large and fast load transients, the output capacitor? size often depends on how much esr is needed to maintain an acceptable level of out- put voltage ripple. the output ripple voltage of a step- down controller equals the total inductor ripple current multiplied by the output capacitor? esr. therefore, the maximum esr required to meet ripple specifications is: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, oscons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high-esr zeros that can affect the overall stability (see the output capacitor stability considerations section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and oscon capacitors in widespread use at the time of publication have typical esr zero frequen- cies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.5a = 16.7m . one 220?/4v sanyo polymer (tpe) capacitor provides 15m (max) esr. this results in a zero at 48khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feed- back loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ?ools?the error comparator into triggering a new cycle immediately after the 400ns minimum off- time period has expired. f rc esr esr out = 1 2 f f esr sw r v i lir esr ripple load max () r v i esr step load max () l r cr l eq eq = max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 29
max1992/max1993 double pulsing is more annoying than harmful, result- ing in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents: for most applications, nontantalum chemistries (ceram- ic, aluminum, or oscon) are preferred due to their resistance to power-up surge currents typical of sys- tems with a mechanical switch or connector in series with the input. if the max1992/max1993 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. in either configuration, choose a capacitor that has less than 10? temperature rise at the rms input current for optimal reliability and lifetime. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, maximum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest possible on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., 8-pin so, dpak, or d 2 pak), and is reasonably priced. ensure that the max1992/max1993 dl gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems can occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power mosfet dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: generally, use a small high-side mosfet to reduce switching losses at high-input voltages. however, the r ds(on) required to stay within package power-dissi- pation limits often limits how small the mosfet can be. the optimum efficiency occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influ- ence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching loss cal- culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ- ing verification using a thermocouple mounted on n h : where c rss is the reverse transfer capacitance of n h , and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied, due to the squared term in the switching- loss equation (c x v in 2 x f sw ). pd n switching vcfi i h in max rss sw load gate () () = () 2 pd n sistive v v ir h out in load ds on (re ) () = ? ? ? ? ? ? () 2 ii vvv v rms load out in out in = () ? ? ? ? ? ? ? ? ? quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 30 ______________________________________________________________________________________
if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ) the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overload conditions that are greater than i load(max) but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, ?verdesign?the cir- cuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. the mosfets must have a relatively large heatsink to han- dle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage drop low enough to prevent the low-side mosfet? body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3 the load current. this diode is optional and can be removed if efficiency is not critical. applications information dropout performance the output voltage adjustable range for continuous-con- duction operation is restricted by the nonadjustable mini- mum off-time one-shot. for best dropout performance, use the slower (200khz) on-time setting. when working with low input voltages, the duty-factor limit must be cal- culated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k-factor. this error is greater at higher frequencies (table 3). also, keep in mind that transient response performance of buck regula- tors operated too close to dropout is poor, and bulk out- put capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down indicates the controller? ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases, unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see the on- time one-shot (ton) section), t off(min) is from the electrical characteristics , and k is taken from table 3. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipat- ed, calculate v sag to be sure of adequate transient response. a dropout design example follows: v out = 2.5v f sw = 300khz k = 3.3?, worst-case k min = 3.0? t off(min) = 500ns v drop1 = v drop2 = 100mv h = 1.5 v vv ns s vv v in min () .. . . .. . = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += ? 25 01 1 1 5 500 30 01 01 347 v vv ht k vv in min out drop off min drop drop () () = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? 1 21 1 ii i lir load valley max load max =+ ? ? ? ? ? ? () () 2 pd n sistive v v ir l out in load ds on (re ) () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ? 1 2 max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 31
max1992/max1993 calculating again with h = 1 and the typical k-factor value (k = 3.3?) gives the absolute limit of dropout: therefore, v in must be greater than 3.06v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47v. multiple output voltage settings (max1993 only) while the max1993 is optimized to work with applica- tions that require two dynamic output voltages, it can produce three or more output voltages if required by using discrete logic or a dac. figure 11 shows an application circuit providing four voltage levels using discrete logic. switching resistors in and out of the resistor network changes the voltage at refin. an edge detection circuit is added to gener- ate a 1? pulse on gate to trigger the fault-blanking and forced-pwm operation. when using pwm mode ( skip = v cc ), the edge detection circuit is only required if fault blanking is enabled. otherwise, leave od unconnected. active bus termination (max1993 only) active bus termination power supplies generate a volt- age rail that tracks a set reference. they are required to source and sink current. ddr memory architecture requires active bus termination. in ddr memory archi- tecture, the termination voltage is set at exactly half the memory supply voltage. configure the max1993 to generate the termination voltage using a resistor- divider at refin. in such an application, the max1993 must be kept in pwm mode ( skip = v cc ) in order for it to source and sink current. figure 12 shows the max1993 configured as a ddr termination regulator. connect gate and fblank to gnd when unused. voltage positioning in applications where fast-load transients occur, the output voltage changes instantly by esr cout x i load . voltage positioning allows the use of fewer out- put capacitors for such applications, and maximizes the output voltage ac and dc tolerance window in tight tolerance applications. figure 13 shows the connection of out and fb in a voltage-positioned circuit. in nonvoltage-positioned cir- cuits, the max1992/max1993 regulate at the output capacitor. in voltage-positioned circuits, the max1992/ max1993 regulate on the inductor side of the current- sense resistor. v out is reduced to: v out(vps) = v out(no load) - r sense i load v vv ns s vv v in min () .. . . .. . = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += ? 25 01 1 1 5 500 33 01 01 306 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 32 ______________________________________________________________________________________ max1993 ref refin gnd gate r4 r3 a c1 r2 r1 b 1000pf 1k 1000pf 1k figure 11. multiple output voltage settings
pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 15). if possible, mount all of the power compo- nents on the topside of the board, with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. minimize current-sensing errors by connecting csp and csn directly across the current-sense resistor (r sense ). when trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst, lx, dh, and dl) away from sensitive analog areas (ref, fb, csp, and csn). layout procedure 1) place the power components first, with ground termi- nals adjacent (n l source, c in , c out , and d l anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the backside opposite n l and n h in order to keep lx, gnd, dh, and the dl gate-drive lines short and wide. the dl and dh gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adap- tive dead-time sensing. 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 9. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power compo- nents go; and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. place the entire dc-to-dc con- verter circuit as close to the load as is practical. max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 33 max1993 c out v in l c in od skip refin gate 10k 10k fblank v ddq = ddr memory supply voltage v tt = termination supply voltage gnd dl 1000pf 1000pf dh lx csn csp r sense fb out v ddq v cc v tt = v ddq 2 figure 12. active bus termination
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages 34 ______________________________________________________________________________________ max1992 c2 voltage-positioned output (v out(vps) ) c out input (v in ) +5v bias supply d bst c bst l1 r sense n h n l c in v cc v dd fb v out(vps) = v out(no load) - r sense i out csn out csp pgnd dl dh bst v+ c1 r1 lx agnd d l figure 13. voltage-positioning output b a a. conventional converter b. voltage-positioned output voltage positioning the output v out esr voltage step (i step x r esr ) capacitive soar (dv/dt = i out /c out ) recovery capacitive sag (dv/dt = i out /c out ) i load figure 14. voltage-positioning transient response
chip information transistor count: 2616 process: bicmos max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages ______________________________________________________________________________________ 35 24 23 22 21 20 1 2 3 4 5 7 8 9 10 11 14 15 16 17 18 thin qfn 4mm x 4mm top view max1993 dl ton fblank lsat pgood ilim 6 ref bst dh v+ 13 skip lx csp out 12 csn fb od refin ovp/uvp shdn v cc gate gnd 19 v dd a "+" sign will replace the first pin indicator on lead-free packages. pin configurations (continued) via to power ground via to analog ground connect gnd and pgnd to the controller at one point only, as shown connect the exposed pad to analog gnd inductor c out c out c in input kelvin sense vias under the sense resistor (see evaluation kit) ground output max1992 figure 15. pc board layout
max1992/max1993 quick-pwm step-down controllers with inductor saturation protection and dynamic output voltages maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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