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intel ? pentium ? m processor with 2-mb l2 cache and 533-mhz front side bus datasheet july 2005 reference number: 305262-002
2 datasheet information in this document is provided in connection wi th intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liabi lity whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended fo r use in medical, life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel? pentium? m processor with 2-mb l2 cache and 533-mhz front side bus may contain design defects or errors known as err ata which may cause the product to deviate from pub lished specifications. curr ent characterized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. ? intel processor numbers are not a measure of performance. proces sor numbers differentiate features within each processor family , not across different processor families. see www.intel .com/products/processor_number for details intel, pentium, and intel speedstep, mmx and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. . *other names and brands may be claimed as the property of others. copyright? 2005, intel corporation. all rights reserved.
datasheet 3 contents 1 introduction.............. ................ ................ ................ ............. ............. ............. ............. .................. 7 1.1 terminology ................................................................................................................. ................. 8 1.2 references .................................................................................................................. ................. 9 2 low power features............................................................................................................ ........ 11 2.1 clock control and low power states ............... .......................................................................... 1 1 2.1.1 normal state.............................................................................................................. .... 11 2.1.2 autohalt powerdown state ......................................................................................... 11 2.1.3 stop-grant state.......................................................................................................... .. 12 2.1.4 halt/grant snoop state............................................................................................... 12 2.1.5 sleep state ............................................................................................................... ..... 12 2.1.6 deep sleep state.......................................................................................................... .13 2.1.7 deeper sleep state ....................................................................................................... 1 3 2.2 enhanced intel speedstep ? technology ................................................................................... 14 2.3 fsb low power enhancements ................................................................................................. 1 5 2.4 processor power status indicator (psi#) sig nal ........................................................................ 15 3 electrical specificati ons ..................................................................................................... ........ 17 3.1 power and ground pins....................................................................................................... ....... 17 3.2 fsb clock (bclk[1:0]) and processor clocking ........................................................................ 17 3.3 voltage identification ...................................................................................................... ............ 17 3.4 catastrophic thermal protection ............................................................................................. ... 18 3.5 signal terminations and unused pins.............. .......................................................................... 1 9 3.6 fsb frequency select signals (bsel[1:0]) ........ ................ ................ ................. ............ .......... 19 3.7 fsb signal groups ........................................................................................................... .......... 19 3.8 cmos signals ................................................................................................................ ............ 20 3.9 maximum ratings ............................................................................................................. .......... 21 3.10 processor dc specifications ................................................................................................ ...... 21 4 package mechanical specifications and pin in formation ....................................................... 27 4.1 processor pinout and pin list............................................................................................... ...... 35 4.2 alphabetical signals reference.............................................................................................. .... 51 5 thermal specifications and de sign considerations................................................................ 59 5.1 thermal specifications ...................................................................................................... ......... 61 5.1.1 thermal diode ............................................................................................................. .. 61 5.1.2 thermal diode offset..................................................................................................... 6 1 5.1.3 intel ? thermal monitor................................................................................................... 62
4 datasheet figures 2-1 clock control states........................................................................................................ ........11 3-1 active vcc and icc load line ...............................................................................................2 3 3-2 deep sleep vcc and icc load line ......................................................................................24 4-1 micro-fcpga package top and bottom isometric views ......................................................27 4-2 micro-fcpga package - top and side views ........................................................................28 4-3 micro-fcpga package - bottom view ................ ....................................................................29 4-4 micro-fcbga package top and bottom isometric view ........................................................31 4-5 micro-fcbga package top and side views ... .......................................................................32 4-6 micro-fcbga package bottom view .................. ....................................................................34 4-7 the coordinates of the proce ssor pins as viewed from the top of the package ..................35 tables 1-1 references .................................................................................................................. .............. 9 3-1 voltage identification definition ........................................................................................... .... 18 3-2 bsel[1:0] encoding for bclk frequency.............. ................ ............. ............. ............. .......... 19 3-3 fsb pin groups.............................................................................................................. ......... 20 3-4 processor dc absolute maximum ratings ............................................................................. 21 3-5 voltage and current specifications ......................................................................................... 2 2 3-6 fsb differential bclk specific ations ...................................................................................... 24 3-7 agtl+ signal group dc specifications....... ........................................................................... 25 3-8 cmos signal group dc specifications .................................................................................. 25 3-9 open drain signal group dc specifications ........................................................................... 26 4-1 micro-fcpga package dimensions ................... .................................................................... 30 4-2 micro-fcbga package dimensions ................... .................................................................... 33 4-3 pin listing by pin name ............................ ......................................................................... ..... 37 4-4 pin listing by pin number ......................... .......................................................................... .... 43 4-5 signal description............ .............................................................................................. .......... 51 5-1 power specifications for intel ? pentium ? m processor........................................................... 60 5-2 thermal diode interface ...... ............................................................................................... ..... 61 5-3 thermal diode specifications ................................................................................................ .. 62
datasheet 5 revision history revision description date 001 initial release january 2005 002 added intel ? pentium ? m processor 780 specifications july 2005
6 datasheet
datasheet 7 introduction 1 introduction the intel ? pentium ? m processor with 533-mhz front side bus (fsb) is the next generation high- performance, low-power mobile processor based on the pentium m processor architecture. all instances of the pentium m processor in this document refer to the pentium m processor with 2-mb l2 cache and 533-mhz front si de bus unless stated otherwise. this document contains specifications for the pentium m processor 780, 770, 760, 750, 740, 730 ? . note: ? intel processor numbers are not a measure of performance. processor numbers differentiate features within each pro cessor family, not across different processor fam ilies. see www.intel.com/ products/processor_number for details. the following list provides some of the key features on this processor: ? supports intel architectur e with dynamic execution ? on-die, primary 32-kb instruction cache and 32-kb write-back data cache ? on-die, 2 mb second level cache with advanced transfer cache architecture ? data prefetch logic ? streaming simd extensions 2 (sse2) ? 533-mhz, source-synchronous fsb ? advanced power management features including enhanced intel speedstep ? technology ? micro-fcpga and micro-fcbga p ackaging technologies, includ ing lead free sli (second level interconnect) technology for the micro-fcbga package (for pentium m processors 780, 770, 760, 750, 740, 730). ? execute disable bit support for enhanced security. the pentium m processor will be manufactured on intel?s advanced 90 nanometer process technology with copper interconnect. the processor maintains support for mmx? technology and internet streaming simd instructions and full compatibility with ia-32 software. the on-die, 32-kb level 1 instruction and data caches alon g with the 2 mb level 2 cache with advanced transfer cache architectur e enable significant performance im provement over ex isting mobile processors. the processor?s data prefetch logic fetches data to the l2 cache before l1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. the streaming simd extensions 2 (sse2) enable break-through levels of performance in multimedia applications including 3-d graphics, video decodi ng/encoding, and speech recognition. the new packed double-precision floating-point instructions enhan ce performance for applications that require greater range and pr ecision, including scientific and engineering applications and advanced 3-d geometry techniques, such as ray tracing. the pentium m processor?s 533-mhz fsb util izes a split-transaction, de ferred reply protocol. the 533-mhz fsb uses source-synchr onous transfer (sst) of address and data to improve performance by transferring data four times per bus clock (4x data transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or 2x address bus. working together, the 4x data bus and 2x
8 datasheet introduction address bus provide a data bus bandwidth of up to 4.3 gb/second. the fsb uses advanced gunning transceiver logic (agtl+) signaling technology, a variant of gtl+ signaling technology with low power enhancements. the processor features enhanced intel speedstep technology, which enables real-time dynamic switching between multiple voltage and frequency points. this results in optimal performance without compromising low power. th e processor features the auto halt, stop grant, deep sleep, and deeper sleep low power states. the pentium m processor utilizes socketable micr o flip-chip pin grid array (micro-fcpga) and surface mount micro flip-chip ba ll grid array (micro-fcbga) p ackage technology. the micro- fcpga package plugs into a 479- hole, surface-mount, zero inserti on force (zif) socket, which is referred to as the mpga479m socket. pentium m processors with cpu signature = 06d8h will also in clude the execute disable bit capability. this feature combined with a support operating system allows memory to be marked as executable or non executable. if code attempts to run in non-executable memory the processor raises an error to the operating system. this feat ure can prevent some cla sses of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. see the intel ? architecture software developer's manual for more detailed information. intel will validate this feature only on intel ? 915 express chipset fami ly-based platforms and recommends customers implement bios changes relate d to this feature, only on intel 915 express chipset family-b ased platforms. note: the term agtl+ is used to refer to assisted gtl+ signalling technology on some intel processors. 1.1 terminology term definition # a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nm i is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). xxxx means that the specification or value is yet to be determined. front side bus (fsb) refers to the interface between the proces sor and system core logic (also known as the chipset components).
datasheet 9 introduction 1.2 references material and concepts available in the following documents may be beneficial when reading this document. chipset references in this document are to intel 915 express chipset family unless specified otherwise. note: all instances of the pentium m processor in this document refer to the pentium m processor with 2-mb l2 cache and 533-mhz front si de bus unless stated otherwise. . note: contact your intel representative for the late st revision and order number of this document. table 1-1. references document document number/location 1 mobile intel ? 915pm/gm/gms and 910gml express chipset datasheet http://www.intel.com/design/ mobile/datashts/305264.htm mobile intel ? 915pm/gm/gms and 910gml express chipset specification update http://www.intel.com/design/ mobile/specupdt/307167.htm intel ? i/o controller hub 6 (ich6) family datasheet http://www.intel.com/design/ chipsets/datashts/301473.htm intel ? i/o controller hub 6 (ich6) family specification update http://www.intel.com/design/ chipsets/specupdt/301474.htm intel ? pentium m processor on 90nm process with 2-mb l2 cache specification update http://www.intel.com/design/ mobile/datashts/302189.htm ia-32 intel ? architecture software developer's manual http://www.intel.com/design/ pentium4/manuals/ index_new.htm volume 1: basic architecture volume 2a: instruction set reference volume 2b: instruction set reference
10 datasheet introduction
datasheet 11 low power features 2 low power features 2.1 clock control and low power states the pentium m processor supports the autohalt, stop grant, sleep, deep sleep, and deeper sleep states for optimal power management. see figure 2-1 for a visual representation of the processor low-power states. 2.1.1 normal state this is the normal operatin g state for the processor. 2.1.2 autohalt powerdown state autohalt is a low-power state en tered when the processor execut es the halt instruction. the processor will transition to th e normal state upon the occurrence of smi# , init#, lint[1:0] (nmi, intr), or fsb interrupt message. res et# will cause the processor to immediately initialize itself. a system management interrupt (smi) handler will return execution to either normal state or the autohalt powerdown state. see the intel architecture software devel oper's manual, volume iii: system programmer's guide for more information. the system can generate a stpclk# while the pr ocessor is in the autohalt powerdown state. when the system deasserts the stpclk# interr upt, the processor will return execution to the halt state. while in autohalt powerdown state, the processor will process bus snoops and interrupts. figure 2-1. clock control states snoop occurs stop grant normal sleep halt/ grant snoop auto halt deep sleep stpclk# asserted slp# asserted slp# de-asserted stpclk# de-asserted snoop serviced hlt instruction snoop serviced snoop occurs dpslp# de-asserted dpslp# asserted stpclk# asserted stpclk# de-asserted halt break v0001-04 core voltage raised core voltage lowered halt break - a20m#, init#, intr, nmi, preq#, reset#, smi#, or apic interrupt deeper sleep
12 datasheet low power features 2.1.3 stop-grant state when the stpclk# pin is asserted, the stop-grant state of the pro cessor is entered 20 bus clocks after the response phase of the processor-issu ed stop grant acknowledge special bus cycle. since the agtl+ signal pins receive power from the fsb, these pins should not be driven (allowing the level to return to v ccp ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the fsb should be driven to the inactive state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the de-assertion of the stpclk# signal. when re-entering the stop-grant state from the sleep st ate, stpclk# should be deasserted ten or more bus clocks after the de-assertion of slp#. a transition to the halt/grant sn oop state will occur when the pr ocessor detects a snoop on the fsb (see section 2.1.4 ). a transition to the sleep state (see section 2.1.5 ) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init# and lint[1:0] will be latched by the processor, and only serviced when the processo r returns to the normal state. only one occurrence of each event will be recognized upon retu rn to the normal state. while in stop-grant state, the processor will process snoops on the fsb and it will latch interrupts delivered on the fsb. the pbe# signal can be driven when the processor is in stop-grant st ate. pbe# will be asserted if there is any pending interrupt latched within th e processor. pending interrupts that are blocked by the eflags.if bit being cl ear will still cause assertion of pb e#. assertion of pbe# indicates to system logic that it should return the processor to the normal state. 2.1.4 halt/grant snoop state the processor will respond to snoop or interrupt transactions on the fsb while in stop-grant state or in autohalt power down state. during a sno op or interrupt transactio n, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the fsb has been serviced (whether by the processor or anothe r agent on the fsb) or the interrupt has been latched. after the snoop is serviced or the interrupt is latched, the processo r will return to the stop- grant state or autohalt power down state, as appropriate. 2.1.5 sleep state the sleep state is a low power state in which th e processor maintains its context, maintains the phase-locked loop (pll), and has stopped all inte rnal clocks. the sleep state can only be entered from stop-grant state. once in the stop-grant stat e, the processor will en ter the sleep state upon the assertion of the slp# signal. the slp# pin should only be asserted when the processor is in the stop grant state. slp# assertions while the processor is not in the stop-grant state is out of specification and may result in unapproved operation. snoop events that occur wh ile in sleep state or during a transi tion into or out of sleep state will cause unpredictable behavior.
datasheet 13 low power features in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the excep tion of slp#, dpslp# or reset#) are allowed on the fsb wh ile the processor is in sleep st ate. any transitio n on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active wh ile the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering an even lowe r power state, the deep sleep state by asserting the dpslp# pin. (see section 2.1.6 .) while the processor is in the sleep state, the slp# pin must be deasserted if another asynchronous fsb event needs to occur. 2.1.6 deep sleep state deep sleep state is a very low po wer state the processor can enter while maintaining context. deep sleep state is entered by asserting the dpslp# pi n while in the sleep state. bclk may be stopped during the deep sleep state for additional platform level power savings. bclk stop/restart timings on intel ? 915pm/gm and intel ? 915gms/ich6-m express chipse t-based platforms with the ck410/ck410m clock chip are as follows: ? deep sleep entry - dpslp# and cpu_stp# are asserted simultaneously. ck410/ck410m will stop/tristate bclk within 2 bclks +/- a few nanoseconds. ? deep sleep exit - dpslp# and cpu_stp# are deasserted simultaneously. ck410/ck410m will drive bclk to differential dc levels with in 2 ~3 ns and starts toggling bclk 2~6 bclk periods later. to re-enter the sleep state, the dpslp# pin mu st be deasserted. bclk can be re-started after dpslp# de-assertion as described above. a pe riod of 30 microseconds (to allow for pll stabilization) must occur before th e processor can be considered to be in the sleep state. once in the sleep state, the slp# pi n must be deasserted to re -enter the stop-grant state. while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions of signals are allowed on the fsb while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. when the processor is in deep sleep state, it wi ll not respond to interrupts or snoop transactions. 2.1.7 deeper sleep state the deeper sleep state is the lowe st state power the processor can en ter. this state is functionally identical to the deep sleep stat e but at a lower core voltage. th e control signals to the voltage regulator to initiate a transition to the deep er sleep state are prov ided on the platform.
14 datasheet low power features 2.2 enhanced intel speedstep ? technology the pentium m processor featur es enhanced intel speedstep technology. unlike previous implementations of intel speedstep technology, this technology enables the processor to switch between multiple frequency and voltage points instead of two. this will enable superior performance with optimal power savings. switching between states is software controlled unlike previous implementations where the ghi# pin is used to toggle between two states. following are the key features of en hanced intel speedstep technology: ? multiple voltage/frequency operating points provide optimal performance at the lowest power. ? voltage/frequency selection is software controlled by writing to processor msr?s (model specific registers) thus el iminating chipset dependency. ? if the target frequency is higher than the curr ent frequency, vcc is ramped up by placing a new value on the vid pins and the pll then locks to the new frequency. ? if the target frequency is lower than the current frequency, the pll locks to the new frequency and the vcc is changed through the vid pin mechanism. ? software transitions are accepted at any time. if a previous transition is in progress, the new transition is deferred until its completion. ? the processor controls voltage ramp rates in ternally to ensure glitch free transitions. ? low transition latency and large number of transitions possible per second. ? processor core (including l2 cach e) is unavailable for up to 10 s during the frequency transition ? the bus protocol (bnr# mechanism) is used to block snooping ? no bus master arbiter disable required prio r to transition and no processor cache flush necessary. ? improved intel ? thermal monitor mode. ? when the on-die thermal sensor indicates th at the die temperature is too high, the processor can automatically perform a transiti on to a lower frequency/voltage specified in a software programmable msr. ? the processor waits for a fixed time period. if the die temperature is down to acceptable levels, an up transition to the prev ious frequency/voltage point occurs. ? an interrupt is generated for the up and down intel thermal monitor transitions enabling better system level thermal management.
datasheet 15 low power features 2.3 fsb low power enhancements the pentium m processor inco rporates the following fs b low power enhancements: ? dynamic fsb power down ? bpri# control for address and control input buffers ? dynamic on die termination disabling ? low vccp (i/o termination voltage) the pentium m processor incorporates the dpwr# signal that controls the data bus input buffers on the processor. the dpwr# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. bpri# control also allows the processor address and control input buffers to be turned off when the bpri# signal is inactive. the on die termination on the processor fsb buffers is disabled when the signals are driven low, resulting in additional power savings. the low i/o termination voltage is on a dedicated voltage plane independen t of the core voltage, enabling low i/o switching power at all times. 2.4 processor power status indicator (psi#) signal the pentium m processor inco rporates the psi# signal that is a sserted when the processor is in a low power (deep sleep or deeper sleep) state. this signal is asserted upo n deep sleep entry and deasserted upon exit. psi# can be used to improve the light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. psi# can also be used to simplify voltage regulator designs since it removes the need for integrated 100 s timers required to mask the pwrgood signal during deeper sleep tr ansitions. it also helps loosen pwrgood monitoring requirements in the deeper sleep state
16 datasheet low power features
datasheet 17 electrical specifications 3 electrical specifications 3.1 power and ground pins for clean, on-chip power distribution, the pentium m processor will have a large number of v cc (power) and v ss (ground) inputs. all power pins must be connected to v cc power planes while all v ss pins must be connected to system ground planes. use of multiple power and ground planes is recommended to reduce i*r drop. the processor v cc pins must be supplied the voltage determined by the vid (voltage id) pins. 3.2 fsb clock (bclk[1:0]) and processor clocking bclk[1:0] directly controls the fsb interface speed as well as the co re frequency of the processor. as in previous generation processors, the pentium m processor core frequency is a multiple of the bclk[1:0] frequency. the pentium m processor uses a differential clocking implementation. 3.3 voltage identification the pentium m processor uses six voltage identif ication pins, vid[5:0], to support automatic selection of power supply voltages. the vid pins for the pentium m processor are cmos outputs driven by the processor vid circuitry. table 3-1 specifies the voltage level corresponding to the state of vid[5:0]. a ?1? in this refers to a high-vol tage level and a ?0? refers to low-voltage level.
18 datasheet electrical specifications table 3-1. voltage identification definition 3.4 catastrophic thermal protection the pentium m processor supports the thermtri p# signal for catastrophic thermal protection. an external thermal sensor should also be used to protect the processor and the system against excessive temperatures. even with the activa tion of thermtrip#, which halts all processor internal clocks and activity, leak age current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. if the external thermal sensor detects a catastrophic pro cessor temperature of 125 c (max imum), or if the thermtrip# signal is asserted, the vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. vid vid 5 4 3 2 1 0 v cc v 5 4 3 2 1 0 v cc v 0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196 0 0 0 0 0 1 1.692 1 0 0 0 0 1 1.180 0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164 0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148 0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132 0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084 0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068 0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052 0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036 0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020 0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004 0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988 0 0 1 1 1 0 1.484 1 0 1 1 1 0 0.972 0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956 0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940 0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924 0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908 0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892 0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876 0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860 0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844 0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828 0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812 0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764 0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748 0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732 0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716 0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700
datasheet 19 electrical specifications 3.5 signal terminations and unused pins all rsvd (reserved) pins must remain unconnected. connection of these pins to v cc , v ss , or to any other signal (including each other) can re sult in component malfunction or incompatibility with future pentium m processors. see section 4.1 for a pin listing of the processor and the location of all rsvd pins. for reliable operation, always connect unused inpu ts or bidirectional signals to an appropriate signal level. unused active low agtl+ inputs may be left as no connects if agtl+ termination is provided on the processor silicon. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected. the test1 and test2 pins must have a stuffing option connection to v ss separately via 1 k ?, pull-down resistors. 3.6 fsb frequency select signals (bsel[1:0]) the bsel[1:0] signals are used to select the fre quency of the processor input clock (bclk[1:0]). these signals should be conn ected to the clock chip and intel 915pm/gm and intel 915gms express chipset on the platform. the bs el encoding for bclk[1:0] is shown in table 3-2 . 3.7 fsb signal groups in order to simplify the following discussion, th e fsb signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when r eceiving. similarly, ?agtl+ output? refers to the agtl+ output group as well as the agtl+ i/o group when driving. with the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals which are dependant upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the s econd set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of bclk0. asychronous signals are st ill present (a20m#, ignne#, et c.) and can become active at any time during the clock cycle. table 3-3 identifies which signal s are common clock, source synchronous, and asynchronous. table 3-2. bsel[1:0] encoding for bclk frequency bsel[1] bsel[0] bclk frequency l h 100 mhz l l 133 mhz h l reserved h h reserved
20 datasheet electrical specifications notes: 1. refer to table 4-5 for signal descr iptions and termination requirements. 2. in processor systems where there is no debug port im plemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. 3. bpm[2:0]# and prdy# are agtl+ output only signals. 3.8 cmos signals cmos input signals are shown in table 3-3 . legacy output ferr#, ierr# and other non-agtl+ signals (thermtrip# and prochot#) utilize open drain output buffers. these signals do not have setup or hold time specifications in relatio n to bclk[1:0]. however, all of the cmos signals are required to be asserted for at least three bcl ks in order for the processor to recognize them. see section 3.10 for the dc and ac specificati ons for the cmos signal groups. table 3-3. fsb pin groups signal group type signals 1 agtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, dpwr#, preq#, reset#, rs[2:0]#, trdy# agtl+ common clock i/o synchronous to bclk[1:0] ads#, bnr#, bpm[3:0]# 3 , br0#, dbsy#, drdy#, hit#, hitm#, lock#, prdy# 3 agtl+ source synchronous i/o synchronous to assoc. strobe agtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# cmos input asynchronous a20m#, dpslp#, ignne#, init#, lint0/intr, lint1/ nmi, pwrgood, smi#, slp#, stpclk# open drain output asynchronous ferr#, ierr#, prochot#, thermtrip# cmos output asynchronous psi#, vid[5:0], bsel[1:0] cmos input synchronous to tck tck, tdi, tms, trst# open drain output synchronous to tck tdo fsb clock clock bclk[1:0], itp_clk[1:0] 2 power/other comp[3:0], dbr# 2 , gtlref, rsvd, test2, test1, thermda, thermdc, v cc , v cca , v cc p, v cc q [1:0], v cc_sense , v ss, v ss_sense signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[31:17]# adstb[1]# d[15:0]#, dinv0# dstbp0#, dstbn0# d[31:16]#, dinv1# dstbp1#, dstbn1# d[47:32]#, dinv2# dstbp2#, dstbn2# d[63:48]#, dinv3# dstbp3#, dstbn3#
datasheet 21 electrical specifications 3.9 maximum ratings table 3-4 lists the processor?s maximum environmental stress ratings. the processor should not receive a clock while subjected to these conditions . functional operating parameters are listed in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains prot ective circuitry to resist damage from electro static discharge (esd), one should always take pr ecautions to avoid high static voltages or electric fields. notes: 1. this rating applies to any processor pin. 2. contact intel for storage requirements in excess of one year. 3.10 processor dc specifications the processor dc specifications in this section are defined at th e processor core (pads) unless noted otherwise. see table 4-5 for the pin signal definitions and signal pin assignments. table through table 3-8 list the dc specifications for the pe ntium m processor and are valid only while meeting specifications for junction temperat ure, clock frequency, and input voltages. the highest frequency mode (hfm) and lowest frequency mode (lfm) refer to the highest and lowest core operating frequencies suppor ted on the processor. active mode load line speci fications apply in all states except in the deep sleep and deeper sleep states. v cc,boot is the default voltage driven by the voltage regulator at power up in order to set the vid values. unless specified otherwise, all specifications for the pe ntium m processor are at tjunction = 100 c. care should be taken to read all notes asso ciated with each parameter. table 3-4. processor dc absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature -40 85 c 2 v cc any processor supply voltage with respect to v ss -0.3 1.6 v 1 v inagtl+ agtl+ buffer dc input voltage with respect to v ss -0.1 1.6 v 1, 2 v inasynch_cmos cmos buffer dc input voltage with respect to v ss -0.1 1.6 v 1, 2
22 datasheet electrical specifications table 3-5. voltage and current specifications symbol parameter min typ max unit notes v cchfm1 vcc at highest frequency mode (hfm) for intel ? pentium ? m processors 730, 740, 750, 760 1.260 1.356 v 1, 2 v cchfm2 vcc at highest frequency mode (hfm) for the pentium m processor 770 1.260 1.372 v 1, 2 v cchfm3 vcc at highest frequency mode (hfm) for the pentium m processor 780 1.260 1.404 v 1, 2 v cclfm vcc at lowest frequency mode (lfm) 0.988 v 1, 2 v cc,boot default v cc voltage for initial power up 1.14 1.20 1.26 v 2 v ccp agtl+ termination voltage 0.997 1.05 1.102 v 2 v cca pll supply voltage 1.425 1.5 1.575 v 2 v ccdprslp, rp1 ripple deeper sleep voltage 0.689 0.748 0.807 v 2,9 v ccdprslp, st1 static deeper sleep voltage 0.699 0.748 0.797 v 2,9 v ccdprslp, rp2 ripple deeper sleep voltage 0.669 0.726 0.783 v 2,9 v ccdprslp, st2 static deeper sleep voltage 0.679 0.726 0.773 v 2,9 i ccdes i cc for pentium m processors recommended design target 27 a 5 i cc icc for pentium m processors a 3,4 processor number core frequency/voltage 780 2.26 ghz and hfm vcc 26 770 2.13 ghz and hfm vcc 26 760 2.0 ghz and hfm vcc 26 750 1.86 ghz and hfm vcc 26 740 1.73 ghz and hfm vcc 26 730 1.6 ghz and hfm vcc 26 not applicable 800 mhz and lfm vcc 12.2 i ah, i sgnt i cc auto-halt & stop-grant a 3,4 lfm 9.2 hfm 23.1 i slp i cc sleep a 3,4 lfm 9.1 hfm 22.7 i dslp i cc deep sleep a 3,4 lfm 8.9 hfm 22.1
datasheet 23 electrical specifications notes: 1. these are vid values. individual pr ocessor vid values may be calibrated during manufacturing such that two devices at the same speed may have different vid se ttings. actual voltage supplie d to the processor should be as specified in the load lines in figures 2 & 3. adherence to load line specifications is required to ensure reliable processor operation. 2. the voltage specifications are assumed to be meas ured at a via on the motherboard?s opposite side of the processor?s socket (or bga) ball with a 100-mh z bandwidth oscilloscope, 1.5-pf maximum probe capacitance, and 1-mohm minimum impedance. the ma ximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 3. specified at 100c tj. 4. specified at the vid voltage. 5. the i ccdes (max) specification comprehends future pr ocessor hfm frequencies. platforms should be designed to this specification. 6. based on simulations and averaged over the durati on of any change in current. specified by design/ characterization at nominal v cc . not 100% tested. 7. measured at the bulk capacitors on the motherboard. 8. the pentium m processor will support deeper sleep volt ages of 0.726v(typical) and 0.748v(typical) with the tolerances specified. a typica l voltage setting between 0.726v and 0.748v may also be used but the minimum/maximum static and ripple tolerances mu st be within the range specified in the table. 9. ? intel processor numbers are not a measure of performanc e. processor numbers differentiate features within each processor family, not acro ss different processor families . see www.intel.com/products/ processor_number for details. i dprslp1 i cc deeper sleep @0.748 v 3.9 a 4,9 i dprslp2 i cc deeper sleep @0.726 v 3.7 a 4,9 di cc/ dt v cc power supply current slew rate 0.5 a/ns 6, 8 i cca i cc for v cca supply 120 ma i ccp i cc for v ccp supply 2.5 a table 3-5. voltage and current specifications symbol parameter min typ max unit notes figure 3-1. active vcc and icc load line
24 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. crossing voltage is defined as abs olute voltage where rising edge of bclk0 is equal to the falling edge of bclk1. 3. threshold region is defined as a region entered about t he crossing voltage in which the differential receiver switches. it includes input threshold hysteresis. 4. for vin between 0 v and v h . 5. cpad includes die capacitance only. no package parasitics are included. 6. ? v cross is defined as the total variation of all crossing voltages as defined in note 2. figure 3-2. deep sleep vcc and icc load line i cc max {hfm|lfm} v cc [v] slope= -3.0 mv/a vcc nom {hfm|lfm} - 1.2% +/-1.5% from nominal =vr error 10mv= ripple i cc [a] 0 deep sleep table 3-6. fsb differenti al bclk specifications symbol parameter min typ max unit notes 1 v l input low voltage 0 v v h input high voltage 0.660 0.710 0.85 v v cross crossing voltage 0.25 0.35 0.55 v 2 ? v cross range of crossing points n/a n/a 0.140 v 6 v th threshold region v cross -0.100 v cross +0.100 v 3 i li input leakage current 100 a 4 cpad pad capacitance 1.8 2.3 2.75 pf 5
datasheet 25 electrical specifications 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. v ih is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. v ih and v oh may experience excursions above vccp. however, input signal drivers must comply with the signal quality specifications in chapter 3 . 5. this is the pull down driver resistance. refer to proc essor i/o buffer models for i/v characteristics. measured at 0.31*vccp. r on (min) = 0.38*r tt , r on (typ) = 0.45*r tt , r on (max) = 0.52*r tt . 6. gtlref should be generated from vccp with a 1% toler ance resistor divider. the vccp referred to in these specifications is the instantaneous vccp. 7. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. measured at 0.31*vccp. r tt is connected to vccp on die. refer to proces sor i/o buffer models for i/v characteristics. 8. specified with on die r tt and r on are turned off. 9. cpad includes die capacitance only. no package parasitics are included. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. the vccp referred to in these specif ications refers to instantaneous vccp. 3. refer to the processor i/o buff er models for i/v characteristics. 4. measured at 0.1*vccp. 5. measured at 0.9*vccp. 6. for vin between 0v and vccp. measured when the driver is tristated. 7. cpad includes die capacitance only. no package parasitics are included. table 3-7. agtl+ signal group dc specifications symbol parameter min typ max unit notes 1 vccp i/o voltage 0.997 1.05 1.102 v gtlref reference voltage 2/3 vccp - 2% 2/3 vccp 2/3 vccp + 2% v6 v ih input high voltage gtlref+0.1 vccp+0.1 v 3,6 v il input low voltage -0.1 gtlref-0.1 v 2,4 v oh output high voltage vccp 6 r tt termination resistance 50 55 61 ?, 7 r on buffer on resistance 22 25 28 ? 5 i li input leakage current 100 a 8 cpad pad capacitance 1.8 2.3 2.75 pf 9 table 3-8. cmos signal group dc specifications symbol parameter min typ max unit notes 1 vccp i/o voltage 0.997 1.05 1.102 v v il input low voltage cmos -0.1 0.3*vccp v 2, 3 v ih input high voltage 0.7*vccp vccp+0.1 v 2 v ol output low voltage -0.1 0 0.1*vccp v 2 v oh output high voltage 0.9*vccp vccp vccp+0.1 v 2 i ol output low current 1.49 4.08 ma 4 i oh output high current 1.49 4.08 ma 5 i li leakage current 100 a 6 cpad pad capacitance 1.0 2.3 3.0 pf
26 datasheet electrical specifications . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. measured at 0.2 v 3. v oh is determined by value of the external pullup resistor to vccp. please refer to platform rddp for details. 4. for vin between 0 v and v oh . 5. cpad includes die capacitance only. no package parasitics are included. table 3-9. open drain sign al group dc specifications symbol parameter min typ max unit notes 1 v oh output high voltage vccp v 3 v ol output low voltage 0 0.20 v i ol output low current 16 50 ma 2 i lo leakage current 200 a 4 cpad pad capacitance 1.7 2.3 3.0 pf 5
datasheet 27 package mechanical specifications and pin information 4 package mechanical specifications and pin information the pentium m processor will be available in 478 pin micro-fcpga and 479 ball micro-fcbga packages. the pentium m processors 780, 770, 760, 750, 740 and 730 will also be available in a lead free sli (second level in terconnect) version of the mi cro-fcbga package. package specifications are the same for all micro-fcbga packages. different views of the micro-fcpga package are shown in figure 4-1 through figure 4-3 . package dimensions are shown in table 4-1 . different views of the micro- fcbga package are shown in figure 4-4 through figure 4-6 . package dimensions are shown in table 4-7 . the micro-fcbga may have capacito rs placed in the area surround ing the die. because the die- side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. doing so may short the capacitors, and possibly damage the device or render it inactive. the use of an insulating material between the capacitors and any thermal so lution should be consider ed to prevent capacitor shorting. note: all dimensions in millimeters. values shown for reference only. refer to table 4-1 for details. figure 4-1. micro-fcpga package top and bottom isometric views top view bottom view label package keepout die capacitor area
28 datasheet package mechanical specifications and pin information note: die is centered. all dimensions in millimeters . values shown for reference only. refer to table 4-1 for details. figure 4-2. micro-fcpga package - top and side views 35 (e) 35 (d) pin a1 corner e1 d1 a 1.25 max (a3) ? 0.32 (b) 478 places 2.03 0.08 (a1) a2 substrate keepout zone do not contact package in s id e th is l in e 7 (k1) 8 places 5 (k) 4 places 0.286 35 (e) 35 (d) pin a1 corner e1 d1 a 1.25 max (a3) ? 0.32 (b) 478 places 2.03 0.08 (a1) a2 substrate keepout zone do not contact package in s id e th is l in e 7 (k1) 8 places 5 (k) 4 places 0.286 0.286
datasheet 29 package mechanical specifications and pin information note: all dimensions in millimeters. values shown for reference only. refer to table 4-1 for details. figure 4-3. micro-fcpga package - bottom view 1 2 3 4 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y aa ab ac ad ae af 25x 1.27 (e) 25x 1.27 (e) 14 (k3) 14 (k3)
30 datasheet package mechanical specifications and pin information 1. overall height with socket is based on design dimens ions of the micro-fcpga package with no thermal solution attached. values are based on design specifications and tolerances . this dimension is subject to change based on socket design, oem motherboard design or oem smt process. 2. all dimensions are prelim inary and subject to change. table 4-1. micro-fcpga package dimensions symbol parameter min max unit a overall height, top of die to package seating plane 1.88 2.02 mm ? overall height, top of die to pcb surface, including socket (refer to note 1) 4.74 5.16 mm a1 pin length 1.95 2.11 mm a2 die height 0.820 mm a3 pin-side capacitor height ? 1.25 mm b pin diameter 0.28 0.36 mm d package substrate length 34.9 35.1 mm e package substrate width 34.9 35.1 mm d1 die length 12.54 mm e1 die width 6.99 mm e pin pitch 1.27 mm k package edge keep-out 5 mm k1 package corner keep-out 7 mm k3 pin-side capacitor boundary 14 mm n pin count 478 each pdie allowable pressure on the die for thermal solution 689 kpa w package weight 4.5 g package surface flatness 0.286 mm
datasheet 31 package mechanical specifications and pin information figure 4-4. micro-fcbga package top and bottom isometric view top view bottom view label die package keepout capacitor area
32 datasheet package mechanical specifications and pin information note: die is centered. all dimensions in millimeters . values shown for reference only. refer to table 4-2 for details. figure 4-5. micro-fcbga package top and side views 35 (e) 35 (d) pin a1 corner e1 d1 a ? 0.78 (b) 479 places k2 substrate keepout zone do not contact package inside this line 7 (k1) 8 places 5 (k) 4 places a2 0.20
datasheet 33 package mechanical specifications and pin information notes: 1. overall height as delivered. values are based on des ign specifications and tole rances. this dimension is subject to change based on oem mother board design or oem smt process. 2. all dimensions are prelim inary and subject to change. table 4-2. micro-fcbga package dimensions symbol parameter min max unit a overall height, as delivered (refer to note 1) 2.60 2.85 mm a2 die height 0.82 mm b ball diameter 0.78 mm d package substrate length 34.9 35.1 mm e package substrate width 34.9 35.1 mm d1 die length 12.54 mm e1 die width 6.99 mm e ball pitch 1.27 mm k package edge keep-out 5 mm k1 package corner keep-out 7 mm k2 die-side capacitor height - 0.7 mm s package edge to first ball center 1.625 mm n ball count 479 each - solder ball coplanarity 0.2 mm pdie allowable pressure on the die for thermal solution - 689 kpa w package weight 4.5 g
34 datasheet package mechanical specifications and pin information note: all dimensions in millim eters. values shown for reference only. refer to ta b l e 4 - 2 for details. figure 4-6. micro-fcbga package bottom view 1 2 3 4 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y aa ab ac ad ae af 25x 1.27 (e) 25x 1.27 (e) 1.625 (s) 4 places 1.625 (s) 4 places
datasheet 35 package mechanical specifications and pin information 4.1 processor pinout and pin list figure 4-7 on the next page shows the top view pinout of pentium m processor. the pin list arranged in two different formats is shown in the following pages. figure 4-7. the coordinates of the processor pins as viewed from the top of the package 12 3 4 56 78910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ignne# ierr# vss slp# dbr# vss bpm[2]# prdy# vss tdo tck vss itp_clk [1] itp_clk [0] vss ther mdc d[0]# vss d[6]# d[2]# vss d[4]# d[1]# vss vss smi# init# vss dpslp# bpm [1]# vss preq# reset# vss trst# bclk1 bclk0 vss proc hot# ther mda vss d[7]# d[3]# vss d[13]# d[9]# vss d[5]# vss a20m# rsvd vss test1 stp clk# vss bpm [0]# bpm [3]# vss tms tdi vss bsel[1] vss bsel[0] therm trip# vss dpwr# d[8]# vss dstbp [0]# dstbn [0]# vss d[15]# d[12]# lint0 vss ferr# lint1 vss vcc vss vcc vss vccp vss vccp vss vccp vss vccp vss vcc vss vcc vss vcc vss d[10]# dinv [0]# vss psi# vid[0] pwr good vcc vss vcc vss vcc vss vccp vss vccp vss vccp vss vcc vss vcc vss vcc vss d[14]# d[11]# vss rsvd vss vid[1] vid[2] vss vss vcc vss vcc vss vccp vss vccp vss vccp vss vccp vss vcc vss vcc vss vcc test2 vss d[21]# vcca vss vid[3] vid[4] vcc vss vcc vss vss d[22]# d[17]# vss rs[0]# drdy# vss vid[5] vss vcc vss vcc d[16]# d[20]# vss d[29]# vss lock# bpri# vss vcc vss vcc vss d[23]# vss d[25]# dinv [1]# rs[1]# vss hit# hitm# vss vccp vss vcc vss dstbn [1]# d[31]# vss bnr# rs[2]# vss defer# vccp vss vccp vss d[18]# dstbp [1]# vss d[26]# dbsy# trdy# vss vss vccp vss vccp d[24]# vss d[28]# d[19]# rsvd ads# vss br0# vccp vss vccp vss vss d[27]# d[30]# vss req[3]# vss req[1]# a[3]# vss vccp vss vccp vccq[0] vss comp [0] comp [1] vss req[0]# a[6]# vss vccp vss vccp vss d[39]# d[37]# vss d[38]# req[4]# req[2]# vss a[9]# vss vccp vss vccp vss dinv [2]# d[34]# vss a[13]# vss adstb [0]# a[4]# vcc vss vccp vss d[35]# vss d[43]# d[41]# vss a[7]# a[5]# vss vss vcc vss vcc d[36]# d[42]# vss d[44]# a[8]# a[10]# vss vccq[1] vcc vss vcc vss vss dstbp [2]# dstbn [2]# vss a[12]# vss a[15]# vss vcc vss vcc d[45]# vss d[47]# d[32]# vss a[16]# a[14]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[40]# d[33]# vss d[46]# comp [3] comp [2] vss a[24]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[50]# d[48]# vss rsvd vss a[20]# a[18]# vss a[25]# a[19]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc d[51]# vss d[52]# d[49]# vss d[53]# rsvd vss a[23]# a[21]# vss a[26]# a[28]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss dinv [3]# d[60]# vss d[54]# d[57]# vss gtlref a[30]# a[27]# vss a[22]# adstb [1]# vss vcc sense vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[59]# d[55]# vss dstbn [3]# dstbp [3]# vss a[31] # a[31]# vss a[29]# a[17]# vss vss sense rsvd vcc vss vcc vss vcc vcc vss vcc vss vcc vss d[58]# vss d[62]# d[56]# vss d[61]# d[63]# a b c d e f g h k l m n p r t u v w y aa ab ac ad ae af vss 123456 789101112131415161718192021 22 23 24 25 26 vss vcc other vss a[11]# vss top view rsvd pin b2 is depopulated on the micro-fcpga package rsvd rsvd vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af j
36 datasheet package mechanical specifications and pin information this page is intentionally left blank.
37 datasheet table 4-3. pin listing by pin name pin name pin number signal buffer type direction a[3]# p4 source synch input/output a[4]# u4 source synch input/output a[5]# v3 source synch input/output a[6]# r3 source synch input/output a[7]# v2 source synch input/output a[8]# w1 source synch input/output a[9]# t4 source synch input/output a[10]# w2 source synch input/output a[11]# y4 source synch input/output a[12]# y1 source synch input/output a[13]# u1 source synch input/output a[14]# aa3 source synch input/output a[15]# y3 source synch input/output a[16]# aa2 source synch input/output a[17]# af4 source synch input/output a[18]# ac4 source synch input/output a[19]# ac7 source synch input/output a[20]# ac3 source synch input/output a[21]# ad3 source synch input/output a[22]# ae4 source synch input/output a[23]# ad2 source synch input/output a[24]# ab4 source synch input/output a[25]# ac6 source synch input/output a[26]# ad5 source synch input/output a[27]# ae2 source synch input/output a[28]# ad6 source synch input/output a[29]# af3 source synch input/output a[30]# ae1 source synch input/output a[31]# af1 source synch input/output a20m# c2 cmos input ads# n2 common clock input/output adstb[0]# u3 source synch input/output adstb[1]# ae5 source synch input/output bclk[0] b15 bus clock input bclk[1] b14 bus clock input bnr# l1 common clock input/output bpm[0]# c8 common clock output bpm[1]# b8 common clock output bpm[2]# a9 common clock output bpm[3]# c9 common clock input/output bpri# j3 common clock input br0# n4 common clock input/output bsel[1] c14 cmos output bsel[0] c16 cmos output comp[0] p25 power/other input/output comp[1] p26 power/other input/output comp[2] ab2 power/other input/output comp[3] ab1 power/other input/output d[0]# a19 source synch input/output d[1]# a25 source synch input/output d[2]# a22 source synch input/output d[3]# b21 source synch input/output d[4]# a24 source synch input/output d[5]# b26 source synch input/output d[6]# a21 source synch input/output d[7]# b20 source synch input/output d[8]# c20 source synch input/output d[9]# b24 source synch input/output d[10]# d24 source synch input/output d[11]# e24 source synch input/output d[12]# c26 source synch input/output d[13]# b23 source synch input/output d[14]# e23 source synch input/output d[15]# c25 source synch input/output d[16]# h23 source synch input/output d[17]# g25 source synch input/output d[18]# l23 source synch input/output d[19]# m26 source synch input/output d[20]# h24 source synch input/output d[21]# f25 source synch input/output d[22]# g24 source synch input/output d[23]# j23 source synch input/output d[24]# m23 source synch input/output d[25]# j25 source synch input/output d[26]# l26 source synch input/output table 4-3. pin listing by pin name pin name pin number signal buffer type direction
datasheet 38 d[27]# n24 source synch input/output d[28]# m25 source synch input/output d[29]# h26 source synch input/output d[30]# n25 source synch input/output d[31]# k25 source synch input/output d[32]# y26 source synch input/output d[33]# aa24 source synch input/output d[34]# t25 source synch input/output d[35]# u23 source synch input/output d[36]# v23 source synch input/output d[37]# r24 source synch input/output d[38]# r26 source synch input/output d[39]# r23 source synch input/output d[40]# aa23 source synch input/output d[41]# u26 source synch input/output d[42]# v24 source synch input/output d[43]# u25 source synch input/output d[44]# v26 source synch input/output d[45]# y23 source synch input/output d[46]# aa26 source synch input/output d[47]# y25 source synch input/output d[48]# ab25 source synch input/output d[49]# ac23 source synch input/output d[50]# ab24 source synch input/output d[51]# ac20 source synch input/output d[52]# ac22 source synch input/output d[53]# ac25 source synch input/output d[54]# ad23 source synch input/output d[55]# ae22 source synch input/output d[56]# af23 source synch input/output d[57]# ad24 source synch input/output d[58]# af20 source synch input/output d[59]# ae21 source synch input/output d[60]# ad21 source synch input/output d[61]# af25 source synch input/output d[62]# af22 source synch input/output d[63]# af26 source synch input/output dbr# a7 cmos output table 4-3. pin listing by pin name pin name pin number signal buffer type direction dbsy# m2 common clock input/output defer# l4 common clock input dinv[0]# d25 source synch input/output dinv[1]# j26 source synch input/output dinv[2]# t24 source synch input/output dinv[3]# ad20 source synch input/output dpslp# b7 cmos input dpwr# c19 common clock input drdy# h2 common clock input/output dstbn[0]# c23 source synch input/output dstbn[1]# k24 source synch input/output dstbn[2]# w25 source synch input/output dstbn[3]# ae24 source synch input/output dstbp[0]# c22 source synch input/output dstbp[1]# l24 source synch input/output dstbp[2]# w24 source synch input/output dstbp[3]# ae25 source synch input/output ferr# d3 open drain output gtlref ad26 power/other input hit# k3 common clock input/output hitm# k4 common clock input/output ierr# a4 open drain output ignne# a3 cmos input init# b5 cmos input itp_clk[0] a16 cmos input itp_clk[1] a15 cmos input lint0 d1 cmos input lint1 d4 cmos input lock# j2 common clock input/output prdy# a10 common clock output preq# b10 common clock input prochot# b17 open drain output psi# e1 cmos output pwrgood e4 cmos input req[0]# r2 source synch input/output req[1]# p3 source synch input/output req[2]# t2 source synch input/output req[3]# p1 source synch input/output table 4-3. pin listing by pin name pin name pin number signal buffer type direction
39 datasheet req[4]# t1 source synch input/output reset# b11 common clock input rs[0]# h1 common clock input rs[1]# k1 common clock input rs[2]# l2 common clock input rsvd af7 reserved rsvd b2 reserved rsvd g1 reserved rsvd c3 reserved rsvd e26 reserved rsvd ac1 reserved rsvd b1 power/other rsvd n1 power/other rsvd ac26 power/other slp# a6 cmos input smi# b4 cmos input stpclk# c6 cmos input tck a13 cmos input tdi c12 cmos input tdo a12 open drain output test1 c5 test test2 f23 test thermda b18 power/other thermdc a18 power/other thermtrip# c17 open drain output tms c11 cmos input trdy# m3 common clock input trst# b13 cmos input vcc d6 power/other vcc d8 power/other vcc d18 power/other vcc d20 power/other vcc d22 power/other vcc e5 power/other vcc e7 power/other vcc e9 power/other vcc e17 power/other vcc e19 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction vcc e21 power/other vcc f6 power/other vcc f8 power/other vcc f18 power/other vcc f20 power/other vcc f22 power/other vcc g5 power/other vcc g21 power/other vcc h6 power/other vcc h22 power/other vcc j5 power/other vcc j21 power/other vcc k22 power/other vcc u5 power/other vcc v6 power/other vcc v22 power/other vcc w5 power/other vcc w21 power/other vcc y6 power/other vcc y22 power/other vcc aa5 power/other vcc aa7 power/other vcc aa9 power/other vcc aa11 power/other vcc aa13 power/other vcc aa15 power/other vcc aa17 power/other vcc aa19 power/other vcc aa21 power/other vcc ab6 power/other vcc ab8 power/other vcc ab10 power/other vcc ab12 power/other vcc ab14 power/other vcc ab16 power/other vcc ab18 power/other vcc ab20 power/other vcc ab22 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction
datasheet 40 vcc ac9 power/other vcc ac11 power/other vcc ac13 power/other vcc ac15 power/other vcc ac17 power/other vcc ac19 power/other vcc ad8 power/other vcc ad10 power/other vcc ad12 power/other vcc ad14 power/other vcc ad16 power/other vcc ad18 power/other vcc ae9 power/other vcc ae11 power/other vcc ae13 power/other vcc ae15 power/other vcc ae17 power/other vcc ae19 power/other vcc af8 power/other vcc af10 power/other vcc af12 power/other vcc af14 power/other vcc af16 power/other vcc af18 power/other vcca f26 power/other vccp d10 power/other vccp d12 power/other vccp d14 power/other vccp d16 power/other vccp e11 power/other vccp e13 power/other vccp e15 power/other vccp f10 power/other vccp f12 power/other vccp f14 power/other vccp f16 power/other vccp k6 power/other vccp l5 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction vccp l21 power/other vccp m6 power/other vccp m22 power/other vccp n5 power/other vccp n21 power/other vccp p6 power/other vccp p22 power/other vccp r5 power/other vccp r21 power/other vccp t6 power/other vccp t22 power/other vccp u21 power/other vccq[0] p23 power/other vccq[1] w4 power/other vccsense ae7 power/other output vid[0] e2 cmos output vid[1] f2 cmos output vid[2] f3 cmos output vid[3] g3 cmos output vid[4] g4 cmos output vid[5] h4 cmos output vss a2 power/other vss a5 power/other vss a8 power/other vss a11 power/other vss a14 power/other vss a17 power/other vss a20 power/other vss a23 power/other vss a26 power/other vss b3 power/other vss b6 power/other vss b9 power/other vss b12 power/other vss b16 power/other vss b19 power/other vss b22 power/other vss b25 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction
41 datasheet vss c1 power/other vss c4 power/other vss c7 power/other vss c10 power/other vss c13 power/other vss c15 power/other vss c18 power/other vss c21 power/other vss c24 power/other vss d2 power/other vss d5 power/other vss d7 power/other vss d9 power/other vss d11 power/other vss d13 power/other vss d15 power/other vss d17 power/other vss d19 power/other vss d21 power/other vss d23 power/other vss d26 power/other vss e3 power/other vss e6 power/other vss e8 power/other vss e10 power/other vss e12 power/other vss e14 power/other vss e16 power/other vss e18 power/other vss e20 power/other vss e22 power/other vss e25 power/other vss f1 power/other vss f4 power/other vss f5 power/other vss f7 power/other vss f9 power/other vss f11 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction vss f13 power/other vss f15 power/other vss f17 power/other vss f19 power/other vss f21 power/other vss f24 power/other vss g2 power/other vss g6 power/other vss g22 power/other vss g23 power/other vss g26 power/other vss h3 power/other vss h5 power/other vss h21 power/other vss h25 power/other vss j1 power/other vss j4 power/other vss j6 power/other vss j22 power/other vss j24 power/other vss k2 power/other vss k5 power/other vss k21 power/other vss k23 power/other vss k26 power/other vss l3 power/other vss l6 power/other vss l22 power/other vss l25 power/other vss m1 power/other vss m4 power/other vss m5 power/other vss m21 power/other vss m24 power/other vss n3 power/other vss n6 power/other vss n22 power/other vss n23 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction
datasheet 42 vss n26 power/other vss p2 power/other vss p5 power/other vss p21 power/other vss p24 power/other vss r1 power/other vss r4 power/other vss r6 power/other vss r22 power/other vss r25 power/other vss t3 power/other vss t5 power/other vss t21 power/other vss t23 power/other vss t26 power/other vss u2 power/other vss u6 power/other vss u22 power/other vss u24 power/other vss v1 power/other vss v4 power/other vss v5 power/other vss v21 power/other vss v25 power/other vss w3 power/other vss w6 power/other vss w22 power/other vss w23 power/other vss w26 power/other vss y2 power/other vss y5 power/other vss y21 power/other vss y24 power/other vss aa1 power/other vss aa4 power/other vss aa6 power/other vss aa8 power/other vss aa10 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction vss aa12 power/other vss aa14 power/other vss aa16 power/other vss aa18 power/other vss aa20 power/other vss aa22 power/other vss aa25 power/other vss ab3 power/other vss ab5 power/other vss ab7 power/other vss ab9 power/other vss ab11 power/other vss ab13 power/other vss ab15 power/other vss ab17 power/other vss ab19 power/other vss ab21 power/other vss ab23 power/other vss ab26 power/other vss ac2 power/other vss ac5 power/other vss ac8 power/other vss ac10 power/other vss ac12 power/other vss ac14 power/other vss ac16 power/other vss ac18 power/other vss ac21 power/other vss ac24 power/other vss ad1 power/other vss ad4 power/other vss ad7 power/other vss ad9 power/other vss ad11 power/other vss ad13 power/other vss ad15 power/other vss ad17 power/other vss ad19 power/other table 4-3. pin listing by pin name pin name pin number signal buffer type direction
43 datasheet vss ad22 power/other vss ad25 power/other vss ae3 power/other vss ae6 power/other vss ae8 power/other vss ae10 power/other vss ae12 power/other vss ae14 power/other vss ae16 power/other vss ae18 power/other vss ae20 power/other vss ae23 power/other vss ae26 power/other vss af2 power/other vss af5 power/other vss af9 power/other vss af11 power/other vss af13 power/other vss af15 power/other vss af17 power/other vss af19 power/other vss af21 power/other vss af24 power/other vsssense af6 power/other output table 4-4. pin listing by pin number pin number pin name signal buffer type direction a2 vss power/other a3 ignne# cmos input a4 ierr# open drain output a5 vss power/other a6 slp# cmos input a7 dbr# cmos output a8 vss power/other a9 bpm[2]# common clock output a10 prdy# common clock output a11 vss power/other a12 tdo open drain output table 4-3. pin listing by pin name pin name pin number signal buffer type direction a13 tck cmos input a14 vss power/other a15 itp_clk[1] cmos input a16 itp_clk[0] cmos input a17 vss power/other a18 thermdc power/other a19 d[0]# source synch input/output a20 vss power/other a21 d[6]# source synch input/output a22 d[2]# source synch input/output a23 vss power/other a24 d[4]# source synch input/output a25 d[1]# source synch input/output a26 vss power/other aa1 vss power/other aa2 a[16]# source synch input/output aa3 a[14]# source synch input/output aa4 vss power/other aa5 vcc power/other aa6 vss power/other aa7 vcc power/other aa8 vss power/other aa9 vcc power/other aa10 vss power/other aa11 vcc power/other aa12 vss power/other aa13 vcc power/other aa14 vss power/other aa15 vcc power/other aa16 vss power/other aa17 vcc power/other aa18 vss power/other aa19 vcc power/other aa20 vss power/other aa21 vcc power/other aa22 vss power/other aa23 d[40]# source synch input/output aa24 d[33]# source synch input/output table 4-4. pin listing by pin number pin number pin name signal buffer type direction
datasheet 44 aa25 vss power/other aa26 d[46]# source synch input/output ab1 comp[3] power/other input/output ab2 comp[2] power/other input/output ab3 vss power/other ab4 a[24]# source synch input/output ab5 vss power/other ab6 vcc power/other ab7 vss power/other ab8 vcc power/other ab9 vss power/other ab10 vcc power/other ab11 vss power/other ab12 vcc power/other ab13 vss power/other ab14 vcc power/other ab15 vss power/other ab16 vcc power/other ab17 vss power/other ab18 vcc power/other ab19 vss power/other ab20 vcc power/other ab21 vss power/other ab22 vcc power/other ab23 vss power/other ab24 d[50]# source synch input/output ab25 d[48]# source synch input/output ab26 vss power/other ac1 rsvd reserved ac2 vss power/other ac3 a[20]# source synch input/output ac4 a[18]# source synch input/output ac5 vss power/other ac6 a[25]# source synch input/output ac7 a[19]# source synch input/output ac8 vss power/other ac9 vcc power/other ac10 vss power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction ac11 vcc power/other ac12 vss power/other ac13 vcc power/other ac14 vss power/other ac15 vcc power/other ac16 vss power/other ac17 vcc power/other ac18 vss power/other ac19 vcc power/other ac20 d[51]# source synch input/output ac21 vss power/other ac22 d[52]# source synch input/output ac23 d[49]# source synch input/output ac24 vss power/other ac25 d[53]# source synch input/output ac26 rsvd reserved ad1 vss power/other ad2 a[23]# source synch input/output ad3 a[21]# source synch input/output ad4 vss power/other ad5 a[26]# source synch input/output ad6 a[28]# source synch input/output ad7 vss power/other ad8 vcc power/other ad9 vss power/other ad10 vcc power/other ad11 vss power/other ad12 vcc power/other ad13 vss power/other ad14 vcc power/other ad15 vss power/other ad16 vcc power/other ad17 vss power/other ad18 vcc power/other ad19 vss power/other ad20 dinv[3]# source synch input/output ad21 d[60]# source synch input/output ad22 vss power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction
45 datasheet ad23 d[54]# source synch input/output ad24 d[57]# source synch input/output ad25 vss power/other ad26 gtlref power/other ae1 a[30]# source synch input/output ae2 a[27]# source synch input/output ae3 vss power/other ae4 a[22]# source synch input/output ae5 adstb[1]# source synch input/output ae6 vss power/other ae7 vccsense power/other output ae8 vss power/other ae9 vcc power/other ae10 vss power/other ae11 vcc power/other ae12 vss power/other ae13 vcc power/other ae14 vss power/other ae15 vcc power/other ae16 vss power/other ae17 vcc power/other ae18 vss power/other ae19 vcc power/other ae20 vss power/other ae21 d[59]# source synch input/output ae22 d[55]# source synch input/output ae23 vss power/other ae24 dstbn[3]# source synch input/output ae25 dstbp[3]# source synch input/output ae26 vss power/other af1 a[31]# source synch input/output af2 vss power/other af3 a[29]# source synch input/output af4 a[17]# source synch input/output af5 vss power/other af6 vsssense power/other output af7 rsvd reserved af8 vcc power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction af9 vss power/other af10 vcc power/other af11 vss power/other af12 vcc power/other af13 vss power/other af14 vcc power/other af15 vss power/other af16 vcc power/other af17 vss power/other af18 vcc power/other af19 vss power/other af20 d[58]# source synch input/output af21 vss power/other af22 d[62]# source synch input/output af23 d[56]# source synch input/output af24 vss power/other af25 d[61]# source synch input/output af26 d[63]# source synch input/output b1 rsvd reserved b2 rsvd reserved b3 vss power/other b4 smi# cmos input b5 init# cmos input b6 vss power/other b7 dpslp# cmos input b8 bpm[1]# common clock output b9 vss power/other b10 preq# common clock input b11 reset# common clock input b12 vss power/other b13 trst# cmos input b14 bclk[1] bus clock input b15 bclk[0] bus clock input b16 vss power/other b17 prochot# open drain output b18 thermda power/other b19 vss power/other b20 d[7]# source synch input/output table 4-4. pin listing by pin number pin number pin name signal buffer type direction
datasheet 46 b21 d[3]# source synch input/output b22 vss power/other b23 d[13]# source synch input/output b24 d[9]# source synch input/output b25 vss power/other b26 d[5]# source synch input/output c1 vss power/other c2 a20m# cmos input c3 rsvd reserved c4 vss power/other c5 test1 test c6 stpclk# cmos input c7 vss power/other c8 bpm[0]# common clock output c9 bpm[3]# common clock input/output c10 vss power/other c11 tms cmos input c12 tdi cmos input c13 vss power/other c14 bsel[1] cmos output c15 vss power/other c16 bsel[0] cmos output c17 thermtrip# open drain output c18 vss power/other c19 dpwr# common clock input c20 d[8]# source synch input/output c21 vss power/other c22 dstbp[0]# source synch input/output c23 dstbn[0]# source synch input/output c24 vss power/other c25 d[15]# source synch input/output c26 d[12]# source synch input/output d1 lint0 cmos input d2 vss power/other d3 ferr# open drain output d4 lint1 cmos input d5 vss power/other d6 vcc power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction d7 vss power/other d8 vcc power/other d9 vss power/other d10 vccp power/other d11 vss power/other d12 vccp power/other d13 vss power/other d14 vccp power/other d15 vss power/other d16 vccp power/other d17 vss power/other d18 vcc power/other d19 vss power/other d20 vcc power/other d21 vss power/other d22 vcc power/other d23 vss power/other d24 d[10]# source synch input/output d25 dinv[0]# source synch input/output d26 vss power/other e1 psi# cmos output e2 vid[0] cmos output e3 vss power/other e4 pwrgood cmos input e5 vcc power/other e6 vss power/other e7 vcc power/other e8 vss power/other e9 vcc power/other e10 vss power/other e11 vccp power/other e12 vss power/other e13 vccp power/other e14 vss power/other e15 vccp power/other e16 vss power/other e17 vcc power/other e18 vss power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction
47 datasheet e19 vcc power/other e20 vss power/other e21 vcc power/other e22 vss power/other e23 d[14]# source synch input/output e24 d[11]# source synch input/output e25 vss power/other e26 rsvd reserved f1 vss power/other f2 vid[1] cmos output f3 vid[2] cmos output f4 vss power/other f5 vss power/other f6 vcc power/other f7 vss power/other f8 vcc power/other f9 vss power/other f10 vccp power/other f11 vss power/other f12 vccp power/other f13 vss power/other f14 vccp power/other f15 vss power/other f16 vccp power/other f17 vss power/other f18 vcc power/other f19 vss power/other f20 vcc power/other f21 vss power/other f22 vcc power/other f23 test2 test f24 vss power/other f25 d[21]# source synch input/output f26 vcca power/other g1 rsvd reserved g2 vss power/other g3 vid[3] cmos output g4 vid[4] cmos output table 4-4. pin listing by pin number pin number pin name signal buffer type direction g5 vcc power/other g6 vss power/other g21 vcc power/other g22 vss power/other g23 vss power/other g24 d[22]# source synch input/output g25 d[17]# source synch input/output g26 vss power/other h1 rs[0]# common clock input h2 drdy# common clock input/output h3 vss power/other h4 vid[5] cmos output h5 vss power/other h6 vcc power/other h21 vss power/other h22 vcc power/other h23 d[16]# source synch input/output h24 d[20]# source synch input/output h25 vss power/other h26 d[29]# source synch input/output j1 vss power/other j2 lock# common clock input/output j3 bpri# common clock input j4 vss power/other j5 vcc power/other j6 vss power/other j21 vcc power/other j22 vss power/other j23 d[23]# source synch input/output j24 vss power/other j25 d[25]# source synch input/output j26 dinv[1]# source synch input/output k1 rs[1]# common clock input k2 vss power/other k3 hit# common clock input/output k4 hitm# common clock input/output k5 vss power/other k6 vccp power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction
datasheet 48 k21 vss power/other k22 vcc power/other k23 vss power/other k24 dstbn[1]# source synch input/output k25 d[31]# source synch input/output k26 vss power/other l1 bnr# common clock input/output l2 rs[2]# common clock input l3 vss power/other l4 defer# common clock input l5 vccp power/other l6 vss power/other l21 vccp power/other l22 vss power/other l23 d[18]# source synch input/output l24 dstbp[1]# source synch input/output l25 vss power/other l26 d[26]# source synch input/output m1 vss power/other m2 dbsy# common clock input/output m3 trdy# common clock input m4 vss power/other m5 vss power/other m6 vccp power/other m21 vss power/other m22 vccp power/other m23 d[24]# source synch input/output m24 vss power/other m25 d[28]# source synch input/output m26 d[19]# source synch input/output n1 rsvd reserved n2 ads# common clock input/output n3 vss power/other n4 br0# common clock input/output n5 vccp power/other n6 vss power/other n21 vccp power/other n22 vss power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction n23 vss power/other n24 d[27]# source synch input/output n25 d[30]# source synch input/output n26 vss power/other p1 req[3]# source synch input/output p2 vss power/other p3 req[1]# source synch input/output p4 a[3]# source synch input/output p5 vss power/other p6 vccp power/other p21 vss power/other p22 vccp power/other p23 vccq[0] power/other p24 vss power/other p25 comp[0] power/other input/output p26 comp[1] power/other input/output r1 vss power/other r2 req[0]# source synch input/output r3 a[6]# source synch input/output r4 vss power/other r5 vccp power/other r6 vss power/other r21 vccp power/other r22 vss power/other r23 d[39]# source synch input/output r24 d[37]# source synch input/output r25 vss power/other r26 d[38]# source synch input/output t1 req[4]# source synch input/output t2 req[2]# source synch input/output t3 vss power/other t4 a[9]# source synch input/output t5 vss power/other t6 vccp power/other t21 vss power/other t22 vccp power/other t23 vss power/other t24 dinv[2]# cmos input/output table 4-4. pin listing by pin number pin number pin name signal buffer type direction
49 datasheet t25 d[34]# source synch input/output t26 vss power/other u1 a[13]# source synch input/output u2 vss power/other u3 adstb[0]# source synch input/output u4 a[4]# source synch input/output u5 vcc power/other u6 vss power/other u21 vccp power/other u22 vss power/other u23 d[35]# source synch input/output u24 vss power/other u25 d[43]# source synch input/output u26 d[41]# source synch input/output v1 vss power/other v2 a[7]# source synch input/output v3 a[5]# source synch input/output v4 vss power/other v5 vss power/other v6 vcc power/other v21 vss power/other v22 vcc power/other v23 d[36]# source synch input/output v24 d[42]# source synch input/output v25 vss power/other v26 d[44]# source synch input/output w1 a[8]# source synch input/output w2 a[10]# source synch input/output w3 vss power/other w4 vccq[1] power/other w5 vcc power/other w6 vss power/other w21 vcc power/other w22 vss power/other w23 vss power/other w24 dstbp[2]# source synch input/output w25 dstbn[2]# source synch input/output w26 vss power/other table 4-4. pin listing by pin number pin number pin name signal buffer type direction y1 a[12]# source synch input/output y2 vss power/other y3 a[15]# source synch input/output y4 a[11]# source synch input/output y5 vss power/other y6 vcc power/other y21 vss power/other y22 vcc power/other y23 d[45]# source synch input/output y24 vss power/other y25 d[47]# source synch input/output y26 d[32]# source synch input/output table 4-4. pin listing by pin number pin number pin name signal buffer type direction
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datasheet 51 4.2 alphabetical signals reference table 4-5. signal description (sheet 1 of 7) name type description a[31:3]# input/ output a[31:3]# (address) define a 2 32 -byte physical memory address space. in sub- phase 1 of the address phase, these pins tr ansmit the address of a transaction. in sub-phase 2, these pins transmit tr ansaction type information. these signals must connect the appropriate pins of both agents on intel ? pentium ? m processor fsb. a[31:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. a ddress signals are used as straps which are sampled before reset# is deasserted. a20m# input if a20m# (address-20 mask) is asse rted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. ads# input/ output ads# (address strobe) is asserted to i ndicate the validity of the transaction address on the a[31:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin parity checking, prot ocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[31:3]# and req[4:0]# on their rising and falling edges. strobes are associat ed with signals as shown below. bclk[1:0] input the differential pair bclk (bus clock) determines the fsb frequency. all fsb agents must receive these signals to dr ive their outputs and latch their inputs. all external timing parameters are spec ified with respect to the rising edge of bclk0 crossing v cross . bnr# input/ output bnr# (block next request) is used to as sert a bus stall by any bus agent who is unable to accept new bus transactions. du ring a bus stall, the current bus owner cannot issue any new transactions. bpm[2:0]# bpm[3] output input/ output bpm[3:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the proc essor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[3:0]# should connect the appropriate pins of all intel ? pentium ? m fsb agents.this includes debug or performance monitoring tools. bpri# input bpri# (bus priority request) is used to arbitrate for ownership of the fsb. it must connect the appropriate pins of both fsb agents. observing bpri# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. br0# input/ output br0# is used by the processor to r equest the bus. the arbitration is done between intel ? pentium ? m (symmetric agent) and intel ? 915pm/gm and intel ? 915gms express chipset gmch-m (high priority agent). signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[31:17]# adstb[1]#
52 datasheet bsel[1:0] output bsel[1:0] (bus select) are used to select the processor input clock frequency. table 3-2 defines the possible combinati ons of the signals and the frequency associated with each combination. t he required frequency is determined by the processor, chipset and clock synthesizer. all agents must operate at the same frequency. the pentium m processor operates at a 533-mhz front side bus frequency (133 mhz bclk). comp[3:0] analog comp[3:0] must be terminated on the system board using precision (1% tolerance) resistors. d[63:0]# input/ output d[63:0]# (data) are the data signals. th ese signals provide a 64-bit data path between the fsb agents, and must connect the appropriate pins on both agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals and will th us be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dinv# . furthermore, the dinv# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dinv# signal. when the dinv# signal is active, the corresponding data group is inverted and therefore sampled active high. dbr# output dbr# (data bus reset) is used only in processor systems where no debug port is implemented on the system board. db r# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemented in the system, dbr# is a no connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the fsb to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on both fsb agents. defer# input defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins of both fsb agents. table 4-5. signal description (sheet 2 of 7) name type description quad-pumped signal groups data group dstbn#/ dstbp# dinv# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3
datasheet 53 dinv[3:0]# input/ output dinv[3:0]# (data bus inversion) are source synchronous and indicate the polarity of the d[63:0]# signals. the dinv [3:0]# signals are activated when the data on the data bus is inverted. the bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. dpslp# input dpslp# when asserted on the platform causes the processor to transition from the sleep state to the deep sleep state. in order to return to the sleep state, dpslp# must be deasserted. dpslp# is driven by the ich6-m chipset. dpwr# input dpwr# is a control signal from the intel ? 915pm/gm/gms express chipsets used to reduce power on intel ? pentium ? m data bus input buffers. drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of both fsb agents. dstbn[3:0]# input/ output data strobe used to latch in d[63:0]#. dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#. table 4-5. signal description (sheet 3 of 7) name type description dinv[3:0]# assignment to data bus bus signal data bus signals dinv[3]# d[63:48]# dinv[2]# d[47:32]# dinv[1]# d[31:16]# dinv[0]# d[15:0]# signals associated strobe d[15:0]#, dinv[0]# dstbn[0]# d[31:16]#, dinv[1]# dstbn[1]# d[47:32]#, dinv[2]# dstbn[2]# d[63:48]#, dinv[3]# dstbn[3]# signals associated strobe d[15:0]#, dinv[0]# dstbp[0]# d[31:16]#, dinv[1]# dstbp[1]# d[47:32]#, dinv[2]# dstbp[2]# d[63:48]#, dinv[3]# dstbp[3]#
54 datasheet ferr#/pbe# output ferr# (floating-point error)pbe# (pending break event) is a multiplexed signal and its meaning is qualified with stpc lk#. when stpclk# is not asserted, ferr#/pbe# indicates a floating point when the processor detects an unmasked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms- dos*-type floating-point error report ing. when stpclk# is asserted, an assertion of ferr#/pbe# indicates t hat the processor has a pending break event waiting for service. the assert ion of ferr#/pbe# indicates that the processor should be returned to the normal state. when ferr#/pbe# is asserted, indicating a break event, it will remain asserted until stpclk# is deasserted. assertion of preq# when stpc lk# is active wi ll also cause an ferr# break event. for additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to volume 3 of the intel ? architecture software developer?s manual and the intel ? processor identification and cpuid instruction application note. gtlref input gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v ccp . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical 1. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modi fied) convey transaction snoop operation results. either fsb agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the fsb. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#, binit#, or init#. ignne# input ignne# (ignore numeric error) is as serted to force the processor to ignore a numeric error and continue to execute nonc ontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous fl oating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. howeve r, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. init# input init# (initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor conti nues to handle snoop requests during init# assertion. init# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write in struction, it must be valid along with the trdy# assertion of the correspondi ng input/output write bus transaction. init# must connect the appropriate pins of both fsb agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itp_clk[1:0] input itp_clk[1:0] are copies of bc lk that are used only in processor systems where no debug port is implemented on the system board. itp_clk[1:0] are used as bclk[1:0] references for a debug port implemented on an interposer. if a debug port is implemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. table 4-5. signal description (sheet 4 of 7) name type description
datasheet 55 lint[1:0] input lint[1:0] (local apic interrupt) mu st connect the appropriate pins of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a tr ansaction must occur atomically. this signal must connect the appropriate pins of both fsb agents. for a locked sequence of transactions, lock# is asse rted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the fsb, it will wait until it observes lock# deas serted. this enables symmetric agents to retain ownership of the fsb throughout the bus locked operation and ensure the atomicity of lock. prdy# output probe ready signal used by debug tools to determine processor debug readiness. preq# input probe request signal used by debug t ools to request debug operation of the processor. prochot# output prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the pr ocessor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit has been activated, if enabled. see chapter 5 for more details. this signal may require voltage translation on the motherboard. psi# output processor power status indicator si gnal. this signal is asserted when the processor is in a lower state (deep sleep and deeper sleep). see section 2.1.5 for more details. pwrgood input pwrgood (power g ood) is a processor input. the processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without gl itches, from the time that the power supplies are turned on until they come with in specification. the signal must then transition monotonically to a high state. the pwrgood signal must be supplied to t he processor; it is used to protect internal circuits against voltage sequenc ing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must connect the appropriate pins of both fsb agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb[0]#. reset# input asserting the reset# signal rese ts the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least two milliseconds after v cc and bclk have reached their proper spec ifications. on observing active reset#, both fsb agents will deassert their outputs within two clocks. all processor straps must be valid within the specified setup time before reset# is deasserted. there is a 55 ohm (nominal) on die pullup resistor on this signal. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the cu rrent transaction), and must connect the appropriate pins of both fsb agents. table 4-5. signal description (sheet 5 of 7) name type description
56 datasheet rsvd reserved/ no connect these pins are reserved and must be left unconnected on the board. however, it is recommended that routing channels to these pins on the board be kept open for possible future use. please refer to the platform design guide for more details. slp# input slp# (sleep), when asserted in stop-grant state, causes the processor to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the ph ase-locked loop (pll) still operating. processors in this state will not rec ognize snoops or interrupts. the processor will recognize only assertion of the reset# signal, deassertion of slp#, and removal of the bclk input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. if dpslp# is asserted while in the sleep state, the processor will exit the sleep state and transition to the deep sleep state. smi# input smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and t he processor begins program execution from the smm handler. if smi# is asserted during the deassertion of reset# the processor will tristate its outputs. stpclk# input stpclk# (stop clock), when asserted, causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal cl ock signals to all processor core units except the fsb and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck input tck (test clock) prov ides the clock input for the processor test bus (also known as the test access port). please refer to the platform design guide for termination requirements and implementation details. tdi input tdi (test data in) transfers serial te st data into the processor. tdi provides the serial input needed for jtag specification support. please refer to the platform design guide for termination requirements and implementation details. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. please refer to the platform design guide for termination requirements and implementation details. test1, test2 input test1 and test2 must have a stuffing option of separate pull down resistors to v ss . please refer to the platform design guide for more details. thermda other thermal diode anode. thermdc other thermal diode cathode. thermtrip# output the processor protects itself fr om catastrophic overheating by use of an internal thermal sensor. this sensor is set we ll above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximat ely 125 c. this is signalled to the system by the thermtrip# (thermal trip) pin. for termination requirements please re fer to the platform design guide . table 4-5. signal description (sheet 6 of 7) name type description
datasheet 57 tms input tms (test mode select) is a jtag s pecification support signal used by debug tools. please refer to the platform desi gn guide for termination requirements and implementation details. trdy# input trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of both fsb agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. please re fer to the platform design guide for termination requirements and implementation details. v cc input processor core power supply. v cca input v cca provides isolated power for the inte rnal processor core pll?s. pins previously named v cca [3:1] pins are now reserved and should be left unconnected on the board. refer to the platform design guide for complete implementation details. v ccp input processor i/o power supply. v cc q [1:0] input quiet power supply for on die comp circuitry. these pi ns should be connected to v ccp on the motherboard. however, these connections should enable addition of decoupling on the v cc q lines if necessary. v ccsense output v ccsense is an isolated low impedance conne ction to processor core power (v cc ). it can be used to sense or measure pow er near the silicon with little noise. please refer to the platform design guide for termination recommendations and more details. vid[5:0] output vid[5:0] (voltage id) pins are used to support automatic selection of power supply voltages (vcc). unlike some prev ious generations of processors, these are cmos signals that are driven by pentium m processor. the voltage supply for these pins must be valid before the vr can supply vcc to the processor. conversely, the vr output must be disabled until the voltage supply for the vid pins becomes valid. the vid pins ar e needed to support the processor voltage specification variations. see table 3-2 for definitions of these pins. the vr must supply the voltage that is requested by the pins, or disable itself. v sssense output v sssense is an isolated low impedance connec tion to processor core v ss . it can be used to sense or measure ground near the silicon with little noise. please refer to the platform design guide for termination recommendations and more details. table 4-5. signal description (sheet 7 of 7) name type description
58 datasheet
datasheet 59 thermal specifications and design considerations 5 thermal specifications and design considerations the pentium m processor requires a thermal solution to maintain temperatures within operating limits as set forth in section 5.1 . any attempt to operate that pr ocessor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. as processor technology changes, thermal management becomes increasingly crucial when building computer systems. maintaining the proper thermal environment is key to reliable, long-term system operation. a co mplete thermal solution includes both component and system level thermal management features. component le vel thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. the solution should make firm contact to the die while mainta ining processor mechanical speci fications such as pressure. a typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processo r via a heat pipe or direct die attachment. a seco ndary fan or air from the processor fan may also be used to cool other platform components or lower the internal ambient temperature within the system. to allow for the optimal operati on and long-term reliability of intel processor-based systems, the system/processor thermal solution should be designed such that the processor must remain within the minimum and maximum junction temperature (tj) specifications at the corresponding thermal design power (tdp) value listed in table 5-1 . thermal solutions not design to provide this level of thermal capability may affect the long-term reliability of the processor and system. the maximum junction temperature is defined by an activation of the processor intel ? thermal monitor. refer to section 5.1.3 for more details. analysis indi cates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the tdp indicated in table 5-1 . the intel thermal monitor feature is designed to help protect the processor in the unlikely event that an a pplication exceeds the tdp recommenda tion for a sustained period of time. for more details on the usage of this feature, refer to section 5.1.3 . in all cases the intel thermal monitor feature must be enabled for the processor to remain within specification.
60 datasheet thermal specifications an d design considerations notes: 1. the tdp specification should be used to design the proc essor thermal solution. the tdp is not the maximum theoretical power the processor can dissipate. 2. not 100% tested. these power specifications are deter mined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. as measured by the on-die intel thermal monitor. the intel thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 5.1 for more details. 4. the intel thermal monitor automatic mode must be enabled for the processor to operate within specifications. table 5-1. power spec ifications for intel ? pentium ? m processor symbol processor number core frequency & voltage thermal design power unit notes tdp 780 2.26 ghz & hfm vcc 27 w at 100 c, notes 1, 4 770 2.13 ghz & hfm vcc 27 760 2.00 ghz & hfm vcc 27 750 1.86 ghz & hfm vcc 27 740 1.73 ghz & hfm vcc 27 730 1.60 ghz & hfm vcc 27 not applicable 800 mhz & lfm vcc 10.8 symbol parameter min typ max unit notes p ah, p sgnt auto halt, stop grant power w at 50 c, note 2 at lfm vcc 5.1 at hfm vcc 16.2 p slp sleep power w at 50 c, note 2 at lfm vcc 4.9 at hfm vcc 15.8 p dslp deep sleep power w at 35 c, note 2 at lfm vcc 3.7 at hfm vcc 12.2 p dprslp1 deeper sleep power @0.748 v 1.2 w at 35 c, note 2 p dprslp2 deeper sleep power @0.726 v 1.1 w at 35 c, note 2 t j junction temperature 0 100 c notes 3, 4
datasheet 61 thermal specifications and design considerations 5.1 thermal specifications 5.1.1 thermal diode the pentium m processor incorporates two method s of monitoring die te mperature, the intel ? thermal monitor and the thermal diode. th e intel thermal monitor (detailed in section 5.1 ) must be used to determine when the maximum specified processor junction temperature has been reached. the second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on th e motherboard, or a stand-alon e measurement kit. the thermal diode may be used to monitor the die temperatur e of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum t j of the processor has been reached. when using the thermal diode, a temperature of fset value must be read from a processor model specific register (msr) and app lied. see section 6.1.2 for more details. please see section 5.1.3 for thermal diode usage recommendatio n when the prochot# signal is not asserted. table 5-2 and table 5-3 provide the diode inte rface and specifications. note: the reading of the external th ermal sensor (on the motherboard ) connected to the processor thermal diode signals, will not necessarily reflect th e temperature of the hottest location on the die. this is due to inaccuracies in th e external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. time ba sed variations can o ccur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the t j temperature can change. offset between the thermal diode based temperatur e reading and the intel thermal monitor reading may be characterized using the intel thermal mo nitor?s automatic mode activation of thermal control circuit. this temperature offset must be taken into account when using the processor thermal diode to implement power management events. 5.1.2 thermal diode offset a temperature offset value (specified as toffset in table 5-3 ) will be programmed into a the pentium m processor model specific register (msr). this offset is determined by using a thermal diode ideality factor mean value of n = 1.0022 (shown in table 5-3 ) as a reference. this offset must be applied to the junction temperature read by the thermal diode. any temperature adjustments due to differences between the reference ideality va lue of 1.0022 and the default ideality values programmed into the on-board thermal sensors, will have to be made before the above offset is applied. table 5-2. thermal diode interface signal name pin/ball number signal description thermda b18 thermal diode anode thermdc a18 thermal diode cathode
62 datasheet thermal specifications an d design considerations notes: 1. intel does not support or recommend operation of t he thermal diode under reverse bias. intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. characterized at 100 c. 3. not 100% tested. specified by design/characterization. 4. the ideality factor, n, represents the deviation fr om ideal diode behavior as exemplified by the diode equation: i fw =i s *(e (qv d /nkt) -1) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). value shown in the table is not the pentium m processo r thermal diode ideality factor. it is a reference value used to calculate pentium m thermal diode temperature offset. 5. the series resistance, r t , is provided to allow for a more accu rate measurement of the diode junction temperature. r t as defined includes the pins of the processo r but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. r t can be used by remote diode thermal sensors with autom atic series resistance cancellation to calibrate out this error term. another application is that a temperature offset ca n be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplifi ed by the equation: t error = [r t *(n-1)*i fwmin ]/[(no/q)*ln n] 6. offset value is programmed in pr ocessor model specific register. 5.1.3 intel ? thermal monitor the intel ? thermal monitor helps control the processo r temperature by activ ating the tcc when the processor silicon reaches it s maximum operating temperature. the temperature at which intel thermal monitor activates the thermal control circu it is not user configurable and is not software visible. bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the cloc ks are on) while the tcc is active. with a properly designed and char acterized thermal solution, it is anticipated that the tcc would only be activated for very short periods of time when running the most power intensive applications. the processo r performance impact due to these brief periods of tcc activation is expected to be so minor that it would not be detectable. an under-designed thermal solution that is not able to prevent excessive act ivation of the tcc in the anti cipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. in addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the t cc is active continuously. the intel thermal monitor controls the proce ssor temperature by modulating (starting and stopping) the processor core clocks or by in itiating an enhanced in tel speedstep technology transition when the processor silicon reaches its maximum oper ating temperature. the intel thermal monitor uses two modes to activate the tcc: automatic mode and on-demand mode. if both modes are activated, au tomatic mode takes precedence. table 5-3. thermal diode specifications symbol parameter min typ max unit notes i fw forward bias current 5 300 a note 1 toffset thermal diode temperature offset -4 11 c 2, 6 n reference diode ideality factor used to calculate temperature offset 1.0022 notes 2, 3, 4 r t series resistance 3.06 ohms 2, 3, 5
datasheet 63 thermal specifications and design considerations note: the intel thermal monitor automatic mode must be enabled through bios for the processor to be operating within specifications. there are two automatic modes call ed intel thermal monitor 1 and intel thermal monitor 2. these modes are selected by writing values to the mo del specific registers (msr s) of the processor. after automatic mode is enabled, the tcc will activate only when the in ternal die temperature reaches the maximum allowe d value for operation. likewise, when intel thermal monitor 2 is enable d, and a high temperature situation exists, the processor will perform an enhanced intel speedst ep technology transitio n to a lower operating point. when the processor temperature drops below th e critical level, the processor will make an enhanced intel speedstep technology transition to the last requested operating point. intel thermal monitor 2 is the recommended mode on pentium m processors. if a processor load based enhanced intel speedstep technology transition (through msr write) is initiated when an intel thermal monitor 2 peri od is active, there are two possible results: 1.if the processor load based enhanced intel speedstep technology transition target frequency is higher than the intel thermal monitor 2 transition based target frequency, the processor load- based transition will be deferred until the intel thermal monitor 2 event has been completed. 2.if the processor load-based enhanced intel speedstep technology transition target frequency is lower than the intel thermal monitor 2 transition based target frequency, the processor will transition to the processor load-based enhanced intel speedstep technology target frequency point. when intel thermal monitor 1 is enabled, and a hi gh temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. cycle times are processor speed dependent and will decrease linearly as processor core freq uencies increase. once the temperature has returned to a non-critical le vel, modulation ceases and tcc goes inactive. a small amount of hysteresis has b een included to prevent rapid act ive/inactive transitions of the tcc when the processor temperatur e is near the trip point. the duty cycle is factory configured and cannot be modified. also, automatic mode doe s not require any additional hardware, software drivers, or interrupt handling routines. proce ssor performance will be decreased by the same amount as the duty cycle when the tcc is ac tive, however, with a properly designed and characterized thermal solution the tcc most likel y will never be activated, or only will be activated briefly during the most power intensive applications. the tcc may also be activated via on-demand mode . if bit 4 of the acpi intel thermal monitor control register is written to a 1, the tcc wi ll be activated immediately, independent of the processor temperature. when usin g on-demand mode to activate the tcc, the duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi intel thermal monitor control register. in automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12 .5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the tcc via on-demand mode at th e same time automatic mode is enabled and a high temperature conditio n exists, automatic mode will take precedence. an external signal, prochot# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. bus snooping and interrupt latching are also active while the tcc is active.
64 datasheet thermal specifications an d design considerations besides the thermal sensor and thermal control circuit, the intel thermal monitor thermal monitor feature also includes one acpi register, one performance counte r register, three model specific registers (msr), and one i/o pin (prochot#). all are available to monito r and control the state of the intel thermal monitor feature. the intel thermal monitor can be configured to generate an interrupt upon the assertion or deassertion of prochot#. note: prochot# will not be asserted when the proces sor is in the stop grant, sleep, deep sleep, and deeper sleep low power states (i nternal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor j unction temperature within the 100 c (maximum) specification. if the platform th ermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. if the processor enters one of the above low power states with prochot# already asserted, prochot# will remain asserted until the processor exits the low power state and the processor junction temperatur e drops below the thermal trip point. if automatic mode is disabled, th e processor will be operating ou t of specification. regardless of enabling the automatic or on-demand modes, in th e event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125 c. at this point the thermtrip# signal will go active. thermtrip# activation is independent of processor activity and does not generate any bus cycles. when thermtrip# is asserted, the proce ssor core voltage must be shut down within the time specified in chapter 3 .

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