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rt9173d 1 www.richtek.com ds9173d-06 december 2007 pin configurations cost-effective, peak 3a sink/source bus termination regulator ordering information general description the rt9173d is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system to comply with the jedec sstl_2 and sstl_18 or other specific interfaces such as hstl, scsi-2 and scsi-3 etc. devices requirements. the regulator is capable of actively sinking or sourcing continuous 2a or up to 3a transient peak current while regulating an output voltage to within 40mv. the output termination voltage cab be tightly regulated to track 1/2v ddq by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the refen pin voltage. the rt9173d also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. the rt9173d are available in the sop-8 (exposed pad) surface mount packages. features z z z z z ideal for ddr-i, ddr-ii and ddr-iii v tt applications z z z z z sink and source current ` ` ` ` ` 2a continuous current ` ` ` ` ` peak 3a for ddri and ddrii ` ` ` ` ` peak 2.5a for ddriii z z z z z integrated power mosfets z z z z z generates termination voltage for sstl_2, sstl _18, hstl, scsi-2 and scsi-3 interfaces z z z z z high accuracy output voltage at full-load z z z z z output adjustment by two external resistors z z z z z low external component count z z z z z shutdown for suspend to ram (str) functionality with high-impedance output z z z z z current limiting protection z z z z z on-chip thermal protection z z z z z available in sop-8 (e xposed pad) packages z z z z z v in and v cntl no power sequence issue z z z z z rohs compliant and 100% lead (pb)-free applications z desktop pcs, notebooks, and workstations z graphics card memory termination z set top boxes, digital tvs, printers z embedded systems z active termination buses z ddr-i, ddr-ii and ddr-iii memory systems (top view) sop-8 (exposed pad) note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100% matte tin (sn) plating. vin gnd refen vout nc nc nc vcntl gnd 2 3 4 5 6 7 8 9 package type sp : sop-8 (exposed pad-option 1) operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) rt9173d
rt9173d 2 ds9173d-06 december 2007 www.richtek.com typical application circuit r 1 = r 2 = 100k , r tt = 50 / 33 / 25 c out(min) = 10 f (ceramic) + 1000 f under the worst case testing condition c ss = 1 f, c in = 470 f (low esr), c cntl = 47 f test circuit figure 1. test circuit for typical operating characteristics curves vin refen gnd vcntl vout rt9173d en 2n7002 r 1 r 2 c ss v in = 2.5v/1.8v/1.5v v cntl = 3.3v c cntl c in r tt c out gnd vin refen gnd vcntl vout rt9173d 2.5v/1.8v/1.5v 3.3v 1.25v/0.9v/0.75v v out
rt9173d 3 www.richtek.com ds9173d-06 december 2007 functional pin description vin (pin 1) input voltage which supplies current to the output pin. connect this pin to a well-decoupled supply voltage. to prevent the input rail from dropping during large load transient, a large, low esr capacitor is recommended to use. the capacitor should be placed as close as possible to the vin pin. gnd [pin 2, exposed pad (9)] common ground (exposed pad is connected to gnd). the gnd pad area should be as large as possible and using many vias to conduct the heat into the buried gnd plate of pcb layer. refen (pin 3) reference voltage input and active low shutdown control pin. two resistors dividing down the vin voltage on the pin to create the regulated output voltage. pulling the pin to ground turns off the device by an open-drain, such as 2n7002, signal n-mosfet. function block diagram gnd vcntl refen current limit thermal protection vout ea + - vin vout (pin 4) regulator output. vout is regulated to refen voltage that is used to terminate the bus resistors. it is capable of sinking and sourcing current while regulating the output rail. to maintain adequate large signal transient response, typical value of 1000 f al electrolytic capacitor with 10 f ceramic capacitors are recommended to reduce the effects of current transients on vout. vcntl (pin 6) vcntl supplies the internal control circuitry and provides the drive voltage. the driving capability of output current is proportioned to the vcntl. connect this pin to 3.3v bias supply to handle large output current with at least 10 f capacitor from this pin to gnd. nc (pin 5, 7, 8) no internal connect.
rt9173d 4 ds9173d-06 december 2007 www.richtek.com electrical characteristics (v in = 2.5v/1.8v/1.5v, v cntl = 3.3v, v refen = 1.25v/0.9v/0.75v, c out = 10 f (ceramic), t a = 25c, unless otherwise specified) parameter symbol test conditions min typ max units input v cntl operation current i cntl i out = 0a -- 1 2.5 ma standby current (note 7) i stby v refen < 0.2v (shutdown), r load = 180 -- 50 90 a output (ddr / ddr ii / ddr iii) output offset voltage (note 5) v os i out = 0a ? 20 -- +20 mv i out = +2a load regulation (note 6) v load i out = ? 2a ? 20 -- +20 mv protection current limit i lim v in = 2.5v/1.8v/1.5v -- 3.4 -- a thermal shutdown temperature t sd 3.3v v cntl 5v 125 170 -- c thermal shutdown hysteresis t sd 3.3v v cntl 5v -- 35 -- c refen shutdown v ih enable 0.6 -- -- shutdown threshold v il shutdown -- -- 0.2 v absolute maximum ratings (note 1) z input voltage, v in ------------------------------------------------------------------------------------------------------ 6v z control voltage, v cntl ----------------------------------------------------------------------------------------------- 6v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) ----------------------------------------------------------------------------------------------- 1.33w z package thermal resistance (note 4) sop-8 (exposed pad), ja ------------------------------------------------------------------------------------------ 75 c/w sop-8 (exposed pad), jc ----------------------------------------------------------------------------------------- 28 c/w z junction temperature ------------------------------------------------------------------------------------------------- 125 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 3) z input voltage, v in ------------------------------------------------------------------------------------------------------ 2.5v to 1.5v 5% z control voltage, v cntl ----------------------------------------------------------------------------------------------- 5v or 3.3v 5% z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c
rt9173d 5 www.richtek.com ds9173d-06 december 2007 note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for sop-8 (exposed pad) package. note 5. v os offset is the voltage measurement defined as v out subtracted from v refen . note 6. regulation is measured at constant junction temperature by using a 5ms current pulse. devices are tested for load regulation in the load range from 0a to 2a. note 7. standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on refen pin (v il < 0.2v). it is measured with v in = v cntl = 5v.
rt9173d 6 ds9173d-06 december 2007 www.richtek.com typical operating characteristics vcntl current vs. temperature 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50 -25 0 25 50 75 100 125 temperature vcntl current (ma) ( c) v in = 2.5v, v cntl = 5v v in = 2.5v, v cntl = 3.3v v in = 1.8v, v cntl = 3.3v v in = 1.8v, v cntl = 5v v in = 1.5v, v cntl = 5v v in = 1.5v, v cntl = 3.3v v in current vs. temperature 2 2.5 3 3.5 4 4.5 5 -50 -25 0 25 50 75 100 125 temperature v in current (ma) ( c) v in = 2.5v, v cntl = 5v v in = 2.5v, v cntl = 3.3v v in = 1.8v, v cntl = 3.3v v in = 1.8v, v cntl = 5v v in = 1.5v, v cntl = 5v v in = 1.5v, v cntl = 3.3v shutdown threshold vs. temperature 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50 -25 0 25 50 75 100 125 temperature shutdown threshold (v) ( c) v cntl = 3.3v, turn on v cntl = 5v, turn off v cntl = 5v, turn on v cntl = 3.3v, turn off output voltage vs. temperature 1.24 1.245 1.25 1.255 1.26 1.265 1.27 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v in = 2.5v output voltage vs. temperature 0.89 0.895 0.9 0.905 0.91 0.915 0.92 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v in = 1.8v output voltage vs. temperature 0.74 0.745 0.75 0.755 0.76 0.765 0.77 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v in = 1.5v
rt9173d 7 www.richtek.com ds9173d-06 december 2007 source current limit vs. temperature 2 2.5 3 3.5 4 4.5 -50 -25 0 25 50 75 100 125 temperature source current limit (a) ( c) v in = 2.5v, v cntl = 5v v in = 2.5v, v cntl = 3.3v v in = 1.8v, v cntl = 3.3v v in = 1.8v, v cntl = 5v v in = 1.5v, v cntl = 5v v in = 1.5v, v cntl = 3.3v sink current limit vs. temperature 2 2.5 3 3.5 4 4.5 -50 -25 0 25 50 75 100 125 temperature sink current limit (a) ( c) v in = 2.5v, v cntl = 5v v in = 2.5v, v cntl = 3.3v v in = 1.8v, v cntl = 3.3v v in = 1.8v, v cntl = 5v v in = 1.5v, v cntl = 5v v in = 1.5v, v cntl = 3.3v 0.9v tt @ 2a transient response output voltage transient (mv) 40 20 0 -20 output current (a) 2 1 0 v in = 1.8v, v cntl = 3.3v, v out = 0.9v swing frequency : 1khz time (250 s/div) sink 0.9v tt @ 2a transient response output voltage transient (mv) 40 20 0 -20 output current (a) 2 1 0 v in = 1.8v, v cntl = 3.3v, v out = 0.9v swing frequency : 1khz time (250 s/div) source 0.75v tt @ 2a transient response output voltage transient (mv) 40 20 0 -20 output current (a) 2 1 0 v in = 1.5v, v cntl = 3.3v, v out = 0.75v swing frequency : 1khz time (250 s/div) sink 0.75v tt @ 2a transient response output voltage transient (mv) 40 20 0 -20 output current (a) 2 1 0 v in = 1.5v, v cntl = 3.3v, v out = 0.75v swing frequency : 1khz time (250 s/div) source
rt9173d 8 ds9173d-06 december 2007 www.richtek.com v in = 1.5v, v cntl = 3.3v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) source v in = 1.5v, v cntl = 3.3v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 sink time (1ms/div) v in = 1.8v, v cntl = 3.3v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 sink time (1ms/div) v in = 1.8v, v cntl = 3.3v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) source 1.25v tt @ 2a transient response output voltage transient (mv) 40 20 0 -20 output current (a) 2 1 0 v in = 2.5v, v cntl = 3.3v, v out = 1.25v swing frequency : 1khz time (250 s/div) sink 1.25v tt @ 2a transient response output voltage transient (mv) 40 20 0 -20 output current (a) 2 1 0 v in = 2.5v, v cntl = 3.3v, v out = 1.25v swing frequency : 1khz time (250 s/div) source
rt9173d 9 www.richtek.com ds9173d-06 december 2007 v in = 2.5v, v cntl = 3.3v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) source v in = 2.5v, v cntl = 3.3v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 sink time (1ms/div)
rt9173d 10 ds9173d-06 december 2007 www.richtek.com general regulator the rt9173d could also serves as a general linear regulator. the rt9173d accepts an external reference voltage at refen pin and provides output voltage regulated to this reference voltage as shown i n figure 3, where v out = v ext x r2/(r1+r2) as other linear regulator, dropout voltage and thermal issue should be special ly considered. figure 4 and 5 show the r ds(on) over temperature of rt9173d in psop-8 (ex posed pad) package. the minimum dropout voltage could be obtained by the product of r ds(on) and output current. for thermal consideration, please refer to the relative sections . application information consideration while designs the resistance of voltage divider make sure the sinking current capa bility of pull-down nmos if the lower resistance was chosen so that the voltage on v refen is below 0.2v. in addition, the capacitor and voltage divider form the low- pass filter. there are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. how to reduce power dissipation on notebook pc or the dual channel ddr sdram application? in notebook application, using richtek's patent ? d istributed bus terminator topology ? with choosing richtek's product is encouraged. distributed bus terminating topology figure 2 figure 4 figure 5 r0 r9 r8 r7 r6 r5 r4 r3 r2 r1 r(2n) r(2n+1) rt9173d rt9173d vout vout refen bus(0) bus(1) bus(2) bus(3) bus(4) bus(5) bus(6) bus(7) bus(8) bus(9) bus(2n) bus(2n+1) terminator resistor r ds(on) vs. temperature 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 temperature r ds(on) ( ? ) ( c) v cntl = 5v r ds(on) vs. temperature 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 temperature r ds(on) ( ? ) ( c) v cntl = 3.3v figure 3 vcntl refen gnd vin vout rt9173d v ext r1 r2 v out
rt9173d 11 www.richtek.com ds9173d-06 december 2007 input capacitor and layout consideration place the input bypass capacitor as close as possible to the rt9173d. a low esr capacitor larger than 470uf is recommended for the input capacitor. use short and wide traces to minimize parasitic resistance and inductance. inappropriate layout may result in large parasitic inductance and cause undesired oscillation between rt9173d and the preceding power converter. thermal consideration rt9173d regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. for continued operation, do not exceed maximum operation junction temperature 125 c. the power dissipation definition in device is: p d = (v in - v out ) x i out + v in x i q the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula: p d(max) = ( t j(max) -t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. the junction to ambient thermal resistance ( ja is layout dependent) for sop-8 package (exposed pad) is 75 c/w on standard jedec 51-7 (4 layers, 2s2p) thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula: p d(max) = (125 c - 25 c) / 75 c/w = 1.33w figure 6 show the package sectional drawing of sop-8 (exposed pad). every package has several thermal dissipation paths. as show in figure 7, the thermal resistance equivalent circuit of sop-8 (exposed pad). the path 2 is the main path due to these materials thermal conductivity. we define the exposed pad is the case point of the path 2. ambient molding compound gold line lead frame die pad case (exposed pad) figure 6. sop-8 (exposed pad) package sectional drawing figure 7. thermal re sistance equivalent circuit the thermal resistance ja of sop-8 (exposed pad) is determined by the package design and the pcb design. however, the package design has been decided. if possible, it's useful to increase thermal performance by the pcb design. the thermal resistance can be decreased by adding copper under the expose pad of sop-8 package. about pcb layout , the figure 8 show the relation between thermal resistance ja and copper area on a standard jedec 51-7 (4 layers, 2s2p) thermal test board at t a = 25 c.we have to consider the copper couldn't stretch infinitely and avoid the tin overflow. we use the ? dog-bone ? copper patterns on the top layer as figure 9. as shown in figure 10, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad of 2 oz. copper (figure 10.a), ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 10.b) reduces the ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 10.e) reduces the ja to 49 c/w. junction r die r die-attach r die-pad r gold-line r lead frame case (exposed pad) r pcb r pcb ambient r molding-compound path 1 path 2 path 3
rt9173d 12 ds9173d-06 december 2007 www.richtek.com ja vs. copper area 30 40 50 60 70 80 90 100 0 10203040506070 copper area (mm 2 ) ja (c/w) figure 8 figure 9.dog-bone layout figure 10. thermal resistance vs. different cooper area layout design figure 10 (a). minimum footprint, ja = 75 c/w figure 10 (b). copper area = 10mm 2 , ja = 64 c/w figure 10 (c). copper area = 30mm 2 , ja = 54 c/w figure 10 (d). copper area = 50mm 2 , ja = 51 c/w figure 10 (e). copper area = 70mm 2 , ja = 49 c/w exposed pad w Q 2.28mm
rt9173d 13 ds9173d-06 december 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com outline information a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package symbol dimensions in millimeters dimensions in inches min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 option 1 x 2.000 2.300 0.079 0.091 y 2.000 2.300 0.079 0.091 option 2 x 2.100 2.500 0.083 0.098 y 3.000 3.500 0.118 0.138

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