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| 1 of 23 rev: 071305 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds1553 is a full-function, year-2000- compliant (y2kc) real-time clock/calendar (rtc) with an rtc alarm, watchdog timer, power-on reset, battery monitor, and 8k x 8 nonvolatile static ram. user access to all registers within the ds1553 is accomplished with a byte-wide interface as shown in figure 1. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour bcd format. corrections for day of month and leap year are made automatically. pin configurations appear at end of data sheet. features integrated nv sram, rtc, crystal, power-fail control circuit, and lithium energy source clock registers are accessed identically to the static ram; these registers are resident in the 16 top ram locations totally nonvolatile with over 10 years of operation in the absence of power precision power-on reset programmable watchdog timer and rtc alarm bcd-coded year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 battery voltage level indicator flag power-fail write protection allows for 10% v cc power-supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ordering information part voltage (v) temp range pin-package top mark** ds1553-70 5.0 0c to +70c 28 edip (0.740) ds1553-70 ds1553-70+ 5.0 0c to +70c 28 edip (0.740) ds1553+70 ds1553-100 5.0 0c to +70c 28 edip (0.740) ds1553-100 ds1553w-120 3.3 0c to +70c 28 edip (0.740) ds1553w-120 ds1553w-120+ 3.3 0c to +70c 28 edip (0.740) ds1553w+120 ds1553w-150 3.3 0c to +70c 28 edip (0.740) ds1553w-150 ds1553p-70 5.0 0c to +70c 34 powercap?* ds1553p-70 ds1553p+70 5.0 0c to +70c 34 powercap* ds1553p+70 ds1553p-100 5.0 0c to +70c 34 powercap* ds1553p-100 ds1553wp-120 3.3 0c to +70c 34 powercap* ds1553wp-120 ds1553wp-120+ 3.3 0c to +70c 34 powercap* ds1553wp+120 ds1553wp-150 3.3 0c to +70c 34 powercap* ds1553wp-150 ds9034pcx 3 0c to +70c ? ds9034pcx + denotes a lead-free/rohs-compliant device. * powercap required, must be ordered separately ** a ?+? symbol anywhere on the top mark indicates a lead-free device. powercap is a registered trademark of dallas semiconductor. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram www.maxim-ic.com
ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 2 of 23 pin description pin edip powercap name function 1 2 rst active-low power-on reset output (open drain) 2 30 a12 3 25 a7 4 24 a6 5 23 a5 6 22 a4 7 21 a3 8 20 a2 9 19 a1 10 18 a0 21 28 a10 23 29 a11 24 27 a9 25 26 a8 address inputs 11 16 dq0 12 15 dq1 13 14 dq2 15 13 dq3 16 12 dq4 17 11 dq5 18 10 dq6 19 9 dq7 data input/outputs 20 8 ce active-low chip enable 22 7 oe active-low output enable 26 1 irq /ft active-low interrupt/frequency test output (open drain) 27 6 we active-low write enable 28 5 v cc power-supply input 17 gnd ground ? 2, 3, 31?34 n.c no connection ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 3 of 23 detailed description the rtc registers in the ds1553 are double-buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. assumin g the internal oscillator is turned on, the internal set of registers is continuously updated. this occurs re gardless of external registers settings to guarantee that accurate rtc information is always maintained. the ds1553 has interrupt ( irq /ft) and reset ( rst ) outputs that can be used to control cpu activity. the irq /ft interrupt output can be used to generate an external interrupt when the rtc register values match user-programmed alarm values. the interrupt is always available while the device is powered from the system supply, and it can be programmed to occu r when in the battery-backed state to serve as a system wakeup. either the irq /ft or rst outputs can also be used as a cpu watchdog timer. cpu activity is monitored and an interrupt or reset output is activated if the correct activity is not detected within programmed limits. the ds1553 pow er-on reset can be used to detect a system power-down or failure and can hold the cpu in a safe reset state until normal power returns and stabilizes. the rst output is used for this function. the ds1553 also contains its own power-fail circuitry, which automatically deselects the device when the v cc supply enters an out-of-tolerance condition. this feature provides a high de gree of data security during unpredictable system operation brought on by low v cc levels. packages the ds1553 is available in a 28-pin dip and a 34-pin powercap module. the 28-pin dip module integrates the crystal, lithium energy source, and silicon in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds 9034pcx) that contains the crystal and battery. this design allows the powe rcap to be mounted on top of the ds1553p after completion of the surface-mount process. mountin g the powercap after the surface-mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. th e powercap module board and powercap are ordered separately and shipped in sepa rate containers. the part numbe r for the powercap is ds9034pcx. figure 1. block diagram ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 4 of 23 table 1. operating modes v cc ce oe we dq0?dq7 mode power v ih x x high-z deselect standby v il x v il d in write active v il v il v ih d out read active v cc > v pf v il v ih v ih high-z read active v so < v cc ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 6 of 23 clock operations table 2 and the following paragraphs describe th e operation of rtc, alarm, and watchdog functions. table 2. register map data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 1fffh 10 year year year 00-99 1ffeh x x x 10 m month month 01-12 1ffdh x x 10 date date date 01-31 1ffch x ft x x x day day 01-07 1ffbh x x 10 hour hour hour 00-23 1ffah x 10 minutes minutes minutes 00-59 1ff9h osc 10 seconds seconds seconds 00-59 1ff8h w r 10 century century control 00-39 1ff7h wds bmb 4 bmb3 bmb2 bmb 1 bmb 0 rb 1 rb0 watchdog 1ff6h ae y abe y y y y y interrupts 1ff5h am4 y 10 date da te alarm date 01-31 1ff4h am3 y 10 hours h ours alarm hours 00-23 1ff3h am2 10 minutes minutes alarm minutes 00-59 1ff2h am1 10 seconds seconds alarm seconds 00-59 1ff1h y y y y y y y y unused ? 1ff0h wf af 0 blf 0 0 0 0 flags ? x = unused, read/writable under write and read bit control ae = alarm flag enable ft = frequency test bit y = unused, read/writable without write and read bit control osc = oscillator start/stop bit abe = alarm in battery-backup mode enable w = write bit am1?am4 = alarm mask bits r = read bit wf = watchdog flag wds = watchdog steering bit af = alarm flag bmb0?bmb4 = watchdog multiplier bits 0 = 0 read only rb0?rb1 = watchdog resolution bits blf = battery low flag clock oscillator control the clock oscillator may be stopped at any time. to increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb of the seconds register (b7 of 1ff9h). setting it to 1 stops the oscillator; setting it to 0 starts the oscillator. the ds1553 is shipped fro m dallas semiconductor with the cloc k oscillator turned off, with the osc bit set to 1. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 7 of 23 reading the clock when reading the rtc data, it is recommended to ha lt updates to the external set of double-buffered rtc registers. this puts the external registers into a static state, allowing data to be read without register values changing during the read process. normal update s to the internal registers continue while in this state. external updates are halted when a 1 is written into the read bit, b6 of the control register (1ff8h). as long as a 1 remains in the cont rol register read bit, updating is halted. after a halt is issued, the registers reflect the rtc count (d ay, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of regi sters resume within 1 second after the read bit is set to 0 for a minimum of 500 s. the read bit must be 0 for a minimum of 500 s to ensure the external registers are updated. setting the clock the 8th bit, b7 of the control register, is the write bit. setting the write bit to 1, like the read bit, halts updates to the ds1553 (1ff8h?1fffh) registers. after setting the write bit to 1, rtc registers can be loaded with the desired rtc count (day, date, and time) in 24-hour bcd format. setting the write bit to 0 then transfers the values written to the internal rtc registers and allows normal operation to resume. clock accuracy (dip module) the ds1553 is guaranteed to keep time accuracy to within 1 minute per month at +25 c. the rtc is calibrated at the factory by dalla s semiconductor using nonvola tile tuning elements and does not require additional calibration. for this r eason, methods of field clock calib ration are not available and not necessary. the electrical environment also affects clock accuracy and caution should be taken to place the rtc in the lowest level emi section of the pc board layout. for additional information, refer to application note 58: crystal considerations with dallas real-time clocks , available on our website at www.maxim-ic.com/appnoteindex.com . clock accuracy (powercap module) the ds1553 and ds9034pcx are each i ndividually tested for accuracy. once mounted together, the module typically keeps time accuracy to within 1.53 minutes per month (35ppm) at +25c. the electrical environment aff ects clock accuracy and caution should be taken to place the rtc in the lowest level emi section of the pc board layout . for additional information, refer to application note 58: crystal considerations with dallas real-time clocks , available on our website at www.maxim-ic.com/appnoteindex.com . frequency test mode the ds1553 frequency test mode uses the open-drain irq /ft output. with the oscillator running, the irq /ft output toggles at 512hz when the ft bit is 1, the alarm flag enable bit (ae) is 0, and the watchdog steering bit (wds) is 1 or the watchdog register is reset (register 1ff7h = 00h). the irq /ft output and the frequency test mode can be used as a measure of the actual frequency of the 32.768khz rtc oscillator. the irq /ft pin is an open-drain output that requires a pullup resistor for proper operation. the ft bit is cleared to 0 on power-up. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 8 of 23 using the clock alarm the alarm settings and control for the ds1553 reside within registers 1ff2h?1ff5h. register 1ff6h contains two alarm-enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the ds1553 is in the battery-backed state of operation to serve as a system wakeup. alarm mask bits am1?am4 control the alarm mode. table 3 shows the possible settings. configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting. table 3. alarm mask bits am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match when the rtc register values match alarm register se ttings, the alarm flag bit (af) is set to 1. if the alarm flag enable (ae) is also set to 1, the alarm condition activates the irq /ft pin. the irq /ft signal is cleared by a read or write to the flags register (address 1ff0h) as shown in figures 2 and 3. when ce is active, the irq /ft signal may be cleared by having the addr ess stable for as short as 15ns and either oe or we active, but it is not guaranteed to be cleared unless t rc is fulfilled. the alarm flag is also cleared by a read or write to the flags register, but the flag does not change states until the end of the read/write cycle and the irq /ft signal has been cleared. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 9 of 23 figure 2. clearing irq waveforms figure 3. clearing irq waveforms the irq /ft pin can also be activated in the battery-backed mode. the irq /ft goes low if an alarm occurs and both abe and ae are set. the abe and ae bits are cleared during the power-up transition, however, an alarm generated during power-up sets af. therefore, the af bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. figure 4 illustrates alarm timing during the battery-backup mode and power-up states. figure 4. backup mode alarm waveforms ce = ? ce , ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 10 of 23 using the watchdog timer the watchdog timer can be used to detect an out-of-control processor. the user programs the watchdog timer by setting the desired amount of timeout into the 8-bit watchdog register (address 1ff7h). the five watchdog register bits bmb4?bmb0 store a bina ry multiplier and the two lower-order bits rb1?rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (f or example: writing 00001110 in the watchdog register = 3 x 1 second or 3 seconds.) if the processor does not reset the timer within the specified period, the watchdog flag (wf) is set and a processor interr upt is generated and stays active until either the watchdog flag (wf) is read or the watchdo g register (1ff7) is read or written. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to 0, the watchdog activates the irq /ft output when the watchdog times out. when wds is set to 1, the watchdog outputs a negative pulse on the rst output for 40ms to 200ms. the watchdog register (1ff7) and the ft bit are reset to 0 at the end of a watchdog timeout when the wds bit is set to 1. the watchdog timer resets when the processor performs a read or write of the watchdog register. the timeout period then starts over. writing a value of 00h to the watchdog register disables the watchdog timer. the watchdog function is automatically disa bled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft output and the frequency test function is activated, the watchdog function prevails a nd the frequency test function is denied. power-on default states upon application of power to the device, th e following register bits are set to 0: wds = 0, bmb0?bmb4 = 0, rb0?rb1 = 0, ae = 0, and abe = 0. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 11 of 23 absolute maximum ratings voltage range on any pin rela tive to ground?????????????????..-0.3v to +6.0v storage temperature range????????????????????????..-40 c to +85 c soldering temperature??????????????...260c for 10 seconds (dip package) (note 8) see ipc/jedec standard j-std-020a for surface-mount devices this is a stress rating only and functional operation of the d evice at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. operating range range temp range v cc commercial 0c to +70c 3.3v 10% or 5v 10% recommended dc operating conditions (t a = over the operating range.) parameter symbol min typ max units notes v cc = 5v 10% v ih 2.2 v cc x +0.3v v 1 logic 1 voltage all inputs v cc = 3.3v 10% v ih 2.0 v cc x +0.3v v 1 v cc = 5v 10% v il -0.3 +0.8 1 logic 0 voltage all inputs v cc = 3.3v 10% v il -0.3 +0.6 1 dc electrical characteristics (v cc = 5.0v ? 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 1 3 ma 2, 3 cmos standby current ( ce ? v cc - 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 v 1 i out = 2.1ma, dq0-7 outputs v ol1 0.4 v 1 output logic 0 voltage i out = 7.0ma, irq /ft and rst outputs v ol2 0.4 v 1, 5 write protection voltage v pf 4.20 4.50 v 1 battery switchover voltage v so v bat v 1, 4 ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 12 of 23 dc electrical characteristics (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current ( ce ? v cc - 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 v 1 i out = 2.1ma, dq0?7 outputs v ol1 0.4 v 1 output logic 0 voltage i out = 7.0ma, irq /ft and rst outputs v ol2 0.4 v 1, 5 write protection voltage v pf 2.75 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 figure 5. read cycle timing diagram ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 13 of 23 read cycle, ac characteristics (v cc = 5.0v ? 10%, t a = over the operating range.) 70ns access 100ns access parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq low-z t cel 5 5 ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq low-z t oel 5 5 ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 5 5 ns read cycle, ac characteristics (v cc = 3.3v 10%, t a = over the operating range.) 120ns access 150ns access parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce to dq low-z t cel 5 5 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns oe to dq low-z t oel 5 5 ns oe access time t oea 100 130 ns oe data off time t oez 35 35 ns output hold from address t oh 5 5 ns ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 14 of 23 write cycle, ac characteristics (v cc = 5.0v 10%, t a = over the operating range.) 70ns access 100ns access parameter symbol min max min max units notes write cycle time t wc 70 100 ns address access time t as 0 0 ns we pulse width t wew 50 70 ns ce pulse width t cew 60 75 ns data setup time t ds 30 40 ns data hold time t dh 0 0 ns address hold time t ah 5 5 ns we data off time t wez 25 35 ns write recovery time t wr 5 5 ns write cycle, ac characteristics (v cc = 3.3v 10%, t a = over the operating range.) 120ns access 150ns access parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 0 0 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 40 50 ns write recovery time t wr 10 10 ns ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 15 of 23 figure 6. write cycle timing, write-enable controlled figure 7. write cycle timing, chip-enable controlled ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 16 of 23 power-up/down characteristics (v cc = 5.0v ? 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 figure 8. power-up/down waveform timing 5v device ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 17 of 23 power-up/down characteristics (v cc = 3.3v ? 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 figure 9. power-up/down waveform timing 3.3v device capacitance (t a = +25c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf 1 capacitance on irq /ft, rst , and dq pins c io 10 pf 1 ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 18 of 23 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltage referenced to ground. 2) typical values are at +25 c and nominal supplies. 3) outputs are open. 4) battery switch over occurs at the lowe r of either the battery voltage or v pf . 5) the irq /ft and rst outputs are open drain. 6) data retention time is at +25 c. 7) each ds1553 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 8) real-time clock modules (dip) can be successfu lly processed through conve ntional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or a pply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 19 of 23 pin configurations powercap is a registered trademark of dallas semiconductor. 1 ir q / ft 2 3 n.c. n.c. rs t v cc w e o e c e dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c. n.c. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 n.c. a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 n.c. x1 gnd v bat x2 34-pin powercap module board (uses ds9034pcx powercap) ds1553 28-pin encapsulated package (700-mil extended) v cc we i r q /ft a 8 a 9 a 11 oe a 10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rs t a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ds1553 top view ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 20 of 23 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg 28-pin dim min max a in. mm 1.470 37.34 1.490 37.85 b in. mm 0.675 17.75 0.740 18.80 c in. mm 0.315 8.51 0.335 9.02 d in. mm 0.075 1.91 0.105 2.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.45 k in. mm 0.015 0.43 0.025 0.58 ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 21 of 23 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) ds1553p pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c ? ? 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: dallas semiconductor recommends that powercap module bases experience one pass through solder reflo w oriented with the label side up (?live-bug?). hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 22 of 23 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) ds1553p with ds9034pcx attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 23 of 23 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) recommended powercap module land pattern inches pkg dim min nom max a ? 1.050 ? b ? 0.826 ? c ? 0.050 ? d ? 0.030 ? e ? 0.112 ? e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > real t ime c loc ks ds1553, ds1553p 64kb, nonvolatile, year-2000-c ompliant timekeeping ram quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-12 of 12 ds1553 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is ds1553-85+ mod;28 pin;630 mm dwg: 56-g0002-001a (pdf) use pkgcode/variation: mdf28+2 * 0c to +70c rohs/lead-free: lead free materials analysis ds1553-100 mod;28 pin;737 mm dwg: 56-g0001-001a (pdf) use pkgcode/variation: mdp28-2 * 0c to +70c rohs/lead-free: no materials analysis ds1553w-120 mod;28 pin;737 mm dwg: 56-g0001-001a (pdf) use pkgcode/variation: mdp28-2 * 0c to +70c rohs/lead-free: no materials analysis ds1553w-150 mod;28 pin;737 mm dwg: 56-g0001-001a (pdf) use pkgcode/variation: mdp28-2 * 0c to +70c rohs/lead-free: no materials analysis ds1553w-120+ mod;28 pin;737 mm dwg: 56-g0001-001a (pdf) use pkgcode/variation: mdp28+2 * 0c to +70c rohs/lead-free: lead free materials analysis ds1553-100+ mod;28 pin;737 mm dwg: 56-g0001-001a (pdf) use pkgcode/variation: mdp28+2 * 0c to +70c rohs/lead-free: lead free materials analysis ds1553wp-120+ pwrc p;34 pin;607 mm dwg: 56-g0003-001a1 (pdf) use pkgcode/variation: pc 1+2 * 0c to +70c rohs/lead-free: lead free materials analysis ds1553wp-150 pwrc p;34 pin;607 mm dwg: 56-g0003-001a1 (pdf) use pkgcode/variation: pc 1-2 * 0c to +70c rohs/lead-free: no materials analysis ds1553wp-120 pwrc p;34 pin;607 mm dwg: 56-g0003-001a1 (pdf) use pkgcode/variation: pc 1-2 * 0c to +70c rohs/lead-free: no materials analysis ds1553p fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is DS1553P-85+ pwrc p;34 pin;607 mm dwg: 56-g0003-001a1 (pdf) use pkgcode/variation: pc 1+2 * 0c to +70c rohs/lead-free: lead free materials analysis ds1553p-100+ pwrc p;34 pin;607 mm dwg: 56-g0003-001a1 (pdf) use pkgcode/variation: pc 1+2 * 0c to +70c rohs/lead-free: lead free materials analysis ds1553p-100 pwrc p;34 pin;607 mm dwg: 56-g0003-001a1 (pdf) use pkgcode/variation: pc 1-2 * 0c to +70c rohs/lead-free: no materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits 2 0 0 5 -0 7 -1 4 t his page las t modified: 2 0 0 7 -0 6 -1 8 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y |
Price & Availability of DS1553P-85
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