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n-channel mosfet apm7316 handling code temp. range package code package code k : sop-8 operating junction temp. range c : -55 to 150c handling code tu : tube tr : tape & reel lead free code l : lead free device blank : original device apm7316 k : apm7316 xxxxx xxxxx - date code lead free code ? 20v/6a, r ds(on) =25m ? (typ.) @ v gs = 4.5v r ds(on) =40m ? (typ.) @ v gs = 2.5v ? ? ? ? ? super high dense cell design ? ? ? ? ? reliable and rugged ? ? ? ? ? lead free available (rohs compliant) g1 s1 s2 g2 d1 d1 d2 d2 ? 8 g1 s1 d1 d1 (8) (7) (2) (1) g2 s2 d2 d2 (6) (5) (4) (3) note: anpec lead-free products contain molding compounds/die attach materials and 100% matte in plate termina- tion finish; which are fully compliant with rohs and compatible with both snpb and lead-free soldiering operations. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j std-020c for msl classifica- tion at lead-free peak reflow temperature.
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(t a = 25 c unless otherwise noted) symbol parameter rating unit v dss drain-source voltage 20 v gss gate-source voltage 16 v i d * continuous drain current 6 i dm * 300 s pulsed drain current v gs =4.5v 24 a i s * diode continuous forward current 2.3 a t j maximum junction temperature 150 t stg storage temperature range -55 to 150 c t a =25 c 2 p d * maximum power dissipation t a =100 c 0.8 w r ja * thermal resistance-junction to ambient 62.5 c/w note: *surface mounted on 1in 2 pad area, t 10sec. apm7316k symbol parameter test condition min. typ. max. unit static characteristics bv dss drain-source breakdown voltage v gs =0v, i ds =250 a 20 v v ds =18v, v gs =0v 1 i dss zero gate voltage drain current t j =85 c 30 a v gs(th) gate threshold voltage v ds =v gs , i ds =250 a 0.5 0.7 1 v i gss gate leakage current v gs =16v, v ds =0v 100 na v gs =4.5v, i ds =6a 25 35 r ds(on) a drain-source on-state resistance v gs =2.5v, i ds =2a 40 50 m ? v sd a diode forward voltage i sd =2.3a, v gs =0v 0.7 1.3 v gate charge characteristics b q g total gate charge 13 17 q gs gate-source charge 4.2 q gd gate-drain charge v ds =10v, v gs =4.5v, i ds =6a 3.3 nc
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%#&' (t a = 25 c unless otherwise noted) apm7316k symbol parameter test condition min. typ. max. unit dynamic characteristics b r g gate resistance v gs =0v,v ds =0v,f=1mhz 2 ? c iss input capacitance 675 c oss output capacitance 180 c rss reverse transfer capacitance v gs =0v, v ds =15v, frequency=1.0mhz 105 pf t d(on) turn-on delay time 16 32 t r turn-on rise time 40 74 t d(off) turn-off delay time 42 78 t f turn-off fall time v dd =10v, r l =10 ? , i ds =1a, v gen =4.5v, r g =6 ? 18 35 ns notes: a : pulse test ; pulse width 300 s, duty cycle 2%. b : guaranteed by design, not subject to production testing.
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- 1e-4 1e-3 0.01 0.1 1 10 30 1e-3 0.01 0.1 1 2 mounted on 1in 2 pad r ja : 62.5 o c/w 0.01 0.02 0.05 0.1 0.2 single pulse duty = 0.5 ()#$
i d - drain current (a) drain current t j - junction temperature ( c) safe operation area v ds - drain - source voltage (v) thermal transient impedance square wave pulse duration (sec) power dissipation p tot - power (w) t j - junction temperature ( c) i d - drain current (a) 0 20406080100120140160 0.0 0.5 1.0 1.5 2.0 2.5 t a =25 o c 0 20406080100120140160 0 2 4 6 8 t a =25 o c,v g =4.5v 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1ms rds(on) limit 1s t a =25 o c 10ms 100ms dc normalized transient thermal resistance
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' r ds(on) - on - resistance (m ? ) drain-source on resistance i d - drain current (a) t j - junction temperature ( c) gate threshold voltage v ds - drain-source voltage (v) i d - drain current (a) output characteristics transfer characteristics v gs - gate - source voltage (v) i d - drain current (a) normalized threshold voltage ()#$
%#&' 02468 0 4 8 12 16 20 24 2.5v 2v 1.5v v gs = 3, 4, 5, 6, 7, 8, 9, 10v 04812162024 0 10 20 30 40 50 60 70 v gs =4.5v v gs =2.5v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 4 8 12 16 20 t j =125 o c t j =25 o c t j =-55 o c -50 -25 0 25 50 75 100 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i ds =250 a
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. v ds - drain - source voltage (v) drain-source on resistance normalized on resistance t j - junction temperature ( c) c - capacitance (pf) v sd - source - drain voltage (v) source-drain diode forward i s - source current (a) capacitance gate charge q g - gate charge (nc) v gs - gate - source voltage (v) ()#$
%#&' 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.1 1 10 20 t j =150 o c t j =25 o c 0 4 8 12 16 20 0 200 400 600 800 1000 frequency=1mhz crss coss ciss 0 5 10 15 20 25 0 2 4 6 8 10 v ds =10v i ds = 6a -50 -25 0 25 50 75 100 125 150 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 r on @t j =25 o c: 25m ? v gs = 4.5v i ds = 6a
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/ millimeters inches dim min. max. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0.020 e2 1.27bsc 0.50bsc 18 8 h e e1 e2 0.015x45 d a a1 0.004max. 1 l sop-8 pin ( reference jedec registration ms-012)
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0 terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb), 100%sn lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 temperature time critical zone t l to t p !
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profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat temperature min (tsmin) temperature max (tsmax) time (min to max) (ts) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: temperature (t l ) time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak/classificatioon temperature (tp) see table 1 see table 2 time within 5 c of actual peak temperature (tp) 10-30 seconds 20-40 seconds ramp-down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. notes: all temperatures refer to topside of the package .measured on the body surface.
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t ao e w po p ko bo d1 d f p1 table 1. snpb entectic process ? package peak reflow temperatures package thickness volume mm 3 <350 volume mm 3 350 <2.5 mm 240 +0/-5 c 225 +0/-5 c 2.5 mm 225 +0/-5 c 225 +0/-5 c table 2. pb-free process ? package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 +0 c* 260 +0 c* 260 +0 c* 1.6 mm ? 2.5 mm 260 +0 c* 250 +0 c* 245 +0 c* 2.5 mm 250 +0 c* 245 +0 c* 245 +0 c* *tolerance: the device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 c. for example 260 c+0 c) at the rated msl level. #!
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%#&' test item method description solderability mil-std-883d-2003 245 c,5 sec holt mil-std 883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100% rh, 121 c tst mil-std 883d-1011.9 -65 c ~ 150 c, 200 cycles !
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anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 #-
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application carrier width cover tape width devices per reel sop- 8 12 9.3 2500 #
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%#&' a j b t2 t1 c application a b c j t1 t2 w p e 330 1 62 1.5 12.75 + 0.1 5 2 + 0.5 12.4 +0.2 2 0.2 12 + 0.3 - 0.1 8 0.1 1.75 0.1 f d d1 po p1 ao bo ko t sop-8 5.5 0.1 1.55 0.1 1.55+ 0.25 4.0 0.1 2.0 0.1 6.4 0.1 5.2 0.1 2.1 0.1 0.3 0.013 (mm)

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