? 2004 california micro devices corp. all rights reserved. 12/07/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 1 pacvga203 vga port companion circuit features ? single-chip solution fo r the vga port interface ? includes esd protection, level shifting, and rgb termination ? seven channels of esd protection for all vga port connector pins, meeting iec-61000-4-2 level-4 esd requirements (8kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines; 4pf typical ?75 ? termination resistors for video lines (matched to 1% typ.) ? ttl to cmos level-trans lating buffers with power- down mode for hsync and vsync lines ? bi-directional level shifting n-channel fets pro- vided for ddc_clk & ddc_data channels ? compact 24-pin qsop package ? lead-free version available applications ? notebook computers with vga port ? desktop pcs with vga port product description the pacvga203 incorporates seven channels of esd protection for all signal lines commonly found in a vga port. esd protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with iec-61000-4-2 level- 4 esd protection (8kv contact discharge). when a channel is subjected to an electrostatic discharge, the esd current pulse is diverted via the protection diodes into either the positive supply rail or ground where it may be safely dissipated. separate positive supply rails are provided for the video, ddc and sync channels to facilitate interf acing with low voltage video controller ics and provide de sign flexibility in multi- supply-voltage environments. two non-inverting drivers provide buffering for the hsync and vsync signals from the video controller ic (sync_in1, sync_in2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and v cc 4 (cont?d next page). simplified electrical schematic video_1 video_2 video_3 3 4 5 2 6 v cc 1 gndd gndd 75 75 75 gnda 8 9 10 term_1 term_2 term_3 gnda 7 r c v cc 2 ddc_in2 17 gndd gndd gndd v cc 3 18 ddc_out2 r c v cc 2 ddc_in1 16 gndd gndd gndd v cc 3 15 ddc_out1 12 14 gndd r b 19 gndd sync_in1 gndd v cc 4 23 sd1 v_bias sync_out1 pwr_up 1 13 20 11 r c gndd 21 gndd sync_in2 v cc 4 1 24 sd2 gndd sync_out2 22 r s r s d1
? 2004 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 12/07/04 pacvga203 product description (cont?d) these drivers have nominal 15 ? output impedance (r s ) which can be combined with an external resistor to match the characteristic impedance of the hsync & vsync lines of the video c ables typically used in pc applications. two n-channel fets provide the level shifting function required when the ddc controller is operated at a lower supply voltage than the monitor. three 75 ? resistors suitable fo r terminating the video signals from the video dac are also provided. these resistors have sepa rate input pins to allow insertion of additional emi filtering, if required, between the termi- nation point and the esd protection diodes. these resistors are matched to better than 2% for excellent signal level matching of the r/g/b signals. when the pwr_up input is driven low, the sync inputs can be floated without causing the sync buffers to draw any current from the v cc 4 supply. when the pwr_up input is low the sync outputs are driven low. v cc 3 can be derived from v cc 4, if desired, by connect- ing v cc 3 to v_bias. in applications where v cc 4 may be powered down, diode d1 blocks any dc current paths from the ddc_out pins back to the powered down v cc 4 rail via the top esd protection diodes. the pacvga203 device is housed in a 24-pin qsop package and is available with optional lead-free finish- ing. ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. package / pinout diagram note: this drawing is not to scale. top view 24-pin qsop 1 2 3 4 5 6 7 8 16 15 14 13 17 18 9 10 20 19 21 22 11 12 23 24 video_3 gndd gnda term_1 term_2 term_3 pwr_up v cc 2 v cc 4 v cc 1 video_1 video_2 sd1 sync_out2 sync_in2 sync_out1 sync_in1 ddc_out2 ddc_in2 ddc_in1 ddc_out1 v cc 3 v_bias sd2 part numbering information pins package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 24 qsop-24 pacvga203q pacvga203 q PACVGA203QR PACVGA203QR
? 2004 california micro devices corp. all rights reserved. 12/07/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 3 pacvga203 pin descriptions lead(s) name description 1v cc 4 positive voltage supply pi n. this is an isolated v cc pin for the sync_1, sync_2, sd1 and sd2 circuits. 2v cc 1 positive voltage supply pi n. this is an isolated v cc pin for the video_1, video_2 and video_3 esd circuits. 3-5 video_1, video_2, video_3 rgb video protection channels. these pins ti e to the rgb video lines (for example, the blue signal) between the vga contro ller device and the video connector. 6 gndd digital ground reference supply pin. 7 gnda ground reference supply pin fo r term_1, term_2 and term_3 pins. 8-10 term_1, term_2, term_3 rgb video termination channels. these pins ti e to the rgb video lin es (for example, the blue signal) providing a 75 ? termination to gnda for the given video channel. 11 pwr_up sync signal output 1. ties to the video connector side of one of the sync lines (for example the horizontal sync signal). 12 v cc 2 positive voltage supply pi n. this is an isolated v cc pin for the ddc_in1 and ddc_in2 input circuits. defines the logic one level for the ddc_outn outputs. 13 v_bias used to derive v cc3 from v cc4 input. 14 v cc 3 positive voltage supply pi n. this is an isolated v cc pin for the ddc_out1 and ddc_out2 esd protection circuits. 15 ddc_out1 ddc signal output 1. connects to the connector side of one of the ddc signals (for example, the bidirectional ddc_data serial line). 16 ddc_in1 ddc signal input 1. connects to the vg a controller side of one of the ddc signals (for example, the bidirectional ddc_data serial line). 17 ddc_in2 ddc signal input 2. connects to the vg a controller side of one of the ddc signals (for example, the bidirectional ddc_clk). 18 ddc_out2 ddc signal output 2. connects to the connector side of one of the ddc signals (for example, the bidirectional ddc_clk). 19 sync_in1 sync signal buffer input 1. connects to the vga controller side of one of the sync lines (for example, the horizontal sync signal). 20 sync_out1 sync signal buffer output 1. connects to the video connector side of one of the sync lines (for example the horizontal sync signal). 21 sync_in2 sync signal buffer input 2. connects to the vga controller side of one of the sync lines (for example, the vertical sync signal). 22 sync_out2 sync signal buffer output 2. connects to the video connector side of one of the sync lines (for example the vertical sync signal). 23 sd1 sync signal filter 1. connects to the vi deo connector side of one of the sync lines (for example the vertical sync signal). 24 sd2 sync signal filter 2. connects to the vi deo connector side of one of the sync lines (for example the horizontal sync signal).
? 2004 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 12/07/04 pacvga203 specifications absolute maximum ratings parameter rating units v cc 1,v cc 2,v cc 3, and v cc 4 supply voltage [gnd - 0.5] to +6.0 v diode d1 forward dc current 100 a operating temperature range -40 to +85 c storage temperature range -65 to +150 c dc voltage at inputs video_1, video_2, video_3 term_1, term_2, term_3 ddc_in1, ddc_in2 ddc_out1, ddc_out2 sync_in1, sync_in2 (gnd - 0.5) to (v cc 1 + 0.5) -6.0, +6.0 (gnd - 0.5) to (v cc 2 + 0.5) (gnd - 0.5) to (v cc 3 + 0.5) (gnd - 0.5) to (v cc 4 + 0.5) v v v v v package power rating 1000 mw standard operat ing conditions parameter rating units operating temperature range 0 to +70 c electrical operating characteristics (see note 1) symbol parameter conditions min typ max units i cc1 v cc 1 supply current v cc 1 = 5.0v, video inputs at v cc 1 or gnd level 10 a i cc2 , i cc3 v cc 2 & v cc 3 supply current v cc 2 = v cc 3 = 5.0v 10 a i cc4 v cc 4 supply current v cc 4 = 5.0v; sync inputs at gnd or v cc 4 level; pwr-up pin at v cc 4; sync outputs unloaded 10 a v cc 4 = 5.0v; sync inputs at 3.0v; pwr-up pin at v cc 4; sync outputs unloaded 200 a v cc 4 = 5.0v; pwr-up i nput at gnd; sync outputs unloaded 10 a v bias v bias open circuit voltage no external current drawn from v bias pin v cc 4-0.8 v r t video termination resistance 71.25 75 78.75 ? r t resistance matching 1 2 %
? 2004 california micro devices corp. all rights reserved. 12/07/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 5 pacvga203 note 1: all parameters specified over standar d operating conditions unless otherwise noted. note 2: this parameter applies only to the hsync and vsync channels. hsync and vsync have 24ma drivers with r s added in series to terminate transmission line. note 3: per the iec-61000-4-2 international esd standard, level 4 contact discharge method. v cc 1, v cc 3 and v cc 4 must be bypassed to gnd via a low impedance ground plane with a 0.2uf, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicable pins and g nd. esd pulse can be positive or negative with respect to gnd. applicable pins are: video_1, video_2, video_3, sd1, sd2, ddc_out1 and ddc_out2. all other pins are esd protected to the industry standard 2kv per the human body model (mil-std-883, method 3015). note 4: this parameter is guaranteed by design and characterization. v ih logic high input voltage v cc 4 = 5.0v; see note 2 2.0 v v il logic low input voltage v cc 4 = 5.0v; see note 2 0.8 v v oh logic high output voltage i oh = -4ma, v cc 4 = 5.0v; see note 2 4.94 v v ol logic low output voltage i ol = 4ma, v cc 4 = 5.0v; see note 2 0.06 v r oh output resistance see note 2 15 ? r ol 15 ? r b ,r p resistor value pwr_up = v cc 3 = 5.0v 0.5 1.0 2.0 m ? r c v cc 2 pull-down resistor value v cc 2 = 3.0v 0.5 1.5 3.0 m ? i n input current video inputs hsync, vsync inputs v cc 1= 5.0v; v in = v cc 1 or gnd v cc 4 = 5.0v; v in = v cc 4 or gnd + 1 + 1 a a i off off-state leakage current, level-shifting nfet (v cc 2 - v ddc_in ) < 0.4v; v ddc_out = v cc 2 (v cc 2 - v ddc_out ) < 0.4v; v ddc_in = v cc 2 10 10 a a v on voltage drop across level shifting nfet when turned on v cc 2= 2.5v; v s = gnd; i ds = 3ma 0.15 v c in input capacitance video_1,video_2 & video_3 inputs note 4 applies for all cases; v cc 1 = 5.0v; v in = 2.5v; measured at 1mhz v cc 1 = 2.5v; v in = 1.25v; measured at 1mhz 3.0 3.0 4.0 4.5 5.0 5.6 pf pf t plh sync drivers l => h propagation delay c l = 50pf; v cc =5.0v,input t r and t f < 5ns 8.0 12.0 ns t phl sync drivers h => l propagation delay c l = 50pf; v cc =5.0v; input t r and t f < 5ns 8.0 12.0 ns t r, t f sync drivers output rise & fall times c l = 50pf; v cc =5.0v; input t r and t f < 5ns (measured 10% - 90%) 5.0 7.0 10.0 ns v esd esd withstand voltage v cc 1 = v cc 3 = v cc 4 = 5v; notes 3 & 4 8kv electrical operating characteristics (see note 1) (cont?d) symbol parameter conditions min typ max units
? 2004 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 12/07/04 pacvga203 test circuit information average current through v cc 4 (i cc 4) the circuit in figure 1 was used to characterize i cc 4 current as sync_in signal frequency varies. a square wave signal was connected to the input of on e of the sync buffers (i.e. pin 19 or pin 21). the frequency of this signal was varied between 0 and 100 khz. the risetime and falltim e was kept constant at 10ns . three different values of c1 were used: 0pf, 50pf and 100pf. the results are plotted in figure 2 . figure 1. sync buffer i cc 4 test circuit figure 2. i cc 4 vs. sync_in frequency performance data 0v v cc 4 +5v sync_in i cc 4 c1 sync_out 3.3v i cc4 vs. sync_in frequency 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 frequency, khz i cc4 ,ua 100pf 50pf 0pf
? 2004 california micro devices corp. all rights reserved. 12/07/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 7 pacvga203 application information figure 3. typical connection diagram a resistor may be necessary between the v cc 3 pin and ground if protection ag ainst a stream of esd pulses is required while the pacvga203 is in th e power-down state. the va lue of this resistor sh ould be chosen such that the extra charge deposited into the v cc 3 bypass capacitor by each esd pul se will be discharged before the next esd pulse occurs. the maximum esd repetition rate sp ecified by the iec-61000-4-2 standard is one pulse per second. when the pacvga203 is in the power-up state, an internal discharge resistor is connected to ground via an fet switch for this purpose. for the same reason, v cc 1 and v cc 4 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. gnda, the reference voltage for the 75 ? resistors is not connected internally to gndd and should ideally be con- nected to the ground of the video dac ic. red r1 r2 8 9 10 19 21 16 17 7 6 14 2 12 video connector video controller h-sync v-sync ddc_data ddc_clk blue grn h-sync v-sync ddc_data ddc_clk r g b pacvga203 gnda gndd ddc_in1 ddc_in2 sync_in1 sync_in2 term_1 term_2 term_3 3 video_1 video_2 video_3 4 5 vf** vf** vf** 0.2uf v cc 2v cc 1 v cc 4 pwr_up ddc_out1 ddc_out2 sync_out1 sync_out2 18 15 22 20 video_dac_v cc 13 v cc 3v_bias 0.2uf gndd 0.2uf 0.2uf gndd sd1 sd2 24 sf** sf** 23 11 1 ddc_v cc 5v vf** - video emi filter sf** - sync emi filter sr* sr* sr* - external resistor to match video cable characteristic impedance.
? 2004 california micro devices corp. all rights reserved. 8 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 12/07/04 pacvga203 mechanical details qsop mechanical specifications: pacvga203 devices are packaged in 24-pin qsop packages. dimensions are presented below. for complete information on the qsop-24 package, see the california micro devices qsop package infor- mation document. * this is an approximate number which may vary. package dimensions for qsop-24 package dimensions package qsop (jedec name is ssop) pins 24 dimensions millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 8.56 8.73 0.337 0.344 e 3.81 3.98 0.150 0.157 e 0.64 bsc 0.025 bsc h 5.79 6.19 0.228 0.244 l 0.40 1.27 0.016 0.050 # per tube 55 pcs* # per tape and reel 2500 pcs controlling dimension: inches mechanical package diagrams e d h top view l end view c e b a a1 seating plane side view 5678 910 1234 20 19 18 17 16 15 24 23 22 21 pin 1 marking 11 12 14 13
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