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_______________general description the max195 is a 16-bit successive-approximation ana- log-to-digital converter (adc) that combines high speed, high accuracy, low power consumption, and a 10? shutdown mode. internal calibration circuitry cor- rects linearity and offset errors to maintain the full rated performance over the operating temperature range with- out external adjustments. the capacitive-dac architec- ture provides an inherent 85ksps track/hold function. the max195, with an external reference (up to +5v), offers a unipolar (0v to v ref ) or bipolar (-v ref to v ref ) pin-selectable input range. separate analog and digital supplies minimize digital-noise coupling. the chip select ( cs ) input controls the three-state serial- data output. the output can be read either during conver- sion as the bits are determined, or following con version at up to 5mbps using the serial clock (sclk). the end-of- conversion ( eoc ) output can be used to interrupt a processor, or can be connected directly to the convert input ( conv ) for continuous, full-speed conversions. the max195 is available in 16-pin dip, wide so, and ceramic sidebraze packages. ________________________applications portable instruments audio industrial controls robotics multiple transducer measurements medical signal acquisition vibrations analysis digital signal processing ____________________________features ? 16 bits, no missing codes ? 90db sinad ? 9.4? conversion time ? 10? (max) shutdown mode ? built-in track/hold ? ac and dc specified ? unipolar (0v to v ref ) and bipolar (-v ref to v ref ) input range ? three-state serial-data output ? small 16-pin dip, so, and ceramic sb packages ______________ordering information max195 16-bit, 85ksps adc with 10? shutdown ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vdda vssa agnd ain vddd sclk clk bp/up/shdn top view max195 ref vssd reset conv cs eoc dgnd dout dip/wide so/ceramic sb max195 ain ref conv sclk clk bp/up/shdn cs reset vssd dgnd vddd vdda agnd vssa dout eoc sar control logic comparator calibration dacs three-state buffer 4 6 11 16 14 15 5 7 10 8 1 9 3 2 13 12 main dac s ________________functional diagram __________________pin configuration 19-0377; rev 1; 12/97 part max195bcpe max195bcwe max195acde 0? to +70? 0? to +70? 0? to +70? temp. range pin-package 16 plastic dip 16 wide so 16 ceramic sb max195bc/d 0? to +70? dice* max195bepe -40? to +85? 16 plastic dip max195bewe -40? to +85? 16 wide so max195aede -40? to +85? 16 ceramic sb max195amde -55? to +125? 16 ceramic sb** max195bmde -55? to +125? 16 ceramic sb** evaluation kit available * dice are specified at t a = +25?, dc parameters only. ** contact factory for availability and processing to mil-std-883. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468.
max195 16-bit, 85ksps adc with 10 a shutdown 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (vddd = vdda = +5v, vssd = vssa = -5v, f clk = 1.7mhz, v ref = +5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. vddd to dgnd ..................................................................... +7v vdda to agnd ...................................................................... +7v vssd to dgnd ......................................................... +0.3v to -6v vssa to agnd ......................................................... +0.3v to -6v vddd to vdda, vssd to vssa .......................................... 0.3v ain, ref .................................... (vssa - 0.3v) to (vdda + 0.3v) agnd to dgnd .................................................................. 0.3v digital inputs to dgnd ............................... -0.3v, (vdda + 0.3v) digital outputs to dgnd ............................ -0.3v, (vdda + 0.3v) continuous power dissipation (t a = +70 c) plastic dip (derate 10.53mw/ c above +70 c) ............ 842mw wide so (derate 9.52mw/ c above +70 c) .................. 762mw ceramic sb (derate 10.53mw/ c above +70 c) ........... 842mw operating temperature ranges max195_c_e ........................................................ 0 c to +70 c max195_e_e ..................................................... -40 c to +85 c max195_mde .................................................. -55 c to +125 c storage temperature range ............................. -65 c to +160 c lead temperature (soldering, 10sec) ............................. +300 c max195a 16 (t clk ) t a = +25 c t a = +25 c unipolar v ref = 4.75v max195a max195b max195a, v ref = 4.75v vssa = -5.25v to -4.75v, v ref = 4.75v max195b, v ref = 4.75v vdda = 4.75v to 5.25v, v ref = 4.75v conditions mhz 1.7 f clk clock frequency (notes 3, 4) s 9.4 t conv conversion time db -90 peak spurious noise (note 2) db -97 -90 thd total harmonic distortion (up to the 5th harmonic) (note 2) v 0 v ref input range db 65 power-supply rejection ratio (vdda and vssa only) 65 1 bits 16 res resolution ppm/ c 0.1 full-scale tempco %fsr unipolar full-scale error 0.0075 unipolar/bipolar offset tempco ppm/ c 0.4 0.003 %fsr 0.004 inl integral nonlinearity 3 lsb 4 unipolar/bipolar offset error units min typ max symbol parameter unipolar pf 250 input capacitance t a = +25 c db 87 90 sinad signal-to-noise plus distortion ratio (note 2) mhz 5 f sclk serial clock frequency bipolar bipolar 125 -v ref v ref v ref = 4.75v %fsr bipolar full-scale error 0.018 max195b lsb 2 dnl accuracy (note 1) analog input dynamic performance (f s = 85khz, bipolar range ain = -5v to +5v, 1khz) (note 1) differential nonlinearity
max195 16-bit, 85ksps adc with 10 a shutdown _______________________________________________________________________________________ 3 electrical characteristics (continued) (vddd = vdda = +5v, vssd = vssa = -5v, f clk = 1.7mhz, v ref = +5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) bp/up/ shdn = open vddd = 5.25v bp/up/ shdn = open bp/up/ shdn = 0v bp/up/ shdn = vddd digital inputs = 0 or 5v vddd = 4.75v conditions na -100 +100 bp/up/ shdn max allowed leakage, mid input v 2.75 v flt bp/up/ shdn voltage, floating v 1.5 vddd - 1.5 v im bp/up/ shdn mid input voltage a -4.0 i il bp/up/ shdn input current, low a 4.0 i ih bp/up/ shdn input current, high v 0.5 v il bp/up/ shdn input low voltage v 2.4 v ih clk, cs , conv , reset , sclk input high voltage v vddd - 0.5 v ih bp/up/ shdn input high voltage a 10 clk, cs , conv , reset , sclk input current v 0.8 v il clk, cs , conv , reset , sclk input low voltage pf 10 clk, cs , conv , reset , sclk input capacitance (note 3) units min typ max symbol parameter output low voltage v ol vddd = 4.75v, i sink = 1.6ma 0.4 v output high voltage v oh vddd = 4.75v, i source = 1ma vddd - 0.5 v dout leakage current i lkg dout = 0 or 5v 10 a output capacitance (note 2) 10 pf vddd 4.75 5.25 v vssd -5.25 -4.75 v vdda by supply-rejection test 4.75 5.25 v vssa by supply-rejection test -5.25 -4.75 v vddd supply current i ddd vddd = vdda = 5.25v, vssd = vssa = -5.25v 2.5 4 ma vssd supply current i ssd vddd = vdda = 5.25v, vssd = vssa = -5.25v 0.9 2 ma vdda supply current i dda vddd = vdda = 5.25v, vssd = vssa = -5.25v 3.8 5 ma vssa supply current i ssa vddd = vdda = 5.25v, vssd = vssa = -5.25v 3.8 5 ma digital inputs (clk, cs , conv , reset , sclk, bp/up/ shdn ) digital outputs (dout, eoc ) power requirements
max195 16-bit, 85ksps adc with 10 a shutdown 4 _______________________________________________________________________________________ vddd = vdda = 5.25v, vssd = vssa = -5.25v vddd = vdda = 5.25v, vssd = vssa = -5.25v, bp/up/ shdn = 0v vddd = vdda = 5.25v, vssd = vssa = -5.25v, bp/up/ shdn = 0v vddd = vdda = 5.25v, vssd = vssa = -5.25v, bp/up/ shdn = 0v vddd = vdda = 5.25v, vssd = vssa = -5.25v, bp/up/ shdn = 0v conditions mw 80 power dissipation a 0.1 5 i ssa vssa shutdown supply current a 0.1 5 i dda vdda shutdown supply current a 1.6 5 i ddd vddd shutdown supply current (note 5) a 0.1 5 i ssd vssd shutdown supply current units min typ max symbol parameter electrical characteristics (continued) (vddd = vdda = +5v, vssd = vssa = -5v, f clk = 1.7mhz, v ref = +5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) timing characteristics (vddd = vdda = +5v, vssd = vssa = -5v, unless otherwise noted.) note 1: accuracy and dynamic performance tests performed after calibration. note 2: guaranteed by design, not tested. note 3: tested with 50% duty cycle. duty cycles from 25% to 75% at 1.7mhz are acceptable. note 4: see external clock section. note 5: measured in shutdown mode with clk and sclk low. power requirements (cont.) parameter symbol conditions t a = +25 c typ t a = 0 c to +70 c min max t a = -40 c to +85 c min max t a = -55 c to +125 c min max units conv pulse width t cw 20 30 35 ns conv to clk falling synchronization (note 2) t cc1 10 10 10 ns conv to clk rising synchronization (note 2) t cc2 40 40 ns data access time t dv c l = 50pf 80 80 40 ns bus relinquish time t dh c l = 10pf 40 40 40 ns clk to eoc high t ceh c l = 50pf 300 300 350 ns clk to eoc low t cel c l = 50pf 300 300 350 ns clk to dout valid t cd c l = 50pf 100 350 100 375 100 400 ns sclk to dout valid t sd c l = 50pf 20 140 20 160 20 160 ns cs to sclk setup time t css 75 75 75 ns cs to sclk hold time t csh -10 -10 -10 ns acquisition time t aq 2.4 2.4 2.4 s calibration time t cal 14,000 x t clk 8.2 8.2 8.2 ms reset to clk setup time t rcs -40 -40 -40 ns reset to clk hold time t rch 120 120 120 start-up time (note 6) t su exiting shutdown 50 ns 90 s note 6: settling time required after deasserting shutdown to achieve less than 0.1lsb additional error.
_______________ detailed description the max195 uses a successive-approximation register (sar) to convert an analog input to a 16-bit digital code, which outputs as a serial data stream. the data bits can be read either during the conversion, at the clk clock rate, or between conversions asynchronous with clk at the sclk rate (up to 5mbps). the max195 includes a capacitive digital-to-analog converter (dac) that provides an inherent track/hold input. the interface and control logic are designed for easy connection to most microprocessors ( ps), limiting the need for external components. in addition to the sar and dac, the max195 includes a serial interface, a sampling comparator used by the sar, ten calibration dacs, and control logic for calibration and conversion. the dac consists of an array of 16 capacitors with binary weighted values plus one ?ummy lsb?capaci - tor (figure 1). during input acquisition in unipolar mode, the array? common terminal is connected to agnd and all free terminals are connected to the input signal (ain). after acquisition, the common terminal is disconnected from agnd and the free terminals are disconnected from ain, trapping a charge proportional to the input voltage on the capacitor array. the free terminal of the msb (largest) capacitor is con - nected to the reference (ref), which pulls the common terminal (connected to the comparator) positive. simultaneously, the free terminals of all other capaci - tors in the array are connected to agnd, which drives the comparator input negative. if the analog input is near v ref , connecting the msb? free terminal to ref only pulls the comparator input slightly positive. however, connecting the remaining capacitor? free ter - minals to ground drives the comparator input well below ground, so the comparator input is negative, the comparator output is low, and the msb is set high. if the analog input is near ground, the comparator output is high and the msb is low. following this, the next largest capacitor is disconnect - ed from agnd and connected to ref, and the com - parator determines the next bit. this continues until all bits have been determined. for a bipolar input range, the msb capacitor is connected to ref rather than ain during input acquisition, which results in an input range of v ref to -v ref . max195 16-bit, 85ksps adc with 10 a shutdown _______________________________________________________________________________________ 5 ______________________________________________________________ pin description pin name function 1 bp/up/ shdn bipolar/unipolar/shutdown input. three-state input selects bipolar or unipolar input range, or shutdown. 0v = shutdown, +5v = unipolar, floating = bipolar. 2 clk conversion clock input 3 sclk serial clock input is used to shift data out between conversions. may be asynchronous to clk. 4 vddd +5v digital power supply 5 dout serial data output, msb first 6 dgnd digital ground 7 eoc end-of-conversion/calibration output?ormally low. rises one clock cycle after the beginning of conversion or calibration and falls one clock cycle after the end of either. may be used as an output framing signal. 8 cs chip-select input?ctive low. enables the serial interface and the three-state data output (dout). 9 conv convert-start input?ctive low. conversion begins on the falling edge after conv goes low if the input signal has been acquired; otherwise, on the falling clock edge after acquisition. 10 reset reset input. pulling reset low places the adc in an inactive state. rising edge resets control logic and begins calibration. 11 vssd -5v digital power supply 12 ref reference input, 0 to 5v 13 ain analog input, 0 to v ref unipolar or v ref bipolar range 14 agnd analog ground 15 vssa -5v analog power supply 16 vdda +5v analog power supply
max195 calibration in an ideal dac, each of the capacitors associated with the data bits would be exactly twice the value of the next smaller capacitor. in practice, this results in a range of values too wide to be realized in an economi - cally feasible size. the capacitor array actually consists of two arrays, which are capacitively coupled to reduce the lsb array? effective value. the capacitors in the msb array are production trimmed to reduce errors. small variations in the lsb capacitors contribute insignificant errors to the 16-bit result. unfortunately, trimming alone does not yield 16-bit per - formance or compensate for changes in performance due to changes in temperature, supply voltage, and other parameters. for this reason, the max195 includes a calibration dac for each capacitor in the msb array. these dacs are capacitively coupled to the main dac output and offset the main dac? output according to the value on their digital inputs. during calibration, the correct digital code to compensate for the error in each msb capacitor is determined and stored. thereafter, the stored code is input to the appropriate calibration dac whenever the corresponding bit in the main dac is high, compensating for errors in the associated capacitor. the max195 calibrates automatically on power-up. to reduce the effects of noise, each calibration experiment is performed many times and the results are averaged. calibration requires about 14,000 clock cycles, or 8.2ms at the highest clock (clk) speed (1.7mhz). in addition to the power-up calibration, bringing reset low halts max195 operation, and bringing it high again initiates a calibration (figure 2). 16-bit, 85ksps adc with 10 a shutdown 6 _______________________________________________________________________________________ msb ain ref agnd dummy lsb 32,768c 16,384c 4c 2c c c eoc clk reset calibration begins calibration ends max195 operation halts t cal t rcs t rch figure 1. capacitor dac functional diagram figure 2. initiating calibration
if the power supplies do not settle within the max195? power-on delay (500ns minimum), power-up calibration may begin with supply voltages that differ from the final values and the converter may not be properly calibrat - ed. if so, recalibrate the converter (pulse reset low) before use. for best dc accuracy, calibrate the max195 any time there is a significant change in sup - ply voltages, temperature, reference voltage, or clock characteristics (see external clock section) because these parameters affect the dc offset. if linearity is the only concern, much larger changes in these parame - ters can be tolerated. because the calibration data is stored digitally, there is no need either to perform frequent conversions to main - tain accuracy or to recalibrate if the max195 has been held in shutdown for long periods. however, recalibra - tion is recommended if it is likely that ambient tempera - ture or supply voltages have significantly changed since the previous calibration. digital interface the digital interface pins consist of bp/up/ shdn , clk, sclk, eoc , cs , conv , and reset . bp/up/ shdn is a three-level input. leave it floating to configure the max195? analog input in bipolar mode (ain = -v ref to v ref ) or connect it high for a unipolar input (ain = 0v to v ref ). bringing bp/up/ shdn low places the max195 in its 10 a shutdown mode. a logic low on reset halts max195 operation. the ris - ing edge of reset initiates calibration as described in the calibration section above. begin a conversion by bringing conv low. after con - version begins, additional convert start pulses are ignored. the convert signal must be synchronized with clk. the falling edge of conv must occur during the period shown in figures 3 and 4. when clk is not directly controlled by your processor, two methods of ensuring synchronization are to drive conv from eoc (continuous conversions) or to gate the conversion-start signal with the conversion clock so that conv can go low only while clk is low (figure 5). ensure that the maximum propagation delay through the gate is less than 40ns. the max195 automatically ensures four clk periods for track/hold acquisition. if, when conv is asserted, at least three clock (clk) cycles have passed since the end of the previous conversion, a conversion will begin on clk? next falling edge and eoc will go high on the following falling clk edge (figure 3). if, when convert is asserted, less than three clock cycles have passed, a conversion will begin on the fourth falling clock edge max195 16-bit, 85ksps adc with 10 a shutdown _______________________________________________________________________________________ 7 track/hold clk conversion begins conversion ends t aq * * the falling edge of conv must occur in this region t cel t cw t ceh t cc2 t cc1 eoc conv figure 3. initiating conversions?t least 3 clk cycles since end of previous conversion.
max195 after the end of the previous conversion and eoc will go high on the following clk falling edge (figure 4). external clock the conversion clock (clk) should have a duty cycle between 25% and 75% at 1.7mhz (the maximum clock frequency). for lower frequency clocks, ensure the min - imum high and low times exceed 150ns. the minimum clock rate for accurate conversion is 125hz for temper - atures up to +70 c or 1khz at +125 c due to leakage of the sampling capacitor array. in addition, clk should not remain high longer than 50ms at tempera - tures up to +70 c or 500 s at +125 c. if clk is held high longer than this, reset must be pulsed low to initi - ate a recalibration because it is possible that state information stored in internal dynamic memory may be lost. the max195? clock can be stopped indefinitely if it is held low. if the frequency, duty cycle, or other aspects of the clock signal? shape change, the offset created by cou - pling between clk and the analog inputs (ain and ref) changes. recalibration corrects for this offset and restores dc accuracy. output data the conversion result, clocked out msb first, is avail - able on dout only when cs is held low. otherwise, dout is in a high-impedance state. there are two ways to read the data on dout. to read the data bits as they are determined (at the clk clock rate), hold cs low during the conversion. to read results between conver - sions, hold cs low and clock sclk at up to 5mhz. if you read the serial data bits as they are determined, eoc frames the data bits (figure 6). conversion begins with the first falling clk edge, after conv goes low and the input signal has been acquired. data bits are shifted out of dout on subsequent falling clk edges. clock data in on clk? rising edge or, if the clock speed is greater than 1mhz, on the following falling edge of clk to meet the maximum clk-to-dout tim - ing specification. see the operating modes and spi/qspi interfaces section for additional informa - tion. reading the serial data during the conversion results in the maximum conversion throughput, because a new conversion can begin immediately after the input acquisition period following the previous con - version. 16-bit, 85ksps adc with 10 a shutdown 8 _______________________________________________________________________________________ track/hold clk conversion begins conversion ends t aq * * the falling edge of conv must occur in this region t cel t cw t ceh t cc2 t cc1 eoc conv figure 4. initiating conversions?ess than 3 clk cycles since end of previous conversion. spi/qspi are trademarks of motorola corp.
if you read the data bits between conversions, you can: 1) count clk cycles until the end of the conversion, or 2) poll eoc to determine when the conversion is finished, or 3) generate an interrupt on eoc ? falling edge. note that the msb conversion result appears at dout after cs goes low, but before the first sclk pulse. each subsequent sclk pulse shifts out the next con - version bit. the 15th sclk pulse shifts out the lsb. additional clock pulses shift out zeros. max195 16-bit, 85ksps adc with 10 a shutdown _______________________________________________________________________________________ 9 clk start conv max195 conv start clk see digital interface section cs conv clk (case 1) clk (case 2) eoc t dv t cd t cw t ceh case 1: clk idles low, data latched on rising edge (cpol = 0, cpha = 0) case 2: clk idles low, data latched on falling edge (cpol = 0, cpha = 1) note: arrows on clk transitions indicate latching edge t cel dout t dh b15 conversion begins conversion ends msb lsb b14 b13 b12 b2 b1 b0 b15 b15 from previous conversion figure 5. gating conv to synchronize with clk figure 6. output data format, reading data during conversion (mode 1)
max195 data is clocked out on sclk? falling edge. clock data in on sclk? rising edge or, for clock speeds above 2.5mhz, on the following falling edge to meet the maximum sclk-to-dout timing specification (figure 7). the maximum sclk speed is 5mhz. see the operating modes and spi/qspi interfaces section for additional information. when the conversion clock is near its maximum (1.7mhz), reading the data after each conversion (during the acquisition time) results in lower throughput (about 70ksps max) than reading the data during conversions, because it takes longer than the minimum input acquisition time (four cycles at 1.7mhz) to clock 16 data bits at 5mbps. after the data has been clocked in, leave some time (about 1 s) for any coupled noise on ain to settle before beginning the next conversion. whichever method is chosen for reading the data, con - versions can be individually initiated by bringing conv low, or they can occur continuously by connecting eoc to conv . figure 8 shows the max195 in its simplest operational configuration. 16-bit, 85ksps adc with 10 a shutdown 10 ______________________________________________________________________________________ eoc cs sclk (case 1) sclk (case 2) case 1: sclk idles low, data latched on rising edge (cpol = 0, cpha = 0) case 2: sclk idles low, data latched on falling edge (cpol = 0, cpha = 1) case 3: sclk idles high, data latched on falling edge (cpol = 1, cpha = 0) note: arrows on sclk transitions indicate latching edge dout sclk (case 3) t conv t dh t sd t dv msb lsb b15 b14 b13 b12 b3 b2 b1 b0 b11 t css t csh max195 10 m f bp/up/ shdn clk sclk vddd dout dgnd reference (0v to vdda) analog input -5v eoc cs vdda vssa agnd ain conversion clock +5v ref vssd reset conv 0.1 m f 10 m f 0.1 m f 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 figure 7. output data format, reading data between conversions (mode 2) figure 8. max195 in the simplest operating configuration
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 11 bridge instrumentation amplifier +5v ain max195 vdda agnd 47 m f low esr 0.1 m f ceramic ref company capacitor factory fax [country code] usa telephone sprague 595d series, 592d series 1-603-224-1430 603-224-1961 avx tps series 1-207-283-1941 800-282-4975 sanyo os-con series, mvgx series 81-7-2070-1174 619-661-6835 nichicon pl series 1-708-843-2798 708-843-7500 figure 9. ratiometric measurement without an accurate reference t ab le 1. lo w-esr capacitor supplier s __________ applications infor mation reference the max195 reference voltage range is 0v to vdda. when choosing the reference voltage, the max195? equivalent input noise (40 v rms in unipolar mode, 80 v rms in bipolar mode) should be considered. also, if v ref exceeds vdda, errors will occur due to the internal protection diodes that will begin to conduct, so use cau - tion when using a reference near vdda (unless v ref and vdda are virtually identical). v ref must never exceed its absolute maximum rating (vdda + 0.3v). the max195 needs a good reference to achieve its rated performance. the most important requirement is that the reference must present a low impedance to the ref input. this is often achieved by buffering the refer - ence through an op amp and bypassing the ref input with a large (1 f to 47 f), low-esr capacitor in parallel with a 0.1 f ceramic capacitor. low-esr capacitors are available from the manufacturers listed in table 1. the reference must drive the main conversion dac capacitors as well as the capacitors in the calibration dacs, all of which may be switching between gnd and ref at the conversion clock frequency. the total capacitive load presented can exceed 1000pf and, unlike the analog input (ain), ref is sampled continu - ously throughout the conversion. the first step in choosing a reference circuit is to decide what kind of performance is required. this often suggests compromises made in the interests of cost and size. it is possible that a system may not require an accurate reference at all. if a system makes a ratiomet - ric measurement such as figure 9? bridge circuit, any relatively noise-free voltage that presents a low imped - ance at the ref input will serve as a reference. the +5v analog supply suffices if you use a large, low- impedance bypass capacitor to keep ref stable dur - ing switching of the capacitor arrays. do not place a resistance between the +5v supply and the bypass capacitor, because it will cause linearity errors due to the dynamic ref input current, which typically ranges from 300 a to 400 a. figure 10 shows a more typical scheme that provides good ac accuracy. the max874? initial accuracy can
max195 be improved by trimming, but the drift is too great to provide good stability over temperature. the max427 buffer provides the necessary drive current to stabilize the ref input quickly after capacitance changes. the reference inaccuracies contribute additional full- scale error. a reference with less than 1 2 16 total error (15 parts per million) over the operating temperature range is required to limit the additional error to less than 1lsb. the max6241 achieves a drift specification of 1ppm/ c (typ). this allows reasonable temperature changes with less than 1lsb error. while the max6241? initial-accuracy specification (0.02%) results in an offset error of about 14lsb, the reference voltage can be trimmed or the offset can be corrected in software if absolute dc accuracy is essential. figure 11? circuit provides outstanding temperature stability and also provides excellent dc accuracy if the initial error is corrected. 16-bit, 85ksps adc with 10 a shutdown 12 ______________________________________________________________________________________ 14 16 15 12 max195 max427 agnd vssa vdda 4 4 7 6 8 6 2 2 3 max874 gnd v in comp v out 4.096v +15v -15v 47 m f low esr 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1000pf 0.1 m f 0.1 m f 1k 10 w 2k ref 1n914 1n914 10 w -5v +5v 6 12 5 4 14 3 2.2 m f v in 3 8v 1 m f 10k 2.2 m f 0.1 m f 2 max6241 in out ref trim nr gnd agnd max195 figure 10. typical reference circuit for ac accuracy figure 11. high-accuracy reference
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 13 input signal 1n914 diode clamps +5v ain max195 -5v vssa vdda +15v -15v 10 w figure 12. analog input protection for overvoltage or improper supply sequence ref and ain input protection the ref and ain signals should not exceed the max195 supply rails. if this can occur, diode clamp the signal to the supply rails. use silicon diodes and a 10 current-limiting resistor (figures 10 and 12) or schottky diodes without the resistor. when using the current-limiting resistor, place the resis - tor between the appropriate input (ain or ref) and any bypass capacitor. while this results in ac transients at the input due to dynamic input currents, the transients settle quickly and do not affect conversion results. improperly placing the bypass capacitor directly at the input forms an rc lowpass filter with the current-limiting resistor, which averages the dynamic input current and causes linearity errors. analog input the max195 uses a capacitive dac that provides an inherent track/hold function. the input impedance is typically 30 in series with 250pf in unipolar mode and 50 in series with 125pf in bipolar mode. input range the analog input range can be either unipolar (0v to v ref ) or bipolar (-v ref to v ref ), depending on the state of the bp/up/ shdn pin (see digital interface sec - tion). the reference range is 0v to vdda. when choos - ing the reference voltage, the equivalent max195 input noise (40 v rms in unipolar mode, 80 v rms in bipolar mode) should be considered. input acquisition and settling four conversion-clock periods are allocated for acquir - ing the input signal. at the highest conversion rate, four clock periods is 2.4 s. if more than three clock cycles have occurred since the end of the previous conver - sion, conversion begins on the next falling clock edge after conv goes low. otherwise, bringing conv low begins a conversion on the fourth falling clock edge after the previous conversion. this scheme ensures the minimum input acquisition time is four clock periods. most applications require an input buffer amplifier. if the input signal is multiplexed, the input channel should be switched near the beginning of a conversion, rather than near the end of or after a conversion (figure 13). this allows time for the input buffer amplifier to respond to a large step change in input signal. the input amplifi - er must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. at the beginning of acquisition, the capacitive dac is connected to the amplifier output, causing some output disturbance. ensure that the sampled voltage has set - tled to within the required limits before the end of the acquisition time. if the frequency of interest is low, ain can be bypassed with a large enough capacitor to charge the capacitive dac with very little change in voltage (figure 14). however, for ac use, ain must be driven by a wideband buffer (at least 10mhz), which must be stable with the dac? capacitive load (in paral - lel with any ain bypass capacitor used) and also must settle quickly (figure 15 or 16).
max195 16-bit, 85ksps adc with 10 a shutdown 14 ______________________________________________________________________________________ max400 4 7 6 2 3 in +15v -15v 1.0 m f 0.1 m f 0.1 m f 1000pf 1k 100 w ain 1n914 1n914 +5v -5v 10 w figure 14. max400 drives ain for low-frequency use eoc a0 a1 clk change mux input here conversion in1 a0 a1 in2 in3 in4 out acquisition max195 4-to-1 mux eoc ain figure 13. change multiplexer input near beginning of conversion to allow time for slewing and settling.
digital noise digital noise can easily be coupled to ain and ref. the conversion clock (clk) and other digital signals that are active during input acquisition contribute noise to the con - version result. if the noise signal is synchronous to the sampling interval, an effective input offset is produced. asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. minimize noise by present - ing a low impedance (at the frequencies contained in the noise signal) at the inputs. this requires bypassing ain to agnd, or buffering the input with an amplifier that has a small-signal bandwidth of several megahertz, or prefer - ably both. ain has a bandwidth of about 16mhz. offsets resulting from synchronous noise (such as the conversion clock) are canceled by the max195? cali - bration scheme. however, because the magnitude of the offset produced by a synchronous signal depends on the signal? shape, recalibration may be appropriate if the shape or relative timing of the clock or other digi - tal signals change, as might occur if more than one clock signal or frequency is used. distortion avoid degrading dynamic performance by choosing an amplifier with distortion much less than the max195? thd (-97db, or 0.0014%) at frequencies of interest. if the chosen amplifier has insufficient common-mode rejection, which results in degraded thd performance, use the inverting configuration (positive input ground - ed) to eliminate errors from this source. low tempera - ture-coefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to self-heat - ing. also, to reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest (figures 14, 15, 16). dc accuracy if dc accuracy is important, choose a buffer with an offset much less than the max195? maximum offset ( 3lsb = 366 v for a 4v input range), or whose offset can be trimmed while maintaining good stability over the required temperature range. recommended circuits figure 14 shows a good circuit for dc and low-frequen - cy use. the max400 has very low offset (10 v) and drift (0.2 v/ c), and low voltage noise (10nv/ hz ) as well. however, its gain-bandwidth product (gbw) is much too low to drive ain directly, so the analog input is bypassed to present a low impedance at high fre - quencies. the large bypass capacitor is isolated from the amplifier output by a 100 resistor, which provides additional noise filtering. since the 15v supplies exceed the ain range, add protection diodes at ain (see ref and ain input protection section). figure 15 shows a wide-bandwidth amplifier (max427) driving a wideband video buffer, which is capable of driving ain and a small bypass capacitor (for noise reduction) directly. the video buffer is inside the max427? feedback loop, providing good dc accura - cy, while the buffer? low output impedance and high- current capability provide good ac performance. ain is diode-clamped to the 5v rails to prevent overvoltage. the max427? 15 v maximum offset voltage, 0.8 v/ c maximum drift, and less than 5nv/ hz noise specifica - tions make this an excellent choice for ac/dc use. max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 15 max427 4 7 6 2 2 3 in +15v -15v 0.0033 m f 0.1 m f 0.1 m f elantec el2003 4 1 7 +15v -15v 0.1 m f 0.1 m f 100pf 1k 1k 1n914 1n914 +5v -5v ain 10 w figure 15. ain buffer for ac/dc use
max195 if 15v supplies are unavailable, figure 16? circuit works very well with the 5v analog supplies used by the max195. the max410 has a minimum 3.5v com - mon-mode input range, with a similar output voltage swing, which allows use of a reference voltage up to 3.5v. the offset voltage (250 v) is about 2lsb. the drift (1 v/ c), unity-gain bandwidth (28mhz), and low voltage noise (2.4nv/ ? hz ) are appropriate for 16-bit performance. operating modes and spi/qspi interfaces the two basic interface modes are defined according to whether serial data is received during the conversion (clocked with clk, sclk unused) or in bursts between conversions (clocked with sclk). each mode is pre - sented interfaced to a qspi processor, but is also com - patible with spi. mode 1 (simultaneous conversion and data transfer) in this mode, each data bit is read from the max195 during the conversion as it is determined. sclk is grounded and clk is used as both the conversion clock and the serial data clock. figure 17 shows a qspi processor connected to the max195 for use in this mode and figure 18 is the associated timing dia - gram. in addition to the standard qspi interface signals, gen - eral i/o lines are used to monitor eoc and to drive bp/up/ shdn and reset . the two general output pins may not be necessary for a given application and, if i/o lines are unavailable, the eoc connection can be omit - ted as well. the eoc signal is monitored during calibration to determine when calibration is finished and before beginning a conversion to ensure the max195 is not in mid-conversion, but it is possible for a system to ignore eoc completely. on power-up or after pulsing reset low, the p must provide 14,000 clk cycles to com - plete the calibration sequence (figure 2). one way to do this is to toggle clk and monitor eoc until it goes low, but it is possible to simply count 14,000 clk cycles to complete the calibration. similarly, it is unnecessary to check the status of eoc before begin - ning a conversion if you are sure the last conversion is complete. this can be done by ensuring that every conversion consists of at least 20 clk cycles. data is clocked out of the max195 on clk? falling edge and can be clocked into the p on the rising edge or the following falling edge. if you clock data in on the rising edge (spi/qspi with cpol = 0 and cpha = 0; standard microwire: hitachi h8), the maximum clk rate is given by: where t cd is the max195? clk-to-dout valid delay and t sd is the data setup time for your p. f = / 1 t + t clk(max) 1 2 cd sd ? ? ? ? 16-bit, 85ksps adc with 10 a shutdown 16 ______________________________________________________________________________________ max195 qspi gpt bp/up/shdn clk sclk eoc dout reset conv cs *oc3 sck *ic1 miso *oc2 * the use of these signals adds flexibility and functionality but is not required to implement the interface. pcs0 figure 17. max195 connection to qspi processor clocking data out during conversions max410 4 7 6 2 3 in +5v -5v 0.1 m f 0.01 m f 22 w 510 w 0.1 m f ain figure 16. 5v buffer for ac/dc use has 3.5v swing microwire is a trademark of national semiconductor corp.
if clocking data in on the falling edge (cpol = 0, cpha = 1), the maximum clk rate is given by: do not exceed the maximum clk frequency given in the electrical characteristics table. to clock data in on the falling edge, your processor hold time must not exceed t cd minimum (100ns). while qspi can provide the required 20 clk cycles as two continuous 10-bit transfers, spi is limited to 8-bit transfers. this means that with spi, a conversion must consist of three 8-bit transfers. ensure that the pauses between 8-bit operations at your selected clock rate are short enough to maintain a 20ms or shorter conver - sion time, or the leakage of the capacitive dac may cause errors. complete source code for the motorola 68hc16 and the max195 evaluation kit (ev kit) using this mode is available with the max195 ev kit. mode 2 (asynchronous data transfer) this mode uses a conversion clock (clk) and a serial clock (sclk). the serial data is clocked out between conversions, which reduces the maximum throughput for high clk rates, but may be more convenient for some applications. figure 19 is a block diagram with a qspi processor (motorola 68hc16) connected to the max195. figure 20 shows the associated timing dia - gram. figure 21 gives an assembly language listing for this arrangement. f = 1 t + t clk(max) cd sd max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 17 eoc clk t cd t dv data latched: t dh cs, conv dout b15 from previous conversion b15 b15 b2 b14 b1 b0 max195 qspi gpt bp/up/shdn sclk eoc dout reset conv 1.7mhz clk ic3 cs oc3 sck ic1 miso oc2 start pcs0 1.3 m s 74hc32 figure 19. max195 connection to qspi processor clocking data out with sclk between conversions figure 18. timing diagram for circuit of figure 17 (mode 1)
max195 an or gate is used to synchronize the ?tart?signal to the asynchronous clk, as described in the external clock section. as with mode 1, the qspi processor must run clk during calibration and either count clk cycles or, as is done here, monitor eoc to determine when cal - ibration is complete. also, eoc is polled by the p to determine when a conversion result is available. when eoc goes low, data is clocked out at the highest qspi data rate (4.19mbps). after the data is transferred, a new conversion can be initiated whenever desired. the timing specification for sclk-to-dout valid (t sd ) imposes some constraints on the serial interface. at sclk rates up to 2.5mbps, data is clocked out of the max195 by a falling edge of sclk and may be clocked into the p by the next rising edge (cpol = 0, cpha = 0). for data rates greater than 2.5mbps (or for lower rates, if desired) it is necessary to clock data out of the max195 on sclk? falling edge and to clock it into the p on sclk? next falling edge (cpol = 0, cpha = 1). also, your processor hold time must not exceed t sd minimum (20ns). as with clk in mode 1, maximum sclk rates may not be possible with some interface specifications that are subsets of spi. supplies, layout, grounding and bypassing for best system performance, use printed circuit boards with separate analog and digital ground planes. wire-wrap boards are not recommended. the two ground planes should be tied together at the low- impedance power-supply source and at the max195 (figure 22.) if the analog and digital supplies come from the same source, isolate the digital supply from the analog supply with a low-value resistor (10 ). constraints on sequencing the four power supplies are as follows. apply vdda before vddd. apply vssa before vssd. apply ain and ref after vdda and vssa are present. the power supplies should settle within the max195? power-on delay (minimum 500ns) or you should recalibrate the converter (pulse reset low) before use. 16-bit, 85ksps adc with 10 a shutdown 18 ______________________________________________________________________________________ cs clk start 588ns 239ns conversion time 4.19mhz 1.3 m s 9.4 m s 17 m s* 5.1 m s 4 m s eoc sclk dout b15 b3 b2 b13 b14 b1 b0 * interrupt latency of the processor figure 20. timing diagram for circuit of figure 19 (mode 2)
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 19 figure 21. max195 code listing for 68hc16 module and circuit of figure 19
max195 16-bit, 85ksps adc with 10 a shutdown 20 ______________________________________________________________________________________ figure 21. max195 code listing for 68hc16 module and circuit of figure 19 (continued)
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 21 be sure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. a 5ma current flowing through a pc board ground trace impedance of only 0.05 creates an error voltage of about 250 v, or about 2lsbs error with a 4v full-scale system. the board layout should ensure as much as possible that digital and analog signal lines are kept separate. do not run analog and digital (especially clock) lines parallel to one another. if you must cross one with the other, do so at right angles. the adc? high-speed comparator is sensitive to high- frequency noise on the vdda and vssa power sup - plies. bypass these supplies to the analog ground plane with 0.1 f in parallel with 1 f or 10 f low-esr capacitors. keep capacitor leads short for best supply- noise rejection. shutdown the max195 may be shut down by pulling bp/up/ shdn low. in addition to lowering power dissipation to 10 w (100 w max) when the device is not in use, you can save considerable power by shutting the converter down for short periods between conversions. there is no need to perform a reset (calibration) after the con - verter has been shut down unless the time in shutdown is long enough that the supply voltages or ambient tem - perature may have changed. the time required for the converter to ?ake up?and settle depends heavily on the amount of additional error acceptable. for 0.5lsb additional error, 3.2 s is suffi - cient settling time and also allows enough time for reac - quisition of the analog input signal. 50 s settling is required for less than 0.1lsb error. figure 23 is a graph of theoretical power consumption vs. conver - sions per second for the max195 that assumes the conversion clock is 1.7mhz and the converter is shut down as much as possible between conversions. stop clk before shutting down the max195. clk must be stopped without generating short clock pulses. short clk pulses (less than 150ns), or shutting down the max195 without stopping clk, may adversely affect the max195? internal calibration data. in applications where clk is free-running and asynchronous, use the circuit of figure 24 to stop clk cleanly. to minimize the time required to settle and perform a conversion, shut the converter down only after a con - version is finished and the desired mode (unipolar or bipolar) has been set. this ensures that the sampling capacitor array is properly connected to the input sig - nal. if shut down in mid-conversion, when awakened, figure 21. max195 code listing for 68hc16 module and circuit of figure 19 (continued)
max195 16-bit, 85ksps adc with 10 a shutdown 22 ______________________________________________________________________________________ max195 10 m f vddd vdda vssa vssd agnd dgnd 5v 5v 0.1 m f 0.1 m f 10 m f 10 w 10 w 10 m f 0.1 m f 0.1 m f 10 m f 100 0.01 1 10 100 1000 10,000 100,000 0.1 max195-fig23 conversions per second power dissipation (mw) 1 10 20 m s wake-up delay 0.25lsb error 3.2 m s wake-up delay 0.5lsb error 50 m s wake-up delay 0.01lsb error the max195 finishes the old conversion, allows four clock (clk) cycles for input acquisition, then begins the new conversion. _____________ dynamic per for mance high-speed sampling capability, 85ksps throughput, and wide dynamic range make the max195 ideal for ac applications and signal processing. to support these and other related applications, fast fourier transform (fft) test techniques are used to guarantee the adc? dynamic frequency response, distortion, and noise at the rated throughput. specifically, this involves applying a low-distortion sine wave to the adc input and recording the digital conversion results for a specified time. the data is then analyzed using an fft algorithm, which determines its spectral content. conversion errors are then seen as spectral elements other than the fundamental input frequency. signal-to-noise ratio and effective number of bits signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other adc output signals. the output band is limited to frequencies above dc and below one-half the adc sample rate. this usually (but not always) includes distortion as well as noise compo - nents. for this reason, the ratio is sometimes referred to as signal-to-noise + distortion (sinad). the theoretical minimum adc noise is caused by quan - tization error and is a direct result of the adc? resolu - tion: snr = (6.02n + 1.76)db, where n is the number of bits of resolution. a perfect 16-bit adc can, there - fore, do no better than 98db. an fft plot of the output shows the output level in various spectral bands. figure 25 shows the result of sampling a pure 1khz sinusoid at 85ksps with the max195. by transposing the equation that converts resolution to snr, we can, from the measured snr, determine the effective resolution or the ?ffective number of bits?the adc provides: n = (snr - 1.76) / 6.02. substituting sinad for snr in this formula results in a better mea - sure of the adc? usefulness. figure 26 shows the effective number of bits as a function of the max195? input frequency calculated from the sinad. if your intended sample rate is much lower than the max195? maximum of 85ksps, you can improve your noise performance by taking more samples than neces - sary (oversampling) and averaging them in software. figure 27 is a histogram showing 16,384 samples for the max195 without averaging, with an ideal ?oiseless conversion,?and with a running average of five sam - ples. the standard deviation is 0.621lsb without aver - aging and 0.382lsb with the running average. if fewer data points are needed, normal averaging (e.g., five data points averaged to produce one data point) can be used instead of a running average, with similar results. figure 22. supply bypassing and grounding figure 23. power dissipation vs. conversions/sec when shutting the max195 down between conversions
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 23 even better than oversampling and averaging is over - sampling and digital filtering. averaging is just a rough (but computationally simple) type of digital filter. finite impulse response (and other) digital filter algorithms are readily available, and are useful even with slow proces - sors if the data rate is low or the data does not need to be processed in real-time. when using averaging, be sure to average an odd number of samples to avoid small offset errors caused by asymmetrical rounding. whether simple averaging or more complex digital fil - tering is used, the effect of oversampling is to spread the noise across a wider bandwidth. digital filtering or averaging then eliminates the portion of this noise that lies above the filter? passband, leaving less noise in the passband than if oversampling was not used. an additional benefit of oversampling is that it simplifies the design or choice of an anti-aliasing pre-filter for the input. you can use a filter with a more gradual rolloff, because the sample rate is much higher than the fre - quency of interest. ck (2 x clk) j q +5v k clk bp/up/shdn ck 2 x clk 1 / 2 74hc73 q (clk) j (clock shutdown) max195 clock shutdown figure 24. circuit to stop free-running asynchronous clk -150 -130 -110 -90 0 5 10 20 25 40 -30 -50 -70 -10 frequency (khz) signal amplitude (db) 15 30 35 f in = 1khz f s = 85khz t a = +25? figure 25. max195 fft plot
max195 16-bit, 85ksps adc with 10 a shutdown 24 ______________________________________________________________________________________ total harmonic distortion if a pure sine wave is input to an adc, ac integral non - linearity (inl) of an adc? transfer function results in harmonics of the input frequency being present in the sampled output data. total harmonic distortion (thd) is the ratio of the rms sum of all the harmonics (in the frequency band above dc and below one-half the sample rate, but not includ - ing the dc component) to the rms amplitude of the fundamental frequency. this is expressed as follows: where v 1 is the fundamental rms amplitude, and v 2 through v n are the amplitudes of the 2nd through nth harmonics. the thd specification in the electrical characteristics includes the 2nd through 5th harmon - ics. in the max195, this distortion is caused primarily by the changes in on-resistance of the ain sampling switches with changing input voltage. these resis - tance changes, together with the dac? capacitance (which can also vary with input voltage), cause a varying time delay for ac signals, which causes sig - nificant distortion at moderately high frequencies (figure 28). spurious-free dynamic range spurious-free dynamic range is the ratio of the funda - mental rms amplitude to the amplitude of the next largest spectral component (in the frequency band above dc and below one-half the sample rate). usually, this peak occurs at some harmonic of the input frequency. however, if the adc is exceptionally linear, it may occur only at a random peak in the adc? noise floor. transfer function figures 29 and 30 show the max195? transfer func - tions. in unipolar mode, the output data is in binary for - mat and in bipolar mode it is offset binary. thd = 20log v2 + v3 + v4 + ... + v v1 2 2 2 n 2 ? ? ? 18 0 8021 14 max195 fg27 output code (hexadecimal) occurrences of output code (thousands) 8024 6 2 4 8 12 16 8022 8023 8026 10 8025 8027 no averaging ideal conversion running average of 5 samples v ref = +4.5v v ain = +2.25v unipolar mode 85ksps 10 12 11 13 14 15 16 0.1 1 10 100 max195-26 frequency (khz) effective bits f s = 85khz t a = +25? figure 27. histogram of 16,384 conversions shows effects of noise and averaging figure 26. effective bits vs. input frequency 100 60 65 0.1 10 100 70 75 80 85 90 95 max195-28 frequency (khz) sinad (db) 1 f s = 85khz t a = +25? figure 28. signal-to-noise + distortion vs. frequency
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 25 11 . . . 111 11 . . . 110 11 . . . 101 11 . . . 100 11 . . . 011 11 . . . 010 00 . . . 110 00 . . . 101 00 . . . 100 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0v v ref - (1lsb) 11 . . . 111 11 . . . 110 11 . . . 101 10 . . . 010 10 . . . 001 10 . . . 000 01 . . . 111 01 . . . 110 00 . . . 010 00 . . . 001 00 . . . 000 -v ref v ref - (1lsb) 0v figure 29. max195 unipolar transfer function figure 30. max195 bipolar transfer function ___________________ chip t opography 0.273" (6.93mm) 0.144" (3.66mm) eoc cs conv reset vssd ref ain agnd vssa vdda bp/up/shdn clk sclk dout dgnd vddd transistor count: 7966 substrate connected to vdda
max195 16-bit, 85ksps adc with 10 a shutdown 26 ______________________________________________________________________________________ ________________________________________________________ package infor mation pdipn.eps
max195 16-bit, 85ksps adc with 10 a shutdown ______________________________________________________________________________________ 27 ___________________________________________ package infor mation (continued) soicw.eps
max195 16-bit, 85ksps adc with 10 a shutdown maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. sbn.eps ___________________________________________ package infor mation (continued)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max195 part number table notes: see the max195 quickview data sheet for further information on this product family or download the max195 full data sheet (pdf, 320kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max195aewe+t -40c to +85c rohs/lead-free: yes max195aewe-t -40c to +85c rohs/lead-free: no max195bc /d rohs/lead-free: no max195bepe+ pdip;16 pin;.300" dwg: 21-0043d (pdf) use pkgcode/variation: p16+8 * -40c to +85c rohs/lead-free: yes materials analysis max195bc pe+ pdip;16 pin;.300" dwg: 21-0043d (pdf) use pkgcode/variation: p16+8 * 0c to +70c rohs/lead-free: yes materials analysis max195bc pe pdip;16 pin;.300" dwg: 21-0043d (pdf) use pkgcode/variation: p16-8 * 0c to +70c rohs/lead-free: no materials analysis max195bepe pdip;16 pin;.300" dwg: 21-0043d (pdf) use pkgcode/variation: p16-8 * -40c to +85c rohs/lead-free: no materials analysis
max195aede -40c to +85c rohs/lead-free: no max195ac de sidebraze;16 pin;.300" dwg: 21-0047b (pdf) use pkgcode/variation: d16-3 * 0c to +70c rohs/lead-free: no materials analysis max195bmde sidebraze;16 pin;.300" dwg: 21-0047b (pdf) use pkgcode/variation: d16-3 * -55c to +125c rohs/lead-free: no materials analysis max195amde sidebraze;16 pin;.300" dwg: 21-0047b (pdf) use pkgcode/variation: d16-3 * -55c to +125c rohs/lead-free: no materials analysis max195ac we-t 0c to +70c rohs/lead-free: no max195ac we soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16-6 * 0c to +70c rohs/lead-free: no materials analysis max195ac we+t 0c to +70c rohs/lead-free: yes max195ac we+ soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16+6 * 0c to +70c rohs/lead-free: yes materials analysis max195bc we soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16-6 * 0c to +70c rohs/lead-free: no materials analysis max195bc we+ soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16+6 * 0c to +70c rohs/lead-free: yes materials analysis max195bc we+t soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16+6 * 0c to +70c rohs/lead-free: yes materials analysis max195bc we-t soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16-6 * 0c to +70c rohs/lead-free: no materials analysis max195bewe+t soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16+6 * -40c to +85c rohs/lead-free: yes materials analysis max195bewe+ soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16+6 * -40c to +85c rohs/lead-free: yes materials analysis max195bewe soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16-6 * -40c to +85c rohs/lead-free: no materials analysis max195bewe-t soic ;16 pin;.300" dwg: 21-0042b (pdf) use pkgcode/variation: w16-6 * -40c to +85c rohs/lead-free: no materials analysis
max195aewe -40c to +85c rohs/lead-free: no max195aewe+ -40c to +85c rohs/lead-free: yes didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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